Silicon carbide semiconductor equipment

Abstract

To provide silicon carbide semiconductor devices with excellent channel mobility.SOLUTION: A silicon carbide semiconductor device has a silicon carbide substrate having a fin-like projection having a first face and a second face opposite to the first face, a gate insulating film provided on the first and second faces, and a gate electrode provided on the gate insulating film, and the plane orientation of the first and second faces are {0-33-8} plane.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device.

Background Art

[0002] As one of the silicon carbide semiconductor devices, a so-called lateral transistor in which source electrodes and drain electrodes are formed on one surface of a silicon carbide substrate is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional silicon carbide semiconductor device, a crystal plane with low mobility is used, so the channel mobility is low.

[0005] An object of the present disclosure is to provide a silicon carbide semiconductor device having excellent channel mobility.

Means for Solving the Problems

[0006] The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a fin-shaped protrusion having a first surface and a second surface opposite to the first surface, a gate insulating film provided on the first surface and the second surface, and a gate electrode provided on the gate insulating film, and the surface orientations of the first surface and the second surface are {0-33-8} planes.

Effects of the Invention

[0007] According to the present disclosure, a silicon carbide semiconductor device having excellent channel mobility can be provided.

Brief Description of the Drawings

[0008] [Figure 1] Figure 1 is a perspective view showing a silicon carbide semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a first cross-sectional view showing a silicon carbide semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a second cross-sectional view showing a silicon carbide semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a schematic diagram showing a first example of a protrusion in a silicon carbide semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a schematic diagram showing a second example of a protrusion in the silicon carbide semiconductor device according to the first embodiment. [Figure 6A] Figure 6A is a cross-sectional view (part 1) of the first cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 6B] Figure 6B is a cross-sectional view (part 1) of a second cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 7A] Figure 7A is a cross-sectional view (part 2) of the first cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 7B] Figure 7B is a cross-sectional view (part 2) of a second cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 8A] Figure 8A is a cross-sectional view (part 3) of the first cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 8B] Figure 8B is a cross-sectional view (part 3) of the second cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 9A] Figure 9A is a cross-sectional view (part 4) of the first cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 9B] Figure 9B is a cross-sectional view (part 4) of the second cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 10A] Figure 10A is a cross-sectional view (part 5) of the first cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 10B] FIG. 10B is a cross-sectional view (Part 5) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 11A] FIG. 11A is a cross-sectional view (Part 6) of a first cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 11B] FIG. 11B is a cross-sectional view (Part 6) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 12A] FIG. 12A is a cross-sectional view (Part 7) of a first cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 12B] FIG. 12B is a cross-sectional view (Part 7) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 13A] FIG. 13A is a cross-sectional view (Part 8) of a first cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 13B] FIG. 13B is a cross-sectional view (Part 8) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 14A] FIG. 14A is a cross-sectional view (Part 9) of a first cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 14B] FIG. 14B is a cross-sectional view (Part 9) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 15A] FIG. 15A is a cross-sectional view (Part 10) of a first cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 15B] FIG. 15B is a cross-sectional view (Part 10) of a second cross-section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 16] FIG. 16 is a perspective view showing a silicon carbide semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view of a third cross-section showing a silicon carbide semiconductor device according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a fourth cross-section showing a silicon carbide semiconductor device according to the second embodiment. [Figure 19A] Figure 19A is a cross-sectional view (part 1) of a third section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 19B] Figure 19B is a cross-sectional view (part 1) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 20A] Figure 20A is a cross-sectional view (part 2) of the third cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 20B] Figure 20B is a cross-sectional view (part 2) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 21A] Figure 21A is a cross-sectional view (part 3) of a third section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 21B] Figure 21B is a cross-sectional view (part 3) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 22A] Figure 22A is a cross-sectional view (part 4) of the third cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 22B] Figure 22B is a cross-sectional view (part 4) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 23A] Figure 23A is a cross-sectional view (the fifth of the five) of the third cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 23B] Figure 23B is a cross-sectional view (the fifth of the fourth cross-sections) showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 24A] Figure 24A is a cross-sectional view (part 6) of the third cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 24B] Figure 24B is a cross-sectional view (the sixth of the four cross-sections) showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 25A] Figure 25A is a cross-sectional view (number 7) of the third cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 25B]Figure 25B is a cross-sectional view (number 7) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 26A] Figure 26A is a cross-sectional view (number 8) of the third cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 26B] Figure 26B is a cross-sectional view (number 8) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 27A] Figure 27A is a cross-sectional view (the ninth of the three cross-sections) showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 27B] Figure 27B is a cross-sectional view (the ninth of the four cross-sections) showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 28A] Figure 28A is a cross-sectional view (part 10) of the third cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 28B] Figure 28B is a cross-sectional view (number 10) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 29A] Figure 29A is a cross-sectional view (part 11) of a third section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 29B] Figure 29B is a cross-sectional view (part 11) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 30A] Figure 30A is a cross-sectional view (part 12) of the third cross-section showing the manufacturing method of a silicon carbide semiconductor device according to the first embodiment. [Figure 30B] Figure 30B is a cross-sectional view (part 12) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 31A] Figure 31A is a cross-sectional view (part 13) of a third section showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Figure 31B] Figure 31B is a cross-sectional view (part 13) of the fourth cross-section showing the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numeral, and the same description is not repeated. In the crystallographic descriptions herein, individual faces are indicated by () and aggregate faces by {}. Also, while negative crystallographic exponents are usually indicated by a "-" (bar) above the number, in this specification a negative sign is placed before the number.

[0011] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure comprises a silicon carbide substrate having fin-shaped protrusions having a first surface and a second surface opposite to the first surface, a gate insulating film provided on the first surface and the second surface, and a gate electrode provided on the gate insulating film, wherein the surface orientation of the first surface and the second surface is {0-33-8}. In this case, since the {0-33-8} surface with high mobility can be used as a channel, a silicon carbide semiconductor device with excellent channel mobility can be obtained.

[0012] [2] In [1], the projection further has a third surface connected to the first and second surfaces, and the gate insulating film and the gate electrode are provided on the third surface in this order, and the surface orientation of the third surface may be the {0001} surface. In this case, since three surfaces can be used as channels, better channel mobility can be obtained.

[0013] [3] In [1] or [2], the projection extends along the first direction, and in a cross section perpendicular to the first direction, the width of the projection at the lower surface position of the gate electrode may be 55 nm or less. In this case, a channel is more easily formed along the entire projection, resulting in better channel mobility.

[0014] [4] In any of [1] to [3], the projection extends along a first direction, and the projection has a first semiconductor region and a second semiconductor region provided on either side of the gate electrode in the first direction, and the first semiconductor region and the second semiconductor region have a first conductivity type and may have a source electrode that is ohmic-jointed with the first semiconductor region and a drain electrode that is ohmic-jointed with the second semiconductor region. In this case, a transverse silicon carbide semiconductor device with excellent channel mobility is obtained.

[0015] [5] In any of [1] to [3], the projection extends along a first direction, and the projection has a first semiconductor region and a second semiconductor region provided on either side of the gate electrode in the first direction, the silicon carbide substrate has a first main surface on which the projection is provided and a second main surface opposite to the first main surface, the silicon carbide substrate has a third semiconductor region provided adjacent to the second semiconductor region and exposed to the second main surface, the first semiconductor region, the second semiconductor region and the third semiconductor region have a first conductivity type, and may have a source electrode that is ohmic-jointed with the first semiconductor region and a drain electrode that is ohmic-jointed with the third semiconductor region at the second main surface. In this case, a vertical silicon carbide semiconductor device with excellent channel mobility can be obtained.

[0016] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments.

[0017] [First Embodiment] The first embodiment relates to a so-called lateral MOSFET (silicon carbide semiconductor device).

[0018] (Silicon carbide semiconductor device) A silicon carbide semiconductor device 1A according to the first embodiment will now be described. Figure 1 is a perspective view showing the silicon carbide semiconductor device 1A according to the first embodiment. Figure 2 is a first cross-sectional view showing the silicon carbide semiconductor device 1A according to the first embodiment. The first cross-section corresponds to the cross-section cut along line II in Figure 1. Figure 3 is a second cross-sectional view showing the silicon carbide semiconductor device 1A according to the first embodiment. The second cross-section corresponds to the cross-section cut along line II-II in Figure 1.

[0019] As shown in Figures 1 to 3, the silicon carbide semiconductor device 1A mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a passivation film 90. In Figure 1, the interlayer insulating film 83, source electrode 60, drain electrode 70, passivation film 90, etc. are omitted from the illustration.

[0020] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 20 and protrusions 30.

[0021] The silicon carbide single crystal substrate 20 is composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 20 contains n-type impurities such as nitrogen (N) and has an n-type conductivity. The silicon carbide single crystal substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a may be a {0001} plane.

[0022] The projection 30 is provided on the first main surface 20a. The projection 30 is made of, for example, polytype 4H hexagonal silicon carbide. The projection 30 is formed by epitaxial growth with the addition of, for example, p-type impurities such as aluminum (Al). The projection 30 extends along a first direction parallel to the first main surface 20a.

[0023] The projection 30 has a fin-like shape defined by a first side surface 30a, a second side surface 30b opposite to the first side surface 30a, and an upper surface 30c connected to the first side surface 30a and the second side surface 30b. The first side surface 30a and the second side surface 30b have {0-33-8} surfaces. In this case, since the {0-33-8} surfaces with high mobility can be used as channels, a silicon carbide semiconductor device 1A with excellent channel mobility can be obtained. The first side surface 30a is a surface inclined by an angle θ1 with respect to the first main surface 20a. The angle θ1 may be, for example, 54.7°±3°. The second side surface 30b is a surface inclined by an angle θ2 with respect to the first main surface 20a. The angle θ2 may be, for example, 54.7°±3°. The upper surface 30c is, for example, a plane parallel to the first main surface 20a. The upper surface 30c may be a {0001} surface. In this case, since three faces can be used as channels, better channel mobility can be obtained.

[0024] In a cross-section perpendicular to the first direction, the width W1 of the projection 30 at the lower surface position of the gate electrode 82 may be 55 nm or less. In this case, a channel is more easily formed over the entire projection 30, resulting in better channel mobility.

[0025] The projection 30 has a body region 31, a source region 32, and a drain region 33.

[0026] The body region 31 contains p-type impurities such as aluminum and has a p-type conductivity.

[0027] The source region 32 is located next to the body region 31 in the first direction. The source region 32 is in contact with the body region 31. The source region 32 contains n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity.

[0028] The drain region 33 is located next to the body region 31 in the first direction. The drain region 33 is in contact with the body region 31. In the first direction, the drain region 33 is separated from the source region 32 by the body region 31. When viewed from a plane perpendicular to the first main surface 20a, the drain region 33 and the source region 32 are located with the gate electrode 82 in between in the first direction. The drain region 33 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The effective concentration of n-type impurities in the drain region 33 may be the same as or approximately the same as the effective concentration of n-type impurities in the source region 32.

[0029] The gate insulating film 81 is provided on the first side surface 30a, the second side surface 30b, and the top surface 30c. The gate insulating film 81 is in contact with the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c. The gate insulating film 81 may also be in contact with the silicon carbide single crystal substrate 20 on the first main surface 20a. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of, for example, a material containing silicon dioxide.

[0030] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 extends, for example, along a second direction that is parallel to the first main surface 20a and perpendicular to the first direction. The gate electrode 82 is made of, for example, polysilicon containing conductive impurities.

[0031] The interlayer insulating film 83 is provided in contact with the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60 and the drain electrode 70. A portion of the interlayer insulating film 83 may be in contact with the source region 32 and the drain region 33. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide.

[0032] The source electrode 60 is provided on the source region 32. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 32. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon (Si). The contact electrode 61 is ohmic bonded to the source region 32. The source wiring 62 is provided on the contact electrode 61. The source wiring 62 is in contact with the contact electrode 61 and the interlayer insulating film 83. The source wiring 62 is made of a material containing, for example, aluminum.

[0033] The drain electrode 70 is provided on the drain region 33. The drain electrode 70 has a contact electrode 71 and a drain wiring 72. The contact electrode 71 is in contact with the drain region 33. The contact electrode 71 is made of a material containing, for example, nickel silicide. The contact electrode 71 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 71 is ohmic bonded to the drain region 33. The drain wiring 72 is provided on the contact electrode 71. The drain wiring 72 is in contact with the contact electrode 71 and the interlayer insulating film 83. The drain wiring 72 is made of a material containing, for example, aluminum.

[0034] The passivation film 90 is provided on the source wiring 62, drain wiring 72, and interlayer insulating film 83. The passivation film 90 is in contact with the source wiring 62, drain wiring 72, and interlayer insulating film 83. The passivation film 90 is made of a material including, for example, polyimide.

[0035] According to the silicon carbide semiconductor device 1A of the first embodiment described above, the silicon carbide substrate 10 has fin-shaped protrusions 30 having a first side surface 30a and a second side surface 30b, and the surface orientation of the first side surface 30a and the second side surface 30b is {0-33-8} plane. In this case, since the {0-33-8} plane with high mobility can be used as a channel, a transverse silicon carbide semiconductor device 1A with excellent channel mobility can be obtained.

[0036] Furthermore, since the silicon carbide semiconductor device 1A according to the first embodiment has a bulk-type field-effect transistor, a bias can be applied to the silicon carbide single crystal substrate 20. This makes it easy to respond to threshold fluctuations that may occur in a FinFET (Fin Field Effect Transistor).

[0037] (Arrangement of protrusions) The arrangement of the protrusions 30 of the silicon carbide semiconductor device 1A according to the first embodiment will be described below.

[0038] Figure 4 is a schematic diagram showing a first example of a projection 30 having of a silicon carbide semiconductor device 1A according to the first embodiment. Figure 4 is a plan view of the projection 30 from a direction perpendicular to the first main surface 20a. In the example shown in Figure 4, one projection 30 extends along a first direction. The projection 30 is covered by source wiring 62, gate electrode 82 and drain wiring 72 which are spaced apart in the first direction. The source wiring 62 and drain wiring 72 are provided on either side of the gate electrode 82 in the first direction.

[0039] Figure 5 is a schematic diagram showing a second example of a projection 30 having of a silicon carbide semiconductor device 1A according to the first embodiment. Figure 5 is a plan view of the projection 30 from a direction perpendicular to the first main surface 20a. In the example shown in Figure 5, three projections 30 are provided in parallel. Specifically, when viewed from a direction perpendicular to the first main surface 20a, the three projections 30 are provided at regular intervals in a second direction perpendicular to the first direction. Each projection 30 extends along the first direction. Each projection 30 is covered by source wiring 62, gate electrode 82, and drain wiring 72, which are provided at intervals in the first direction. The source wiring 62 and drain wiring 72 are provided on either side of the gate electrode 82 in the first direction. When the three projections 30 are provided in parallel, the drain output can be increased.

[0040] Figure 4 shows the case where there is one projection 30, and Figure 5 shows the case where there are three projections 30, but the number of projections 30 is not limited. For example, there may be two projections 30, or there may be four or more.

[0041] (Manufacturing method for silicon carbide semiconductor devices) A method for manufacturing the silicon carbide semiconductor device 1A according to the first embodiment will now be described. Figures 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are cross-sectional views of the first cross section showing the method for manufacturing the silicon carbide semiconductor device 1A according to the first embodiment. The first cross section corresponds to the cross section cut along line II in Figure 1. Figures 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, 14B, and 15B are cross-sectional views of the second cross section showing the method for manufacturing the silicon carbide semiconductor device 1A according to the first embodiment. The second cross section corresponds to the cross section cut along line II-II in Figure 1.

[0042] First, a silicon carbide single crystal substrate 20 is prepared as shown in Figures 6A and 6B. The silicon carbide single crystal substrate 20 contains n-type impurities such as nitrogen and has an n-type conductivity. The silicon carbide single crystal substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a.

[0043] Next, as shown in Figures 7A and 7B, a silicon carbide epitaxial layer 30X is formed on the first main surface 20a. The silicon carbide epitaxial layer 30X can be formed by epitaxial growth with the addition of p-type impurities such as aluminum.

[0044] Next, as shown in Figures 8A and 8B, a fin-shaped projection 30 is formed that extends along the first direction and has a first side surface 30a, a second side surface 30b, and an upper surface 30c. The projection 30 can be formed as follows.

[0045] First, a mask (not shown) having an opening is formed on the region where the protrusion 30 is not to be formed. Next, the silicon carbide epitaxial layer 30X is removed by etching using the mask. By etching, a protrusion is formed on the region where the protrusion 30 is to be formed, having a side portion that is substantially perpendicular to the first main surface 20a and an upper portion that is continuously provided with the side portion and substantially parallel to the first main surface 20a.

[0046] Next, thermal etching is performed on the protrusions. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with the mask formed. The at least one type of halogen atom includes at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere contains, for example, chlorine (Cl2), boron trichloride (BCl3), sulfur hexafluoride (SF6), or carbon tetrafluoride (CF4). For example, a mixed gas of chlorine gas and oxygen (O2) gas is used as the reactive gas, and thermal etching is performed at a heat treatment temperature of 800°C to 900°C. In addition to the chlorine gas and oxygen gas mentioned above, the reactive gas may also contain a carrier gas. As the carrier gas, for example, nitrogen (N2) gas, argon (Ar) gas, or helium (He) gas can be used.

[0047] The above thermal etching process forms a projection 30 on the first main surface 20a. The projection 30 has a first side surface 30a, a second side surface 30b, and a top surface 30c. The first side surface 30a and the second side surface 30b have {0-33-8} planes. The top surface 30c has a {0001} plane. After thermal etching, the mask is removed. In this way, a silicon carbide substrate 10 having a silicon carbide single crystal substrate 20 and a projection 30 is obtained.

[0048] Next, as shown in Figures 9A and 9B, ion implantation is performed to form a source region 32 and a drain region 33 in the projection 30. In ion implantation, n-type impurities such as nitrogen or phosphorus are implanted. This forms a source region 32 and a drain region 33 in the projection 30. The body region 31 is formed from the portion of the projection 30 that has not been implanted with impurity ions. Next, activation annealing is performed to activate the impurity ions implanted in the projection 30. The atmosphere for activation annealing is preferably an inert gas atmosphere, such as an argon (Ar) atmosphere.

[0049] Next, as shown in Figures 10A and 10B, a gate insulating film 81 is formed. For example, by thermal oxidation of the silicon carbide substrate 10, a gate insulating film 81 is formed that is in contact with the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c, and in contact with the silicon carbide single crystal substrate 20 on the first main surface 20a. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 81 that is in contact with the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c, and in contact with the silicon carbide single crystal substrate 20 on the first main surface 20a. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first side surface 30a, the second side surface 30b, the top surface 30c, and the first main surface 20a have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0050] Next, the silicon carbide substrate 10 may be heat-treated (NO annealing) in a nitric oxide (NO) gas atmosphere. During NO annealing, the silicon carbide substrate 10 is held under conditions, for example, between 1100°C and 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 31. As a result, the formation of interface ranks in the interface region is suppressed, thereby improving channel mobility.

[0051] Next, as shown in Figures 11A and 11B, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by a low-pressure chemical vapor deposition (LP-CVD) method. The gate electrode 82 is positioned to face the body region 31.

[0052] Next, an interlayer insulating film 83 is formed as shown in Figures 12A and 12B. Specifically, the interlayer insulating film 83 is formed to cover the gate electrode 82 and to be in contact with the source region 32 and the drain region 33. The interlayer insulating film 83 is formed, for example, by the CVD method.

[0053] Next, as shown in Figures 13A and 13B, metal films (not shown) for the contact electrodes 61 and 71 that are in contact with the source region 32 and the drain region 33 are formed on the first side surface 30a, the second side surface 30b, and the top surface 30c. The metal films for the contact electrodes 61 and 71 are formed, for example, by sputtering. Next, alloying annealing is performed. The metal films for the contact electrodes 61 and 71 are held at a temperature of, for example, 900°C to 1100°C. As a result, at least a portion of the metal films for the contact electrodes 61 and 71 react with the silicon contained in the silicon carbide substrate 10 and silicide is formed. This forms the contact electrodes 61 and 71 that are ohmic-bonded to the source region 32 and the drain region 33.

[0054] Next, as shown in Figures 14A and 14B, the source wiring 62 and drain wiring 72 are formed. Specifically, the source wiring 62 that covers the contact electrode 61 and the drain wiring 72 that covers the contact electrode 71 are formed. The source wiring 62 and drain wiring 72 are formed, for example, by sputtering. In this way, a source electrode 60 having the contact electrode 61 and the source wiring 62, and a drain electrode 70 having the contact electrode 71 and the drain wiring 72 are formed.

[0055] Next, a passivation film 90 is formed as shown in Figures 15A and 15B. Specifically, a passivation film 90 is formed to cover the source wiring 62, drain wiring 72, and interlayer insulating film 83. The passivation film 90 is formed, for example, by a coating method.

[0056] In this way, a silicon carbide semiconductor device 1A including a field-effect transistor can be manufactured.

[0057] [Second Embodiment] The second embodiment relates to a so-called vertical MOSFET (silicon carbide semiconductor device).

[0058] (Silicon carbide semiconductor device) A silicon carbide semiconductor device 1B according to the second embodiment will now be described. Figure 16 is a perspective view showing the silicon carbide semiconductor device 1B according to the second embodiment. Figure 17 is a cross-sectional view of the third cross section showing the silicon carbide semiconductor device 1B according to the second embodiment. The third cross section corresponds to the cross section cut along line III-III in Figure 16. Figure 18 is a cross-sectional view of the fourth cross section showing the silicon carbide semiconductor device 1B according to the second embodiment. The fourth cross section corresponds to the cross section cut along line IV-IV in Figure 16.

[0059] As shown in Figures 16 to 18, the silicon carbide semiconductor device 1B mainly comprises a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a passivation film 90. In Figure 16, the interlayer insulating film 83, source electrode 60, passivation film 90, etc. are omitted from the illustration.

[0060] The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 20 and protrusions 30.

[0061] The silicon carbide single crystal substrate 20 is composed of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 20 contains n-type impurities such as nitrogen and has an n-type conductivity. The silicon carbide single crystal substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a may be a {0001} plane.

[0062] The projection 30 is provided on the first main surface 20a. The projection 30 is made of, for example, polytype 4H hexagonal silicon carbide. The projection 30 is formed by epitaxial growth with the addition of, for example, p-type impurities such as aluminum. The projection 30 extends along a first direction parallel to the first main surface 20a.

[0063] The projection 30 has a fin-like shape defined by a first side surface 30a, a second side surface 30b opposite to the first side surface 30a, and an upper surface 30c connected to the first side surface 30a and the second side surface 30b. The first side surface 30a and the second side surface 30b have {0-33-8} surfaces. In this case, since the {0-33-8} surfaces with high mobility can be used as channels, a silicon carbide semiconductor device 1A with excellent channel mobility can be obtained. The first side surface 30a is a surface inclined by an angle θ1 with respect to the first main surface 20a. The angle θ1 may be, for example, 54.7°±3°. The second side surface 30b is a surface inclined by an angle θ2 with respect to the first main surface 20a. The angle θ2 may be, for example, 54.7°±3°. The upper surface 30c is, for example, a plane parallel to the first main surface 20a. The upper surface 30c may be a {0001} surface. In this case, since three faces can be used as channels, better channel mobility can be obtained.

[0064] In a cross-section perpendicular to the first direction, the width W1 of the projection 30 at the lower surface position of the gate electrode 82 may be 55 nm or less. In this case, a channel is more easily formed over the entire projection 30, resulting in better channel mobility.

[0065] The projection 30 has a body region 31, a source region 32, a first connection region 34, and a second connection region 35.

[0066] The body region 31 contains p-type impurities such as aluminum and has a p-type conductivity. The body region 31 has a first region 31A and a second region 31B. The first region 31A is provided on the silicon carbide single crystal substrate 20. The first region 31A is in contact with the first main surface 20a. The second region 31B is provided on the first region 31A. The second region 31B is in contact with the first region 31A, the source region 32, the second connection region 35, and the gate insulating film 81.

[0067] The source region 32 is provided on the first region 31A. The source region 32 is provided next to the second region 31B in the first direction. The source region 32 is in contact with the second region 31B. The source region 32 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity.

[0068] The first connection region 34 is provided on the silicon carbide single crystal substrate 20. The first connection region 34 is in contact with the first main surface 20a. The first connection region 34 is provided next to the first region 31A in the first direction. The first connection region 34 is in contact with the first region 31A. When viewed from a plane in a direction perpendicular to the first main surface 20a, the first connection region 34 and the source region 32 are provided with the gate electrode 82 in the first direction. The first connection region 34 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity.

[0069] The second connection region 35 is provided on top of the first connection region 34. The second connection region 35 is provided next to the second region 31B in the first direction. The second connection region 35 is in contact with the second region 31B. The second connection region 35 is provided such that it is separated from the source region 32 by the second region 31B in the first direction. When viewed from a plane perpendicular to the first main surface 20a, the second connection region 35 and the source region 32 are provided with the gate electrode 82 in the first direction. The second connection region 35 contains n-type impurities such as nitrogen or phosphorus and has an n-type conductivity. The effective concentration of n-type impurities in the second connection region 35 may be the same as or approximately the same as the effective concentration of n-type impurities in the source region 32. The effective concentration of n-type impurities in the second connection region 35 may be higher than the effective concentration of n-type impurities in the first connection region 34.

[0070] The gate insulating film 81 is provided on the first side surface 30a, the second side surface 30b, and the top surface 30c. The gate insulating film 81 is in contact with the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c. The gate insulating film 81 may also be in contact with the silicon carbide single crystal substrate 20 on the first main surface 20a. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is composed of, for example, a material containing silicon dioxide.

[0071] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 extends, for example, along a second direction that is parallel to the first main surface 20a and perpendicular to the first direction. The gate electrode 82 is made of, for example, polysilicon containing conductive impurities.

[0072] The interlayer insulating film 83 is provided in contact with the gate electrode 82. The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 electrically insulates the gate electrode 82 from the source electrode 60. A portion of the interlayer insulating film 83 may be in contact with the source region 32 and the second connection region 35. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide.

[0073] The source electrode 60 is provided on the source region 32. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 32. The contact electrode 61 is made of a material containing, for example, nickel silicide. The contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 61 is ohmic bonded to the source region 32. The source wiring 62 is provided on the contact electrode 61. The source wiring 62 is in contact with the contact electrode 61 and the interlayer insulating film 83. The source wiring 62 is made of a material containing, for example, aluminum.

[0074] The drain electrode 70 is in contact with the second main surface 20b. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 20 at the second main surface 20b. The drain electrode 70 is electrically connected to the first connection region 34. The drain electrode 70 is made of a material containing, for example, nickel silicide. The drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is ohmic bonded to the silicon carbide single crystal substrate 20.

[0075] The passivation film 90 is provided on the source wiring 62 and the interlayer insulating film 83. The passivation film 90 is in contact with the source wiring 62 and the interlayer insulating film 83. The passivation film 90 is made of a material including, for example, polyimide.

[0076] According to the silicon carbide semiconductor device 1B of the second embodiment described above, the silicon carbide substrate 10 has fin-shaped protrusions 30 having a first side surface 30a and a second side surface 30b, and the surface orientation of the first side surface 30a and the second side surface 30b is {0-33-8} plane. In this case, since the {0-33-8} plane with high mobility can be used as a channel, a vertical silicon carbide semiconductor device 1A with excellent channel mobility can be obtained.

[0077] (Manufacturing method for silicon carbide semiconductor devices) A method for manufacturing the silicon carbide semiconductor device 1B according to the second embodiment will now be described. Figures 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A are cross-sectional views of the third section showing the method for manufacturing the silicon carbide semiconductor device 1B according to the second embodiment. The third section corresponds to the section cut along line III-III in Figure 16. Figures 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30B, and 31B are cross-sectional views of the fourth section showing the method for manufacturing the silicon carbide semiconductor device 1B according to the second embodiment. The fourth section corresponds to the section cut along line IV-IV in Figure 16.

[0078] First, a silicon carbide single crystal substrate 20 is prepared as shown in Figures 19A and 19B. The silicon carbide single crystal substrate 20 contains n-type impurities such as nitrogen and has an n-type conductivity. The silicon carbide single crystal substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a.

[0079] Next, as shown in Figures 20A and 20B, a first silicon carbide epitaxial layer 30Y is formed on the first main surface 20a. The first silicon carbide epitaxial layer 30Y can be formed by epitaxial growth with the addition of p-type impurities such as aluminum.

[0080] Next, as shown in Figures 21A and 21B, ion implantation is performed to form a first connection region 34 in the first silicon carbide epitaxial layer 30Y. In ion implantation, n-type impurities such as nitrogen or phosphorus are implanted.

[0081] Next, as shown in Figures 22A and 22B, a second silicon carbide epitaxial layer 30Z is formed on the first silicon carbide epitaxial layer 30Y. The second silicon carbide epitaxial layer 30Z can be formed by epitaxial growth with the addition of p-type impurities such as aluminum.

[0082] Next, as shown in Figures 23A and 23B, a fin-shaped projection 30 is formed that extends along the first direction and has a first side surface 30a, a second side surface 30b, and an upper surface 30c. The projection 30 can be formed as follows.

[0083] First, a mask (not shown) having an opening is formed on the region where the protrusion 30 is not to be formed. Next, the first silicon carbide epitaxial layer 30Y and the second silicon carbide epitaxial layer 30Z are removed by etching using the mask. By etching, a protrusion is formed on the region where the protrusion 30 is to be formed, having a side portion that is substantially perpendicular to the first main surface 20a and an upper portion that is continuously provided with the side portion and substantially parallel to the first main surface 20a.

[0084] Next, thermal etching is performed on the protrusions. Thermal etching can be performed by heating in an atmosphere containing a reactive gas having at least one type of halogen atom, with the mask formed. The at least one type of halogen atom includes at least one of chlorine atoms and fluorine atoms. The atmosphere contains, for example, chlorine, boron trichloride, sulfur hexafluoride, or carbon tetrafluoride. For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and thermal etching is performed at a heat treatment temperature of 800°C to 900°C. In addition to the chlorine gas and oxygen gas mentioned above, the reactive gas may also contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas, or helium gas can be used.

[0085] The above thermal etching process forms a projection 30 on the first main surface 20a. The projection 30 has a first side surface 30a, a second side surface 30b, and a top surface 30c. The first side surface 30a and the second side surface 30b have {0-33-8} planes. The top surface 30c has a {0001} plane. After thermal etching, the mask is removed. In this way, a silicon carbide substrate 10 having a silicon carbide single crystal substrate 20 and a projection 30 is obtained.

[0086] Next, as shown in Figures 24A and 24B, ion implantation is performed to form a source region 32 and a second connection region 35 in the projection 30. In ion implantation, n-type impurities such as nitrogen or phosphorus are implanted. This forms the source region 32 and the second connection region 35 in the projection 30. The body region 31 is formed from the portion of the projection 30 that has not been implanted with impurity ions. The body region 31 has a first region 31A and a second region 31B. Next, activation annealing is performed to activate the impurity ions implanted in the projection 30. The atmosphere for activation annealing is preferably an inert gas atmosphere, such as an argon atmosphere.

[0087] Next, as shown in Figures 25A and 25B, a gate insulating film 81 is formed. For example, by thermal oxidation of the silicon carbide substrate 10, a gate insulating film 81 is formed that contacts the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c, and contacts the silicon carbide single crystal substrate 20 on the first main surface 20a. Specifically, the silicon carbide substrate 10 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300°C to 1400°C. This forms a gate insulating film 81 that contacts the body region 31 on the first side surface 30a, the second side surface 30b, and the top surface 30c, and contacts the silicon carbide single crystal substrate 20 on the first main surface 20a. When the gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of the silicon carbide substrate 10 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first side surface 30a, the second side surface 30b, the top surface 30c, and the first main surface 20a have moved slightly to the interface between the gate insulating film 81 and the silicon carbide substrate 10 after thermal oxidation.

[0088] Next, the silicon carbide substrate 10 may be heat-treated (NO annealing) in a nitric oxide gas atmosphere. During NO annealing, the silicon carbide substrate 10 is held under conditions, for example, between 1100°C and 1400°C. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 31. As a result, the formation of interface ranks in the interface region is suppressed, thereby improving channel mobility.

[0089] Next, as shown in Figures 26A and 26B, a gate electrode 82 is formed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by a reduced-pressure CVD method. The gate electrode 82 is positioned to face the body region 31.

[0090] Next, as shown in Figures 27A and 27B, an interlayer insulating film 83 is formed. Specifically, the interlayer insulating film 83 is formed to cover the gate electrode 82. The interlayer insulating film 83 is formed, for example, by the CVD method.

[0091] Next, as shown in Figures 28A and 28B, a metal film (not shown) for the contact electrode 61 that contacts the source region 32 is formed on the first side surface 30a, the second side surface 30b, and the top surface 30c. The metal film for the contact electrode 61 is formed, for example, by sputtering. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900°C to 1100°C. As a result, at least a portion of the metal film for the contact electrode 61 reacts with the silicon contained in the silicon carbide substrate 10 and silicides. This forms a contact electrode 61 that ohmic-bonds with the source region 32.

[0092] Next, as shown in Figures 29A and 29B, source wiring 62 is formed. Specifically, source wiring 62 is formed to cover the contact electrode 61. Source wiring 62 is formed, for example, by sputtering. In this way, a source electrode 60 having the contact electrode 61 and source wiring 62 is formed.

[0093] Next, a passivation film 90 is formed as shown in Figures 30A and 30B. Specifically, a passivation film 90 is formed to cover the source wiring 62 and the interlayer insulating film 83. The passivation film 90 is formed, for example, by a coating method.

[0094] Next, as shown in Figures 31A and 31B, the second main surface 20b is polished to thin the silicon carbide single crystal substrate 20. Then, a metal film (not shown) for the drain electrode 70, which is in contact with the silicon carbide single crystal substrate 20, is formed on the second main surface 20b. The metal film for the drain electrode 70 is formed, for example, by sputtering. Next, alloying annealing is performed. The metal film for the drain electrode 70 is held at a temperature of, for example, 900°C to 1100°C. As a result, at least a portion of the metal film for the drain electrode 70 reacts with the silicon contained in the silicon carbide substrate 10 and silicides. This forms a drain electrode 70 that is ohmic bonded to the silicon carbide single crystal substrate 20.

[0095] In this way, a silicon carbide semiconductor device 1B including a field-effect transistor can be manufactured.

[0096] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of Symbols]

[0097] 1A, 1B Silicon Carbide Semiconductor Devices 10 Silicon carbide substrate 20 Silicon carbide single crystal substrate 20a First main surface 20b 2nd principal surface 30 protrusions 30a 1st side 30b 2nd side 30c top 30X silicon carbide epitaxial layer 30Y First silicon carbide epitaxial layer 30Z Silicon Carbide Epitaxial Layer 31 Body Region 31A 1st area 31B 2nd area 32 Source Area 33 Drain area 34. First connection area 35 Second Connection Area 60 source electrodes 61 Contact electrodes 62 Source Wiring 70 Drain electrode 71 Contact electrodes 72 Drain wiring 81 Gate Insulator 82 Grid gate 83 Interlayer insulating film 90 Passivation membrane

Claims

1. A silicon carbide substrate having fin-shaped protrusions having a first surface and a second surface opposite to the first surface, A gate insulating film provided on the first surface and the second surface, A gate electrode provided on the gate insulating film, It has, The first and second faces have a {0-33-8} plane orientation. The projection extends along the first direction, The projection has a first semiconductor region and a second semiconductor region provided on either side of the gate electrode in the first direction, The first semiconductor region and the second semiconductor region have a first conductivity type, A source electrode that forms an ohmic junction with the first semiconductor region, A drain electrode that forms an ohmic junction with the second semiconductor region, Having, Silicon carbide semiconductor device.

2. A silicon carbide substrate having fin-shaped protrusions having a first surface and a second surface opposite to the first surface, A gate insulating film provided on the first surface and the second surface, A gate electrode provided on the gate insulating film, It has, The first and second faces have a {0-33-8} plane orientation. The projection extends along the first direction, The projection has a first semiconductor region and a second semiconductor region provided on either side of the gate electrode in the first direction, The silicon carbide substrate has a first main surface on which the protrusions are provided, and a second main surface opposite to the first main surface. The silicon carbide substrate is provided adjacent to the second semiconductor region and has a third semiconductor region exposed on the second main surface. The first semiconductor region, the second semiconductor region, and the third semiconductor region have a first conductivity type, A source electrode that forms an ohmic junction with the first semiconductor region, A drain electrode that forms an ohmic junction with the third semiconductor region and the second main surface, Having, Silicon carbide semiconductor device.

3. The projection further has a third surface connected to the first surface and the second surface, On the third surface, the gate insulating film and the gate electrode are provided in this order. The plane orientation of the third plane is the {0001} plane. A silicon carbide semiconductor device according to claim 1 or claim 2.

4. In a cross section perpendicular to the first direction, the width of the projection at the lower surface position of the gate electrode is 55 nm or less. A silicon carbide semiconductor device according to claim 1 or claim 2.

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