Optical computing device and optical computing method

Abstract

Provided is an optical computation device comprising: an address conversion unit that coverts a plurality of bit values to an address value which is used as an input port number; and a port conversion unit that includes a shuffle circuit which outputs light, input from an input port having said input port number, from an output port having an output port number corresponding to the results of computation executed with respect to the input port number.

Description

[Technical Field]

[0001] This invention relates to data processing methods used in optical communication and optical computing infrastructure, etc. [Background technology]

[0002] In the prior art, optical computing circuits utilizing optical computing elements have been proposed (for example, Non-Patent Document 1). In the prior art, optical circuits are realized using optical computing elements such as Ψ gates, Y gates, and Mach-Zehnder interferometric optical switches (MZI optical switches). Non-Patent Document 1 proposes a computing method that uses MZI optical switches for the nonlinear computing part of an encryption scheme and Y gates for the linear computing part.

[0003] In conventional calculation methods, the bits of an optical signal were represented as "0" or "1" based on the magnitude of the light's amplitude (or the intensity of the light (the square of the light's amplitude)) or the phase of the light. For example, if the phase difference between two optical signals was 0, it was represented as bit 0, and if the phase difference was π, it was represented as bit 1. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Cryptographic circuit technology using optical logic gates, Junko Takahashi, Koji Senda, Kimihiro Yamakoshi, Shota Kita, Akihiko Shinke, NTT Technical Journal 2021.11, pp.59-63. [Overview of the project] [Problems that the invention aims to solve]

[0005] Conventional computation methods, especially when performing multi-bit calculations, require connecting multiple optical logic gates, resulting in significant optical loss. Therefore, to obtain correct calculation results, frequent conversion from optical signals to electrical signals (photoelectric conversion) was necessary during the calculation process.

[0006] In addition, in operations using a Ψ gate or a Y gate (an optical gate excluding the bias light of the Ψ gate), when using the operation result as the input for the next operation, it was necessary to frequently perform photoelectric conversion during the operation in order to change the phase difference of the input optical signal according to the operation result. Performing photoelectric conversion during the operation leads to an increase in operation delay and power consumption.

[0007] In particular, it is difficult to perform operations with multiple stages of non-linear operations (for example, exclusive OR (XOR)) connected using optical logic gates, and in order to obtain a correct operation result, threshold processing by an electric circuit was required at the end of the operation (Non-Patent Document 1).

[0008] The present invention has been made in view of the above points, and an object thereof is to provide a technique for reducing photoelectric conversion processing in optical operations.

Means for Solving the Problems

[0009] According to the disclosed technique, an address conversion unit that converts a plurality of bit values into an address value used as an input port number, a port conversion unit including a shuffle circuit that outputs the light input from the input port of the input port number from the output port of the output port number corresponding to the result of the operation on the input port number An optical operation device including is provided.

Effects of the Invention

[0010] According to the disclosed technique, it becomes possible to reduce photoelectric conversion processing in optical operations.

Brief Description of the Drawings

[0011] [Figure 1] It is a diagram showing the basic configuration of the optical operation device 100. [Figure 2] It is a diagram for explaining the operation method of the sign bit. [Figure 3] It is a diagram showing a configuration example of the optical operation device 100 in Example 1-1-1. [Figure 4]This diagram shows an example configuration of an MZI optical switch. [Figure 5] This diagram illustrates the operation of the MZI optical switch. [Figure 6] This figure shows an example configuration of the optical computing device 100 in Example 1-1-2. [Figure 7] This figure shows an example configuration of the optical computing device 100 in Example 1-1-2. [Figure 8] This figure shows an example configuration of the optical computing device 100 in Example 1-1-2. [Figure 9] This is a diagram illustrating the error detection method. [Figure 10] This figure shows an example configuration of the optical computing device 100 in Example 1-2. [Figure 11] This figure shows an example configuration of the optical computing device 100 in Example 2-1-1. [Figure 12] This figure shows an example configuration of the optical computing device 100 in Example 2-1-2. [Figure 13] This is a diagram to explain the operation of MixColumns. [Figure 14] This figure shows an example configuration of the optical computing device 100 in Example 2-2. [Figure 15] This diagram shows an example configuration of the doubling circuit 123 (shuffle circuit 121). [Figure 16] This figure shows an example configuration of the bit decomposition circuit 122. [Figure 17] This figure shows an example configuration of the multi-bit XOR operation circuit 130. [Figure 18] This figure shows an example configuration of the address translation unit 110. [Modes for carrying out the invention]

[0012] Hereinafter, embodiments of the present invention (this embodiment) will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the embodiments described below.

[0013] (Basic configuration of an optical computing device) In the technology according to this embodiment, the optical computing device 100 performs calculations based on optical wiring by representing multiple bits with optical port numbers, enabling the construction of arbitrary functions and arbitrary calculations. This reduces the number of optical logic gates used in calculations and the number of photoelectric conversions.

[0014] Figure 1 shows the basic configuration of the optical computing device 100 in this embodiment. The optical computing device 100 receives the optical signal output from the optical output device 200 as input, performs optical calculations, and outputs the optical signal to the optical detection device 300. When using an optical computing device 100 that uses electrical signals for path control, an electrical signal output device 400 that outputs electrical signals is also used.

[0015] As shown in Figure 1, the optical computing unit 100 has an address translation unit 110 and a port translation unit 120. The address translation unit 110 converts bit values ​​(optical bit signals) represented by optical signals (or electrical signals) to corresponding address values. The port translation unit 120 performs calculations as port translation of optical signals.

[0016] For example, the address translation unit 110 converts the bit value (0,1,0) to the address value 010, and the optical signal is input to the input port position (port number) in the port translation unit 120 that corresponds to that address value.

[0017] The port conversion unit 120 includes a shuffle circuit 121 and a bit decomposition circuit 122. The shuffle circuit 121 has multiple input ports into which optical signals are input and multiple output ports into which optical signals are output, and the input ports and output ports are connected according to a predetermined rule. The connection method may be a waveguide, an optical fiber, or any other method.

[0018] Each input and output port is assigned a port number. When an optical signal input to an input port with a certain port number (let's call it port number A) is output from an output port with a certain port number (let's call it port number B), this means that a conversion (operation) has been performed from port number A to port number B.

[0019] The input and output ports are wired according to a predetermined rule so that port number conversion corresponds to the desired operation.

[0020] The bit decomposition circuit 122 performs a process (bit decomposition) in the shuffle circuit 121 to convert the port number of the output port from which the optical signal was output back into a bit value.

[0021] As described above, by first converting the bit values ​​represented by optical signals into address values, subsequent calculations can be performed using only optical wiring. The technology according to this embodiment makes it possible to perform arbitrary calculations with N-bit input and M-bit output based on optical wiring (where N and M are arbitrary integers). Below, more specific configurations and operation examples of the optical computing device 100 will be described in Example 1 and Example 2.

[0022] (Example 1: Error correction calculation method) First, let's describe Example 1. In Example 1, the optical computing device 100 performs calculations for error correction processing.

[0023] In error correction processing, generally, the information bit sender generates a code bit, transmits both the information bit and the code bit, and the receiver uses the received information bit and code bit to perform error correction processing.

[0024] Here, we describe an example where the information bits (the number of bits of information transmitted and received between the sender and receiver) are 4 bits, and the code bits used for detecting a 1-bit error are 3 bits. However, this is just one example, and the same calculation method is possible for any number of bits. Note that the error correction process described below can detect a 1-bit arithmetic error, but the application of the technology according to this embodiment does not depend on the number of bits in the error.

[0025] Below, the operation for generating sign bits will be described as Example 1-1, and the operation for error detection will be described as Example 1-2.

[0026] (Example 1-1: Generation of sign bits) When configuring an optical computing device 100 that generates code bits from information bits, the value of the code bit corresponding to the bit value of the information bit is calculated in advance. In this case, the code bit (3 bits) of the Hamming code for the information bit (4 bits) is calculated in advance.

[0027] As a method for calculating the code bit, one can use the method disclosed in the reference "Let's grasp the basic framework of Hamming codes: Basic course on error detection and correction, Part 2, Embedded Technology Lab. Published September 23, 2020." An example of this method is shown in Figure 2. As shown in Figure 2, each bit of the information bits (4 bits) is represented by the 3 bits corresponding to its position, and the code bit corresponding to that information bit can be obtained by performing an exclusive OR (XOR) operation between the 3 bits corresponding to 1 in the information bits.

[0028] In the shuffle circuit 121, each information bit value is assigned to the port number of the input port, each sign bit value is assigned to the port number of the output port, and the input port and output port are connected so that the sign bits correspond to the information bits.

[0029] The following describes an example configuration of an optical computing device 100 for generating code bits corresponding to arbitrary information bits. Examples 1-1-1 and 1-1-2 are described below.

[0030] <Example 1-1-1: Example of using an MZI optical switch for address translation> Figure 3 shows an example configuration of the optical computing device 100 in Example 1-1-1. As shown in Figure 3, the optical computing device 100 has an address translation unit 110 and a port translation unit 120. The port translation unit 120 has a shuffle circuit 121 and a bit decomposition circuit 122.

[0031] The address translation unit 110 has a configuration in which multiple stages, each consisting of one or more MZI optical switches arranged in parallel, are connected in series.

[0032] Figure 4 shows an example configuration of an MZI optical switch. An MZI optical switch is a type of optical logic gate and consists of two optical couplers and an arm with a phase shifter embedded on one or both sides. In the example in Figure 4, the phase shifter is embedded in the lower path.

[0033] The MZI optical switch operates as a switch that changes the phase difference between two optical paths by altering the refractive index of the optical waveguide depending on whether or not a voltage is applied to the path in which a phase shifter is embedded, thereby switching the optical path.

[0034] For example, as shown in Figure 5(b), when light is input to the upper path and a voltage is applied to the path with the embedded phase shifter (corresponding to bit "1" of the electrical signal), the optical signal is output from the straight path (upper side). As shown in (a), when no voltage is applied (corresponding to bit "0" of the electrical signal), the optical signal is output from the crossed path (lower side). The same applies when light is input to the lower path, as shown in (c) and (d).

[0035] Thus, with the MZI optical switch, it is possible to switch the path of the optical signal by switching the voltage on and off. Here, as an example, let's consider the case where the phase shifter is located on the underside of the arm.

[0036] In the address translation unit 110 shown in Figure 3, in the information bits ((x3, x2, x1, x0): x0 is the least significant bit), x3 corresponds to stage A, x2 corresponds to stage B, x1 corresponds to stage C, and x0 corresponds to stage D. In stage D, the number of paths (ports) that can output optical signals is 2 4 It is an individual.

[0037] In the example shown in Figure 3, in each of stages A through C, the output arm (path) of each MZI optical switch is connected to the lower arm of the input side of the MZI optical switch in the next stage. However, this is just an example. The output arm of the MZI optical switch may also be connected to the upper arm of the input side of the MZI optical switch in the next stage.

[0038] In the address translation unit 110 shown in Figure 3, the path of light emitted from the light source (optical output device 200) is switched depending on the information bits (4 bits), and the light reaches the input of the port translation unit 120.

[0039] For example, in the example in Figure 3, when the information bits are (0,0,0,0), the light passes through the arms of each of the highest-order MZI optical switches and reaches the port with port number 0000 in the port conversion unit 120 (specifically, the shuffle circuit 121). In other words, the port number of the port reached when the information bits are (0,0,0,0) is set to 0000. Alternatively, the connection of the address conversion unit 110 may be set so that when the information bits are (0,0,0,0), the light arrives at the input port with port number 0000.

[0040] Similarly, when the information bits are (0,0,0,1), light is output from the second port from the top of the 16 output paths (output ports) in the D stage of the address translation unit 110, and the light arrives at the second input port from the top of the 16 input ports of the port translation unit 121. Let the port number of this input port be 0001.

[0041] In the address translation unit 110, the path of light is switched by the input of light to the MZI optical switch, so that light passes through only one point in the address translation unit 110.

[0042] The implementation method of the MZI optical switch used in this embodiment is not limited to a specific method. For example, the MZI optical switch may be one that operates using thermal effects, one that operates by carrier injection, or one that uses any other method.

[0043] Next, the port conversion unit 120, which consists of a shuffle circuit 121 and a bit decomposition circuit 122, will be described in detail.

[0044] In the shuffle circuit 121, the input port and output port are connected so that light propagates from the input port with a port number corresponding to the information bits (4 bits) to the output port with a port number corresponding to the sign bits (3 bits). The propagation of light from the input port with a port number corresponding to the information bits (4 bits) to the output port with a port number corresponding to the sign bits (3 bits) is equivalent to performing an operation to generate sign bits (3 bits) from information bits (4 bits).

[0045] In other words, if the 3-bit value representing the bit position of each bit in the information bits (4 bits) is determined (see Figure 2), the sign bit corresponding to the information bits (4 bits) can be calculated. Therefore, by wiring the ports with corresponding port numbers, the sign bit corresponding to the information bits can be calculated.

[0046] Generally, the values ​​representing each bit position in memory are often fixed, so by pre-connecting the input port and output port as in this embodiment, the sign bit for the information bit can be calculated.

[0047] For example, by connecting the input port of the port number corresponding to the information bit (1001) to the output port of the port number corresponding to its sign bit (100), light input from the input port corresponding to the information bit (1001) reaches the output port of port number 100. Thus, the port number corresponding to the sign bit can be obtained.

[0048] The bit decomposition circuit 122 decomposes the output (port number) of the shuffle circuit 121 into bit values. Specifically, for each bit of the output (3-bit port number) from the shuffle circuit 121, the bit decomposition circuit 122 propagates light to the output port corresponding to its value (0 or 1). The bit decomposition circuit 122 can be implemented using a waveguide or optical fiber to facilitate this light propagation.

[0049] For example, if the output of the shuffle circuit 121 is 000, that is, if light is output from the output port of port number 000 in the shuffle circuit 121, light is input from the input port corresponding to port number 000 in the bit decomposition circuit 122, and the light reaches the port position (y2,y1,y0)=(0,0,0) (y0 is the least significant bit). Therefore, the output result is the bit value (0,0,0). This output result is converted into an optical signal, input to the optical transmission path, and transmitted to the receiver.

[0050] Similarly, if the output of the shuffle circuit 121 is 101, the light will arrive at (y2,y1,y0)=(1,0,1), and the received light will output the bit value (1,0,1). Here, the shuffle circuit 121 and the bit decomposition circuit 122 can also be implemented in a single circuit.

[0051] As described above, by using the port conversion unit 120, the bit signal can be converted to an address, and then the sign bit can be calculated without photoelectric conversion.

[0052] <Example 1-1-2: An example of using a Ψ gate for address translation> Figure 6 shows an example of the configuration of the optical computing device 100 in Example 1-1-2. The address translation unit 110 of the optical computing device 100 shown in Figure 6 has a configuration in which multiple Y branches and multiple Ψ gates are connected as shown. The port translation unit 120 is the same as the one described in Example 1-1-1. Note that "branch" may also be called a "branching element".

[0053] The Y branch in the address translation unit 110 splits the optical signal into two, and the Ψ gate takes the two input optical signals and the bias light (auxiliary light) as inputs and functions as an AND gate for the two input optical signals.

[0054] The Ψ gate is a logic gate that utilizes optical interference and introduces the concept of bias light, allowing it to change the intensity (amplitude) and phase of the bias light, thereby enabling the operation of typical logic gates with a single gate (3 inputs, 1 output) (Reference: S. Kita, K. Nozaki, K. Tanaka, A. Shinya and M. Notomi, Ultrashort low-loss Ψ gates for linear optical logic on Si photonics platform, Communications Physics, 3, Article number: 33 (2020)).

[0055] In Example 1-1-2, the information bits (x3, x2, x1, x0) and their negation ( - x3, - x2, - x1, - x0) is used as the input to the address translation unit 110 (x0 is the least significant bit). For example, x0=1 represents the state in which light is emitted from the light source (optical output device 200). - x0=0 represents the state where no light is emitted from the light source (a state of no light). For convenience, in the text of this specification, symbols that would normally be placed at the beginning of a word are placed to the upper left of the word. - "x0" is an example of this.

[0056] As shown in Figure 6, the input is a sequence of bits and their negations arranged alternately. In the example in Figure 6, the address translation unit 110 has eight Y branches, eight Ψ gates, eight Y gates, sixteen Y gates, and sixteen Ψ gates from the input side, and these are connected as shown in the figure (connected so that light can pass through).

[0057] In the example in Figure 6, if the information bits are (x3, x2, x1, x0) = (0, 0, 0, 0), the light is output from the first Ψ gate from the top of the 16 Ψ gates in the last stage. Therefore, the first Ψ gate is connected to input port 0 of the shuffle circuit 121.

[0058] If the information bits (x3, x2, x1, x0) = (0, 0, 0, 1), then the light is output from the 5th Ψ gate from the top of the 16 Ψ gates in the last stage. Therefore, the 5th Ψ gate is connected to input port 1 of the shuffle circuit 121. The same applies to the other information bits.

[0059] The calculations performed in the port conversion unit 121 are as described above. In this embodiment, it is possible to generate code bits by using optical signals as information bits without using electrical signals for inputting information bits.

[0060] Figure 7 shows another example of the address translation unit 110 configuration. In the example shown in Figure 7, a four-branch optical gate is used. A four-branch optical gate divides one beam of light into four equal paths.

[0061] As shown in Figure 7, the address translation unit 110 includes eight Y-branches, eight Ψ gates, eight 4-branches, and sixteen Ψ gates from the input side, and these are connected as shown in the figure. With this configuration, the number of branch gates can be reduced by 16 compared to the configuration in Figure 6.

[0062] Figure 8 also shows an example configuration of the address translation unit 110 using an 8-branch optical gate and a 4-input AND gate. In the configuration shown in Figure 8, only one branch and one 4-input logic gate are needed, allowing for a simple configuration. The 4-input logic gate may be realized by connecting two Ψ gates in stages, or by using a single logic gate that extends the Ψ gate to 5 inputs (four inputs and bias light).

[0063] (Examples 1-2: Error detection) Next, as Example 1-2, the configuration and operation of an optical computing device 100 that performs error detection based on the code bits generated by the technology of Example 1-1 will be described.

[0064] Error detection can be performed using the method described in the reference "Understanding the Basics of Hamming Codes: Basic Course on Error Detection and Correction, Part 2," Embedded Technology Lab., published September 23, 2020.

[0065] An example of this method is shown in Figure 9. As shown in Figure 9, similar to the generation of the sign bit, each bit is represented by a value (3 bits) that represents a predetermined bit position, and an exclusive OR operation is performed between the 3 bits that are "1" in the bit sequence consisting of the information bit and the sign bit. Here, it is assumed that if there is an error, the location of the error is one (any one bit out of 7 bits). If the result of the exclusive OR is 000, it means there is no error, and if it is anything other than 000, it indicates the location of the error.

[0066] Figure 10 shows an example configuration of an optical computing device 100 that performs error detection. As shown in Figure 10, the optical computing device 100 has an address translation unit 110 and a port translation unit 120. The port translation unit 120 has a shuffle circuit 121 and a bit decomposition circuit 122.

[0067] The address translation unit 110 has a configuration in which multiple stages, each consisting of one or more MZI optical switches arranged in parallel, are connected in series.

[0068] The address conversion unit 110 has stages corresponding to each bit in a total of 7 bits of information bits and sign bits ((x6, x5, x4, x3, x2, x1, x0): x0 is the least significant bit). In each stage, the output-side arm (path) of each MZI optical switch is connected to the lower-side arm on the input side of the MZI optical switch in the next stage. However, this is an example. The output-side arm of the MZI optical switch may be connected to the upper-side arm on the input side of the MZI optical switch in the next stage.

[0069] In the address conversion unit 110, similar to the sign bit generation, the path of the light emitted from the light source (optical output device 200) is switched depending on the "information bits + sign bits" (7 bits) given as an electrical signal, and the light reaches the input of the port conversion unit 120.

[0070] For example, in the example of FIG. 10, when the information bits + sign bits are (0, 0, 0, 0, 0, 0, 0), the light passes through the arms of the uppermost MZI optical switches, and the light reaches the port with the port number 0000000 in the port conversion unit 120 (specifically, the shuffle circuit 121). In other words, the port number of the port that reaches when the information bits are (0, 0, 0, 0, 0, 0, 0) is set to 0000000. The same applies to other port numbers.

[0071] Similar to the sign bit generation, the output result of the address conversion unit 110 is used as the input to the shuffle circuit 121. Assuming that an error may occur in only 1 bit at this time, the output of the address conversion unit 110 is 2 7 (= 2 4 × 2 3 ) cases, which is {(2 patterns of information bit patterns 4 ) × (2 patterns of "no error + error") 3 cases)}.

[0072] That is, since there are 2 patterns of "no error + error", 2 cases of "information bits + sign bits" 3 cases are divided into 2 7 cases by 2 3To match the street, the shuffle circuit 121 has two input ports. 7 1, output port 2 3 Let's consider them as one, 2 7 From 2 3 The conversion to will be performed by the shuffle circuit 121. The input port is assigned the value of "information bit + sign bit" as the port number, and the output port is 2 3 Assign each of the three 3-bit values ​​as a port number.

[0073] Since the values ​​representing each bit position in Figure 9 are fixed, the output value of the shuffle circuit 121 (the value indicating no error or the value indicating an error position) for each of the 7 bits of "information bit + sign bit" is uniquely determined. Therefore, the output values ​​of the shuffle circuit 121 for each of the 7 bits of "information bit + sign bit" are calculated in advance, and the input port and output port corresponding to these values ​​(port numbers) are connected. As a result, the port number of the output port from which the light input to the input port is output becomes a 3-bit value indicating either no error or the value indicating an error position.

[0074] The configuration and calculation process of the subsequent bit decomposition circuit 122 are the same as in the case of generating the sign bit in Example 1-1-1. In this way, when detecting an error from the information bit and the sign bit, photoelectric conversion is not required during the calculation, and the port conversion unit 120 can perform the calculation using only optical wiring.

[0075] (Example 2: Calculation method for encryption) Next, Example 2 will be described. In Example 2, the optical computing device 100 performs calculations in a symmetric-key encryption scheme. Symmetric-key encryption calculations mainly consist of nonlinear calculations (S-box) and linear calculations. Below, the nonlinear calculations will be described as Example 2-1 and the linear calculations as Example 2-2. Note that the nonlinear and linear calculation units of the key scheduling section can also be calculated in the same way as described in Example 2.

[0076] (Example 2-1: Nonlinear Calculation Processing) Here, as examples of nonlinear computation, we will explain the computation of the S-box of Advanced Encryption Standard (AES) (Example 2-1-1) and the computation of the S-box of PRESENT (Example 2-1-2).

[0077] <Example 2-1-1: AES S-box calculation processing> Figure 11 shows an example configuration of the optical computing device 100 in Example 2-1-1. As shown in Figure 11, the optical computing device 100 has an address translation unit 110 and a port translation unit 120. The port translation unit 120 has a shuffle circuit 121. The address translation unit 110 has a configuration in which multiple stages of one or more MZI optical switches arranged in parallel are connected in series.

[0078] The AES S-box is a table conversion that converts 8 bits of input to 8 bits of output on a one-to-one basis (see Figure 7 in "Federal Information Processing Standards Publication 197, November 26, 2001 Announcing the ADVANCED ENCRYPTION STANDARD (AES), https: / / nvlpubs.nist.gov / nistpubs / fips / nist.fips.197.pdf").

[0079] In the address translation unit 110 shown in Figure 11, there is a stage for each bit of the input bits given as an electrical signal ((x7, x6, x5, x4, x3, x2, x1, x0): x0 is the least significant bit), and an electrical signal (ON / OFF) is applied to each MZI optical switch in each stage. In the last stage, the number of paths (ports) that can output light is 2 8 It is an individual.

[0080] In the example shown in Figure 11, the output arm (path) of each MZI optical switch in each stage is connected to the lower input arm of the next stage's MZI optical switch. However, this is just an example. The output arm of one MZI optical switch may be connected to the upper input arm of the next stage's MZI optical switch.

[0081] In the address translation unit 110 shown in Figure 11, the path of light emitted from the light source (optical output device 200) is switched depending on the input bits (8 bits) of the S-box, and the light reaches one input of the port translation unit 120. In other words, the output of the address translation unit 110 is determined to be one path by the value of the 8 input bits of the S-box.

[0082] For example, in the example in Figure 11, when the input bits are (0,0,0,0,0,0,0,0), the light passes through the arms of each of the highest-order MZI optical switches and reaches the port with port number 00000000 in the port conversion unit 120 (specifically the shuffle circuit 121). In other words, the port number of the port reached when the input bits are (0,0,0,0,0,0,0,0) is set to 0000000. The same applies to the other input bits.

[0083] The port conversion unit 120 consists of a shuffle circuit 121 and uses the output light from the address conversion unit 110 as its input light. The shuffle circuit 121 connects the input ports and output ports so that light propagates from the input port with a port number corresponding to the input bits (8 bits) to the output port with a port number corresponding to the output bits (8 bits). Which input port is connected to which output port is determined based on AES S-box table conversion.

[0084] In other words, the shuffle circuit 121 has pre-wired the optical signals based on the AES S-box table conversion method, so the input light to the shuffle circuit 121 is converted to the corresponding S-box output port. For example, if the input to the shuffle circuit 121 is (00) in hexadecimal, it is connected to the output port (63), so the light reaches the port number (63), and the output value becomes (63).

[0085] As described above, S-box operations for 8 bits are possible. Therefore, S-box operations for 16 bytes can be realized by, for example, repeating the above process 16 times in chronological order, using 16 of the above optical computing devices 100, or performing the calculation with one optical computing device 100 using 16 wavelengths.

[0086] As described above, once the input values ​​are converted to addresses, subsequent calculations can be performed solely through wiring.

[0087] <Example 2-1-2: S-box calculation processing for PRESENT> Figure 12 shows an example configuration of the optical computing device 100 in Example 2-1-2. The address translation unit 110 of the optical computing device 100 shown in Figure 12 has a configuration in which multiple Y branches and multiple Ψ gates are connected as shown. The port translation unit 120 is the same as the one described in Example 2-1-2 (the number of ports is different).

[0088] The optical computing device 100 shown in Figure 12 calculates the S-box of the encryption scheme PRESENT (Reference: A. Bogdanov, LR Knudsen, G. Leander, C. Paar, A. Poschmann, MJB Robshaw, Y. Seurin, and C. Vikkelsoe, PRESENT: An Ultra-Lightweight Block Cipher, CHES 2007: Cryptographic Hardware and Embedded Systems - CHES 2007 pp 450-466).

[0089] The configuration of the address translation unit 110 and the connection configuration to the shuffle circuit 121 shown here are the same as those of the address translation unit 110 and the connection configuration to the shuffle circuit 121 in Embodiment 1-1-2 shown in Figure 6.

[0090] In this embodiment 2-1-2, the four bits of the S-box input and their negative values ​​determine whether or not to emit light from the light source. The light emitted from the light source passes through the Y branch and the Ψ gate and is input to the shuffle circuit 121. Since the shuffle circuit 121 has already wired the light based on the S-box table conversion of PRESENT, the input light to the shuffle circuit 121 is converted to the output port of the corresponding S-box.

[0091] For example, if the input to the shuffle circuit is (0) in hexadecimal, it is connected to the output port (C), so light reaches the port number (C), and the output value becomes (C).

[0092] Regarding the address translation unit 110, similar to Example 1-1-2, the configuration in Figure 12 may be replaced with the configuration using four branches shown in Figure 7, or with the configuration using eight branches shown in Figure 8.

[0093] Similar to Example 2-1-1, 16 bytes of calculation can be achieved by, for example, repeating the above process 16 times in a time series, using 16 of the above optical computing devices 100, or performing the calculation with one optical computing device 100 using 16 wavelengths.

[0094] As described above, in this embodiment as well, once the input value is converted to an address, subsequent calculations can be performed solely through wiring.

[0095] In Example 2-1 (Examples 2-1-1 and 2-1-2), in the case of cryptographic operations, a nonlinear or linear operation follows the S-box (for example, ShiftRows in the case of AES), and since subsequent operations can also be performed using port numbers, the bit decomposition circuit 122 is omitted. However, the bit decomposition circuit 122 may be inserted. Furthermore, the technique of Example 2-1 can also be applied to S-box operations (table substitution) of other cryptographics.

[0096] (Example 2-2: Linear arithmetic processing) Next, Example 2-2 will be described. In Example 2-2, the configuration and operation of the optical computing device 100, which performs MixColumns calculations, a linear operation of the AES encryption scheme, will be described.

[0097] First, the operation of MixColumns will be explained with reference to Figure 13. As shown in Figure 13, the operation of MixColumns consists of 8-bit multiplication and exclusive OR, and the input and output are 32 bits. Note that each element of the matrix shown in Figure 13 is represented in hexadecimal notation. Furthermore, for convenience of description, the symbol "XOR" will be used to represent exclusive OR in the text of the following specification.

[0098] Here, we will describe the optical computing device 100 for performing the 8-bit (y1) operation shown in Figure 13 (1). The same applies to the other 8-bit {y2, y3, y4}. The equation shown in Figure 13 (1) can be transformed as follows.

[0099] y1={02}·x1XOR {02}·x2XOR x2XOR x3XOR x4 Figure 14 shows an example configuration of the optical computing device 100 that calculates the transformed y1. The optical computing device 100 includes an address translation unit 110, a doubling circuit 123, a bit decomposition circuit 122, a multi-bit XOR operation circuit 130, and a photoelectric conversion unit 140. The address translation unit 110 is not shown in Figure 14 because its configuration is the same as that of the address translation unit 110 described earlier. The photoelectric conversion unit 140 may also be an external device to the optical computing device 100. Here, when calculating y1, it may be implemented using a tripling circuit as shown in equation (1) in Figure 13.

[0100] The doubling circuit 123 corresponds to the shuffle circuit 121. The doubling circuit 123 and the bit decomposition circuit 122 may be collectively called the port conversion unit 120. Furthermore, the optical computing device 100 may include all of the "address conversion unit 110, doubling circuit 123, bit decomposition circuit 122, and multi-bit XOR operation circuit 130," or the "address conversion unit 110, doubling circuit 123, and bit decomposition circuit 122" may be one optical computing device 100, and the "multi-bit XOR operation circuit 130" may be another optical computing device 100.

[0101] Furthermore, if a circuit that performs calculations using only optical signals is used as the multi-bit XOR operation circuit 130, the photoelectric conversion unit 140 is unnecessary.

[0102] In the configuration shown in Figure 14, for the input values ​​{x1, x2, x3, x4} after address translation, {x1 and x2} are input to the doubling circuit 123 to obtain {z1 and z2}. Then, {z1, z2, x2, x3, x4} are input to the bit decomposition circuit 122, and the obtained result is input to the multi-bit XOR operation circuit 130 via the photoelectric conversion unit 140.

[0103] If bit decomposition for {x3,x4} has already been completed, the bit decomposition circuit 122 can be used as a direct input.

[0104] Here, the doubling circuit 123 in Figure 14 may be provided for both x1 and x2 (i.e., two doubling circuits 123 may be used), or {z1, z2} may be calculated simultaneously using one doubling circuit 123 by wavelength multiplexing.

[0105] Furthermore, a circuit equivalent to the "bit decomposition circuit 122 and multi-bit XOR operation circuit 130" may be configured so that the arithmetic processing of the "bit decomposition circuit 122 and multi-bit XOR operation circuit 130" is performed together by wiring alone. Examples of the configuration of each circuit are described below.

[0106] <Doubling circuit 123> Figure 15 shows the configuration of the doubling circuit 123 (shuffle circuit 121). The doubling operation involves a left shift and, if the most significant bit is "1", calculating the exclusive OR of the irreducible polynomial (1b) (Reference: Federal Information Processing Standards Publication 197, November 26, 2001 Announcing the ADVANCED ENCRYPTION STANDARD (AES), https: / / nvlpubs.nist.gov / nistpubs / fips / nist.fips.197.pdf).

[0107] By connecting the input to the output corresponding to the result of doubling, the doubling circuit 123 (shuffle circuit 121) shown in Figure 15 can be realized. For 8-bit values ​​{x1, x2}, {z1, z2} can be calculated using the doubling circuit 123 (shuffle circuit 121).

[0108] <Bit Decomposition Circuit 122> Figure 16 shows an example of the configuration of the bit decomposition circuit 122. In the 8-bit bit decomposition circuit 122, each value of {z1, z2, x2, x3, x4} is obtained from the address value as shown in Figure 16 (x 7 ,x 6 ,x 5 ,x 4 ,x 3 ,x 2 ,x 1 ,x 0 Convert to (x 0 (where is the least significant bit value). In the configuration shown in Figure 14, bit decomposition circuits 122 were used for each bit {z1, z2, x2, x3, x4}, but a single circuit may be used by wavelength multiplexing.

[0109] <Multi-bit XOR operation circuit 130> Figure 17 shows an example configuration of the multi-bit XOR arithmetic circuit 130. As shown in Figure 17, the multi-bit XOR arithmetic circuit 130 has an address translation unit 110 and a shuffle circuit 121.

[0110] The address translation unit 110 takes the bit-decomposed value obtained by the bit decomposition circuit 122 as input and performs a 5-bit address translation. The shuffle circuit 121 is wired (connection of input port and output port) based on the result of a 5-bit XOR operation and outputs the result of the XOR operation to make the input 5 bits.

[0111] Figure 17 shows the least significant bit of each {z1, z2, x2, x3, x4} ({z 0 1,z 0 2,x 0 2,x 0 3,x 0 This shows the case of performing a 5-bit XOR operation (represented as 4). For operations on the other bits (bits 2-8), one circuit may be used by wavelength multiplexing, or eight circuits may be used.

[0112] Here, a circuit using an MZI optical switch (Figure 18) is used as the address translation unit 110, so the input to the address translation unit 110 is an electrical signal. For this reason, a photoelectric converter 140 is required between the bit decomposition circuit 122 and the multi-bit XOR operation circuit 130. However, if a configuration using a Ψ gate as shown in Figure 12 is adopted as the address translation unit 110, the photoelectric converter 140 is not required.

[0113] In Figure 17, after address translation, the light is input to the shuffle circuit 121 for 5-bit XOR operation, and the result of the XOR operation (z 0 1XOR z 0 2XOR x 0 2XOR x 0 3XOR x 0 4) The calculation result is obtained when light reaches the port that indicates "0" or "1".

[0114] Here, we have shown an address translation unit 110 that performs 5-bit address translation and a shuffle circuit 121 for 5-bit XOR operations. However, since the next operation in MixColumns is an XOR operation with the key, an address translation unit 110 that performs 6-bit address translation and a shuffle circuit 121 for 6-bit XOR operations may also be used.

[0115] In this way, multi-bit XOR operations (nonlinear operations), which were difficult to perform with optical logic gates alone, can be performed using only address translation and wiring, eliminating the need for threshold processing by electrical circuits.

[0116] As described above, the technology according to Embodiment 2 makes it possible to perform nonlinear and linear operations in cryptographic calculations using the address translation unit 110 and the port translation unit 120 (shuffle circuit 122, etc.). In the case of AES, the ShiftRows calculation can also be performed by wiring, so the entire calculation of one round of the cryptographic calculation unit can be performed using the technology according to Embodiment 2.

[0117] (Summary of examples and effects) The technology described above allows various arbitrary operations to be performed using optical wiring by representing multiple bits of an optical signal with optical port numbers. This reduces the number of optical logic gates used in operations and also reduces the number of photoelectric conversions. Furthermore, while operations using Ψ gates and MZI are basically 1-bit operations, the technology described in this embodiment allows multi-bit operations, such as 8-bit operations as seen in cryptographic S-box operations, to be performed in a single operation, thereby reducing the number of operations.

[0118] In other words, conventional technology uses Ψ gates or MZI gates for calculations, treating amplitude and phase as units of bits and performing calculations bit by bit. Furthermore, when calculations become complex, such as cryptographic operations, multi-stage calculations are required, necessitating photoelectric conversion and phase conversion. In contrast, this technology allows any calculation to be performed solely through wiring by simply converting the bit value to a port number, resulting in benefits such as reducing the number of photoelectric conversions and simplifying implementation.

[0119] (Note) This specification discloses at least the optical computing apparatus and optical computing method described in the following sections. (Additional note 1) An address translation unit that converts multiple bit values ​​into an address value used as an input port number, A port conversion unit including a shuffle circuit that outputs light input from the input port of the aforementioned input port number from the output port of the output port number corresponding to the result of a calculation on the aforementioned input port number. An optical computing device equipped with the following features. (Additional note 2) The address translation unit includes a plurality of Mach-Zehnder interferometric optical switches that input the plurality of bit values ​​as electrical signals. The optical computing device described in Appendix 1. (Additional note 3) The address translation unit includes a plurality of branching elements that input the plurality of bit values ​​as optical signals, and a plurality of optical logic gates. The optical computing device described in Appendix 1. (Additional note 4) The port conversion unit includes a bit decomposition circuit that decomposes a sequence of bit values ​​corresponding to the output port number into individual bit values. An optical computing device as described in any one of the appendices 1 to 3. (Additional note 5) The port conversion unit performs at least one of the following operations as the operation: an operation to generate a sign bit from an information bit; an operation to detect an error from the information bit and the sign bit; a nonlinear operation in cryptographic processing; and a linear operation in cryptographic processing. An optical computing device as described in any one of the appendices 1 through 4. (Additional note 6) An optical computing method performed by an optical computing device, An address translation step that converts multiple bit values ​​into an address value used as an input port number, A port conversion step in which light input from the input port of the aforementioned input port number is output from the output port of the output port number corresponding to the result of a calculation on the aforementioned input port number. An optical computing method comprising [a specific component].

[0120] Although this embodiment has been described above, the present invention is not limited to this specific embodiment, and various modifications and changes are possible within the scope of the gist of the invention as described in the claims. [Explanation of symbols]

[0121] 100 Optical calculation device 110 Address Translation Unit 120 Port Conversion Unit 121 Shuffle Circuit 122-bit decomposition circuit 123 Doubling circuit 130-bit multi-bit XOR operation circuit 140 Photoelectric conversion unit 200 Optical output device 300 Light detection device 400 Electrical signal output device

Claims

1. An address translation unit that converts multiple bit values ​​into an address value used as an input port number, A port conversion unit including a shuffle circuit that outputs light input from the input port of the aforementioned input port number from the output port of the output port number corresponding to the result of a calculation on the aforementioned input port number. An optical computing device equipped with the following features.

2. The address translation unit includes a plurality of Mach-Zehnder interferometric optical switches that input the plurality of bit values ​​as electrical signals. The optical computing device according to claim 1.

3. The address translation unit includes a plurality of branching elements that input the plurality of bit values ​​as optical signals, and a plurality of optical logic gates. The optical computing device according to claim 1.

4. The port conversion unit includes a bit decomposition circuit that decomposes a sequence of bit values ​​corresponding to the output port number into individual bit values. The optical computing device according to any one of claims 1 to 3.

5. The port conversion unit performs at least one of the following operations as the operation: an operation to generate a sign bit from an information bit; an operation to detect an error from the information bit and the sign bit; a nonlinear operation in cryptographic processing; and a linear operation in cryptographic processing. The optical computing device according to any one of claims 1 to 3.

6. A method of optical computation performed by an optical computing device, An address translation step that converts multiple bit values ​​into an address value used as an input port number, A port conversion step in which light input from the input port of the aforementioned input port number is output from the output port of the output port number corresponding to the result of a calculation on the aforementioned input port number. A light computing method comprising the following features.

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