Manufacturing method for semiconductor devices

Abstract

To provide a technique to precisely inject impurities into the desired area at the bottom of a trench.SOLUTION: A method for manufacturing a semiconductor device comprises: a step for forming a trench on the top surface of a semiconductor substrate composed of a wide bandgap semiconductor; a step for forming a resist layer covering the bottom surface and sides of the trench; a step for reducing the thickness of the resist layer covering the bottom surface and leaving the resist layer covering the sides by performing photolithography, in which light is irradiated onto the resist layer from the bottom surface of the semiconductor substrate; and a step for forming a p-type bottom region in the area exposed at the bottom of the trench by injecting p-type impurities from the top side of the semiconductor substrate.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

Background Art

[0002] In a semiconductor device having a trench, in order to relieve the electric field concentration near the bottom of the trench, a technique of forming a p-type electric field relaxation layer in a range exposed at the bottom of the trench is known. Patent Document 1 discloses a method for manufacturing a semiconductor device having such an electric field relaxation layer. In the manufacturing method of Patent Document 1, first, a mask having an opening is formed on the upper surface of a semiconductor substrate, and a trench is formed on the upper surface of the semiconductor substrate through the mask. Next, by subjecting the semiconductor substrate to a thermal oxidation treatment, an insulating film is formed on the inner surface of the trench. Then, by implanting p-type impurities into the bottom surface of the trench through the formed insulating film and the mask used for forming the trench, a p-type electric field relaxation layer is formed in a range exposed at the bottom surface of the trench.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Insulating films formed by thermal oxidation treatment, such as the technique described in Patent Document 1, have high density and excellent impurity shielding properties. In the technique of Patent Document 1, since insulating films are also formed on the bottom surface of the trench, it is necessary to inject impurities with high energy in order to form an electric field relaxation layer in the area exposed on the bottom surface of the trench. As a result, impurities are partially injected into unintended areas (for example, the sides of the trench). When p-type impurities are injected into the sides of the trench, the current path narrows, leading to an increase in on-resistance. This specification provides a technique for accurately injecting impurities into a desired area at the bottom of a trench. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device (10) disclosed herein comprises the steps of: forming a trench (22) on the upper surface (12a) of a semiconductor substrate (12) made of a wide bandgap semiconductor; forming a resist layer (44) that covers the bottom surface (22a) and side surface (22b) of the trench; performing photolithography by irradiating the resist layer with light (80) from the lower side of the semiconductor substrate to reduce the thickness of the resist layer covering the bottom surface and leave the resist layer covering the side surface intact; and injecting p-type impurities (90) from the upper side of the semiconductor substrate to form p-type bottom regions (38a, 38b) in the area exposed to the bottom surface of the trench.

[0006] In this specification, "reducing the thickness of the resist layer" includes not only thinning the resist layer but also reducing its thickness to zero (i.e., removing the resist layer).

[0007] In the above manufacturing method, a trench is formed on the upper surface of the semiconductor substrate, and then a resist layer is formed to cover the bottom and sides of the trench. Next, photolithography is performed from the bottom side of the semiconductor substrate. Since wide-bandgap semiconductors are light-transmitting, the resist layer can be exposed even when light is irradiated from the bottom side of the semiconductor substrate. In this step, the thickness of the resist layer covering the bottom of the trench is reduced, while the resist layer covering the sides of the trench remains. Subsequently, a bottom region is formed by injecting p-type impurities into the bottom of the trench from the upper side of the semiconductor substrate. Thus, in the above manufacturing method, the sides of the trench are covered by the resist layer, while the bottom of the trench is covered by a reduced-thickness resist layer or is not covered by a resist layer when p-type impurities are injected. Therefore, it is possible to inject p-type impurities into the bottom of the trench while suppressing the injection of p-type impurities into the sides of the trench. Note that the density of the resist layer is relatively low, and the resist layer has low impurity shielding properties. Therefore, even if a resist layer remains covering the bottom of the trench after photolithography, the thickness of the resist layer is reduced, allowing p-type impurities to be injected into the bottom of the trench at a low energy through the resist layer. [Brief explanation of the drawing]

[0008] [Figure 1] Cross-sectional view of a semiconductor substrate before processing. [Figure 2] A diagram illustrating the insulating film formation process of the semiconductor device in the embodiment. [Figure 3] A diagram illustrating the trench formation process of the semiconductor device in the example. [Figure 4] A diagram illustrating the resist layer formation process of the semiconductor device in the example. [Figure 5] A diagram illustrating the photolithography process of the semiconductor device in the example. [Figure 6] A diagram illustrating the process of forming the bottom region of the semiconductor device in the embodiment. [Figure 7] Cross-sectional view of a semiconductor device manufactured by the manufacturing process of the example. [Modes for carrying out the invention]

[0009] In one example of a manufacturing method disclosed herein, the step of performing photolithography, in which light is irradiated onto the resist layer, may involve removing the resist layer covering the bottom surface.

[0010] In this configuration, the bottom of the trench is exposed from the resist layer, allowing p-type impurities to be implanted into the bottom of the trench at a lower energy level.

[0011] In one example of a manufacturing method disclosed herein, the step of forming the resist layer may be performed to form a resist layer that covers an area spanning from the side surface of the trench to the upper surface of the semiconductor substrate, and the step of performing photolithography by irradiating the resist layer with light may leave the resist layer covering the upper surface of the semiconductor substrate intact.

[0012] In this specification, the term "resist layer covering the upper surface of a semiconductor substrate" includes not only a configuration in which the resist layer is in direct contact with the upper surface of the semiconductor substrate, but also a configuration in which the resist layer covers the upper surface of the semiconductor substrate via other components. In such a configuration, p-type impurities are injected while the resist layer remains present from the side of the trench across the upper surface of the semiconductor substrate. Therefore, the injection of p-type impurities not only into the side of the trench but also into the upper surface of the semiconductor substrate is suppressed.

[0013] (Examples) A method for manufacturing the semiconductor device of the embodiment will be described with reference to the drawings. First, a semiconductor substrate 12 made of silicon carbide (SiC), as shown in Figure 1, is prepared. As shown in Figure 1, the semiconductor substrate 12 has an n-type drain region 36, an n-type drift region 34 provided on the upper surface of the drain region 36, a p-type body region 32 provided on the upper surface of the drift region 34, and an n-type source region 30 provided on the upper surface of the body region 32. The semiconductor substrate 12 can be manufactured, for example, by sequentially epitaxially growing the drift region 34, the body region 32, and the source region 30 on the drain region 36. Note that the material of the semiconductor substrate 12 is not limited to SiC, and may be made of other wide-bandgap semiconductors such as nitride semiconductors, gallium oxide, or diamond.

[0014] Next, as shown in Figure 2, an insulating film 40 having an opening 42 is formed on the upper surface 12a of the semiconductor substrate 12. The insulating film 40 is made of silicon oxide, silicon nitride, or the like.

[0015] Next, as shown in Figure 3, a trench 22 is formed on the upper surface 12a of the semiconductor substrate 12 through an opening 42 in the insulating film 40 by etching. In this process, a trench 22 is formed from the upper surface 12a of the semiconductor substrate 12, penetrating the source region 30 and the body region 32 and reaching the drift region 34. In addition, in this process, the insulating film 40 is etched together with the semiconductor substrate 12 during the formation of the trench 22, thus reducing the thickness of the insulating film 40. Although not shown, in Figure 3, multiple trenches similar to the trench 22 are formed on the left and right sides of the trench 22.

[0016] Next, as shown in Figure 4, a resist layer 44 is formed that covers an area spanning from the bottom surface 22a and side surface 22b of the trench 22 to the top surface 12a of the semiconductor substrate 12. More specifically, the resist layer 44 is formed to cover an area spanning from the inner surface of the trench 22 to the top surface of the insulating film 40 remaining on the top surface 12a of the semiconductor substrate 12. The material of the resist layer 44 is not particularly limited, but for example, it can be composed mainly of a novolac resin.

[0017] Next, as shown in Figure 5, photolithography is performed on the resist layer 44. Note that Figure 5 is inverted vertically compared to the other figures. In this step, as shown in Figure 5, first, a mask 46 having an opening 48 is formed on the lower surface 12b of the semiconductor substrate 12. The opening 48 is formed at a position corresponding to the bottom surface 22a of the trench 22. Next, by irradiating the semiconductor substrate 12 with light 80 from the lower surface 12b side of the semiconductor substrate 12, the resist layer 44 is selectively exposed through the mask 46. As a result, the resist layer 44 in the exposed area (the area covering the bottom surface 22a of the trench 22) reacts with light 80, and the solubility of that area increases. After that, by immersing the semiconductor substrate 12 in a developer solution (for example, an organic solvent), the resist layer 44 in the area covering the bottom surface 22a of the trench 22 is removed, as shown in Figure 5. Furthermore, the resist layer 44 covering the side surface 22b of the trench 22 and the upper surface 12a of the semiconductor substrate 12 is not exposed due to the presence of the mask 46, and therefore remains without dissolving in the developer solution.

[0018] Next, as shown in FIG. 6, a p-type bottom region 38a is formed in a range exposed on the bottom surface 22a of the trench 22. In this step, p-type impurities 90 are implanted from the upper surface 12a side of the semiconductor substrate 12. Since the upper surface 12a of the semiconductor substrate 12 and the side surface 22b of the trench 22 are covered with the resist layer 44, the p-type impurities 90 are shielded by the resist layer 44. Since the bottom surface 22a of the trench 22 is not covered with the resist layer 44, the p-type impurities 90 can be implanted only in the range exposed on the bottom surface 22a of the semiconductor substrate 12. In the step of performing photolithography, the resist layer 44 remains at the corner 22c (the connection portion between the bottom surface 22a and the side surface 22b) of the trench 22. That is, a part of the bottom surface 22a is covered with the resist layer 44. However, in the process of implanting the p-type impurities 90 into the bottom surface 22a of the trench 22, the p-type impurities 90 are also slightly implanted in the vicinity of the corner 22c. Therefore, in this step, a bottom region 38b having a p-type impurity concentration lower than that of the bottom region 38a is formed in the vicinity of the corner 22c.

[0019] Thereafter, as shown in FIG. 7, after removing the resist layer 44, the semiconductor device 10 is completed by forming a gate insulating film 24, a gate electrode 26, an interlayer insulating film 28, an upper electrode 70, and a lower electrode 72 using a known method.

[0020] As described above, in the manufacturing method of this embodiment, after forming the trench 22 on the upper surface 12a of the semiconductor substrate 12, a resist layer 44 that covers the bottom surface 22a and the side surface 22b of the trench 22 is formed. Next, photolithography is performed from the lower surface 12b side of the semiconductor substrate 12. Since the semiconductor substrate 12 made of a wide bandgap semiconductor has light transmissivity, the resist layer 44 can be exposed even when light is irradiated from the lower surface 12b side of the semiconductor substrate 12. As described above, the photolithography is performed so as to remove the resist layer 44 covering the bottom surface 22a of the trench 22 and leave the resist layer 44 covering the side surface 22b of the trench 22. Thereafter, a p-type impurity 90 is implanted into the bottom surface 22a of the trench 22 from the upper surface 12a side of the semiconductor substrate 12 to form the bottom region 38a. Thus, in the manufacturing method of this embodiment, while the side surface 22b of the trench 22 is covered with the resist layer 44, the p-type impurity 90 is implanted into the bottom surface 22a of the trench 22 in a state where it is not covered with the resist layer 44. Therefore, it is possible to implant the p-type impurity 90 into the bottom surface 22a of the trench 22 at a low energy while suppressing the implantation of the p-type impurity 90 into the side surface 22b of the trench 22.

[0021] Also, in the manufacturing method of this embodiment, the bottom region 38a is formed in the range exposed on the bottom surface 22a of the trench 22, and a low-concentration bottom region 38b is formed in the vicinity of the corner portion 22c of the trench 22. Since the bottom region 38b has a low p-type impurity concentration, when the semiconductor device 10 is turned off, the depletion layer spreads from the bottom region 38b to a wide range in the drift region 34. As a result, the capacitance (i.e., the feedback capacitance) between the gate electrode 26 and the drift region 34 becomes small. As a result, the switching speed of the semiconductor device 10 is improved, and the switching loss can be reduced.

[0022] In the above-described embodiment, in the photolithography step (Figure 5), all of the resist layer 44 covering the bottom surface 22a of the trench 22 was removed, but a portion of the resist layer 44 covering the bottom surface 22a may be left intact. In other words, in this step, the thickness of the resist layer 44 covering the bottom surface 22a of the trench 22 should be reduced by photolithography. The density of the resist layer 44 is relatively low, and the resist layer 44 has low shielding properties against impurities. Therefore, by reducing the thickness of the resist layer 44 covering the bottom surface 22a, the shielding properties against impurities are further reduced, and p-type impurities 90 can be injected into the bottom surface 22a of the trench 22 with low energy.

[0023] Furthermore, in the above-described embodiment, it is not necessary to form a resist layer 44 on the upper surface 12a of the semiconductor substrate 12. In this case, the insulating film 40 remaining after the trench formation process may be used as a mask against the implantation of p-type impurities 90.

[0024] Furthermore, the above-described embodiment illustrates an example of manufacturing a MOSFET (metal-oxide-semiconductor field-effect transistor) as the semiconductor device 10. However, the technology disclosed herein may also be used, for example, to manufacture an IGBT (insulated-gate bipolar transistor). By changing the drain region 36 to a p-type region, an IGBT structure can be obtained.

[0025] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0026] 10: Semiconductor device, 12: Semiconductor substrate, 12a: Top surface, 12b: Bottom surface, 22: Trench, 22a: Bottom surface, 22b: Side surface, 30: Source region, 32: Body region, 34: Drift region, 36: Drain region, 38a: Bottom region, 38b: Bottom region, 44: Resist layer, 70: Upper electrode, 72: Lower electrode, 80: Light, 90: p-type impurity

Claims

1. A method for manufacturing a semiconductor device (10), A step of forming a trench (22) on the upper surface (12a) of a semiconductor substrate (12) made of a wide bandgap semiconductor, A step of forming a resist layer (44) that covers the bottom surface (22a) and side surface (22b) of the trench, The process involves performing photolithography by irradiating the resist layer with light (80) from the lower side of the semiconductor substrate, thereby reducing the thickness of the resist layer covering the bottom surface and leaving the resist layer covering the side surface intact. A step of forming a p-type bottom region (38a, 38b) in the area exposed to the bottom surface of the trench by injecting p-type impurities (90) from the upper surface side of the semiconductor substrate, A manufacturing method that includes the following features.

2. The manufacturing method according to claim 1, wherein in the step of performing photolithography by irradiating the resist layer with light, the resist layer covering the bottom surface is removed.

3. In the step of forming the resist layer, the resist layer is formed to cover an area extending from the side surface of the trench to the upper surface of the semiconductor substrate. The manufacturing method according to claim 1 or 2, wherein in the step of performing photolithography by irradiating the resist layer with light, the resist layer covering the upper surface of the semiconductor substrate is left intact.

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