Semiconductor devices and power converters

The semiconductor device employs a polysilicon field plate connected via separate Al electrodes to improve resistance to high temperature and humidity, addressing corrosion and connectivity issues in power semiconductors, ensuring reliable operation.

JP7835974B2Active Publication Date: 2026-03-26MINEBEA POWER SEMICON DEVICE INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-12-13
Publication Date
2026-03-26

AI Technical Summary

Technical Problem

Conventional power semiconductors face issues with corrosion and melting of aluminum electrodes in high-temperature and high-humidity environments, leading to breakdown voltage failure and increased leakage current due to moisture ingress and capacitive coupling, and lack suitable connectivity between field limiting layers and field plates.

Method used

A semiconductor device with a polysilicon field plate connected to a floating field limiting layer via separate Al electrodes, arranged alternately to minimize contact resistance and electric field, ensuring reliable connections and improved resistance to high temperature and humidity.

Benefits of technology

The solution provides enhanced resistance to high temperature and humidity bias, preventing corrosion and melting of Al electrodes, while maintaining low contact resistance and effective connectivity between field limiting layers and field plates.

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Abstract

To provide: a semiconductor device which has higher resistance to bias at high temperatures and high humidities than ever before, while achieving a good connection between a field limiting layer and a field plate; and a power conversion device in which the semiconductor device is used.SOLUTION: A semiconductor device according to the present invention includes a floating field limiting layer 102 that is provided in a termination region, and a field plate 105 that is electrically connected to the field limiting layer 102, The field plate 105 is formed of polysilicon, the field plate 105 and the field limiting layer 102 are connected to each other via an Al electrode 108, and the connection between the field limiting layer 102 and the Al electrode 108 and the connection between the field plate 105 and the Al electrode 108 are established at different contacts 109 and 110.SELECTED DRAWING: Figure 2
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Description

Technical Field

[0001] The present invention relates to a semiconductor device and a power conversion device.

Background Art

[0002] Power semiconductors are used in various harsh environments, so they need to meet many reliability evaluation items. One of the reliability evaluation items is high-temperature and high-humidity bias resistance. A power semiconductor has an active region for passing current and a termination region for holding breakdown voltage. The termination region has a p-type field limiting layer (in the case of an n-type structure) for holding breakdown voltage and a floating field plate (aluminum (Al) electrode) connected to the field limiting layer.

[0003] In conventional power semiconductors, in a high-temperature and high-humidity environment, when moisture enters the termination region and a voltage is applied between the Al electrodes, which are the field plates, there are problems such as corrosion and melting of the Al electrodes, resulting in the inability to hold breakdown voltage or an increase in leakage current.

[0004] As a technique for forming the field plate in the termination region with a material other than Al, for example, there is Patent Document 1. Patent Document 1 shows that the field plate (115) is formed of polysilicon having a higher resistance than Al. Patent Document 1 is not for the purpose of improving high-temperature and high-humidity bias resistance, which is an object of the present invention, but for the purpose of preventing migration of Al due to the current flowing through the field plate.

[0005] Furthermore, Patent Document 1 shows two structures for electrically connecting a p-type field-limiting layer (114) and a field plate (115): one in which the polysilicon field plate (115) is directly connected to the field-limiting layer (114) (Figure 1), and another in which the field-limiting layer (114) and the field plate (115) are connected via the contact (402) of an aluminum contact electrode (401) without direct connection (Figures 4 and 5). Patent Document 1 also shows a structure in which capacitance is formed between the field plate (115) and the field-limiting layer (114) via a gate oxide film (108) (Figure 7). [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2003-158258 [Overview of the project] [Problems that the invention aims to solve]

[0007] In the aforementioned Patent Document 1, the inventors considered the following problems with respect to the connection structure between the field limiting layer and the field plate. In switching devices such as Insulated Gate Bipolar Transistors (IGBTs), polysilicon is used as the gate electrode material, so a gate oxide film usually exists between the polysilicon and Si. In order to directly connect the polysilicon and the field limiting layer, it is necessary to add a separate patterning process including photolithography and etching to process the field oxide film, which includes the gate oxide film.

[0008] Furthermore, in a structure where the field limiting layer and the polysilicon field plate are connected via an aluminum contact electrode, the aluminum contact electrode and the polysilicon make contact only on a small portion of the side wall or top of the polysilicon, as shown in Figure 5 of Patent Document 1, resulting in high contact resistance. Patent Document 1 states that the increased contact resistance can further suppress Al migration, but in the present invention, it is not necessary to increase the bonding resistance between the field limiting layer and the polysilicon. The objective is to ensure reliable contact, therefore, the above connection method is not suitable in the present invention.

[0009] Furthermore, capacitive coupling, as described above, results in high resistance (high impedance) and is therefore not a suitable connection method in this invention.

[0010] Furthermore, Patent Document 1 discloses only a single field-limiting layer structure, and does not consider cases where there are multiple field-limiting layers. Also, it does not consider the arrangement of aluminum contact electrodes within the chip.

[0011] In view of the above circumstances, the present invention aims to provide a semiconductor device and a power conversion device using the same that have improved resistance to high temperature and high humidity bias compared to conventional devices, and also achieve good connectivity between the field limiting layer and the field plate. [Means for solving the problem]

[0012] To solve the above problems, one embodiment of the present invention provides a semiconductor device comprising a floating field-limiting layer provided in a termination region and a field plate electrically connected to the field-limiting layer, wherein the field plate is formed of polysilicon, and the field plate and the field-limiting layer are connected via Al electrodes. Multiple field limiting layers, field plates, and Al electrodes are arranged, and the multiple Al electrodes form a group of electrodes arranged alternately such that, when viewed on the upper surface of the semiconductor device, adjacent Al electrodes do not line up in a straight line. The connection between the field limiting layer and the Al electrode, and the connection between the field plate and the Al electrode, are connected by different contacts. Furthermore, each of the multiple Al electrodes has only one contact for the connection between the field limiting layer and the Al electrode, and only one contact for the connection between the field plate and the Al electrode. It is characterized by the following.

[0013] Furthermore, one embodiment of the power conversion device of the present invention is a power conversion device having a pair of DC terminals, an AC terminal number equal to the number of phases of the AC output, a switching leg number equal to the number of phases of the AC output, which is connected in series between the pair of DC terminals and consists of two parallel circuits, each consisting of a switching element and a diode connected antiparallel to the switching element, and a gate circuit for controlling the switching element, wherein at least one of the switching element and the diode is the semiconductor device described above.

[0014] A more specific configuration of the present invention is described in the claims. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a semiconductor device and a power conversion device using the same that have improved resistance to high temperature and high humidity bias compared to conventional devices, and also achieve good connectivity between the field limiting layer and the field plate.

[0016] Other issues, configurations, and effects not mentioned above will be clarified by the following description of the embodiments. [Brief explanation of the drawing]

[0017] [Figure 1] Top view of the semiconductor device of the present invention [Figure 2] A partial enlarged view of Figure 1 and its cross-sectional view. [Figure 3] Circuit diagram showing the schematic configuration of the power conversion device of the present invention. [Modes for carrying out the invention]

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. [Examples]

[0019] FIG. 1 is a top view of the semiconductor device of the present invention, and FIG. 2 is a partially enlarged view and a cross-sectional view of FIG. 1. The upper figure of FIG. 2 is an enlarged view of the Al electrode group 113 in FIG. 1, and the lower figure of FIG. 2 is a cross-sectional view taken along line A-A' of the upper figure of FIG. 2. As shown in FIG. 1, the semiconductor device 112 of this embodiment includes an anode electrode 106 provided in the central active region, and a polysilicon field plate 105 and an Al electrode 108 in a termination region provided on the outer periphery of the active region. A guard ring 107 is provided on the outer periphery of the termination region. In this embodiment, an example applied to a diode is described, but it is not limited thereto, and it may be applied to switching elements such as IGBTs and MOSFETs.

[0020] As shown in FIG. 2, in order to maintain the breakdown voltage, the termination region is provided with a p-type well layer 101 connected to the anode electrode 106, a plurality of floating p-type field limiting layers 102, and an n+-channel stopper layer 103 formed at the chip end on the surface of the n-layer substrate 100. The p-type well layer 101 extends from the active region and is connected to the anode electrode 106. The channel stopper layer 103 is connected to the guard ring electrode 107. Note that the conductivity type (n, p) may be inverted. FIG. 2 shows a case where there are four field limiting layers 102, but the number of field limiting layers 102 may be at least one, and the number is not limited.

[0021] The field limiting layer 102 in the termination region is electrically connected to the polysilicon field plate 105 via the Al electrode 108. Here, in order to ensure high temperature and high humidity bias resistance, the Al electrode 108 is provided only on a part of the polysilicon field plate 105. In this embodiment, a contact 110 for connecting the Al electrode 108 and the field limiting layer 102 and a contact 109 for connecting the Al electrode 108 and the polysilicon field plate 105 are provided separately. That is, a contact hole 114 for connecting the Al electrode 108 and the field plate 105 is provided in the interlayer film 104a to form the contact 109, and a contact hole 115 for connecting the Al electrode 108 and the field limiting layer is provided in the interlayer film 104a and the interlayer film 104b to form the contact 110. In FIG. 2, the contact between one Al electrode 108 and one polysilicon field plate 105 is one, but the number of contacts may be one or more, and a plurality of contacts may be provided. Similarly, the contact between one Al electrode 108 and one field limiting layer 102 is one, but the number of contacts may be one or more, and a plurality of contacts may be provided.

[0022] In order to securely connect the Al electrode 108 and the field limiting layer 102, a polysilicon removal region 111 is provided around the contact 110 so as not to provide the polysilicon field plate 105.

[0023] Also, as shown in the upper figure of FIG. 2, the Al electrode group is arranged alternately so that adjacent Al electrodes 108 are not arranged in a straight line. By adopting such a configuration, a large distance between adjacent Al electrodes can be ensured, and corrosion and melting of the Al electrode 108 due to a potential difference can be prevented.

[0024] This structure improves resistance to high temperature and high humidity bias by replacing the Al electrode field plate with a polysilicon field plate, thereby avoiding corrosion and melting of the Al electrode. Furthermore, while Al electrodes are used to electrically connect the field limiting layer and the polysilicon field plate, connecting the field limiting layer to the Al electrode and the field plate to the Al electrode with different contacts ensures reliable contact outside the sidewalls of the polysilicon field plate, reducing contact resistance and achieving a good connection. Additionally, minimizing the Al electrode area and arranging the Al electrode regions alternately mitigates the electric field between the Al electrodes, ensuring resistance to high temperature and high humidity bias. [Examples]

[0025] Next, a power conversion device using the semiconductor device of the present invention described above will be explained. Figure 3 is a circuit diagram showing the schematic configuration of the power conversion device of the present invention. Figure 3 shows an example of the circuit configuration of the power conversion device 500 of this embodiment and the relationship between the DC power supply and the three-phase AC motor (AC load).

[0026] In the power conversion device 500 of this embodiment, the semiconductor device of the present invention described above is used as one or all of the power switching elements 501 to 506 and diodes 521 to 526. The power switching elements 501 to 506 are, for example, IGBTs, and the elements 521 to 526 are diodes.

[0027] As shown in Figure 3, the power converter 500 of this embodiment includes a pair of DC terminals, P terminal 531 and N terminal 532, and AC terminals, U terminal 533, V terminal 534 and W terminal 535, which are the same number as the number of phases of the AC output.

[0028] Furthermore, it includes a switching leg consisting of a series connection of a pair of power switching elements 501 and 502, with a U terminal 533 connected to the series connection point as its output. It also includes a switching leg consisting of a series connection of power switching elements 503 and 504 having the same configuration, with a V terminal 534 connected to the series connection point as its output. Furthermore, it includes a switching leg consisting of a series connection of power switching elements 505 and 506 having the same configuration, with a W terminal 535 connected to the series connection point as its output.

[0029] The three-phase switching legs, consisting of power switching elements 501 to 506, are connected between the DC terminals P terminal 531 and N terminal 532, and DC power is supplied from a DC power supply (not shown). The three-phase AC terminals U terminal 533, V terminal 534, and W terminal 535 of the power converter 500 are connected as a three-phase AC power supply to a three-phase AC motor (not shown).

[0030] The power switching element 501 and the diode 521, which is connected in antiparallel to the power switching element 501, are connected to form a parallel circuit. Similarly, the power switching element 502 and the diode 522, the power switching element 503 and the diode 523, the power switching element 504 and the diode 524, the power switching element 505 and the diode 525, and the power switching element 506 and the diode 526 are connected to form a parallel circuit. A parallel circuit including the power switching element 501 and a parallel circuit including the power switching element 502 are connected in series. Similarly, a parallel circuit including the power switching element 503 and a parallel circuit including the power switching element 504 are connected in series, and a parallel circuit including the power switching element 505 and a parallel circuit including the power switching element 506 are connected in series.

[0031] Each of the power switching elements 501 to 506, which consist of IGBTs, has a gate input terminal connected to a gate circuit 511 to 516, and each power switching element 501 to 506 is controlled by the gate circuits 511 to 516. The gate circuits 511 to 516 are controlled collectively by a control circuit (not shown).

[0032] The gate circuits 511-516 comprehensively and appropriately control the power switching elements 501-506 so that the DC power from the DC power supply is converted into three-phase AC power, which is output from terminals U 533, V 534, and W 535.

[0033] By applying the semiconductor device of the present invention described above to the power conversion device 500, it is possible to provide a power conversion device that has improved resistance to high temperature and high humidity bias compared to conventional devices, and also achieves good connection between the field limiting layer and the field plate.

[0034] As described above, the present invention provides a semiconductor device and a power conversion device using the same that have improved resistance to high temperature and high humidity bias compared to conventional devices, and also achieve good connectivity between the field limiting layer and the field plate.

[0035] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of Symbols]

[0036] 100...n-layer, 101...p-type well layer (main junction), 102...field limiting layer (floating layer), 103...channel stopper layer, 104a,104b...interlayer film, 105...polysilicon field plate, 106...anode electrode, 107...guard ring electrode, 108...Al electrode, 109...contact (connecting Al electrode and polysilicon field plate), 110...contact (connecting Al electrode and field limiting layer), 111...polysilicon cutout region, 112...semiconductor device, 113...Al electrode group, 500...power converter, 501~506...power switching element, 511~516...gate circuit, 521~526...diode, 531...P terminal, 532...N terminal, 533...U terminal, 534...V terminal, 535...W terminal.

Claims

1. A semiconductor device comprising a floating field-limiting layer provided in a termination region and a field plate electrically connected to the field-limiting layer, The field plate is formed of polysilicon, The field plate and the field limiting layer are connected via an Al electrode. Multiple field limiting layers, field plates, and Al electrodes are arranged in each case. The multiple Al electrodes constitute a group of electrodes arranged in an alternating pattern such that, when viewed from the top surface of the semiconductor device, adjacent Al electrodes are not aligned in a straight line. The connection between the field limiting layer and the Al electrode, and the connection between the field plate and the Al electrode are connected by different contacts. A semiconductor device characterized in that each of the plurality of Al electrodes has only one contact for the connection between the field limiting layer and the Al electrode, and only one contact for the connection between the field plate and the Al electrode.

2. In the semiconductor device described in claim 1, A semiconductor device characterized in that, when the upper surface of the semiconductor device is viewed, in each of the plurality of Al electrodes, the contacts connecting the field limiting layer and the Al electrode, and the contacts connecting the field plate and the Al electrode, are aligned in a direction perpendicular to the direction in which the field plate extends.

3. In the semiconductor device described in claim 1, A semiconductor device characterized by having multiple electrode groups of the Al electrodes arranged in an alternating pattern.

4. A pair of DC terminals, The same number of AC terminals as the number of phases of the AC output, Two parallel circuits, each consisting of a switching element and a diode connected in antiparallel to the switching element, are connected in series between the pair of DC terminals, and the number of switching legs is equal to the number of phases of the AC output. A power conversion device having a gate circuit for controlling the switching element, A power conversion device characterized in that at least one of the switching element and the diode is a semiconductor device according to any one of claims 1 to 3.

Citation Information

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