Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing occurrence of a withstand voltage reduction phenomenon such as a sudden current flowing between drain and source electrodes.SOLUTION: A semiconductor device includes an n-type semiconductor layer arranged on a first main surface of a semiconductor substrate; a pair of trenches formed at a distance from each other on a surface of the semiconductor layer on an opposite side of the semiconductor substrate; a pair of gate electrodes buried in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer on the opposite side of the semiconductor substrate; and a drain electrode formed on a second main surface of the semiconductor substrate. The source electrode includes a first electrode that makes Schottky contact with a first region, which is a portion of an inter-electrode region of the pair of gate electrodes in the surface of the semiconductor layer, and a second electrode that makes ohmic contact with a second region different from the first region in the inter-electrode region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to semiconductor equipment Place To relate to. [Background technology]

[0002] A single-conductivity transistor has been developed in which the conductivity type of the semiconductor substrate and the semiconductor layer formed on the semiconductor substrate are the same (see Patent Document 1). In an n-type single-conductivity transistor, if a high voltage is continuously applied between the drain-source electrodes, a breakdown voltage phenomenon may occur, in which a current suddenly flows between the drain-source electrodes. The reason for this is that when a high voltage is applied between the drain and source electrodes, holes and electrons are generated within the n-type semiconductor layer. The electrons generated within the n-type semiconductor layer flow through the n-type semiconductor layer to the drain electrode. On the other hand, the holes generated within the n-type semiconductor layer move towards the vicinity of the source electrode. However, since the source electrode is in ohmic contact with the n-type semiconductor layer, a barrier exists at the interface between the source electrode and the n-type semiconductor layer that prevents the movement of holes from the n-type semiconductor layer to the source electrode. As a result, the holes cannot move to the source electrode and accumulate in the n-type semiconductor layer. As holes accumulate in the n-type semiconductor layer, the barrier for electrons at the interface between the source electrode and the n-type semiconductor layer decreases. This causes a breakdown voltage phenomenon, such as a sudden current flow from the drain electrode to the source electrode. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-42892 [Overview of the project] [Problems that the invention aims to solve]

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of a breakdown voltage phenomenon, such as a sudden current flow between the drain-source electrode. [Means for solving the problem]

[0005] The objective of the present invention is to provide a semiconductor device that can suppress the occurrence of breakdown voltage drop phenomena, such as a sudden current flow between the drain-source electrodes. Place The purpose is to provide.

[0006] This configuration can suppress the occurrence of voltage drop phenomena, such as a sudden current flow between the drain and source electrodes. One embodiment of the present disclosure provides a semiconductor device comprising: an n-type semiconductor substrate having a first main surface and a second main surface opposite to it; an n-type semiconductor layer disposed on the first main surface of the semiconductor substrate; a pair of trenches formed at intervals from each other on the surface of the semiconductor layer opposite to the semiconductor substrate; a pair of gate electrodes embedded in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer opposite to the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate, wherein the gate electrodes are made of an n-type semiconductor and the gate insulating film is made of AlN or SiN.

[0007] This configuration can suppress the occurrence of voltage drop phenomena, such as a sudden current flow between the drain and source electrodes. One embodiment of the present disclosure includes a step of forming an n-type semiconductor layer on an n-type semiconductor substrate, a step of forming a pair of trenches spaced apart from each other on a surface of the semiconductor layer opposite to the semiconductor substrate, a step of embedding a pair of gate electrodes in the pair of trenches via a gate insulating film, a source electrode forming step of forming a source electrode on a surface of the semiconductor layer opposite to the semiconductor substrate, and a step of forming a drain electrode on a second main surface of the semiconductor substrate. The source electrode forming step includes a first electrode forming step of forming a first electrode that forms a Schottky contact with a first region that is a part of a region between the pair of gate electrodes on the surface of the semiconductor layer, and a second electrode forming step of forming a second electrode that forms an ohmic contact with a second region different from the first region in the region between the pair of gate electrodes, and provides a method for manufacturing a semiconductor device.

[0008] With this manufacturing method, a semiconductor device capable of suppressing the occurrence of a breakdown voltage drop phenomenon such as a sudden flow of current between drain-source electrodes can be obtained.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1. [Figure 4A] FIG. 4A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device of FIG. 1, and is a cross-sectional view corresponding to the cut surface of FIG. 2. [Figure 4B] FIG. 4B is a cross-sectional view showing the next step of FIG. 4A. [Figure 4C] FIG. 4C is a cross-sectional view showing the next step of FIG. 4B. [Figure 4D] FIG. 4D is a cross-sectional view showing the next step of FIG. 4C. [Figure 4E] FIG. 4E is a cross-sectional view showing the next step of FIG. 4D. [Figure 4F]FIG. 4F is a cross-sectional view showing the next step of FIG. 4E. [Figure 5A] FIG. 5A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device of FIG. 1, and is a cross-sectional view corresponding to the cutting plane of FIG. 3. [Figure 5B] FIG. 5B is a cross-sectional view showing the next step of FIG. 5A. [Figure 6] FIG. 6 is a cross-sectional view showing a modified example of the first embodiment, and is a cross-sectional view corresponding to the cutting plane of FIG. 3. [Figure 7] FIG. 7 is a schematic plan view of a semiconductor device according to a second embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. 7. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 7. [Figure 10] FIG. 10 is a schematic plan view of a semiconductor device according to a third embodiment of the present invention. [Figure 11] FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10. [Figure 12A] FIG. 12A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device of FIG. 10, and is a cross-sectional view corresponding to the cutting plane of FIG. 11. [Figure 12B] FIG. 12B is a cross-sectional view showing the next step of FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional view showing the next step of FIG. 12B.

Mode for Carrying Out the Invention

[0010] [Description of Embodiments of the Present Disclosure] One embodiment of the present disclosure provides a semiconductor device comprising: an n-type semiconductor substrate having a first main surface and a second main surface opposite to it; an n-type semiconductor layer disposed on the first main surface of the semiconductor substrate; a pair of trenches formed spaced apart from each other on the surface of the semiconductor layer opposite to the semiconductor substrate; a pair of gate electrodes embedded in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer opposite to the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate, wherein the source electrode includes a first electrode that makes Schottky contact with a first region which is a part of the inter-gate electrode region on the surface of the semiconductor layer, and a second electrode that makes ohmic contact with a second region in the inter-gate region which is different from the first region.

[0011] This configuration can suppress the occurrence of voltage drop phenomena, such as a sudden current flow between the drain and source electrodes. In one embodiment of the present disclosure, a recess is selectively formed in the intervening region, and the first electrode is embedded in the recess. In one embodiment of the present disclosure, the depth position of the lower end of the first electrode is deeper than the depth position of the upper surface of the gate electrode and shallower than the depth position of the lower surface of the gate electrode.

[0012] In one embodiment of the present disclosure, the depth position of the lower end of the first electrode is deeper than the depth position of the upper surface of the gate electrode, and shallower than the depth position of the vertical center of the gate electrode. In one embodiment of the present disclosure, a high-concentration region is formed in the surface layer directly beneath the second electrode in the semiconductor layer, where the n-type impurity concentration is higher than that of other regions of the semiconductor layer.

[0013] In one embodiment of this disclosure, the n-type impurity concentration in the high-concentration region is 1 × 10 17 cm 3 ~1 × 10 21 cm 3Therefore, the concentration of n-type impurities in regions other than the high-concentration region in the semiconductor layer is 1 × 10⁻⁶ 15 cm 3 ~1 × 10 18 cm 3 That is the case. In one embodiment of the present disclosure, the second electrode comprises a laminated film of a Ti film formed on the semiconductor layer and an Au film formed on the Ti film, or a single Ti film.

[0014] In one embodiment of the present disclosure, the first electrode is made of a Ni film, a Pt film, a TiN film, a Mo film, or a Pb film. One embodiment of the present disclosure provides a semiconductor device comprising: an n-type semiconductor substrate having a first main surface and a second main surface opposite to it; an n-type semiconductor layer disposed on the first main surface of the semiconductor substrate; a pair of trenches formed at intervals from each other on the surface of the semiconductor layer opposite to the semiconductor substrate; a pair of gate electrodes embedded in the pair of trenches; a gate insulating film interposed between the gate electrodes and the semiconductor layer; a source electrode formed on the surface of the semiconductor layer opposite to the semiconductor substrate; and a drain electrode formed on the second main surface of the semiconductor substrate, wherein the gate electrodes are made of an n-type semiconductor and the gate insulating film is made of AlN or SiN.

[0015] This configuration can suppress the occurrence of voltage drop phenomena, such as a sudden current flow between the drain and source electrodes. In one embodiment of the present disclosure, the gate electrode is made of n-type polysilicon. In one embodiment of the present disclosure, the semiconductor substrate is comprised of a Si substrate, a SiC substrate, a GaN substrate, or a Ga2O3 substrate.

[0016] In one embodiment of the present disclosure, the semiconductor layer consists of a Ga2O3 layer or a ZnO layer. One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising the steps of: forming an n-type semiconductor layer on an n-type semiconductor substrate; forming a pair of trenches spaced apart from each other on the surface of the semiconductor layer opposite to the semiconductor substrate; embedding a pair of gate electrodes in the pair of trenches via a gate insulating film; forming a source electrode on the surface of the semiconductor layer opposite to the semiconductor substrate; and forming a drain electrode on the second main surface of the semiconductor substrate, wherein the source electrode formation step comprises a first electrode formation step of forming a first electrode that makes Schottky contact with a first region which is a part of the inter-gate electrode region on the surface of the semiconductor layer; and a second electrode formation step of forming a second electrode that makes ohmic contact with a second region of the inter-gate electrode region which is different from the first region.

[0017] This manufacturing method provides a semiconductor device that can suppress the occurrence of voltage drop phenomena, such as a sudden current flow between the drain-source electrodes. In one embodiment of the present disclosure, the first electrode formation step includes the step of selectively forming a recess in the intervening region and the step of embedding the first electrode in the recess. [Detailed description of embodiments of this disclosure] Hereinafter, embodiments of this invention will be described in detail with reference to the accompanying drawings.

[0018] Figure 1 is a schematic plan view of a semiconductor device according to the first embodiment of this invention. Figure 2 is a cross-sectional view taken along the line II-II in Figure 1. Figure 3 is a cross-sectional view taken along the line III-III in Figure 1. In Figure 1, the configuration above the surface of the semiconductor layer 3 is omitted. For the sake of explanation, the X and Y directions shown in Figures 1 to 3 may be used below. The X direction is a predetermined direction along the surface of the semiconductor substrate 2 in a plan view, and the Y direction is a direction along the surface of the semiconductor substrate 2 in a plan view that is perpendicular to the X direction. The same applies to Figures 6 to 11.

[0019] The semiconductor device 1 is an n-type single-conduction-type transistor and is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device 1 includes a semiconductor substrate 2 having a first main surface 2a and a second main surface 2b on the opposite side thereof, and a semiconductor layer 3 formed on the first main surface 2a of the semiconductor substrate 2. The conductivity types of the semiconductor substrate 2 and the semiconductor layer 3 are n-type. The first main surface 2a is rectangular in a plan view, having two sides parallel to the X direction and two sides parallel to the Y direction.

[0020] In this embodiment, the semiconductor substrate 2 is made of a Si substrate. The semiconductor substrate 2 may be a SiC substrate, a GaN substrate, a Ga2O3 substrate, or the like. The resistivity of the semiconductor substrate 2 is about 0.001 Ωmm to 0.5 Ωmm. The n-type impurity concentration of the semiconductor layer 3 is 1×10 15 cm -3 or more and 1×10 18 cm -3 or less, which is preferable. In this embodiment, the semiconductor layer 3 is made of an oxide semiconductor such as Ga2O3 or ZnO. In this embodiment, the semiconductor layer 3 is made of a Ga2O3 layer. The film thickness of the semiconductor layer 3 is about 0.5 μm to 5 μm. In this embodiment, the film thickness of the semiconductor layer 3 is about 3 μm. The semiconductor layer 3 functions as a drain region (drift layer) of the electrolytic effect transistor.

[0021] On the surface (upper surface) of the semiconductor layer 3 opposite to the semiconductor substrate 2, a plurality of trenches 4 are formed at intervals in the X direction and extending in the Y direction. That is, the plurality of trenches 4 are formed in a stripe shape. The trench 4 extends from the upper surface of the semiconductor layer 3 to the middle part of the thickness of the semiconductor layer 3. When the outer surface distance (periodic structure width) between two adjacent trenches 4 is A (see FIG. 2), the inner surface distance (distance between the trenches 4) B between two adjacent trenches 4 is preferably A / 4 < B < 3A / 4, and more preferably B = A / 2. A is about 100 nm to 2000 nm. B is about 10 nm to 200 nm. The depth of the trench 4 will be described later.

[0022] A gate electrode 5 is embedded in the trench 4. A gate insulating film 6 is interposed between the gate electrode 5 and the semiconductor layer 3. In this embodiment, the gate insulating film 6 is formed on the side and bottom surfaces of the trench 4 and includes a first gate insulating film 6A that covers the side and bottom surfaces of the gate electrode 5 and a second gate insulating film 6B that covers the top surface of the gate electrode 5. In this embodiment, the top surface of the second gate insulating film 6B and the top surface of the semiconductor layer 3 are substantially flush.

[0023] The gate electrode 5 may be p-type polysilicon or n-type polysilicon. In that case, the p-type impurity concentration or n-type impurity concentration is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following is preferable: The gate electrode 5 may be composed of another semiconductor or metal. The gate insulating film 6 is made of, for example, an Al2O3 film. The gate insulating film 6 may also be made of an SiO2 film. The thickness of the gate insulating film 6 is approximately 5 nm to 30 nm.

[0024] A recess 8 is selectively formed in the region between adjacent gate electrodes 5 on the upper surface of the semiconductor layer 3 (more precisely, the region 7 between the gate insulating film 6 covering adjacent gate electrodes 5). In this embodiment, the recess 8 is formed in the middle of the length of the region 7 (middle in the Y direction). The width of the recess 8 (length in the X direction) is equal to the width of the region 7, and both sides of the recess 8 are formed by the gate insulating film 6 covering adjacent gate electrodes 5. The bottom surface of the recess 8 is formed by the semiconductor layer 3. In this embodiment, the bottom surface of the recess 8 is an example of the "first region" in the present invention.

[0025] A first electrode 11 is embedded within the recess 8, making Schottky contact with the bottom surface of the recess 8. In this embodiment, the first electrode 11 is embedded throughout the entire space within the recess 8. The first electrode 11 is made of a material that makes Schottky contact with the semiconductor layer 3, such as Ni, Pt, TiN, Mo, or Pb. In this embodiment, the first electrode 11 is made of Ni. In the region of the semiconductor layer 3 where recesses 8 are not formed, a high-concentration region 3a with a high n-type impurity concentration is formed. The n-type impurity concentration in the high-concentration region 3a is 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following is preferable: The depth of the high-concentration region 3a from the surface of the semiconductor layer 3 is preferably 0.1 μm or more and 0.5 μm or less.

[0026] A second electrode 12 is formed in a surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, making ohmic contact with the upper surface of the semiconductor layer 3. The second electrode 12 may be formed so as to cover the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B in a region of the surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction. The second electrode 12 is in ohmic contact with the upper surface of the semiconductor layer 3 (the surface of the high-concentration region 3a) and is also in contact with the upper surface of the first electrode 11. In other words, the second electrode 12 is electrically connected to the first electrode 11. Since the second electrode 12 is in ohmic contact with the surface of the high-concentration region 3a, the contact resistance between the second electrode 12 and the semiconductor layer 3 can be reduced.

[0027] The second electrode 12 is made of a material that makes ohmic contact with the semiconductor layer 3, such as a Ti film, or a Ti / Au multilayer film consisting of a lower Ti film and an upper Au film. In this embodiment, the second electrode 12 is made of a Ti film. The source electrode 10 is composed of the first electrode 11 and the second electrode 12. In this embodiment, the region of the inter-region 7 other than the recess 8 in which the second electrode 12 is formed corresponds to the "second region" in the present invention.

[0028] A gate pad (not shown) may be placed above one end in the Y direction where the second electrode 12 is not formed, within a surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, to which all gate electrodes 5 are electrically connected. A drain electrode 13 is formed on the second main surface 2b of the semiconductor substrate 2. The drain electrode 13 is made of a material that makes ohmic contact with the semiconductor layer 3, such as a Ti film, a Ti / Au multilayer film consisting of a Ti film formed on the second main surface 2b and an Au film laminated on the Ti film, etc. In this embodiment, the drain electrode 13 is made of a Ti film.

[0029] In this semiconductor device 1, a depletion layer is formed in the region between adjacent gate electrodes 5 in the semiconductor layer 6, and the current between the drain and source electrodes is controlled by expanding or contracting the width of the depletion layer using the gate voltage. When semiconductor device 1 is used as a normally-off type transistor, for example, a predetermined voltage is applied between the source electrode 10 and the drain electrode 13, with the drain electrode 13 being positive. In this state, an off voltage (0V) or an on voltage (a predetermined positive voltage) is applied to the gate electrode 5, with the source electrode 10 as the reference potential (0V).

[0030] When an off-voltage is applied to the gate electrode 5, a wide depletion layer is formed in the region between adjacent gate electrode 5s within the semiconductor layer 6 (more precisely, the region between the gate insulating films 6 covering adjacent gate electrode 5s), with both sides in the X direction in contact with the corresponding gate insulating films 6. This puts the transistor in the off state. When an on-voltage is applied to the gate electrode 5, the width of the depletion layer narrows, and both sides of the depletion layer in the X direction recede inward beyond the corresponding gate insulating films 6. This puts the transistor in the on state.

[0031] A comparative example will be a semiconductor device with almost the same configuration as semiconductor device 1, but in which the source electrode 10 consists only of a second electrode 12 that makes ohmic contact with the semiconductor layer 3. In other words, the comparative example does not have a first electrode 11 that makes Schottky contact with the semiconductor layer 3. In the comparative example, if a high voltage is continuously applied between the drain and source electrodes, a breakdown voltage drop phenomenon may occur, such as a sudden current flow between the drain and source electrodes. This is because when a high voltage is applied between the drain and source electrodes, holes and electrons are generated within the semiconductor layer 3. The electrons generated within the semiconductor layer 3 flow to the drain electrode through the semiconductor layer 3. On the other hand, the holes generated within the semiconductor layer 3 move towards the vicinity of the source electrode 10 (second electrode 12) through the depletion layer within the semiconductor layer 3. However, since the source electrode 10 is in ohmic contact with the semiconductor layer 3, a barrier exists at the interface between the source electrode 10 and the n-type semiconductor layer 3 that prevents the movement of holes from the n-type semiconductor layer 3 to the source electrode 10. As a result, the holes cannot move to the source electrode 10 and accumulate in the semiconductor layer 3. As holes accumulate in the semiconductor layer 3, the barrier to electrons at the interface between the source electrode 10 and the semiconductor layer 3 becomes lower. This causes a breakdown voltage drop phenomenon, such as a sudden current flow between the drain and source electrodes.

[0032] In the first embodiment described above, the source electrode 10 consists of a first electrode 11 that makes Schottky contact with a portion of the inter-region 7 between adjacent gate electrodes 5 on the upper surface of the semiconductor layer 3, and a second electrode 12 that makes ohmic contact with the other portion of the inter-region 7. Since the first electrode 11 makes Schottky contact with a portion of the inter-region 7, there is no barrier at the interface between the first electrode 11 and the semiconductor layer 3 that prevents the movement of holes from the semiconductor layer 3 to the first electrode 11.

[0033] As a result, the holes that have moved near the source electrode 10 move from the semiconductor layer 3 to the first electrode 11. That is, the holes that have moved near the source electrode 10 are extracted by the first electrode 11. Thereby, accumulation of holes in the semiconductor layer 3 can be suppressed, so that the occurrence of a breakdown voltage drop phenomenon such as a sudden current flowing between the drain and source electrodes when the transistor is off can be suppressed.

[0034] In the above-described first embodiment, the first electrode 11 is embedded in the recess 8 formed on the surface of the semiconductor layer 3. Thereby, the Schottky structure at the interface between the first electrode 11 and the semiconductor layer 3 can reach or approach the depletion layer in the semiconductor layer 3, so that holes can be more effectively extracted by the first electrode 11. Hereinafter, the depth of the trench 4 and the depth position of the gate electrode 5 will be described.

[0035] Referring to FIG. 2, if the film thickness of the semiconductor layer 3 is a and the depth of the high-concentration region 3a from the surface of the semiconductor layer 3 is b, the depth c of the trench 4 needs to be greater than b and less than a. The depth c of the trench 4 is preferably [b + {(a - b) / 4}] < c < b + {3(a - b) / 4}]. Referring to FIG. 3, the depth from the surface of the semiconductor layer 3 to the upper surface of the gate electrode 5 is d, the depth from the surface of the semiconductor layer 3 to the lower surface of the first electrode 11 is e, and the depth from the surface of the semiconductor layer 3 to the lower surface of the gate electrode 5 is g.

[0036] In order to reach or approach the Schottky structure at the interface between the first electrode 11 and the semiconductor layer 3 to the depletion layer in the semiconductor layer 3, the depth e from the surface of the semiconductor layer 3 to the lower surface of the first electrode 11 preferably satisfies the first condition represented by the following formula (1). d < e < g …(1) Let f be the depth from the surface of the semiconductor layer 3 to the center of the gate electrode 5 in the vertical direction. In order to suppress electric field concentration near the lower corner of the gate insulating film 6 in the semiconductor layer 3 and the increase in capacitance between the gate electrode 5 and the first electrode 11, it is preferable that the depth e from the surface of the semiconductor layer 3 to the lower surface of the first electrode 11 satisfies the second condition shown in equation (2).

[0037] d <e<f …(2) In other words, the depth e from the surface of the semiconductor layer 3 to the bottom surface of the first electrode 11 preferably satisfies the first condition, and more preferably satisfies the second condition. Figures 4A to 4F are cross-sectional views illustrating an example of the manufacturing method of the semiconductor device 1 described above, and are cross-sectional views corresponding to the cross-section in Figure 2. Figures 5A and 5B are cross-sectional views illustrating an example of the manufacturing method of the semiconductor device 1 described above, and are cross-sectional views corresponding to the cross-section in Figure 3.

[0038] First, as shown in Figure 4A, an n-type semiconductor layer 3 is epitaxially grown on an n-type semiconductor substrate 2, for example, by the HVPE (Hydride Vapor Phase Epitaxy) method. The semiconductor substrate 2 is, for example, a Si substrate, and the semiconductor layer 3 is, for example, a Ga2O3 layer. The semiconductor layer 3 may also be formed on the semiconductor substrate 2 by the MOCVD (Metal Organic Chemical Vapor Deposition) method, MBE (Molecular Beam Epitaxy) method, or the like.

[0039] Next, as shown in Figure 4B, n-type impurities are implanted into the entire surface layer of the semiconductor layer 3. Then, an activation annealing treatment is performed. The temperature of the activation annealing treatment is preferably 800°C or higher, and more preferably 900°C to 1000°C. As a result, a high-concentration region 3a with a high concentration of n-type impurities is formed throughout the entire surface layer of the semiconductor layer 3. Next, as shown in Figure 4C, multiple trenches 4 are formed on the surface of the semiconductor layer 3 by photolithography and dry etching using the MOCVD method. For example, Cl2, BCl3, etc., are used as etching gases.

[0040] Next, as shown in Figure 4D, a first gate insulating film 6A is formed on the side and bottom surfaces of the trench 4, for example, by the ALD (Atomic Layer Deposition) method. The first gate insulating film 6A consists of, for example, an Al2O3 film. When using the ALD method, the raw materials are TMA (trimethylaluminum) and H2O. The formation of the first gate insulating film 6A on the sides and bottom of the trench 4 may be carried out by forming a resist that covers the portion of the entire surface other than the area corresponding to the trench 4, and then using the resist as a mask to form an insulating material film, which is the material film for the first gate insulating film 6A, on the inner surface of the trench 4. Alternatively, the insulating material film, which is the material film for the first gate insulating film 6A, may be formed over the entire surface, and then the insulating material film may be patterned by dry etching. Instead of the ALD method, the PCVD (Plasma Enhanced Chemical Vapor Deposition) method or the sputtering method may be used.

[0041] Next, as shown in Figure 4E, the material for the gate electrode 5 is embedded in the space surrounded by the first gate insulating film 6A within the trench 4. The material for the gate electrode 5 is, for example, polysilicon. This forms the gate electrode 5. Then, a second gate insulating film 6B is formed to cover the upper surface of the gate electrode 5. This forms the gate insulating film 6 that covers the sides, bottom, and top surfaces of the gate electrode 5.

[0042] Next, as shown in Figure 5A, recesses 8 are formed on the surface of the semiconductor layer 3 by photolithography and dry etching. For example, Cl2, BCl3, etc., are used as etching gases. Then, for example, by sputtering, a first electrode 11 that makes Schottky contact with the bottom surface of the recess 8 is embedded in the recess 8. The first electrode 11 is made of, for example, Ni.

[0043] Next, as shown in Figures 4F and 5B, a second electrode 12 is formed, for example by sputtering, in a surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction. The second electrode 12 is made of, for example, Ti. Finally, a drain electrode 13 is formed on the second main surface 2b of the semiconductor substrate 2. The drain electrode 13 is made of, for example, Ti. This results in a semiconductor device 1 as shown in Figures 1 to 3.

[0044] Figure 6 is a cross-sectional view illustrating a modified example of the first embodiment, and is a cross-sectional view corresponding to the cross-section in Figure 3. As shown in Figure 6, the first electrode 11 only needs to be in Schottky contact with the bottom surface of the recess 8, and does not need to be embedded in the entire space within the recess 8. In Figure 6, the first electrode 11 is embedded in approximately the lower half of the recess 8. In this modified example, after the first electrode 11 is embedded in the recess 8, a part of the second electrode 12 enters the space remaining in the recess 8 and makes contact with the first electrode 11.

[0045] Figure 7 is a schematic plan view of a semiconductor device according to a second embodiment of the present invention. Figure 8 is a cross-sectional view taken along the line VIII-VIII in Figure 7. Figure 9 is a cross-sectional view taken along the line IX-IX in Figure 7. In Figure 7, the configuration above the surface of the semiconductor layer 3 is omitted. In Figures 7, 8, and 9, the parts corresponding to the parts in Figures 1, 2, and 3 described above are denoted by the same reference numerals as in Figures 1, 2, and 3. In the semiconductor device 1A according to the second embodiment, the recess 8 is not formed. Therefore, the first electrode 11 is not embedded in the recess 8, but is formed on the surface of the semiconductor layer 3. The first electrode 11 is in Schottky contact with the surface of the semiconductor layer 3.

[0046] Specifically, the first electrode 11 is positioned in a first electrode formation region 21, which is a part of the region between adjacent gate electrodes 5 on the upper surface of the semiconductor layer 3 (more precisely, the region 7 between the gate insulating film 6 covering adjacent gate electrodes 5). The first electrode 11 is in Schottky contact with the first electrode formation region 21. In this embodiment, the first electrode formation region 21 is formed in the middle of the length of the intervening region 7 (middle in the Y direction). The width (length in the X direction) of the first electrode formation region 21 is equal to the width of the intervening region 7. The first electrode 11 is made of a material that makes Schottky contact with the semiconductor layer 3, such as Ni, Pt, TiN, Mo, or Pb. In this embodiment, the first electrode 11 is made of Ni. The first electrode formation region 21 is an example of the "first region" in the present invention.

[0047] In the region other than the first region 21 on the surface of the semiconductor layer 3, a high-concentration region 3a with a high n-type impurity concentration is formed. The n-type impurity concentration in the high-concentration region 3a is 1 × 10⁻⁶ 17 cm -3 The above 1 x 10 21 cm -3 The following is preferable: The depth of the high-concentration region 3a from the surface of the semiconductor layer 3 is preferably 0.1 μm or more and 0.5 μm or less. A second electrode 12 is formed in a surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B. The second electrode 12 may be formed so as to cover the upper surface of the semiconductor layer 3, the upper surface and side surface of the first electrode 11, and the upper surface of the second gate insulating film 6B in a region of the surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction. The second electrode 12 is in ohmic contact with the upper surface of the semiconductor layer 3 and is also in contact with the upper surface and side surface of the first electrode 11. In other words, the second electrode 12 is electrically connected to the first electrode 11. The region in the intermediate region 7 other than the first electrode formation region 21 in which the second electrode 12 is formed corresponds to the "second region" in the present invention.

[0048] The second electrode 12 is made of a material that makes ohmic contact with the semiconductor layer 3, such as a Ti film, or a Ti / Au multilayer film consisting of a lower Ti film and an upper Au film. In this embodiment, the second electrode 12 is made of a Ti film. The source electrode 10 is composed of the first electrode 11 and the second electrode 12. A gate pad (not shown) may be placed above one end in the Y direction where the second electrode 12 is not formed, within a surface region including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, to which all gate electrodes 5 are electrically connected.

[0049] In this embodiment as well, there is no barrier at the interface between the first electrode 11 and the semiconductor layer 3 that prevents the movement of holes from the semiconductor layer 3 to the first electrode 11. Therefore, when the transistor is turned off, holes that have moved to the source electrode 10 can be extracted by the first electrode 11. This suppresses the accumulation of holes in the semiconductor layer 3, and thus suppresses the occurrence of breakdown voltage drop phenomena, such as a sudden current flow between the drain and source electrodes when the transistor is turned off.

[0050] The manufacturing process of the semiconductor device 1A according to the second embodiment is similar to the manufacturing process of the semiconductor device 1 according to the first embodiment. However, in the process shown in Figure 4B, a high-density region 3a is formed on the surface of the semiconductor layer 3 in a region other than the first electrode formation region 21. Also, in the process shown in Figure 5A, the recess 8 is not formed, and the first electrode 11 is formed on the first electrode formation region 21 on the surface of the semiconductor layer 3. Figure 4F In the process shown in Figure 5B, the second electrode 12 is formed in a region of the surface area including the upper surface of the semiconductor layer 3, the upper surface of the first electrode 11, and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction, so as to cover the upper surface of the semiconductor layer 3, the upper surface and side of the first electrode 11, and the upper surface of the second gate insulating film 6B.

[0051] Figure 10 is a schematic plan view of a semiconductor device according to a third embodiment of the present invention. Figure 11 is a cross-sectional view taken along the line XI-XI in Figure 10. In Figure 10, the configuration above the surface of the semiconductor layer 3 is omitted. In Figures 10 and 11, parts corresponding to parts in Figures 1 and 2 are denoted by the same reference numerals as in Figures 1 and 2. In the semiconductor device 1B according to the third embodiment, unlike the semiconductor device 1 according to the first embodiment, there is no first electrode 11 that makes Schottky contact with the surface of the semiconductor layer 3. Furthermore, the semiconductor device 1B according to the third embodiment is characterized by the materials of the gate electrode 5 and the gate insulating film 6.

[0052] In the semiconductor device 1B according to the third embodiment, a high-concentration region 3a with a high n-type impurity concentration is formed over the entire surface of the semiconductor layer 3. A source electrode 10 is formed in the surface region including the upper surface of the semiconductor layer 3 and the upper surface of the second gate insulating film 6B, making ohmic contact with the upper surface of the semiconductor layer 3 (the surface of the high-concentration region 3a). The source electrode 10 may be formed to cover the upper surface of the semiconductor layer 3 and the upper surface of the second gate insulating film 6B in a region of the surface region including the upper surface of the semiconductor layer 3 and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction. The source electrode 10 is made of a material that makes ohmic contact with the semiconductor layer 3, such as a Ti film or a Ti / Au multilayer film consisting of a lower Ti film and an upper Au film. In this embodiment, the source electrode 10 is made of a Ti film.

[0053] A gate pad (not shown) may be placed above one end in the Y direction where the second electrode 12 is not formed, within a surface region including the upper surface of the semiconductor layer 3 and the upper surface of the second gate insulating film 6B, to which all gate electrodes 5 are electrically connected. In the semiconductor device 1B according to the third embodiment, the gate electrode 5 is made of n-type polysilicon. The gate insulating film 6 (first gate insulating film 6A, second gate insulating film 6B) is made of an AlN film or a SiN film.

[0054] Furthermore, the semiconductor layer 3 is made of an oxide semiconductor such as Ga2O3 or ZnO, similar to the semiconductor device 1 in the third embodiment. In the third embodiment, the semiconductor layer 3 is made of a Ga2O3 layer. Generally, Al2O3 or SiO2 is used as the material for the gate insulating film 6. When the gate insulating film 6 is made of Al2O3 or SiO2, a barrier exists at the interface between the semiconductor layer 3 and the gate insulating film 6 that prevents the movement of holes from the semiconductor layer 3 to the gate insulating film 6. Therefore, when the transistor is off, holes generated in the semiconductor layer 3 cannot escape to the gate electrode 5 via the gate insulating film 6.

[0055] In the third embodiment, since the gate insulating film 6 is composed of an AlN film or a SiN film, there is no barrier at the interface between the semiconductor layer 3 and the gate insulating film 6 that prevents the movement of holes from the semiconductor layer 3 to the gate insulating film 6. Therefore, holes generated in the semiconductor layer 3 when the transistor is off can be released to the gate electrode 5 via the gate insulating film 6. However, if a p-type semiconductor or metal is used as the material for the gate electrode 5, holes will flow from the gate electrode 5 into the semiconductor layer 3 when an on-voltage is applied to the gate electrode 5. In the third embodiment, since the gate electrode 5 is made of n-type polysilicon, it is possible to prevent holes from flowing from the gate electrode 5 into the semiconductor layer 3 when an on-voltage is applied to the gate electrode 5.

[0056] In other words, in the third embodiment, holes generated in the semiconductor layer 3 when the transistor is off can be released to the gate electrode 5 via the gate insulating film 6. This suppresses the accumulation of holes in the semiconductor layer 3, thereby suppressing the occurrence of breakdown voltage drop phenomena, such as a sudden current flow between the drain-source electrodes when the transistor is off. Figures 12A to 12C are cross-sectional views illustrating an example of a manufacturing method for the semiconductor device 1B described above, and are cross-sectional views corresponding to the cross-section in Figure 11.

[0057] When manufacturing semiconductor device 1B, the same process as described above in Figures 4A to 4C is carried out. In this case, the cross-sectional views in Figures 4A to 4C can be considered to be the cross-sectional views corresponding to the cross-section in Figure 11. Once the trench 4 is formed by the process shown in Figure 4C, a first gate insulating film 6A is formed on the side and bottom surfaces of the trench 4, for example, by the ALD method, as shown in Figure 12A. The first gate insulating film 6A is composed of an AlN film or a SiN film. Instead of the ALD method, the PCVD method or sputtering method may be used.

[0058] Next, as shown in Figure 12B, the material for the gate electrode 5 is embedded in the space surrounded by the first gate insulating film 6A within the trench 4. The material for the gate electrode 5 is n-type polysilicon. This forms the gate electrode 5. Then, a second gate insulating film 6B is formed to cover the upper surface of the gate electrode 5. The second gate insulating film 6B is made of the same material as the second gate insulating film 6A. This forms the gate insulating film 6 that covers the sides, bottom, and top surfaces of the gate electrode 5.

[0059] Next, as shown in Figure 12C, the second electrode 12 is formed, for example, by sputtering, in a surface region including the upper surface of the semiconductor layer 3 and the upper surface of the second gate insulating film 6B, excluding one end in the Y direction. The second electrode 12 is made of, for example, Ti. Finally, a drain electrode 13 is formed on the second main surface 2b of the semiconductor substrate 2. The drain electrode 13 is made of, for example, Ti. This yields a semiconductor device 1B as shown in Figures 10 and 11.

[0060] Although the first to third embodiments of this disclosure have been described above, the invention can also be implemented in other embodiments. For example, in the first to third embodiments described above, a high-concentration region 3a with a high n-type impurity concentration is formed in part or all of the surface layer of the semiconductor layer 4, but the high-concentration region 3a does not have to be formed. While embodiments of this disclosure have been described in detail, these are merely examples used to illustrate the technical content of this disclosure, and this disclosure should not be construed as being limited to these examples. The scope of this disclosure is limited only to the attached claims. [Explanation of Symbols]

[0061] 1,1A,1B Semiconductor equipment 2 Semiconductor substrates 2a 1st principal surface 2b 2nd principal surface 3 Semiconductor layer 3a High concentration area 4 Trench 5 gates 6 Gate insulating film 6A First gate insulating film 6B Second gate insulating film 7 interspace area 8 recesses 10 Source electrodes 11 1st electrode 12 2nd electrode 13 Drain electrode 21 First electrode formation area

Claims

1. An n-type semiconductor substrate having a first main surface and a second main surface on the opposite side thereof, An n-type semiconductor layer disposed on the first main surface of the semiconductor substrate, A pair of trenches are formed on the surface of the semiconductor layer opposite to the semiconductor substrate, spaced apart from each other. A pair of gate electrodes embedded in the pair of trenches, A gate insulating film interposed between the gate electrode and the semiconductor layer, A source electrode formed on the surface of the semiconductor layer opposite to the semiconductor substrate, The semiconductor substrate includes a drain electrode formed on the second main surface, The source electrode includes a first electrode that makes Schottky contact with a first region which is a part of the inter-gate region of the pair of gate electrodes on the surface of the semiconductor layer, and a second electrode that makes ohmic contact with a second region in the inter-gate region which is different from the first region. The material of the first electrode and the material of the second electrode are different. A semiconductor device in which the bottom surface of the first electrode that contacts the surface of the semiconductor layer and the bottom surface of the second electrode that contacts the surface of the semiconductor layer are flush.

2. The semiconductor device according to claim 1, wherein a high-concentration region is formed in the surface layer directly beneath the second electrode in the semiconductor layer, where the n-type impurity concentration is higher than that of the n-type impurity concentration in the surface layer directly beneath the first electrode in the semiconductor layer.

3. The semiconductor device according to claim 1 or 2, wherein the first electrode is made of a Ni film, a Pt film, a TiN film, a Mo film, or a Pb film, and the second electrode is made of a laminated film of a Ti film formed on the semiconductor layer and an Au film formed on the Ti film, or a single Ti film.

4. An n-type semiconductor substrate having a first main surface and a second main surface on the opposite side thereof, An n-type semiconductor layer disposed on the first main surface of the semiconductor substrate, A pair of trenches are formed on the surface of the semiconductor layer opposite to the semiconductor substrate, spaced apart from each other. A pair of gate electrodes embedded in the pair of trenches, A gate insulating film interposed between the gate electrode and the semiconductor layer, A source electrode formed on the surface of the semiconductor layer opposite to the semiconductor substrate, The semiconductor substrate includes a drain electrode formed on the second main surface, The gate insulating film is formed on the side and bottom surfaces of the trench and consists of a first gate insulating film that covers the side and bottom surfaces of the gate electrode within the trench and a second gate insulating film that covers the top surface of the gate electrode. The source electrode includes a first electrode that makes Schottky contact with a first region which is a part of the inter-gate insulating film region covering each of the pair of gate electrodes on the surface of the semiconductor layer, and a second electrode that makes ohmic contact with a second region in the inter-gate region which is different from the first region. The pair of trenches are spaced apart in a first direction along the surface of the semiconductor layer and extend in a second direction that is along the surface of the semiconductor layer and perpendicular to the first direction. A recess is formed in the intermediate portion of the second direction length of the intervening region. The first electrode is embedded in the recess, The length of the recess in the first direction is equal to the length of the intervening region in the first direction, and both sides of the recess facing the first direction are formed by the gate insulating film covering each of the pair of gate electrodes. A semiconductor device in which the material of the first electrode and the material of the second electrode are different.

5. The semiconductor device according to claim 4, wherein the depth position of the lower end of the first electrode is deeper than the depth position of the upper surface of the gate electrode and shallower than the depth position of the lower surface of the gate electrode.

6. The semiconductor device according to claim 4, wherein the depth position of the lower end of the first electrode is deeper than the depth position of the upper surface of the gate electrode and shallower than the depth position of the center in the vertical direction of the gate electrode.

7. The semiconductor device according to any one of claims 4 to 6, wherein a high-concentration region is formed in the surface layer directly beneath the second electrode in the semiconductor layer, where the n-type impurity concentration is higher than that of other regions of the semiconductor layer.

8. The n-type impurity concentration in the aforementioned high-concentration region is 1 × 10 １７ cm －３ ~1 x 10 ２１ cm －３ Therefore, the concentration of n-type impurities in regions other than the high-concentration region in the semiconductor layer is 1 × 10 １５ cm －３ ~1 x 10 １８ cm －３ The semiconductor device according to claim 7.

9. The semiconductor device according to any one of claims 4 to 8, wherein the first electrode is made of a Ni film, a Pt film, a TiN film, a Mo film, or a Pb film, and the second electrode is made of a laminated film of a Ti film formed on the semiconductor layer and an Au film formed on the Ti film, or a single Ti film.

Images