Semiconductor wafers, semiconductor equipment, power converters, and cooling systems

Abstract

The purpose of the present invention is to provide a technology that is capable of suppressing the extension of a crack to the lower side of an interlayer insulating film when external stress associated with heat shrinkage stress is applied to a corner of a semiconductor element. A semiconductor wafer (1) is provided with a semiconductor substrate (10) in which an interlayer insulating film (9) and a surface protective film (8) covering the interlayer insulating film (9) are laminated atop the upper surface. A plurality of semiconductor elements (3), which are cut into small pieces by dicing along an opening (2a) formed in the surface protective film (8), are formed on the semiconductor substrate (10). The end of the interlayer insulating film (9) is set further back than the end of the surface protective film (8) in relation to the end of the semiconductor substrate (10) to be formed by dicing. In each of the diced semiconductor elements (3), the shape of the end of the interlayer insulating film (9) is set so that the distance Lx from the corner of the semiconductor substrate (10) to be formed by dicing to the end of the interlayer insulating film (9) and the thickness d of the semiconductor substrate (10) satisfy a relationship defined in expression 1.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor wafer, a semiconductor device, a power conversion device, and a cooling system.

Background Art

[0002] Patent Document 1 discloses a structure in which a surface protection film is formed so as to overlap and cover an interlayer insulating film on a semiconductor wafer and an interlayer film thereon. For example, in this structure, the length from the end of the semiconductor element excluding the width of the opening of the surface protection film of 80 μm and the groove of the scribe line of 50 μm to the surface protection film is 30 μm / 2 = 15 μm, and the thickness of the product is 180 μm.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the technique described in Patent Document 1, since the length from the end of the semiconductor element to the surface protection film is as short as about 15 μm, an external stress associated with thermal shrinkage stress is applied to the end of the semiconductor element, resulting in a problem that cracks are likely to occur from the surface protection film to the lower side of the interlayer insulating film. When the crack extends to the lower side of the interlayer insulating film, the breakdown voltage of the semiconductor element decreases, so the length of the crack becomes important. Among the ends of the semiconductor element, the external stress associated with thermal shrinkage stress becomes large at the four corners, so the breakdown voltage of the semiconductor element is likely to decrease when the crack extends to the lower side of the interlayer insulating film.

[0005] Furthermore, such semiconductor elements are mounted in power modules. For example, power modules in power converters installed in vehicles have a wider operating temperature range (e.g., between -40°C and 150°C) compared to power modules used indoors, and are used in harsh heat cycle environments. Also, in low-temperature environments, torque is applied to the motor during startup, causing the temperature of the entire drive equipment to rise rapidly. This has led to problems such as delamination between the sealing resin and the semiconductor element in the power module, resulting in dielectric breakdown of the semiconductor element.

[0006] Therefore, the present disclosure aims to provide a technology that can suppress the propagation of cracks to the underside of the interlayer insulating film when external stress due to thermal contraction stress is applied to the corners of a semiconductor device. [Means for solving the problem]

[0007] The semiconductor wafer according to this disclosure comprises a semiconductor substrate on which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on the upper surface, and a plurality of semiconductor elements that are divided into small pieces by dicing along an opening formed in the surface protective film are formed on the semiconductor wafer, wherein the edge of the interlayer insulating film is set back from the edge of the surface protective film with respect to the edge of the semiconductor substrate to be formed by dicing, and the shape of the edge of the interlayer insulating film is set such that the distance Lx from the corner of the semiconductor substrate to be formed by dicing to the edge of the interlayer insulating film and the thickness d of the semiconductor substrate satisfy the relationship in Equation 1 for each of the semiconductor elements after dicing. Furthermore, the thickness d of the semiconductor substrate is 100 μm or more. ru. [Effects of the Invention]

[0008] According to this disclosure, since the distance Lx from the corner of the semiconductor substrate to the edge of the interlayer insulating film is increased, it is possible to suppress the propagation of cracks to the underside of the interlayer insulating film when external stress due to thermal contraction stress is applied to the corner of the semiconductor device.

[0009] The purpose, features, aspects, and benefits of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0010] [Figure 1] This is a top view of a semiconductor wafer according to Embodiment 1. [Figure 2] These are a top view and a cross-sectional view of the corner portion of a semiconductor element to be formed by dicing in a semiconductor wafer according to Embodiment 1. [Figure 3] This graph shows the relationship between the length of cracks originating from the corners of a semiconductor device and the thickness of the semiconductor device when external stress due to thermal contraction stress is applied to the corners of the semiconductor device. [Figure 4] This is a cross-sectional view of a corner portion of a semiconductor element to be formed by dicing in a semiconductor wafer according to Embodiment 3. [Figure 5] This is a cross-sectional view of a corner portion of a semiconductor element to be formed by dicing in a semiconductor wafer according to Embodiment 4. [Figure 6] This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 5 is applied. [Figure 7] This is a block diagram showing the configuration of the cooling system according to Embodiment 6. [Modes for carrying out the invention]

[0011] <Embodiment 1> Embodiment 1 will be described below with reference to the drawings. Figure 1 is a top view of a semiconductor wafer 1 according to Embodiment 1. Figure 2(a) is a top view of the corner of a semiconductor element 3 to be formed by dicing in the semiconductor wafer 1 according to Embodiment 1. Figure 2(b) is a cross-sectional view of the corner of a semiconductor element 3 to be formed by dicing in the semiconductor wafer 1 according to Embodiment 1.

[0012] As shown in FIG. 1, the semiconductor wafer 1 is formed in a disc shape. In a region of the semiconductor wafer 1 excluding the peripheral portion, a plurality of semiconductor elements 3 to be diced into small pieces are formed. Further, in a region of the semiconductor wafer 1 excluding the peripheral portion, a plurality of dicing lines 2 for dividing into a plurality of semiconductor elements 3 are formed in a direction intersecting each other. Each semiconductor element 3 obtained from the semiconductor wafer 1 is mounted on a semiconductor device (power module) through known processes.

[0013] As shown in FIGS. 2(a) and (b), the semiconductor wafer 1 includes a semiconductor substrate 10, an interlayer insulating film 9, and a surface protection film 8.

[0014] The semiconductor substrate 10 is formed in a disc shape. The base material of the semiconductor substrate 10 is SiC. Note that the base material of the semiconductor substrate 10 may be Si or GaN. An interlayer insulating film 9 and a surface protection film 8 are laminated on the upper surface of the semiconductor substrate 10.

[0015] [[ID=!12]]The interlayer insulating film 9 is, for example, a TEOS film and covers the upper surface of the semiconductor substrate 10. Specifically, the interlayer insulating film 9 is provided in a region excluding the peripheral portion of the semiconductor element 3 to be formed by dicing, and portions corresponding to the four corners of the semiconductor element 3 in the interlayer insulating film 9 are formed in a curved shape with rounded corners in a top view.

[0016] The surface protection film 8 is, for example, polyimide and is provided to cover the interlayer insulating film 9 from above. The dicing line 2 is formed by an opening 2a that opens upward. The end of the interlayer insulating film 9 retreats from the end of the surface protection film 8 with respect to the end of the semiconductor substrate 10 to be formed by dicing. That is, the surface protection film 8 covers the entire interlayer insulating film 9. Note that the arrow in FIG. 2(b) indicates the direction in which cracks extend

[0017] It should be noted that in the translation of the content you provided, there may be some professional terms that need to be further verified according to the specific context of semiconductor technology. If you have any questions, please feel free to let me know. Also, there seems to be an incorrect tag "!12" in your original text, which I have translated as "12" as is, but you may need to check its accuracy.In Embodiment 1, when an external stress due to thermal contraction stress is applied to the corner of the semiconductor element 3, in order to suppress the crack from extending to the lower side of the interlayer insulating film 9, in each semiconductor element 3 after dicing, the distance Lx from the corner of the semiconductor substrate 10 to be formed by dicing to the end of the interlayer insulating film 9 and the thickness d of the semiconductor substrate 10 satisfy the relationship of Equation (1), and the shape of the end of the interlayer insulating film 9 is set.

[0018] [Equation]

[0019] Hereinafter, the reason why the effect that the crack can be suppressed from extending to the lower side of the interlayer insulating film 9 when an external stress due to thermal contraction stress is applied to the corner of the semiconductor element 3 can be obtained by setting the shape of the end of the interlayer insulating film 9 to satisfy the relationship of Equation (1) will be described. FIG. 3 is a graph showing the relationship between the crack length D from the corner of the semiconductor element 3 and the thickness d of the semiconductor element 3 when an external stress due to thermal contraction stress is applied to the corner of the semiconductor element 3.

[0020] As the thickness d of the semiconductor element 3 increases, the thermal contraction stress on the semiconductor element 3 increases, so that an external stress is likely to be applied. The location where the external stress is highest is the corner of the semiconductor element 3, and cracks are likely to occur at that location. Therefore, as the thickness d of the semiconductor substrate 10 (hereinafter also referred to as "thickness d") increases, measures against cracks are required. Specifically, by increasing the length of the distance Lx (hereinafter also referred to as "distance Lx") from the corner of the semiconductor substrate 10 to the end of the interlayer insulating film 9, even if a crack occurs, it is difficult for the crack to extend to the end of the interlayer insulating film 9. Therefore, as the thickness d increases, it is necessary to increase the distance Lx. The inventor of the present application conducted experiments using semiconductor elements 3 with different thicknesses d and found that the relationship between the distance Lx and the thickness d is represented by a linear relational expression of Equation (1).

[0021] Figure 3 shows the relationship between the length D of cracks from the corners of semiconductor elements 3 and the thickness d, using data from evaluating semiconductor elements 3 with different thicknesses d. As shown in Figure 3, the crack length D is longer for the semiconductor element 3 with d = 300 μm than for the semiconductor element 3 with d = 100 μm, and this relationship can be expressed by the linear relationship given by Equation 1. When the distance Lx is longer than the crack length D, the crack does not extend to the edge of the interlayer insulating film 9, and thus the above effect is obtained by satisfying Equation 1.

[0022] Here, the thickness d is, for example, about 100 μm, and the distance Lx is, for example, about 300 μm. The interlayer insulating film 9 is completely covered to its edges by the surface protective film 8, and the width over which the interlayer insulating film 9 is covered by the surface protective film 8 is, for example, about 1 / 3 of the distance Lx.

[0023] As described above, the semiconductor wafer 1 according to Embodiment 1 comprises a semiconductor substrate 10 on which an interlayer insulating film 9 and a surface protective film 8 covering the interlayer insulating film 9 are laminated on the upper surface, and a plurality of semiconductor elements 3 are formed on the semiconductor substrate 10, which are to be divided into small pieces by dicing along an opening 2a formed in the surface protective film 8. The edge of the interlayer insulating film 9 is set back from the edge of the surface protective film 8 relative to the edge of the semiconductor substrate 10 to be formed by dicing, and the shape of the edge of the interlayer insulating film 9 is set such that, in each semiconductor element 3 after dicing, the distance Lx from the corner of the semiconductor substrate 10 to be formed by dicing to the edge of the interlayer insulating film 9 and the thickness d of the semiconductor substrate 10 satisfy the relationship in Equation 1.

[0024] Therefore, the distance Lx from the corner of the semiconductor substrate 10 to the edge of the interlayer insulating film 9 becomes longer, which suppresses the propagation of cracks to the underside of the interlayer insulating film 9 when external stress due to thermal contraction stress is applied to the corner of the semiconductor element 3. As a result, the durability of the semiconductor device equipped with the semiconductor element 3 obtained from the semiconductor wafer 1 is improved.

[0025] <Embodiment 2> Next, the semiconductor wafer 1 according to Embodiment 2 will be described. In Embodiment 2, the same reference numerals are used for components that are the same as those described in Embodiment 1, and their descriptions are omitted.

[0026] The distance Lx is affected by the finish of the dicing line 2, which is the degree to which the width W and kerf width C of the dicing line are removed. Therefore, in order to set the shape of the end of the interlayer insulating film 9 with high precision, it is necessary to consider the finish of the dicing line 2. Accordingly, in Embodiment 2, in order to take into account the finish of the dicing line 2, the shape of the end of the interlayer insulating film 9 is set to satisfy the relationship shown in Equation 2 below, in addition to Equation 1.

[0027] The shape of the edge of the interlayer insulating film 9 is set such that the width W of the dicing line 2, the kerf width C which is the width of the dicing line 2 that is removed by dicing, the width L from the edge of the surface protective film 8 to the edge of the interlayer insulating film 9 in each semiconductor element 3, the curvature R of the interlayer insulating film 9 at the corner of the semiconductor element 3, and the distance Lx satisfy the relationship in Equation 2.

[0028]

number

[0029] The derivation of equation 2 will be explained using Figure 2. As shown in Figure 2, the diagonal length of a square with side length R + L + (WC) / 2 is Lx + R. The diagonal length of this square can be expressed by the equation Lx + R = R + L + (WC) / 2) × √2. Equation 2 can be obtained from this equation.

[0030] Here, the width W of the dicing line 2 is, for example, about 150 μm, and the kerf width C is, for example, about 50 μm. Also, in each semiconductor element 3, the width L from the edge of the surface protective film 8 to the edge of the interlayer insulating film 9 is, for example, about 80 μm, and the curvature R of the interlayer insulating film 9 is, for example, about 500 μm. As a result, the distance Lx is, for example, 391 μm. In addition to the relationship in Equation 1, setting the shape of the edge of the interlayer insulating film 9 so as to satisfy the relationship in Equation 2 is also applicable in the cases of Embodiments 3 and 4 below.

[0031] As described above, in the semiconductor wafer 1 according to Embodiment 2, the shape of the edges of the interlayer insulating film 9 is set to satisfy not only the relationship in Equation 1 but also the relationship in Equation 2. Therefore, by considering the finish of the dicing line 2, the shape of the edges of the interlayer insulating film 9 can be set with high precision. This further improves the effect of suppressing the propagation of cracks to the underside of the interlayer insulating film 9 when external stress due to thermal shrinkage stress is applied to the corners of the semiconductor element 3.

[0032] <Embodiment 3> Next, a semiconductor wafer 1A according to Embodiment 3 will be described. Figure 4 is a cross-sectional view of the corner of a semiconductor element 3A to be formed by dicing in the semiconductor wafer 1A according to Embodiment 3. In Embodiment 3, the same reference numerals are used for components that are the same as those described in Embodiments 1 and 2, and their descriptions are omitted.

[0033] As shown in Figure 4, in Embodiment 3, an AlSi film 14 is placed on the outer circumferential surface of the end of the interlayer insulating film 9 so as to cover the end of the interlayer insulating film 9 in each semiconductor element 3A. The AlSi film 14 is placed so as to cover the entire outer circumferential surface of the end of the interlayer insulating film 9 and functions as a buffer against cracks extending from the corners of the semiconductor element 3A. Note that the AlSi film 14 is not only placed on the outer circumferential surface of the end of the interlayer insulating film 9, but may also extend from the end of the interlayer insulating film 9 onto the upper surface of the interlayer insulating film 9.

[0034] As described above, in the semiconductor wafer 1A according to Embodiment 3, an AlSi film 14 is arranged on the outer circumferential surface of the edge of the interlayer insulating film 9 so as to cover the edge of the interlayer insulating film 9 in each semiconductor element 3A. Therefore, since the AlSi film 14 functions as a buffer against cracks extending from the corners of the semiconductor element 3A, the effect of suppressing the extension of cracks to the underside of the interlayer insulating film 9 when external stress due to thermal contraction stress is applied to the corners of the semiconductor element 3 can be further improved.

[0035] <Embodiment 4> Next, a semiconductor wafer 1B according to Embodiment 4 will be described. Figure 5 is a cross-sectional view of the corner of a semiconductor element 3B to be formed by dicing in the semiconductor wafer 1B according to Embodiment 4. In Embodiment 4, the same reference numerals are used for components that are the same as those described in Embodiments 1 to 3, and their descriptions are omitted.

[0036] As shown in Figure 5, in Embodiment 4, the AlSi film 14 is formed to be thicker than the interlayer insulating film 9 and is arranged in each semiconductor element 3B from the outer peripheral surface of the end of the interlayer insulating film 9 to the edge of the semiconductor substrate 10 to be formed by dicing. The AlSi film 14 is arranged to cover the entire outer peripheral surface of the end of the interlayer insulating film 9 and the surrounding upper surface portion, and functions as a buffer against cracks extending from the corners of the semiconductor element 3A.

[0037] If the AlSi film 14 is not placed between the semiconductor substrate 10 and the surface protective film 8, external stress is applied to the contact point between the semiconductor substrate 10 and the surface protective film 8. In contrast, in Embodiment 4, the AlSi film 14 is placed in each semiconductor element 3B from the edge of the interlayer insulating film 9 to the edge of the semiconductor substrate 10 to be formed by dicing. In other words, because the AlSi film 14 is placed from the edge of the interlayer insulating film 9 to the edge of the semiconductor element 3B, external stress is applied to the contact point between the edge of the surface protective film 8, which is laminated to cover the interlayer insulating film 9, and the AlSi film 14, which is placed from the edge of the interlayer insulating film 9 to the edge of the semiconductor element 3A. Since the coefficient of linear expansion of the AlSi film 14 is larger than that of the semiconductor substrate 10, the external stress applied to this contact point is more easily relieved.

[0038] As described above, in the semiconductor wafer 1B according to Embodiment 4, when external stress due to thermal shrinkage stress is applied to the corners of the semiconductor element 3, the effect of suppressing crack propagation to the underside of the interlayer insulating film 9 can be further improved compared to the case of Embodiment 3.

[0039] <Embodiment 5> This embodiment applies the semiconductor devices described in Embodiments 1 to 4 above to a power converter. The application of the semiconductor devices described in Embodiments 1 to 4 is not limited to a specific power converter, but below, Embodiment 5 will describe the case in which the semiconductor devices described in Embodiments 1 to 4 are applied to a three-phase inverter.

[0040] Figure 6 is a block diagram showing the configuration of a power conversion system to which the power conversion device 16 according to Embodiment 5 is applied.

[0041] The power conversion system shown in Figure 6 consists of a power source 15, a power converter 16, and a load 18. The power source 15 is a DC power source and supplies DC power to the power converter 16. The power source 15 can be made up of various components, for example, a DC grid, a solar cell, or a battery, or it may be made up of a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power source 15 may be made up of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0042] The power converter 16 is a three-phase inverter connected between the power supply 15 and the load 18. It converts the DC power supplied from the power supply 15 into AC power and supplies AC power to the load 18. As shown in Figure 6, the power converter 16 includes a main conversion circuit 17 that converts DC power into AC power and outputs it, a drive circuit 19 that outputs drive signals to drive each switching element of the main conversion circuit 17, and a control circuit 20 that outputs control signals to the drive circuit 19 to control the drive circuit 19.

[0043] Load 18 is a three-phase motor driven by AC power supplied from power converter 16. Note that load 18 is not limited to a specific application; it is a motor mounted in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0044] The details of the power conversion device 16 are described below. The main conversion circuit 17 includes switching elements (not shown) and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power supply 15 into AC power and supplies it to the load 18. There are various specific circuit configurations for the main conversion circuit 17, but the main conversion circuit 17 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. At least one of the switching elements and freewheeling diodes of the main conversion circuit 17 is a semiconductor device according to any of the embodiments 1 to 4 described above. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 17, are connected to the load 18.

[0045] The drive circuit 19 generates drive signals to drive the switching elements of the main conversion circuit 17 and supplies them to the control electrodes of the switching elements of the main conversion circuit 17. Specifically, according to the control signal from the control circuit 20 described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than or equal to the threshold voltage of the switching elements.

[0046] The control circuit 20 controls the switching elements of the main converter circuit 17 so that the desired power is supplied to the load 18. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 17 should be in the ON state based on the power to be supplied to the load 18. For example, the main converter circuit 17 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 20 then outputs a control command (control signal) to the drive circuit 19 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 19 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0047] In the power conversion device according to this embodiment, since the semiconductor devices according to embodiments 1 to 4 are used as switching elements in the main conversion circuit 17, improved durability can be achieved.

[0048] In this embodiment, an example of applying the semiconductor devices according to Embodiments 1 to 4 to a two-level three-phase inverter has been described. However, the application of the semiconductor devices according to Embodiments 1 to 4 is not limited to this, and they can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. Furthermore, when supplying power to a single-phase load, the semiconductor devices according to Embodiments 1 to 4 may be applied to a single-phase inverter. In addition, when supplying power to a DC load, it is also possible to apply the semiconductor devices according to Embodiments 1 to 4 to a DC / DC converter or an AC / DC converter.

[0049] Furthermore, the power conversion device using the semiconductor device according to Embodiments 1 to 4 is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply for electrical discharge machining equipment, laser processing equipment, induction heating cookers, or contactless power supply systems, and can even be used as a power conditioner for solar power generation systems or energy storage systems.

[0050] <Embodiment 6> Next, the cooling system 26 according to Embodiment 6 will be described. Figure 7 is a block diagram showing the configuration of the cooling system 26 according to Embodiment 6.

[0051] For example, power modules (semiconductor devices) used in power conversion devices installed in vehicles have a wider operating temperature range (e.g., from -40°C to 150°C) compared to power modules used indoors, and are used in harsh thermal cycling environments.

[0052] Furthermore, in low-temperature environments, torque is applied to the motor during startup, causing the temperature of the entire drive system to rise rapidly. For example, in winter when snow is present, high torque is required, placing a high load on the drive system. This has led to problems such as delamination between the sealing resin and semiconductor elements in the power module, resulting in dielectric breakdown of the semiconductor elements. Embodiment 6 was implemented to solve these problems and will be described in detail below.

[0053] As shown in Figure 7, the cooling system 26 includes a radiator 21, a pump 22, a battery cooling device 23, a flow rate regulator 24, a refrigerant flow path 25, and a PCU cooling device 27.

[0054] The cooling system 26 has a radiator (heat exchanger) 21 to which devices for cooling a PCU (not shown) and a battery (not shown) are connected in parallel via a refrigerant flow path 25. The refrigerant flowing through the refrigerant flow path 25 flows in the direction F shown in the figure when the pump 22 is operated. The refrigerant that has passed through the radiator 21 may have a flow rate control device 24 at the branching point where it branches off to the battery cooling device 23 and the PCU. The battery cooling device 23 and the PCU cooling device 27 may be connected in series with respect to the radiator 21.

[0055] This suppresses cracking between the sealing resin (not shown) and the semiconductor element 3 (see Figure 1) in the semiconductor device, thereby reducing the cooling load on the PCU cooling device 27 and allowing more cooling capacity to be distributed to the battery. By improving the cooling performance of the battery, the vehicle's driving range can be further extended. Furthermore, the size of the PCU cooling device 27 for cooling the PCU equipped with the semiconductor device can be reduced. Consequently, space inside the vehicle can be used more effectively.

[0056] Although this disclosure has been described in detail, the above description is illustrative and not limiting in all respects. It is understood that countless variations not illustrated are conceivable.

[0057] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate. [Explanation of symbols]

[0058] 1 Semiconductor wafer, 2a Aperture, 3, 3A, 3B Semiconductor elements, 8 Surface protective film, 9 Interlayer insulating film, 10 Semiconductor substrate, 14 AlSi film, 16 Power converter, 17 Main converter circuit, 19 Drive circuit, 20 Control circuit, 21 Radiator, 23 Battery cooling device, 25 Refrigerant flow path, 26 Cooling system, 27 PCU cooling device.

Claims

1. A semiconductor wafer comprising a semiconductor substrate on which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on the upper surface, wherein a plurality of semiconductor elements are formed on the semiconductor substrate, which are divided into small pieces by dicing along an opening formed in the surface protective film, The edges of the interlayer insulating film are set back from the edges of the surface protective film relative to the edges of the semiconductor substrate to be formed by dicing. In each of the semiconductor elements after dicing, the distance Lx from the corner of the semiconductor substrate to be formed by dicing to the edge of the interlayer insulating film and the thickness d of the semiconductor substrate are: 【Number 1】 The shape of the end of the interlayer insulating film is set to satisfy the following relationship: The thickness d of the semiconductor substrate is 100 μm or more. Semiconductor wafer.

2. At the corners of each semiconductor element, the interlayer insulating film is formed in a curved shape when viewed from above. The width W of the dicing line, the kerf width C which is the width of the dicing line removed by the dicing, the width L from the edge of the surface protective film to the edge of the interlayer insulating film in each semiconductor element, the curvature R of the interlayer insulating film at the corner of the semiconductor element, and the distance Lx are, [Math 2] The semiconductor wafer according to claim 1, wherein the shape of the end of the interlayer insulating film is set to satisfy the following relationship.

3. The semiconductor wafer according to claim 1 or claim 2, wherein in each of the semiconductor elements, an AlSi film is disposed on the outer peripheral surface of the end of the interlayer insulating film so as to cover the end of the interlayer insulating film.

4. The semiconductor wafer according to claim 3, wherein the AlSi film is formed to be thicker than the interlayer insulating film and is arranged in each semiconductor element from the outer peripheral surface of the end of the interlayer insulating film to the end of the semiconductor substrate to be formed by dicing.

5. A semiconductor device comprising the semiconductor element obtained from the semiconductor wafer according to claim 1 or claim 2.

6. A semiconductor element comprising a semiconductor substrate on which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on the upper surface, The end of the interlayer insulating film is set back from the end of the surface protective film relative to the end of the semiconductor substrate, which is the end of the semiconductor element. In the semiconductor device described above, the distance Lx from the corner of the semiconductor substrate to the edge of the interlayer insulating film and the thickness d of the semiconductor substrate are, [Math 3] The shape of the end of the interlayer insulating film is set to satisfy the following relationship: The thickness d of the semiconductor substrate is 100 μm or more. Semiconductor equipment.

7. The semiconductor device according to claim 6, wherein an AlSi film is disposed on the outer peripheral surface of the end of the interlayer insulating film so as to cover the end of the interlayer insulating film in the semiconductor device.

8. The semiconductor device according to claim 7, wherein the AlSi film is formed to be thicker than the interlayer insulating film and is arranged in the semiconductor device from the outer peripheral surface of the end of the interlayer insulating film to the end of the semiconductor substrate.

9. A semiconductor device according to claim 5, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with this device.

10. A PCU including the semiconductor device described in claim 5, A radiator that cools the refrigerant, A battery that supplies power to the aforementioned PCU, A battery cooling device that cools the battery with the aforementioned refrigerant, A PCU cooling device that cools the PCU with the aforementioned refrigerant, A refrigerant flow path through which the aforementioned refrigerant flows, A cooling system equipped with a cooling system.

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