Gate driver with temperature monitoring function

Abstract

To provide a galvanically isolated gate driver for a power transistor, and a power switching system including the same.SOLUTION: In a power switching system, a gate driver 300 includes: a gate-driver temperature sensor 310 configured to measure a gate-driver temperature TGD; a gate-driver temperature sense circuit 400 configured to receive a signal (e.g., voltage) corresponding to the gate-driver temperature and output an internal fault signal based on the gated driver temperature; a transistor temperature sense circuit 510 configured to receive a transistor temperature from a transistor temperature sensor 330; and a transistor temperature monitor circuit 520. The transistor temperature sense circuit is configured to output an external fault signal based on the transistor temperature. The transistor temperature monitor circuit 520 is configured to output an external monitor signal based on the transistor temperature.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 219,876, filed on 9 July 2021.

[0002] (Field of invention) This disclosure relates to a power switching system, and more specifically to an isolated gate driver having a circuit for monitoring and transmitting temperature. [Background technology]

[0003] A gate driver is an integrated circuit configured to convert low-voltage (LV) switching signals into high-voltage (HV) signals suitable for driving power transistors ON / OFF. Some systems (e.g., automotive systems, computer systems) require monitoring of thermal conditions to protect against failures that could lead to damage. [Overview of the project]

[0004] In some embodiments, the technology described herein relates to a power switching system comprising: a power transistor and a switch module including a transistor temperature sensor configured to measure the transistor temperature of the power transistor; a gate driver coupled to the switch module, comprising: a gate driver temperature sensor configured to measure the gate driver temperature of the gate driver; a gate driver temperature sense circuit configured to output an internal fault signal based on the gate driver temperature; a transistor temperature sense circuit configured to receive the transistor temperature from the transistor temperature sensor and output an external fault signal based on the transistor temperature; and a transceiver configured to transmit a combined signal corresponding to the internal fault signal and the external fault signal across the isolation barrier of the gate driver via a shared communication channel.

[0005] In some embodiments, the technology described herein relates to a power switching system in which a transceiver is configured to transmit a composite signal to the low-voltage side of a gate driver via a shared communication channel, the composite signal comprising a first pulse train signal corresponding to an internal fault signal and a second pulse train signal corresponding to an external fault signal; output a ready signal on the ready pin of the gate driver, the ready signal corresponding to the first pulse train signal; and output a detected temperature fault signal on the temperature fault pin of the gate driver, the detected temperature fault signal corresponding to the second pulse train signal.

[0006] In some embodiments, the technology described herein relates to a power switching system in which a gate driver temperature sensing circuit includes a comparator, the comparator configured to receive a voltage from a gate driver temperature sensor on a first input and a thermal shutdown threshold voltage on a second input, the comparator further configured to output an internal fault signal, the internal fault signal being at a normal level when there is no thermal fault in the gate driver.

[0007] In some embodiments, the technology described herein relates to a power switching system in which a transistor temperature sensing circuit includes a comparator, the comparator configured to receive a voltage from a transistor temperature sensor at a first input and a fault threshold voltage at a second input, the comparator further configured to output an external fault signal, the external fault signal being at a fault level when a thermal fault is present in the power transistor.

[0008] In some embodiments, the technology described herein relates to a power switching system comprising: a transceiver comprising a ready encoder configured to generate a first pulse train signal while an internal fault signal is at a normal level and not otherwise; and a temperature fault encoder configured to generate a second pulse train signal while a transistor temperature is at a fault level and not otherwise, wherein the first pulse train signal has a lower bandwidth than the second pulse train signal and the second pulse train signal has a higher bandwidth than the first pulse train signal; and a multiplexer configured to combine the output of the ready encoder and the output of the temperature fault encoder to generate a composite signal and transmit the composite signal to the high-voltage side of a transformer.

[0009] In some embodiments, the technology described herein relates to a power switching system, the transceiver further comprising a ready decoder, which is configured to receive a composite signal from the low-voltage side of a transformer, and includes a filter configured to separate the first pulse train signal from the composite signal based on a lower bandwidth of the first pulse train signal, and a pulse detector configured to detect pulses in the first pulse train signal and output a ready signal at a ready level while pulses of the first pulse train signal are detected.

[0010] In some embodiments, the technology described herein relates to a power switching system wherein a pulse detector is further configured to output a ready signal at a non-ready level after no multiple pulses of a first pulse train signal have been detected.

[0011] In some embodiments, the technology described herein relates to a power switching system, the transceiver further comprising a temperature fault decoder configured to receive a composite signal from the low-voltage side of a transformer, the temperature fault decoder comprising a frequency detector configured to detect a higher bandwidth of a second pulse train signal and to detect a fault signal at a fault level while the second pulse train signal is detected in the composite signal.

[0012] In some embodiments, the technology described herein relates to a power switching system wherein a frequency detector is further configured to output a fault signal at a non-fault level while a second pulse train signal is not detected in the combined signal.

[0013] In some embodiments, the technology described herein relates to a power switching system comprising: a transistor temperature sensor is a first transistor temperature sensor configured to measure a first transistor temperature of a power transistor; a switch module further includes a second transistor temperature sensor configured to measure a second transistor temperature of a power transistor; a transistor temperature sense circuit is a first temperature sense circuit configured to receive a first transistor temperature from the first transistor temperature sensor and output a first signal based on the first transistor temperature; a gate driver is a second temperature sense circuit configured to receive a second transistor temperature from the second transistor temperature sensor and output a second signal based on the second transistor temperature; and a logic gate configured to receive a first signal and a second signal and output an external fault signal, wherein the external fault signal has a level corresponding to a thermal fault when either the first signal or the second signal has a level corresponding to a thermal fault of the power transistor.

[0014] In some embodiments, the technology described herein relates to a power switching system, wherein the gate driver transceiver is a first transceiver, the gate driver further comprises a transistor temperature monitoring circuit configured to output an external monitoring signal by comparing the transistor temperature with a ramp signal, the external monitoring signal being pulse-width modulated (PWM) according to the transistor temperature, and a second transceiver configured to transmit the external monitoring signal across the isolation barrier of the gate driver via a dedicated communication channel.

[0015] In some embodiments, the technology described herein relates to a power switching system, wherein the second transceiver further includes an inverter configured to invert an external monitoring signal to a relatively lower level for a longer period of time than the external monitoring signal is at a relatively high level, while the transistor temperature of the power transistor is within the normal temperature range of the power transistor, in order to reduce the power consumed by the second transceiver.

[0016] In some embodiments, the technology described herein relates to a power switching system, wherein a gate driver is coupled to a transistor temperature sensor by a first temperature sense pin, and the gate driver further includes a second temperature sense pin and a deactivation circuit configured to deactivate the second temperature sense pin when the second temperature sense pin is not coupled to the second temperature sensor in order to reduce the power consumed by the gate driver.

[0017] In some embodiments, the technique described herein is a method for monitoring the thermal state in a power switching system, comprising: receiving the transistor temperature of a power transistor at a sense pin of a gate driver; comparing the transistor temperature with a fault threshold and generating an external fault signal based on the comparison; measuring the gate driver temperature by a gate driver sensor of the gate driver; comparing the gate driver temperature with a thermal shutdown threshold and generating an internal fault signal based on the comparison; generating a first pulse train signal based on the internal fault signal; generating a second pulse train signal based on the external fault signal; combining the first pulse train signal and the second pulse train signal to generate a composite signal; and transmitting the composite signal across the isolation barrier of the gate driver via a shared communication channel.

[0018] In some embodiments, the technique described herein further includes decoding a composite signal based on a first pulse train signal to generate a ready signal, and decoding the composite signal based on a second pulse train signal to generate a detected temperature fault signal, wherein the ready signal corresponds to a thermal fault state of the gate driver temperature, and the detected temperature fault signal corresponds to a thermal fault state of the power transistor.

[0019] In some embodiments, the technique described herein further includes generating an external monitoring signal by comparing the transistor temperature with a ramp signal, wherein the external monitoring signal is pulse-width modulated (PWM) according to the transistor temperature, and transmitting the external monitoring signal across the isolation barrier of the gate driver via a dedicated communication channel.

[0020] In some embodiments, the techniques described herein include a method for transmitting an external monitoring signal over a dedicated communication channel, which involves inverting the external monitoring signal to reduce the power consumed for transmitting the external monitoring signal across the isolation barrier of a gate driver.

[0021] In some aspects, the technology described herein relates to a gate driver including a temperature detection and monitoring circuit that includes a gate driver temperature sensor configured to measure the gate driver temperature of the gate driver, a gate driver temperature sense circuit configured to output an internal fault signal based on the gate driver temperature, a transistor temperature sense circuit coupled to the gate driver that receives the transistor temperature from a transistor temperature sensor and is configured to output an external fault signal based on the transistor temperature, and a transceiver configured to transmit a composite signal corresponding to the internal fault signal and the external fault signal across a separation barrier of the gate driver via a shared communication channel.

[0022] In some aspects, the technology described herein relates to a gate driver in which the transceiver is configured to transmit, via a shared communication channel, to the low voltage side of the gate driver, a composite signal including a first pulse train signal corresponding to the internal fault signal and a second pulse train signal corresponding to the external fault signal; output, at a ready pin of the gate driver, a ready signal corresponding to the first pulse train signal; and output, at a temperature fault pin of the gate driver, a detected temperature fault signal corresponding to the second pulse train signal.

[0023] In some aspects, the technology described herein relates to a gate driver, further including a transistor temperature monitoring circuit configured to generate a pulse width modulation signal corresponding to the transistor temperature and transmitted to the low voltage side of the gate driver via a dedicated communication channel.

[0024] The foregoing exemplary summary, other exemplary objects and / or advantages of the present disclosure, and the manner in which they are achieved, are further described in the following detailed description and its accompanying drawings.

Brief Description of the Drawings

[0025] [Figure 1] This is a block diagram illustrating a power switching system in one possible implementation configuration of the disclosure. [Figure 2] This is a flowchart of a method for monitoring the thermal state in a power switching system in one possible implementation of the present disclosure. [Figure 3] This is a block diagram schematically showing the circuit of a power switching system in one possible implementation form of the disclosure. [Figure 4] This is a schematic diagram of a gate driver temperature sensing circuit in one possible implementation form of the present disclosure. [Figure 5] This is a schematic diagram showing a transistor temperature detection and monitoring circuit according to one implementation form of the present disclosure. [Figure 6] The present disclosure shows signals from a transistor temperature sensing circuit and a transistor temperature monitoring circuit for the first and second temperature sense inputs of a gate driver, according to one possible implementation. [Figure 7] This disclosure shows a partial block diagram of the high-voltage side of a gate driver for a power switching system in one possible implementation configuration. [Figure 8] This disclosure shows a partial block diagram of the low-voltage side of a gate driver for a power switching system in one possible implementation configuration. [Figure 9] This is a schematic diagram of a disabling circuit for a temperature sense pin of a gate driver in one possible implementation of the present disclosure.

[0026] The components of a drawing are not necessarily scaled to each other. Across multiple drawings, the same reference number indicates the corresponding part. [Modes for carrying out the invention]

[0027] High-current switching can be achieved using power transistors. Power transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). Power transistors can be manufactured using silicon (Si) or silicon carbide (SiC) processes. In high-voltage (HV) circuits, power transistors may be configured to conduct current in the ON state or to interrupt current in the OFF state. The state of a power transistor may be set by a gate driver coupled to the power transistor's control terminal (e.g., the gate terminal).

[0028] A gate driver is configured to convert a low-voltage (LV) signal from a controller into a high-voltage (HV) signal for a power transistor. Thus, a gate driver may have a low-voltage side containing low-voltage circuits / devices that handle signals to low-voltage ground, and a high-voltage side containing high-voltage circuits / devices that have signals to high-voltage (i.e., power) ground. To isolate these grounds and prevent low-voltage electronics on the low-voltage side from being damaged by high-voltage signals on the high-voltage side, an isolation barrier is included in the gate driver. In other words, the isolation barrier can provide galvanic isolation between the low-voltage and high-voltage sides of the gate driver. Transmission of signals through (i.e., across) the isolation barrier may be performed using inductive coupling of magnetic signals. A transformer may be configured to provide both inductive coupling and the isolation barrier. Transmission of signals through (i.e., across) the isolation barrier may also be performed using capacitive coupling of electrical signals. A capacitor (or a plurality of capacitors) may be configured to provide both capacitive coupling and the isolation barrier. The technology of this disclosure can utilize any of these implementations.

[0029] The isolation barrier may be implemented as a transformer having a primary winding on the LV side of the gate driver and a secondary winding on the HV side of the gate driver. The transformer can magnetically couple signals within the transformer's frequency bandwidth between its windings. Thus, the gate driver may include a transmitter configured to encode (e.g., modulate) a signal so that the signal has a bandwidth (e.g., frequency) suitable for magnetic coupling, and a receiver configured to decode the encoded signal after it has been magnetically coupled. The transmitter and receiver may collectively be referred to as a transceiver.

[0030] In recent years, gate drivers have been required to perform more functions than just switching. For example, gate drivers may be expected to perform fault monitoring and reporting functions. These additional functions may increase the number of signals that must be transmitted across the isolation barrier, which in turn may increase the size of the gate driver and / or the power consumed by the gate driver. Furthermore, depending on the implementation, redundant fault detection may be required. One technical challenge in meeting these requirements is maintaining a reasonable size, cost, and complexity for the gate driver. This disclosure describes a gate driver that reduces the complexity and power consumption of its thermal monitoring (i.e., temperature monitoring), fault detection, and thermal reporting circuits.

[0031] High current levels switched by power transistors can cause damage or pose a danger if a malfunction (i.e., failure) occurs during the operation of the power transistor. High temperatures of power transistors and / or gate drivers can indicate malfunction. Therefore, temperature sensors can be included in the power system to measure the temperature of power transistors and / or gate drivers. A gate driver may be configured to generate a fault if one (or more) of the measured temperatures exceed a threshold and to communicate the fault to a controller, which may be programmed to take measures to reduce the temperature or to completely stop operation. In some implementations, continuous measurement of the power transistor temperature is required in addition to fault signals for diagnosis. This disclosure further describes a gate driver that can provide redundancy between real-time temperature monitoring and over-temperature (i.e., fault) detection.

[0032] Gate drivers can be used in a variety of applications, such as automotive or computing. Each application may have different requirements for temperature safety. For example, some applications may require multiple (e.g., two) temperature sensors. Measuring the temperature of a power transistor using redundant sensors can increase the certainty that a failure event can be detected and addressed before it becomes severe. This additional functionality requires the gate driver to consume more power, which is undesirable when used in applications that do not have such stringent requirements. This disclosure further describes a gate driver that can reduce power consumption in applications that do not require two or more temperature sensors. In other words, the gate driver of this disclosure can automatically detect the absence of a temperature sensor and, in response to this detection, reduce the power consumed by the gate driver.

[0033] Figure 1 is a schematic block diagram illustrating a power switching system according to one possible implementation of the present disclosure. The power switching system 100 includes a controller 110, a gate driver 150, and a switch module 130. The controller 110 can be configured to transmit LV switching signals to the gate driver 150 to control the power transistor 135 to an ON or OFF state. Furthermore, the controller 110 can be configured to receive feedback signals from the gate driver to indicate the state of the gate driver 150 and / or the power transistor 135 (e.g., a thermal failure state). These feedback signals can be transmitted pin-to-pin between the gate driver 150 and the controller 110. In other words, the feedback signals do not require digitization and communication circuits necessary to return this information via a digital bus. The feedback signals may be signals (i.e., binary) with HIGH or LOW levels to indicate a state, or analog signals (e.g., voltage) corresponding to a continuous range of values.

[0034] The gate driver 150 can be configured to send a ready signal (RDY) to the controller 110 via the ready pin 155. The level of the ready signal indicates whether the gate driver 150 is in a thermal failure state (i.e., not ready for operation) or not (i.e., ready for operation). A thermal failure state can occur when the gate driver 150 is at a temperature outside its normal operating range (e.g., above 100°C). For example, if the gate driver temperature is above the maximum temperature (i.e., above the thermal shutdown (TSD) threshold), the RDY signal on the ready pin 155 may indicate that a thermal failure exists in the gate driver. In one possible implementation, the RDY signal is HIGH for a normal gate driver temperature and LOW for an abnormal (i.e., high) gate driver temperature (i.e., failure).

[0035] The gate driver 150 can be further configured to transmit a detected temperature fault signal (TSFLT) at fault pin 156 to the controller 110. The level of the detected temperature fault signal indicates whether the power transistor 135 is in a thermal fault state or not. A thermal fault state can occur when the power transistor 135 is outside its normal operating range (e.g., 100°C ≤ T ≤ 175°C) (e.g., above 175°C). For example, if the transistor temperature of the power transistor 135 is higher than the maximum temperature (i.e., exceeds the fault threshold), the TSFLT signal at fault pin 156 may indicate that a thermal fault exists in the switch module 130 (i.e., the power transistor 135). In one possible implementation, the TSFLT signal is HIGH for a normal transistor temperature and LOW for an abnormal (i.e., high) transistor temperature.

[0036] The gate driver 150 may be further configured to transmit a transistor temperature signal (TSPWM) on a pulse-width modulated output pin (i.e., PWM output pin 157) to the controller 110. The transistor temperature signal (TSPWM) may be a square wave signal of a pulse-width modulated frequency (e.g., 10 kHz) having a duty cycle corresponding to a first signal (i.e., a first transistor temperature (TS1)) received at a first temperature sense pin 151 or a second signal (i.e., a second transistor temperature TS2) received at a second temperature sense pin 152. In one possible implementation, temperatures in the range of -40°C to +175°C may be mapped to duty cycles in the range of 10% to 90%. Thus, the controller may be configured to continuously measure the duty cycle of the TSPWM signal to monitor the temperature of the power transistor 135.

[0037] The gate driver 150 includes an isolation barrier 102 that separates the high-voltage side 103 of the gate driver from the low-voltage side 104 of the gate driver. Signals from the high-voltage side of the gate driver output at the ready pin 155 and fault pin 156 may be transmitted across the isolation barrier 102 via a shared communication channel 158, and signals from the high-voltage side of the gate driver output at the PWM output pin 157 may be transmitted across the isolation barrier 102 of the gate driver 150 via a dedicated communication channel 159.

[0038] The first temperature sense pin 151 may be coupled to the first transistor temperature sensor 131 of the switch module 130. The first transistor temperature sensor 131 may be configured to measure the first transistor temperature (i.e., TS1) of the power transistor 135. The second temperature sense pin 152 is optionally coupled to the second transistor temperature sensor 132 of the switch module 130. The second transistor temperature sensor 132 may be configured to measure the second transistor temperature (i.e., TS2) of the power transistor 135. The first transistor temperature sensor 131 and the second transistor temperature sensor 132 may be the same type of sensor (e.g., a thermistor, NTC, etc.) or different. Furthermore, the second transistor temperature sensor 132 may be integrated with the switch module 130, or it may be a single device coupled to the switch module 130 or other circuits in the power switching system 100.

[0039] The gate driver 150 may include a gate driver temperature sensor 160 configured to measure the gate driver temperature of the gate driver 150. The gate driver temperature sensor 160 may be integrated with other circuitry of the gate driver 150 in a common package (i.e., an integrated circuit (IC)). Fault signals (e.g., thermal shutdown, IGBT temperature detection) determined based on signals from a first temperature sense pin 151 and the gate driver temperature sensor 160 (and optionally a second temperature sense pin) may be transmitted across the isolation barrier 102 via a shared communication channel 158. Furthermore, real-time temperature based on signals at the first temperature sense pin (and optionally a second temperature sense pin) may be transmitted across the isolation barrier 102 via a dedicated communication channel 159. Thus, the methods of this disclosure describe multiple communication paths for temperature information that provide an additional layer of safety to the system.

[0040] The power switching system 100 shown in Figure 1 may have a switch module 130 coupled to the output pin 153 of the gate driver 150 so that the output signal (OUT) from the gate driver can control the on / off state of the power transistor 135 (e.g., IGBT). The switch module 130 may also be further coupled to the ground pin 154. The gate driver 150 and the switch module 130 are grounded to the power supply ground 140.

[0041] Figure 2 shows a method for monitoring the thermal state in a power switching system. For example, the gate driver 150 may be configured to perform the operation of this method. Thus, temperature and faults can be referred to as internal if they correspond to circuits within the gate driver 150, and as external if they correspond to circuits coupled to the outside of the gate driver 150 (e.g., the switch module 130).

[0042] Method 200 includes step 205 of measuring the gate driver temperature, such as from a gate driver temperature sensor 160. Method 200 further includes step 210 of determining an internal fault condition by comparing the gate driver temperature with a thermal shutdown (TSD) threshold 215. The comparison may result in the generation of an internal fault signal. The internal fault signal may have two levels (e.g., binary level) corresponding to the presence or absence of the internal fault condition. Method 200 further includes step 220 of generating a first pulse train signal based on the internal fault signal. For example, pulses may be generated while the internal fault condition is not present (i.e., during normal conditions) and not transmitted while the internal fault condition is present (i.e., during thermal shutdown).

[0043] Method 200 further includes step 230 receiving a transistor temperature 225, such as a first transistor temperature (i.e., TS1), from a first transistor temperature sensor 131 at a first temperature sense pin 151. Method 200 further includes step 235 determining an external fault condition by comparing the transistor temperature 225 with a fault threshold 240. The comparison may result in the generation of an external fault signal. The external fault signal may have two levels (e.g., binary level) corresponding to the presence / absence of the external fault condition. Method 200 further includes step 245 generating a second pulse train signal based on the external fault signal. For example, pulses may be generated while the external fault condition is present and not transmitted while the external fault condition is absent (i.e., while in a normal state).

[0044] Method 200 further includes step 250 of combining a first pulse train signal and a second pulse train signal to form a composite signal. The first and second pulse train signals may have different bandwidths. For example, the pulses of the first pulse train signal may have a first pulse width that is longer than the second pulse width of the pulses of the second pulse train signal. Furthermore, the first period of the first pulse train signal may be longer than the second period of the second pulse train signal. In one possible implementation, the first pulse train signal may include a first pulse width of 65 nanoseconds (65 ns) and a first period of 3 microseconds (3 μs), and the second pulse train signal may include a second pulse width of 10 ns and a second period of 150 ns. Thus, the first pulse train signal may have a lower bandwidth than the second pulse train signal. The composite signal may include pulses of the first pulse width and first period, as well as pulses of the second pulse width and second period.

[0045] Method 200 further includes step 255 of transmitting a composite signal over a shared communication channel 158. This advantageously simplifies the electronics required for the communication of the two signals from the high-voltage side 103 to the low-voltage side 104 of the gate driver 150.

[0046] Method 200 further includes step 260 of decoding a composite signal based on a first pulse train signal. Decoding step 260 may include filtering the composite signal to reconstruct the first pulse train signal from the composite signal. Decoding step 260 may further include detecting pulses to generate a ready signal (RDY) at the ready pin 155.

[0047] Method 200 further includes step 270 of decoding the composite signal based on a second pulse train signal. Decoding step 270 may include detecting high frequencies in the composite signal to determine that the second pulse train signal is present in the composite signal. Based on this determination, the decoding step can generate a detected temperature fault signal (TSFLT) at fault pin 156.

[0048] Figure 3 is a schematic block diagram showing the circuit of a power switching system according to one possible implementation of the present disclosure. The block diagram includes a device and circuit of a gate driver 300 which can be configured to perform the operation of the method described above. The gate driver 300 has a gate driver temperature (T GD This may include a gate driver temperature sensor 310 configured to measure the gate driver temperature. A signal (e.g., voltage) corresponding to the gate driver temperature is received by a gate driver temperature sense circuit 400 configured to output an internal fault signal based on the gate driver temperature.

[0049] Figure 4 is a schematic diagram of a gate driver temperature sense circuit in one possible implementation of the present disclosure. The gate driver temperature sense circuit 400 may include a comparator 401 configured to receive a voltage from a gate driver temperature sensor 310 at a first input 410 and a thermal shutdown threshold voltage (VREF) at a second input 420. The thermal shutdown threshold voltage can be generated using various circuits and devices (e.g., voltage dividers, current / resistors, bandgap references, etc.). The comparator is configured to output an internal fault signal. The internal fault signal is a voltage (VREF) that is at a LOW level when the voltage from the gate driver temperature sensor is below the thermal shutdown threshold voltage. TSD ) may also be used. Furthermore, the voltage (V TSD ) may be at a HIGH level when the voltage from the gate driver temperature sensor exceeds the thermal shutdown threshold voltage.

[0050] Returning to Figure 3, the gate driver 300 further includes a transistor temperature sense circuit 510 and a transistor temperature monitoring circuit 520 configured to receive transistor temperature from the transistor temperature sensor 330. The transistor temperature sense circuit can be configured to output an external fault signal based on the transistor temperature, and the transistor temperature monitoring circuit 520 can be configured to output an external monitoring signal based on the transistor temperature.

[0051] Figure 5 is a schematic diagram showing a transistor temperature sensing and monitoring circuit according to one implementation of the present disclosure. The temperature sensing and monitoring circuit 500 includes a transistor temperature sense circuit 510 and a transistor temperature monitoring circuit 520. The temperature sensing and monitoring circuit 500 may be coupled to a first or second temperature sense pin of a gate driver to receive transistor temperatures (e.g., TS1, TS2) from transistor temperature sensors (e.g., a first transistor temperature sensor 131, a second transistor temperature sensor 132). If the power switching system includes two temperature sensors, the gate driver may include a temperature sensing and monitoring circuit 500 for each transistor temperature sensor.

[0052] The transistor temperature sense circuit 510 of the temperature detection and monitoring circuit 500 includes a first comparator 511. The first comparator is coupled to a first temperature sense pin 151 (or a second temperature sense pin 152) of the gate driver. The first comparator 511 can be configured to receive a signal corresponding to the transistor temperature from a first transistor temperature sensor 131 (or a second transistor temperature sensor 132) at its first input. If the first transistor temperature sensor 131 (or a second transistor temperature sensor 132) is implemented as a thermistor, the signal may be a voltage that decreases as the transistor temperature rises. The first comparator 511 measures this voltage against a fault threshold voltage (V) received at its second input. FLT The first comparator 511 may be configured to compare the voltage from the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) with the fault threshold voltage (V). FLT When the voltage is less than (V), it is at a HIGH level. TSFLT) It can be. In this case, since the HIGH level corresponds to a high physical temperature where the low voltage output by the thermistor indicates a thermal failure of the power transistor. In fact, the signal level can be reversed. Generally, the disclosure of specific signal levels herein is provided to assist in understanding the method of implementing possible embodiments and should not be considered as limiting the present invention.

[0053] The transistor temperature monitoring circuit 520 of the temperature detection and monitoring circuit 500 includes a second comparator 521. The second comparator 521 is coupled to the first temperature sense pin 151 (or the second temperature sense pin 152) of the gate driver. The second comparator 521 can be configured to receive a signal corresponding to the transistor temperature at the first input of the second comparator 521 from the first transistor temperature sensor 131 (or the second transistor temperature sensor 132). When the first transistor temperature sensor 131 (or the second transistor temperature sensor 132) is implemented as a thermistor, the signal may be a voltage that decreases as the transistor temperature rises. Accordingly, the second comparator 521 may be configured to compare this voltage with the lamp signal 522 to generate an external monitoring signal. The external monitoring signal may be a voltage (V TSPWM ) that is pulse-width modulated according to the comparison.

[0054] FIG. 6 shows signals from a transistor temperature sense circuit and a transistor temperature monitoring circuit for the first temperature sense input and the second temperature sense input of a gate driver according to a possible implementation of the present disclosure. In the first graph 601, the voltage (V TS1 ) from the first transistor temperature sensor is compared with the lamp signal to generate a PWM voltage (V TSPWM ) (i.e., the external monitoring signal) that is at a HIGH level when the lamp signal exceeds V TS1 . As shown in the second graph 602, the duty cycle of the PWM voltage is the voltage V TS1It increases as the temperature decreases. In other words, the duty cycle increases as the transistor temperature rises. In one possible implementation, a duty cycle exceeding the maximum duty cycle may trigger a failure.

[0055] In the first graph 601, the voltage from the second transistor temperature sensor (V TS2 ) is the fault threshold voltage (V FLT It is compared to V. TS2 When the voltage drops below the fault threshold voltage, the state of the external fault signal may change. As shown in the third graph 603, the inverted external fault signal may change from a non-fault state (i.e., HIGH) to a fault state (i.e., LOW). In this case as well, the levels corresponding to the fault / non-fault states may be modified to match the logic of a particular implementation.

[0056] Returning to Figure 3, the gate driver 300 further includes a first transceiver 320 configured to traverse the isolation barrier 102 and transmit internal fault signals from the gate driver temperature sense circuit 400 and external fault signals from the transistor temperature sense circuit 510 via a shared communication channel. The first transceiver 320 (i.e., the shared transceiver) may include a plurality of encoders 321 that process (e.g., modulate) the signal for transmission and a plurality of decoders 322 that process (e.g., detect) the received signal. The first transceiver 320 may output a ready signal (RDY) on the ready pin 155. The ready signal (RDY) may be at a level indicating that the gate driver is at a normal operating temperature, or it may be at a non-ready level indicating that the gate driver is not at a normal operating temperature (i.e., an over-temperature condition). The first transceiver 320 may also output a fault signal on the fault pin 156. The fault signal (TSFLT) may be at a level indicating that the power transistor 135 is at a normal operating temperature, or it may be at a non-ready level indicating that the power transistor is not at a normal operating temperature (e.g., overheated).

[0057] As shown in Figure 3, the gate driver 300 further includes a second transceiver 340 configured to cross the isolation barrier 102 and transmit an external monitoring signal from the transistor temperature monitoring circuit 520 via a dedicated communication channel. The second transceiver 340 (i.e., the dedicated transceiver) may include an encoder 341 for processing (e.g., modulating) the signal for transmission and a decoder 342 for processing (e.g., detecting) the received signal. The second transceiver 340 may output a temperature monitoring signal (i.e., a PWM signal) on a PWM output pin 157. The PWM signal (TSPWM) may have a duty cycle corresponding to the temperature measurement of the power transistor.

[0058] Figure 7 shows a partial block diagram of the high-voltage side of a gate driver for a power switching system in one possible implementation of the present disclosure. Figure 7 includes the transmitter portion of the first transceiver 320. The transmitter portion of the first transceiver receives an internal fault signal (V TSD The transmitter portion of the first transceiver includes a ready encoder 710 configured to generate a first pulse train signal while the external fault signal (V) is at a normal level, and not generate a fault signal otherwise. TSFLT The first transceiver further includes a temperature fault encoder 720 configured to generate a second pulse train signal while the first pulse train signal (A) is at a fault level, and not generate a second pulse train signal otherwise. The transmitter portion of the first transceiver further includes a multiplexer 730. The multiplexer is configured to generate a combined signal (TX_IN) from the first pulse train signal (A) and the second pulse train signal (B). For example, the multiplexer 730 receives an external fault signal (V) TSFLT When ) is at a HIGH level, the second pulse train signal is selected, and the external fault signal (V TSFLT The transmitter may be configured to select a first pulse train signal when ) is at a LOW level. The transmitter can then transmit the combined signal to the high-voltage winding 740 (i.e., the side) of the first transformer (HV TX).

[0059] Figure 7 shows the transmitter portion of the second transceiver 340. The transmitter portion of the second transceiver includes a PWM inverter (i.e., inverter 750) configured to invert the external monitoring signal so that it is at a relatively low level for a longer period of time than it is at a relatively high level, while the transistor temperature is within a typical temperature range (e.g., 100°C ≤ T ≤ 175°C) which may correspond to duty cycles within a typical duty cycle range (e.g., 67% ≤ DUTY ≤ 90%). Since inverter 750 can consume less current at the LOW level than at the HIGH level, the current consumed by the transmitter portion of the second transceiver can be reduced. In other words, the transistor temperature monitoring circuit 520 may output a PWM signal that is at a HIGH level for most of the time during operation within the normal temperature range, and the inverter can output an inverted version of this PWM signal that is at a LOW level for most of the time. The inverted PWM signal (C) transmits the same information but requires less power. Next, the transmitter can transmit an inverted PWM signal (C) to the high-voltage winding 760 (i.e., side) of the second transformer (HV TX).

[0060] Figure 8 shows a partial block diagram of the low-voltage side of a gate driver for a power switching system according to one possible implementation of the present disclosure. Figure 8 includes the receiver portion of the first transceiver 320. The receiver portion of the first transceiver receives a combined signal from the low-voltage winding 840 of the first transformer. The combined signal is then split into two channels.

[0061] The first channel includes a ready decoder, which includes a filter 810 configured to output a signal (FILT_OUT) from which a first pulse train signal has been restored (i.e., separated) from the composite signal. For example, the filter 810 may have a relatively high time constant (e.g., 20 ns) so that a first pulse train signal with a lower bandwidth can pass through the filter 810 while a second pulse train signal with a higher bandwidth is blocked (i.e., attenuated). In other words, the filter 810 may be a low-pass filter. The ready decoder further includes a decoder implemented as a pulse detector 820 configured to detect pulses in the first pulse train signal. The pulse detector 820 may output a ready signal while pulses are detected and output a non-ready signal after a certain number (e.g., 3) of pulse absences (i.e., no pulses).

[0062] The second channel includes a temperature fault decoder configured to receive a composite signal (RX_OUT) from the low-voltage winding 840 of the first transformer. The temperature fault decoder includes a decoder implemented as a frequency detector 830, configured to detect the higher bandwidth of the second pulse train signal and to output a fault signal at a fault level while the second pulse train signal is detected in the composite signal.

[0063] Figure 8 further includes the receiver portion of the second transceiver 340. The receiver portion of the second transceiver receives an inverted PWM signal from the low-voltage winding 850 of the second transformer. The receiver portion of the second transceiver includes a PWM decoder 860 configured to restore the PWM signal by inverting the inverted PWM signal.

[0064] As shown in Figure 5, the gate driver includes a current source 530 for reading signals from the temperature sense pin. The gate driver may include multiple (e.g., two) temperature sense pins for redundant sensing, but not all implementations use all temperature sense pins. In these implementations, the current source associated with unused temperature sense pins may consume power (current) unnecessarily. As a result, the gate driver may include a nullification circuit configured to disable the temperature sense pin when it is not coupled to the temperature sensor in order to reduce the power consumed by the gate driver.

[0065] Figure 9 is a schematic diagram of a disable circuit for a temperature sense pin of a gate driver according to one possible implementation of the present disclosure. The disable circuit includes a switch 920 configured to discouple a current source 530 from the temperature sense pin 910 when the pin is not coupled to the sensor.

[0066] The deactivation circuit may be coupled to a high-voltage supply rail (e.g., 15V), while the signal at the temperature sense pin 910 may be low-voltage (e.g., 5V). When the temperature sense pin is decoupled, it may experience voltage float through the current source 530 to the high-voltage supply rail. To prevent this, the deactivation circuit includes a low-voltage rail 911 supplied by a low-dropout voltage regulator (LDO912). The low-voltage rail 911 is connected to a pull-up resistor (R PU The temperature sense pin 910 is coupled via a ) . In this case, the floating temperature sense pin is pulled up to the low-voltage rail 911. In this state, the deactivation voltage (TSDIS) is pulled to HIGH, and as a result, switch 920 opens. However, if the temperature sense pin is not floating (i.e., coupled to the sensor), the deactivation voltage (TSDIS) is pulled to LOW, and as a result, switch 920 closes.

[0067] Typical implementations have been disclosed in the specification and / or in the drawings. This disclosure is not limited to such exemplary implementations. The use of the terms "and / or" includes any and all combinations of one or more of the relevant enumerated items. The drawings are schematic and therefore not necessarily to scale. Unless otherwise specified, specific terms are used in a general and descriptive sense and not for limiting purposes.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art. Methods and materials similar to or equivalent to those described herein and materials may be used in the practice or testing of the present disclosure. Where used herein and in the appended claims, the singular forms "a," "an," and "the" include multiple references unless otherwise clearly indicated by the context. The term "includes" and its variations as used herein are synonymous with "includes" and its variations and are open and non-restrictive terms. The terms "optional" or "optionally" as used herein mean that the features, events, or circumstances described thereafter may or may not occur, and that the description includes both cases in which such features, events, or circumstances occur and cases in which they do not occur. Ranges may be expressed herein as "about" one particular value to and / or "about" another particular value. Where such ranges are expressed, embodiments include "about" one particular value to and / or another particular value. Similarly, when values ​​are expressed as approximations using the antecedent "approximately," it will be understood that certain values ​​form a different form. It will also be understood that the endpoint of each range is significant with respect to the other endpoint, and also significant independently of the other endpoint.

[0069] Several implementation configurations can be implemented using various semiconductor processing and / or packaging techniques. Some implementation configurations can be implemented using various types of semiconductor processing techniques associated with semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0070] While some features relating to the implementation of the disclosure have been described herein, those skilled in the art will find many variations, substitutions, alterations, and equivalents. Therefore, it will be understood that the attached claims are designed to encompass all such modifications and alterations within the scope of implementation. It should be understood that these are presented merely as examples, not limitations, and that various modifications in form and detail are possible. Any part of the apparatus and / or methods described herein can be combined in any combination, except for mutually exclusive combinations. The various apparatuses described herein may include various combinations and / or partial combinations of the functions, components, and / or features of the various apparatuses described herein.

[0071] In the above description, when an element is said to be on another element, connected, electrically connected, coupled, or electrically coupled, it will be understood that the element may be directly placed on, connected to, or coupled to another element, or one or more intervening elements may be present. On the other hand, when an element is said to be directly placed on, directly connected to, or directly coupled to another element or layer, there are no intervening elements or layers. Although the terms directly placed, directly connected, or directly coupled may not be used throughout the detailed description of the present invention, elements illustrated as directly placed, directly connected, or directly coupled can be referred to as such. The claims of this application (if included) may be amended to describe the exemplary relationships described or illustrated herein.

[0072] In this specification, the singular form may include the plural form unless explicitly stated otherwise in terms of context. Terms indicating spatial relativeity (e.g., overall, up, above, down, below, lower, downward, etc.) are intended to include various orientations of the device in use or operation, in addition to the directions shown in the drawings. In some implementations, the relative terms up and down may include vertically up and vertically down, respectively. In some implementations, the term adjacent may include laterally adjacent or horizontally adjacent.

Claims

1. A power switching system, A switch module including a power transistor and a transistor temperature sensor configured to measure the transistor temperature of the power transistor, A gate driver coupled to the aforementioned switch module, A gate driver temperature sensor configured to measure the gate driver temperature of the aforementioned gate driver, A gate driver temperature sense circuit configured to output a first pulse train signal corresponding to an internal fault signal based on the gate driver temperature, A transistor temperature sense circuit configured to receive the transistor temperature from the transistor temperature sensor and output a second pulse train signal corresponding to an external fault signal based on the transistor temperature, A transceiver configured to transmit a combined signal including the first pulse train signal and the second pulse train signal across the isolation barrier of the gate driver via a shared communication channel, A gate driver, including A power switching system equipped with the following features.

2. The aforementioned transceiver is The synthesized signal is transmitted to the low-voltage side of the gate driver via the shared communication channel. The ready signal is output at the ready pin of the gate driver, and the ready signal corresponds to the first pulse train signal. The detected temperature fault signal is output at the temperature fault pin of the gate driver, and the detected temperature fault signal corresponds to the second pulse train signal. A power switching system according to claim 1, configured to perform the following:

3. The gate driver temperature sensing circuit includes a comparator, which is configured to receive a voltage from the gate driver temperature sensor on a first input and a thermal shutdown threshold voltage on a second input, and the comparator is further configured to output the internal fault signal, which is at a normal level when there is no thermal fault in the gate driver. The power switching system according to claim 1, wherein the transistor temperature sense circuit includes a comparator, the comparator configured to receive a voltage from the transistor temperature sensor at a first input and a fault threshold voltage at a second input, the comparator further configured to output the external fault signal, the external fault signal being at a fault level when a thermal fault is present in the power transistor.

4. The aforementioned transceiver is A ready encoder configured to generate a first pulse train signal while the internal fault signal is at the normal level, and not generate the first pulse train signal otherwise, A temperature fault encoder configured to generate a second pulse train signal while the transistor temperature is at the fault level, and not generate the second pulse train signal otherwise, wherein the first pulse train signal has a lower bandwidth than the second pulse train signal, and the second pulse train signal has a higher bandwidth than the first pulse train signal. A multiplexer configured to generate a combined signal by combining the output of the ready encoder and the output of the temperature fault encoder, and to transmit the combined signal to the high-voltage side of a transformer, A ready decoder configured to receive the combined signal from the low-voltage side of the transformer, A filter configured to separate the first pulse train signal from the composite signal based on the lower bandwidth of the first pulse train signal, A pulse detector configured to detect pulses in the first pulse train signal, output a ready signal at a ready level while the pulses in the first pulse train signal are detected, and output a ready signal at a non-ready level after no multiple pulses in the first pulse train signal have been detected, A ready decoder, including A temperature fault decoder configured to receive the composite signal from the low-voltage side of the transformer, A frequency detector configured to detect the higher bandwidth of the second pulse train signal, and to output a fault signal at a fault level while the second pulse train signal is detected in the composite signal, and at a non-fault level while the second pulse train signal is not detected in the composite signal. A temperature-faulty decoder, The power switching system according to claim 3, including the above.

5. The transistor temperature sensor is a first transistor temperature sensor configured to measure the first transistor temperature of the power transistor, and the switch module is A second transistor temperature sensor configured to measure the second transistor temperature of the power transistor, It further includes, The transistor temperature sense circuit is a first temperature sense circuit configured to receive the first transistor temperature from the first transistor temperature sensor and output a first signal based on the first transistor temperature, and the gate driver is A second temperature sense circuit configured to receive the second transistor temperature from the second transistor temperature sensor and output a second signal based on the second transistor temperature, A logic gate configured to receive the first signal and the second signal and output the external fault signal, wherein the external fault signal has a level corresponding to a thermal fault when either the first signal or the second signal has a level corresponding to a thermal fault of the power transistor, The power switching system according to claim 1, further comprising:

6. The transceiver of the gate driver is a first transceiver, and the gate driver is A transistor temperature monitoring circuit configured to output an external monitoring signal by comparing the transistor temperature with a ramp signal, wherein the external monitoring signal is pulse-width modulated (PWM) according to the transistor temperature. A second transceiver configured to transmit the external monitoring signal across the isolation barrier of the gate driver via a dedicated communication channel, In order to reduce the power consumed by the second transceiver, an inverter is configured to invert the external monitoring signal to a relatively lower level for a longer period of time than the external monitoring signal is at a relatively high level, while the transistor temperature of the power transistor is within the normal temperature range of the power transistor. A second transceiver, The power switching system according to claim 1, further comprising:

7. The power switching system according to claim 1, wherein the gate driver is coupled to the transistor temperature sensor by a first temperature sense pin, and the gate driver further includes a second temperature sense pin and a deactivation circuit configured to deactivate the second temperature sense pin when the second temperature sense pin is not coupled to the second temperature sensor in order to reduce the power consumed by the gate driver.

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