Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide semiconductor devices with excellent reliability.SOLUTION: A semiconductor device of the embodiment has a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film, and the lower end of the first field plate electrode is located on the second side of the first electrode film that is in contact with the second electrode film side than the first side that is in contact with the first insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] Semiconductor devices such as transistors and diodes are used in circuits such as switching power supply circuits and inverter circuits. These semiconductor devices require high voltage resistance and low on-resistance. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Patent No. 5662367 [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a highly reliable semiconductor device and a highly reliable method for manufacturing a semiconductor device. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film, wherein the lower end of the first field plate electrode is located on a second surface that contacts the second electrode film side rather than a first surface that contacts the first insulating film of the first electrode film. The first field plate electrode is embedded in the second electrode film. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the embodiment. [Figure 2] A schematic top view of the semiconductor device according to the embodiment. [Figure 3]Schematic cross-sectional views of the semiconductor device of the embodiment (FIGS. 3(a), 3(b), 3(c), 3(d)). [Figure 4] Process flow diagram of the semiconductor device of the embodiment. [Figure 5] Process flow diagram of the semiconductor device of the embodiment. [Figure 6] Process flow diagram of the semiconductor device of the embodiment. [Figure 7] Process flow diagram of the semiconductor device of the embodiment. [Figure 8] Process flow diagram of the semiconductor device of the embodiment. [Figure 9] Process flow diagram of the semiconductor device of the embodiment. [Figure 10] Process flow diagram of the semiconductor device of the embodiment. [Figure 11] Process flow diagram of the semiconductor device of the embodiment. [Figure 12] Process flow diagram of the semiconductor device of the embodiment. [Figure 13] Process flow diagram of the semiconductor device of the embodiment. [Figure 14] Process flow diagram of the semiconductor device of the embodiment. [Figure 15] Process flow diagram of the semiconductor device of the embodiment. [Figure 16] Process flow diagram of the semiconductor device of the embodiment. [Figure 17] Schematic cross-sectional view of the semiconductor device of the embodiment. [Figure 18] Schematic cross-sectional view of the semiconductor device of the embodiment. [Figure 19] Schematic cross-sectional view of the semiconductor device of the embodiment.

Embodiments of the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described may be omitted.

[0008] In this specification, the "nitride semiconductor layer" includes "GaN-based semiconductors". The "GaN-based semiconductor" is a general term for semiconductors including gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their intermediate compositions.

[0009] In this specification, "undoped" means that the impurity concentration is 2×10 16 cm -3 or less.

[0010] In this specification, to indicate the positional relationship of components and the like, the upward direction of the drawing is described as "up", and the downward direction of the drawing is described as "down". In this specification, the concepts of "up" and "down" are not necessarily terms indicating the relationship with the direction of gravity.

[0011] The physical properties in the specification are values in an atmospheric environment at 25°C. The physical property values and the like described in the semiconductor device are also physical property values related to the manufacturing method of the semiconductor device. The physical property values and the like described in the manufacturing method of the semiconductor device are also physical property values related to the semiconductor device.

[0012] (First Embodiment) The first embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of the first embodiment includes a semiconductor element having a semiconductor layer and a wiring layer on the semiconductor element. Hereinafter, a GaN-based semiconductor device will be described as an example, but the semiconductor element may be a lateral transistor other than GaN-based.

[0013] FIG. 1 is a schematic cross-sectional view of the semiconductor device 100 of the first embodiment. FIG. 2 shows a schematic top view of the semiconductor device 100. FIG. 2 shows a schematic cross-sectional view of the A-A' cross-section of FIG. 1. The semiconductor device 100 is, for example, a HEMT (High Electron Mobility Transistor) using a GaN-based semiconductor. The semiconductor device 100 has an element region that operates as a transistor and a non-element region that does not operate as a transistor.

[0014] The semiconductor device 100 in FIG. 1 includes a semiconductor layer 1, a first insulating film 2, a first electrode 3, a second electrode 4, a third electrode 5, a first field plate electrode 6, a second field plate electrode 7, a third field plate electrode 8, a second insulating film 9, and a third insulating film 10.

[0015] The semiconductor layer 1 is laminated, for example, in the order of a substrate 1A, a buffer layer 1B, a channel layer 1C (first nitride semiconductor layer), and a barrier layer 1D (second nitride semiconductor layer). The semiconductor layer 1 includes an element region and an element isolation region. An element isolation region is provided from the surface of the barrier layer 1D of the semiconductor layer 1 on the upper side and the lower side in FIG. 2 toward the substrate 1A. The region where the element isolation region is not provided is the element region.

[0016] The substrate 1A is formed of, for example, silicon (Si). In addition to silicon, for example, sapphire (Al2O3) or silicon carbide (SiC) can also be applied.

[0017] A buffer layer 1B is provided on the substrate 1A. The buffer layer 1B has a function of relaxing the lattice mismatch between the substrate 1A and the channel layer 1C. The buffer layer 1B is formed, for example, in a multilayer structure of aluminum gallium nitride (Al W Ga 1-W N (0 < W ≤ 1)).

[0018] The channel layer 1C is provided on the buffer layer 1B. The channel layer 1C is also referred to as an electron traveling layer. The channel layer 1C is, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0 ≤ X < 1)). More specifically, the channel layer 1C is, for example, undoped gallium nitride (GaN). The thickness of the channel layer 1C is, for example, 0.1 [μm] or more and 10 [μm] or less. In the embodiment, the thickness is the length (height) of each member in the third direction (Z direction) which is the stacking direction of the channel layer 1C and the barrier layer 1D including the channel layer 1C.

[0019] The barrier layer 1D is provided on the channel layer 1C. The barrier layer 1D is also referred to as an electron supply layer. The bandgap of the barrier layer 1D is larger than that of the channel layer 1C. The barrier layer 1D is, for example, undoped aluminum gallium nitride (Al Y Ga 1-Y N (0 < Y ≤ 1, X < Y)). More specifically, the barrier layer 1D is, for example, undoped Al 0.25 Ga 0.75 N. The thickness of the barrier layer 1D is, for example, 2 [nm] or more and 100 [nm] or less.

[0020] Between the channel layer 1C and the barrier layer 1D is a hetero-junction interface. A two-dimensional electron gas (2DEG) is formed at the hetero-junction interface and serves as the carrier of the semiconductor device 100.

[0021] The element isolation region is a high-resistance region formed by ion implantation. The high-resistance region will be described in the second embodiment. The element isolation region is, for example, formed at least inside the channel layer 1C. As the ion species for element isolation, for example, nitrogen, argon, etc. can be applied. Also, the dose amount associated with ion implantation is, for example, about 1×10 14 [ions / cm 2 . The acceleration energy for ion implantation is, for example, about 100 [keV] or more and 200 [keV] or less. The region where the element isolation region is formed (the boundary between the element isolation region and the element region) can be confirmed by cross-sectional observation using a transmission electron microscope (TEM), etc.

[0022] A gate insulating film (hereinafter referred to as gate insulating film 2) which is a first insulating film 2 is provided between the first electrode 3 and the barrier layer 1D, and the semiconductor device 100 can be made into an MIS (Metal Insulator Semiconductor) type HEMT. The gate insulating film 2 is provided between the second electrode 4 and the third electrode 5. The gate insulating layer 2 is, for example, an oxide or an oxynitride. The gate insulating film 2 is, for example, silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide, silicon oxynitride, or aluminum oxynitride. The gate insulating film 2 is a dense insulating film. The thickness of the gate insulating film 2 is preferably, for example, 10 [nm] or more and 300 [nm] or less, preferably 100 [nm] or more and 300 [nm] or less, and more preferably 100 [nm] or more and 200 [nm] or less.

[0023] The first electrode (gate electrode) 3 is an electrode having a plurality of fingers extending in a first direction (X direction). Each comb-shaped finger of the gate electrode 3 extends in the first direction, and each finger is aligned in a second direction (Y direction). The gate electrode 3 is an electrode provided on a first insulating film (gate insulating film) 2 provided on a channel layer 1C and a barrier layer 1D. The gate electrode 3 is electrically connected to the channel layer 1C and the barrier layer 1D. The gate electrode 3 is in direct contact with, for example, the first insulating film 2. The gate electrode 3 is provided between the second electrode 4 and the third electrode 5. The gate electrode 3 or the first field plate electrode 6 is connected to the first electrode pad (gate electrode pad) 3A. When the first field plate electrode 6 is connected to the first electrode pad 3C, for example, the gate electrode 3 has the shape of only the finger portion.

[0024] The first direction intersects with the second and third directions. The second direction intersects with the first and third directions (Z direction). Preferably, the first direction is perpendicular to the plane formed by the second and third directions, the second direction is perpendicular to the plane formed by the first and third directions, and the third direction is perpendicular to the plane formed by the first and second directions.

[0025] The gate electrode 3 includes a first electrode film (first gate electrode film) 3A and a second electrode film (second gate electrode film) 3B. Preferably, the first gate electrode film 3A and the second gate electrode film 3B are stacked. Preferably, the semiconductor layer 1, gate insulating film 2, first gate electrode film 3A, and second gate electrode film 3B are stacked in the third direction in that order.

[0026] The surface of the first gate electrode film 3A facing the semiconductor layer 1 is opposite the gate insulating film 2. Preferably, the surface of the first gate electrode film 3A facing the gate insulating film 2 is in direct contact with the gate insulating film 2. Preferably, the entire surface of the surface of the first gate electrode film 3A facing the gate insulating film 2 is in direct contact with the gate insulating film 2. The first gate electrode film 3A suppresses the diffusion of metal (specifically Al) into the gate insulating film 2.

[0027] The surface of the first gate electrode film 3A facing the second gate electrode film 3B is opposite the second gate electrode film 3B. Preferably, the surface of the first gate electrode film 3A facing the second gate electrode film 3B is in direct contact with the second gate electrode film 3B. Preferably, the entire surface of the surface of the first gate electrode film 3A facing the second gate electrode film 3B is in direct contact with the surface of the second gate electrode film 3B facing the semiconductor layer 1. Preferably, the entire surface of the surface of the first gate electrode film 3A facing the second gate electrode film 3B is in direct contact with the entire surface of the surface of the second gate electrode film 3B facing the semiconductor layer 1.

[0028] The surface of the second gate electrode film 3B facing the first gate electrode film 3A is opposite the first gate electrode film 3A. Preferably, the surface of the second gate electrode film 3B facing the first gate electrode film 3A is in direct contact with the first gate electrode film 3A. Preferably, the entire surface of the second gate electrode film 3B facing the first gate electrode film 3A is in direct contact with the surface of the first gate electrode film 3A facing the first field plate electrode 6. Preferably, the entire surface of the second gate electrode film 3B facing the first gate electrode film 3A is in direct contact with the entire surface of the surface of the first gate electrode film 3A facing the first field plate electrode 6.

[0029] The first gate electrode film 3A is a single-layer or multi-layer conductive film. The first gate electrode film 3A contains a metal nitride and / or alloy. Preferably, the first gate electrode film 3A contains M1AlN (a nitride containing the element M1 and aluminum) and / or M2AlW (an alloy containing the element M2, aluminum, and tungsten). Preferably, the first gate electrode film 3A contains M1AlN or M2AlW. M1 is one or more selected from the group consisting of Ti, W, Ta, Nb, V, and Zr. Preferably, M1 contains Ti, and more preferably Ti. M2 is one or more selected from the group consisting of Ti, Zr, and C. Preferably, the first gate electrode film 3A contains an Al-free region. The Al-free region of the first gate electrode film 3A is preferably M1N and / or M2W, and more preferably M1N or M2W. Preferably, M2 contains Ti, and more preferably Ti. The first gate electrode film 3A contains, for example, one or more selected from the group consisting of TiAlN, WAlN, and TaAlN, and preferably one selected from the group consisting of AlTiN, WAlN, and TaAlN. The amount of Al contained in the first gate electrode film 3A is preferably 0 [wt%] or more and 10 [wt%] or less. The first gate electrode film 3A may also contain Cu and / or Si in amounts of 0 [wt%] or more and 1 [wt%] or less.

[0030] The second gate electrode film 3B is a single-layer or multi-layer conductive film. The film resistance of the second gate electrode film 3B is preferably lower than that of the first gate electrode film 3A. The second gate electrode film 3B contains elements included in the first field plate electrode 6. The second gate electrode film 3B contains metals, alloys, and / or metal nitrides. The second gate electrode film 3B preferably contains M3Al (an alloy containing the element M3 and aluminum) and / or M4AlN (a nitride containing the element M4 and Al). The second gate electrode film 3B preferably contains M3Al or M4AlN. M3 is one or more selected from the group consisting of Ti, Nb, V, and Zr. The second gate electrode film 3B preferably includes a region that does not contain Al. The Al-free region of the second gate electrode film 3B is preferably M3 and / or M4N, and preferably M3 or M4W. M3 preferably contains Ti, and more preferably Ti. M4 is one or more selected from the group consisting of Ti, W, Ta, and Zr. M4 preferably contains Ti, and more preferably Ti. The first gate electrode film 3A contains, for example, one or more selected from the group consisting of AlTiW and AlTiTa, and preferably one selected from the group consisting of AlTi, AlW and AlTa. The amount of Al contained in the second gate electrode film 3B is preferably 0 [wt%] or more and 10 [wt%] or less. The second gate electrode film 3B may also contain 0 [wt%] or more and 1 [wt%] or less of Cu and / or Si.

[0031] Preferably, the element M1 of the first gate electrode film 3A includes one or more elements selected from the group consisting of one or more elements included as the element M3 in the second gate electrode film 3B and / or one or more elements included as the element M4.

[0032] It is preferable that one of the first gate electrode film 3A and the second gate electrode film 3B has a strong tensile stress and the other has a strong compressive stress. When this relationship is satisfied, the stress in one of the first gate electrode film 3A and the second gate electrode film 3B can be relieved by the stress in the other. From the viewpoint of stress relief, it is preferable that the first gate electrode film 3A and the second gate electrode film 3B are films with different compositions. If they are films with different compositions, the types of elements contained in the first gate electrode film 3A and the second gate electrode film 3B are not the same (some or all are different), or the types of elements contained in the first gate electrode film 3A and the second gate electrode film 3B are the same, but the elemental ratios are different.

[0033] From the viewpoint of stress relaxation, the combination of the first gate electrode film 3A and the second gate electrode film 3B (first gate electrode film 3A / second gate electrode film 3B) is preferably TiN / Ti, TiW / Ti, TaN / Ta, or TaW / Ta. After the elements of the first field plate electrode 6 have diffused, these will include the above-mentioned Al. If Al is included, the combination of the first gate electrode film 3A and the second gate electrode film 3B (first gate electrode film 3A / second gate electrode film 3B) is preferably AlTiN / AlTi, AlTiW / AlTi, AlTaN / AlTa, or AlTaW / AlTa.

[0034] Figures 3(a), 3(b), 3(c), and 3(d) show schematic cross-sectional views of the gate electrode 3 in an enlarged view. Referring to the schematic cross-sectional views in Figure 3, the relationship between the position of the lower end of the first field plate electrode 6 and the first gate electrode film 3A, and / or the relationship between the position of the lower end of the first field plate electrode 6 and the second gate electrode film 3B will be explained. In all of the forms shown in Figures 3(a), 3(b), 3(c), and 3(d), the lower end of the first field plate electrode 6 is located on the second surface that contacts the second gate electrode film 3B rather than the first surface that contacts the gate insulating film 2 of the first gate electrode film 3A.

[0035] Figure 3(a) shows a configuration in which the lower end surface of the first field plate electrode 6 and the upper end surface of the second gate electrode film 3B are in direct contact. The second gate electrode film 3B and the first field plate electrode 6 are in direct contact. Figure 3(a) shows a configuration in which the contact area between the second gate electrode film 3B and the first field plate electrode 6 is small. Since the thickness of the first gate electrode film 3A does not change depending on the position and shape of the first field plate electrode 6, it has high barrier properties that prevent Al from diffusing into the gate insulating film 2.

[0036] Figure 3(b) shows a configuration in which the lower end of the first field plate electrode 6 is embedded in the second gate electrode film 3B, and the first field plate electrode 6 does not penetrate the second gate electrode film 3B. The lower end of the first field plate electrode 6 and a portion of the side surface on the lower end side of the first field plate electrode 6 are in direct contact with the second gate electrode film 3B. Since the thickness of the first gate electrode film 3A does not change with the position and shape of the first field plate electrode 6, it has high barrier properties that prevent Al from diffusing into the gate insulating film 2.

[0037] Figure 3(c) shows a configuration in which the first field plate electrode 6 penetrates the second gate electrode film 3B, and the lower end surface of the first field plate electrode 6 and the upper end surface of the first gate electrode film 3A are in direct contact. The first field plate electrode 6 is not embedded in the first gate electrode film 3A. A portion of the lower end side surface of the first field plate electrode 6 is in direct contact with the second gate electrode film 3B. Since the thickness of the first gate electrode film 3A does not change with the position and shape of the first field plate electrode 6, it has high barrier properties that prevent Al from diffusing into the gate insulating film 2.

[0038] Figure 3(d) shows a configuration in which the first field plate electrode 6 penetrates the second gate electrode film 3B, but does not penetrate the first gate electrode film 3A, and the lower end of the first field plate electrode 6 is embedded in the first gate electrode film 3A. The first field plate electrode 6 is not embedded in the first gate electrode film 3A. A part of the lower end side surface of the first field plate electrode 6 is in direct contact with the second gate electrode film 3B. The thickness of the first gate electrode film 3A varies depending on the lower end position of the first field plate electrode 6, but because the gate electrode 3 has the two-layer structure of the embodiment, the minimum thickness of the first gate electrode film 3A can be made sufficiently thick. The configuration shown in Figure 3(d) also has sufficiently high barrier properties to prevent Al from diffusing into the gate insulating film 2.

[0039] The minimum and maximum thickness of the first gate electrode film 3A is preferably 10 nm or more and 100 nm or less. If the thickness of the first gate electrode film 3A is too thick, the gate electrode 3 will have high resistance. Also, if the thickness of the first gate electrode film 3A is too thick, the first gate electrode film 3A and the gate insulating film 2 are more likely to peel off. If the thickness of the first gate electrode film 3A is too thin, the metal contained in the first field plate electrode 6 will easily diffuse into the gate insulating film 2 when the first field plate electrode 6 is alloyed. In other words, if the thickness of the first gate electrode film 3A is too thin, its function as a barrier metal will be reduced.

[0040] The thickness of the first gate electrode film 3A and the second gate electrode film 3B is the length of the first gate electrode film 3A in the stacking direction of the first gate electrode film 3A and the second gate electrode film 3B. The thickness of the first gate electrode film 3A can be determined from a cross-sectional view in the same direction as the schematic cross-sectional view in Figure 1.

[0041] The minimum thickness of the first gate electrode film 3A is the thickness of the thinnest part of the first gate electrode film 3A. When the first field plate electrode 6 is embedded in the first gate electrode film 3A, the minimum thickness of the first gate electrode film 3A is the thinnest part of the recessed portion of the first gate electrode film 3A where the first field plate electrode 6 is embedded.

[0042] The maximum thickness of the first gate electrode film 3A is the thickness of the thickest part of the first gate electrode film 3A. When the first field plate electrode 6 is embedded in the first gate electrode film 3A, the maximum thickness of the first gate electrode film 3A is the thickness of the thickest part of the first gate electrode film 3A excluding the recessed area where the first field plate electrode 6 is embedded.

[0043] The minimum thickness of the first gate electrode film 3A is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less.

[0044] The maximum thickness of the first gate electrode film 3A is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less.

[0045] If the difference between the minimum and maximum thickness of the first gate electrode film 3A is large, the stress difference within the first gate electrode film 3A may become large. The maximum thickness of the first gate electrode film 3A is preferably 2.0 times or more and 1.0 times or less than or equal to the minimum thickness of the first gate electrode film 3A, and more preferably 1.5 times or more and 1.0 times or less. When the above thickness relationship is satisfied, the minimum thickness of the first gate electrode film 3A is preferably 10 [nm] or more and 200 [nm] or less, and the maximum thickness of the first gate electrode film 3A is preferably 10 [nm] or more and 200 [nm] or less.

[0046] When the first field plate electrode 6 is embedded in the first gate electrode film 3A, a large difference between the minimum and maximum thickness of the first gate electrode film 3A can lead to a large stress difference within the first gate electrode film 3A. The maximum thickness of the first gate electrode film 3A is preferably 0.3 to 0.9 times, and more preferably 0.5 to 0.9 times, of the minimum thickness of the first gate electrode film 3A. When the above thickness relationship is satisfied, the minimum thickness of the first gate electrode film 3A is preferably 10 nm to 200 nm, and the maximum thickness of the first gate electrode film 3A is preferably 10 nm to 200 nm.

[0047] The maximum thickness of the second gate electrode film 3B is preferably 10 nm or more and 100 nm or less. If the thickness of the second gate electrode film 3B is too thick, the electrode thickness increases, and the gate electrode step becomes larger, resulting in poor coverage of the insulating film deposited on top of it. If the thickness of the first gate electrode film 3A is too thin, the first field plate electrode 6 is more likely to penetrate the first gate electrode film 3A. If the thickness of the first gate electrode film 3A is too thin, the stress relaxation effect is reduced. The maximum thickness of the second gate electrode film 3B is preferably 10 nm or more and 100 nm or less, and more preferably 30 nm or more and 50 nm or less. The second gate electrode film 3B may be penetrated by the first field plate electrode 6 (minimum thickness of the second gate electrode film 3B is 0 nm).

[0048] The ratio of the maximum thickness of the first gate electrode film 3A to the maximum thickness of the second gate electrode film 3B (maximum thickness of the second gate electrode film 3B / maximum thickness of the first gate electrode film 3A) is preferably 0.3 or more and 2.0 or less, and more preferably 0.5 or more and 1.5 or less.

[0049] The area of ​​the first gate electrode film 3A (the area of ​​the surface of the first gate electrode film 3A facing the second gate electrode film 3B) is preferably 0.5 times or more and 1.5 times or less, and more preferably 0.8 times or more and 1.2 times or less, the area of ​​the second gate electrode film 3B (the area of ​​the surface of the second gate electrode film 3B facing the first gate electrode film 3A).

[0050] The semiconductor device 100 includes a first field plate electrode 6. By providing a field plate electrode, electric field concentration on the electrode can be mitigated. The area enclosed by the dashed line in Figure 1 represents the first field plate electrode 6. The first field plate electrode 6 is a gate field plate electrode (hereinafter referred to as a gate FP electrode) connected to the gate electrode 3. The gate FP electrode 6 is not limited to a shape and structure intended for electric field mitigation, and may also be used as a wiring component to reduce the wiring resistance on the gate side. The gate FP electrode 6 is connected to the gate electrode 3, which has relatively high resistance, and the resistance between the gate electrode 3 and the gate FP electrode 6 is reduced.

[0051] The gate FP electrode 6 is provided on the gate electrode 3. The gate FP electrode 6 is electrically and directly connected to the gate electrode 3. The gate FP electrode 6 includes, for example, a columnar portion in contact with the gate electrode 3 and a plate-shaped portion in contact with the columnar portion. The columnar portion is the portion sandwiched between the first interlayer insulating film 9 of the gate FP electrode 6, and the portion other than the columnar portion is the plate-shaped portion. The plate-shaped portion of the gate FP electrode 6 may have steps or be flat. The columnar portion is sandwiched between the plate-shaped portion and the gate electrode 3. Preferably, the width of the plate-shaped portion of the gate FP electrode 6 in the second direction is longer than the width of the gate electrode 3 in the second direction. Preferably, the width of the columnar portion of the gate FP electrode 6 in the second direction is shorter than the width of the gate electrode 3 in the second direction. Another gate FP electrode (not shown) connected to the gate electrode 3 can be provided between the gate FP electrode 6 and the third electrode 5. The end face of the gate FP electrode 6 (including gate FP electrodes not shown, which may be used as optional) on the third electrode 5 side is preferably located on the second electrode 4 side of the end face of the second field plate electrode 7 on the third electrode 5 side in the second direction.

[0052] The gate FP electrode 6 is a conductor mainly composed of Al. The gate FP electrode 6 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95% or more Al, and even more preferably 99 wt% or more Al. In addition to Al, the gate FP electrode 6 preferably contains one or more materials selected from the group consisting of Cu, Si, and Ti.

[0053] It is preferable that the gate FP electrode 6 and the second gate electrode film 3B are in ohmic contact. It is also preferable that the second gate electrode film 3B and the first gate electrode film 3A are in ohmic contact.

[0054] The length of the plate-shaped portion of the gate FP electrode 6 in the second direction (Y direction) is preferably greater than or equal to the length of the first gate electrode film 3A in the second direction, and more preferably 1.1 times or more and 2.5 times or less the length of the first gate electrode film 3A in the second direction.

[0055] It is preferable that the end of the gate FP electrode 6 on the source electrode 4 side is located closer to the source electrode 4 than the end of the first gate electrode film 3A on the source electrode 4 side. It is also preferable that the end of the gate FP electrode 6 on the drain electrode 5 side is located closer to the drain electrode 5 than the end of the first gate electrode film 3A on the drain electrode 5 side.

[0056] The length of the plate-shaped portion of the gate FP electrode 6 in the second direction (Y direction) is preferably greater than or equal to the length of the second gate electrode film 3B in the second direction, and more preferably 1.1 times or more and 2.5 times the length of the second gate electrode film 3B in the second direction.

[0057] It is preferable that the end of the gate FP electrode 6 on the source electrode 4 side is located closer to the source electrode 4 than the end face of the second gate electrode film 3B on the source electrode 4 side. It is also preferable that the end of the gate FP electrode 6 on the drain electrode 5 side is located closer to the drain electrode 5 than the end of the second gate electrode film 3B on the drain electrode 5 side.

[0058] The length of the columnar portion of the gate FP electrode 6 in the second direction (Y direction) is preferably less than the length of the first gate electrode film 3A in the second direction, and more preferably 0.2 times or more and 0.9 times or less the length of the first gate electrode film 3A in the second direction. The length of the first gate electrode film 3A in the second direction is preferably 150 nm or more longer than the length of the columnar portion of the gate FP electrode in the second direction, and more preferably 150 nm or more and 1000 nm or less longer.

[0059] The length of the columnar portion of the gate FP electrode in the second direction (Y direction) is preferably less than the length of the second gate electrode film 3B in the second direction, and more preferably 0.2 times or more and 0.9 times or less the length of the second gate electrode film 3B in the second direction. The length of the second gate electrode film 3B in the second direction is preferably 150 nm or more longer than the length of the columnar portion of the gate FP electrode in the second direction, and more preferably 150 nm or more and 1000 nm or less longer.

[0060] The second electrode 4 is a source electrode having a plurality of fingers extending in the first direction. Each comb-shaped finger of the source electrode 4 extends in the first direction, and each finger is aligned in the second direction (Y direction). For example, the fingers of the source electrode 4 are sandwiched between the fingers of the gate electrode 3. The source electrode 4 is provided on the semiconductor layer 1, more specifically on the channel layer 1C and the barrier layer 1D. The source electrode 4 is electrically connected to the channel layer 1C and the barrier layer 1D. For example, the source electrode 4 or the second field plate electrode 7 is connected to the second electrode pad (source electrode pad) 4A. When the second field plate electrode 7 is connected to the second electrode pad 4A, for example, the source electrode 4 has the shape of only the finger portion.

[0061] The source electrode 4 is, for example, a metal electrode. The source electrode 4 is, for example, an aluminum film mainly composed of aluminum and containing 50 wt% or more aluminum, an aluminum alloy film containing 50 wt% or more aluminum, or a multilayer film of titanium (Ti) and aluminum (Al). It is desirable that there be an ohmic contact between the source electrode 4 and the barrier layer 1D.

[0062] The semiconductor device 100 preferably includes a second field plate electrode 7. Providing a field plate electrode can mitigate electric field concentration on the electrode. The area enclosed by the dashed line in Figure 1 represents the second field plate electrode 7. The second field plate electrode 7 is a source field plate electrode (hereinafter referred to as the first source FP electrode) connected to the source electrode 4. The first source FP electrode 7 is positioned above the source electrode 4, the gate electrode 3 and gate FP electrode 6 that sandwich the intermediate source electrode 4, so that the source electrode 4 is located in the middle or approximately in the middle.

[0063] The first source FP electrode 7 is a conductor mainly composed of Al. The first source FP electrode 7 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95% or more Al, and even more preferably 99 wt% or more Al. The gate FP electrode 6 preferably contains one or more materials selected from the group consisting of Cu, Si, and Ti in addition to Al.

[0064] The third electrode 5 is a drain electrode having a plurality of fingers extending in the first direction (X direction). Each comb-shaped finger of the drain electrode 5 extends in the first direction, and each finger is aligned in the second direction (Y direction). The fingers of the drain electrode 5 are oriented in the opposite direction to the fingers of the source electrode 4, that is, the source electrode 4 and the drain electrode 5 are positioned facing each other. The drain electrode 5 is provided on the channel layer 1C and the barrier layer 1D. The drain electrode 5 is electrically connected to the channel layer 1C and the barrier layer 1D. The drain electrode 5 is in contact with the barrier layer 1D, for example. For example, the drain electrode 5 or the third field plate electrode 8 (drain FP electrode) is connected to the third electrode pad (drain electrode pad) 5A. When the drain FP electrode 8 is connected to the third electrode pad 5A, for example, the drain electrode 5 has the shape of only the finger portion.

[0065] The drain electrode 5 is, for example, a metal electrode. The drain electrode 5 is, for example, an aluminum film mainly composed of aluminum and containing 50 [wt%] or more aluminum, an aluminum alloy film containing 50 [wt%] or more aluminum, or a multilayer film of titanium (Ti) and aluminum (Al). It is desirable that there is an ohmic contact between the drain electrode 5 and the barrier layer 1D.

[0066] The distance between the source electrode 4 and the drain electrode 5 is, for example, between 5 [μm] and 30 [μm].

[0067] Furthermore, the source electrode 4 and drain electrode 5 can also be configured to be in direct contact with the channel layer 1C.

[0068] The drain FP electrode 8 is a conductor mainly composed of Al. The drain FP electrode 8 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95% or more Al, and even more preferably 99 wt% or more Al. The gate FP electrode 6 preferably contains one or more materials selected from the group consisting of Cu, Si, and Ti in addition to Al.

[0069] The second insulating film 9 is an interlayer insulating film (hereinafter referred to as the first interlayer insulating film 9). The first interlayer insulating film 9 is provided between the gate insulating film 2 and the third insulating film 10. The first interlayer insulating film 9 covers the gate electrode 3, the source electrode 4, and the drain electrode 5. The first interlayer insulating film 9 is, for example, an oxide or a nitride. The first interlayer insulating film 9 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-dielectric constant (high-k) material. Examples of high-k materials include hafnium oxide (HfO2). The first interlayer insulating film 9 is a low-density insulating film. The first interlayer insulating film 9 is a less dense insulating film than the gate insulating film 2. Also, the thickness of the first interlayer insulating film 9 is thicker than the gate insulating film 2, for example, 20 nm to 500 nm. In the semiconductor device 100 of Figure 1, the first interlayer insulating film 9 has a step. By planarizing the first interlayer insulating film 9 after its formation, a first interlayer insulating film 9 without any steps can be used in the semiconductor device 100.

[0070] The third insulating film 10 is an interlayer insulating film (hereinafter referred to as the second interlayer insulating film 10). The second interlayer insulating film 10 is provided on top of the first interlayer insulating film 9. The second interlayer insulating film 10 covers the gate FP electrode 6, the source electrode 4, and the drain electrode 5. The second interlayer insulating film 10 is, for example, an oxide or a nitride. The second interlayer insulating film 10 is, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-dielectric constant (high-k) material. Examples of high-k materials include hafnium oxide (HfO2). The thickness of the second interlayer insulating film 10 is thicker than the gate insulating film 2, for example, 50 nm to 2000 nm.

[0071] The manufacturing method of the semiconductor device 100 will be described below with reference to the schematic process diagrams in Figures 5 to 13. A flowchart of the manufacturing method of the semiconductor device 100 is shown in Figure 4. The manufacturing method of the semiconductor device 100 includes the steps of: providing a first insulating film (gate insulating film) 2 on a semiconductor layer 1 (S01); forming a first electrode film (first gate electrode film) 3A and a second electrode film (second gate electrode film) 3B on the first insulating film 2 (S02); forming a second insulating film (first interlayer insulating film) 9 on the first insulating film 2 and the second gate electrode film 3B (S03); opening the second insulating film 9 on the second gate electrode film 3B to form a first via V1 (S04); forming a first field plate electrode (gate FP electrode) 6 on the first via V1 (S05); and heating the first field plate electrode 6 and the second gate electrode film 3B to alloy the first field plate electrode 6 and the second gate electrode film 3B (S06).

[0072] Referring to the schematic process diagram in Figure 5, the process (S01) of providing a first insulating film (gate insulating film) 2 on the semiconductor layer 1 will be explained. By providing the gate insulating film 2 on the semiconductor layer 1, a component 101 with the gate insulating film 2 provided on the semiconductor layer 1 is obtained. For example, SiN or SiO2 can be formed by plasma CVD (Chemical Vapor Deposition).

[0073] Referring to the schematic process diagram in Figure 6, the process (S02) of forming the first gate electrode film 3A and the second gate electrode film 3B on the gate insulating film 2 will be described. For example, a solid first gate electrode film 3A is formed on the gate insulating film 2 of member 101. For example, a solid second gate electrode film 3B is formed on the solid first gate electrode film 3A. Then, the first gate electrode film 3A and the second gate electrode film 3B are patterned. Then, member 102 is obtained on which the patterned and stacked first gate electrode film 3A and second gate electrode film 3B are provided on the gate insulating film 2.

[0074] In the step (S02) of forming a first gate electrode film 3A and a second gate electrode film 3B on the gate insulating film 2, for example, one or more or one selected from the group consisting of TiN, WN, and TaN is deposited by sputtering to obtain the first gate electrode film 3A. When Al diffuses from the gate FP electrode 6 into the TiN film by alloying treatment by heating, the part where Al has diffused becomes TiAlN, and the first gate electrode film 3A becomes a TiAlN film.

[0075] In the step (S02) of forming a first gate electrode film 3A and a second gate electrode film 3B on the gate insulating film 2, for example, one or more or one selected from the group consisting of Ti, W, and Ta is deposited by sputtering to obtain the second gate electrode film 3B. When Al diffuses from the gate FP electrode 6 into the Ti film by alloying treatment by heating, the diffused portion becomes a TiAl alloy, and the second gate electrode film 3B becomes a TiAl film.

[0076] Referring to the schematic process diagram in Figure 7, the process (S03) of forming the first interlayer insulating film 9 on the first insulating film 2 and the second gate electrode film 3B will be described. The first interlayer insulating film 9 is formed on the gate insulating film 2 and the second gate electrode film 3B of member 102 to obtain member 103. After the formation of the first interlayer insulating film 9, planarization treatment such as CMP (chemical mechanical polishing) may be performed as needed.

[0077] Referring to the schematic process diagram in Figure 8, the process (S04) of opening the first interlayer insulating film 9 on the second gate electrode film 3B to form the first via V1 will be described. The first interlayer insulating film 9 of member 103 is opened to form the first via V1. The first via V1 is obtained by processing the first interlayer insulating film 9, for example by etching using a mask, so that the second gate electrode film 3B is exposed. The first via V1 penetrates the first interlayer insulating film 9. The first via V1 may penetrate the second gate electrode film 3B, but it does not penetrate the first gate electrode film 3A. If it penetrates the first gate electrode film 3A, the barrier properties of the first gate electrode film 3A will be greatly reduced, so Al and Ti will diffuse into the gate insulating film 2 during the heat treatment, making the gate insulating film 2 more susceptible to destruction.

[0078] The minimum thickness of the first gate electrode film 3A after processing the first via V1 is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less. The maximum thickness of the first gate electrode film 3A after processing the first via V1 is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less.

[0079] The diameter (maximum diameter) of the first via V1 is typically preferably between 100 nm and 1000 nm.

[0080] Referring to the schematic process diagram in Figure 9, the process (S05) of forming the first field plate electrode (gate FP electrode) 6 in the first via V1 will be described. A gate FP electrode 6X (the gate FP electrode 6 before heating is shown as gate FP electrode 6X) is formed in the first via V1 and on the first interlayer insulating film 9 of member 104 to obtain member 105. A solid film of a conductive material mainly composed of Al is formed on the first interlayer insulating film 9 and in the first via V1, and the gate FP electrode 6 is formed by processing it to the shape of the gate FP electrode 6. The conductive material mainly composed of Al contains 80 wt% or more of Al, preferably 90 wt% or more of Al, more preferably 95% or more of Al, and even more preferably 99 wt% or more of Al. The gate FP electrode 6 before heat treatment may also contain Cu and / or Si in addition to Al.

[0081] Referring to the schematic process diagram in Figure 10, the step (S06) of heating the first field plate electrode 6 and the second gate electrode film 3B to alloy them will be described. The alloying treatment by heating is performed after the step (S05) of forming the first field plate electrode (gate FP electrode) 6 on the first via V1. The heat treatment, including the alloying treatment by heating, may be performed on any of the members 105, 106, 107, 108, 109, or 110. The heat treatment, including the alloying treatment by heating, can be performed multiple times.

[0082] The alloying treatment by heating is typically preferably carried out at 550°C to 650°C for 10 to 60 minutes. The heating is preferably performed in an N2 atmosphere. When the heating treatment is performed, the metals contained in the second gate electrode film 3B and the gate FP electrode 6 diffuse with each other, causing the second gate electrode film 3B and the gate FP electrode 6 to become an alloy.

[0083] For example, if the second gate electrode film 3B contains Ti and the gate FP electrode 6 contains Al, Ti diffuses into the gate FP electrode 6, where Al and Ti alloy together, and Al diffuses into the second gate electrode film 3B, where Ti and Al alloy together.

[0084] The formation of the source electrode 4, drain electrode 5, first source FP electrode 7, drain FP electrode 8, and second interlayer insulating film 10 will also be explained with reference to Figures 11 to 14.

[0085] The schematic process diagram in Figure 11 relates to the process of forming a second via V2 for the source electrode 4 and a third via V3 for the drain electrode 5 on member 105. In this process, member 106 is obtained in which the second via V2 and the third via V3, which penetrate the gate insulating film 2 and the first interlayer insulating film 9, are formed. The gate electrode 3 shown in the schematic process diagram in Figure 11 is sandwiched between the second via V2 and the third via V3 in the Y direction. The second via V2 and the third via V3 are formed, for example, by etching using a mask.

[0086] The schematic process diagram in Figure 11 relates to the process of forming the source electrode 4 and the drain electrode 5 on member 106. In the schematic process diagram in Figure 11, electrodes are formed before the heat treatment for alloying. Therefore, in the schematic process diagram in Figure 11 and other diagrams, the precursor of the source electrode 4 before alloying by heat treatment is shown as source electrode 4X, and the precursor of the drain electrode 5 before alloying by heat treatment is shown as drain electrode 5X. Member 107 in Figure 11 is obtained by forming the source electrode 4X and the drain electrode 5X on member 106. Member 107 with the source electrode 4X and drain electrode 5X formed is obtained by depositing a metal film on member 106 and patterning it.

[0087] The schematic diagram of the process in Figure 12 relates to the process of forming a second interlayer insulating film 10 on the first interlayer insulating film 9 of member 107. Member 108 is obtained by forming the second interlayer insulating film 10 on the first interlayer insulating film 9 of member 107, the source electrode 4X and the drain electrode 5X, and the source electrode 4X and drain electrode 5X. The second interlayer insulating film 10 is preferably a film that has undergone a planarization treatment.

[0088] The schematic diagram of the process in Figure 13 relates to the process of forming a fourth via V4 by opening the second interlayer insulating film 10 on the source electrode 4X of member 108, and forming a fifth via V5 by opening the second interlayer insulating film 10 on the drain electrode 5X. In this process, member 109 is obtained in which two vias (fourth via V4 and fifth via V5) are provided in the second interlayer insulating film 10. The fourth via V4 and fifth via V5 are formed, for example, by etching using a mask.

[0089] Figure 14 shows a schematic process diagram relating to the process of forming a first source FP electrode 7 and a drain FP electrode 8 on member 109. In the schematic process diagram of Figure 14, the FP electrodes are formed before the heat treatment for alloying. Therefore, in the schematic process diagram of Figure 14, the precursor of the first source FP electrode 7 before alloying by heat treatment is shown as the first source FP electrode 7X, and the precursor of the drain FP electrode 8 before alloying by heat treatment is shown as the drain FP electrode 8X. The member 110 shown in Figure 14 is obtained by forming the first source FP electrode 7X and the drain FP electrode 8X on member 109. By depositing a metal film on member 109 and patterning it, member 110 with the first source FP electrode 7X and drain FP electrode 8X formed on it is obtained.

[0090] Let's consider the case where the second gate electrode film 3B is absent during the alloying heat treatment. If the second gate electrode film 3B is absent, one possible method is to thicken the first gate electrode film 3A so that it does not penetrate when forming the first via V1. If the first gate electrode film 3A is thickened, for example, TiN or TiW may be used for the first gate electrode film 3A, and a large film stress will be generated due to the stress difference between the film in contact with the first gate electrode film 3A during heating. Then, after heating, the gate insulating film 2 and the first gate electrode film 3A are prone to delamination. If the gate insulating film 2 and the first gate electrode film 3A delaminate, the bias will not be applied, and the semiconductor device 100 will not be able to be turned off.

[0091] Let's consider the case where the second gate electrode film 3B is absent during the alloying heat treatment. If the second gate electrode film 3B is absent, for example, one method is to not make the first gate electrode film 3A thick when forming the first via V1. However, if the film is made thicker, the gate electrode 3 will become highly resistive. If the first gate electrode film 3A is not made thick enough, when forming the first via V1, the first via V1 will penetrate the first interlayer insulating film 9 with high certainty, and the first gate electrode film 3A will also be etched (over-etched). If the first gate electrode film 3A is deeply over-etched, the thickness of the first gate electrode film 3A in the etched portion will be thin. The thin first gate electrode film 3A has reduced metal diffusion barrier properties. When the barrier properties of the first gate electrode film 3A are reduced, Al and other elements from the gate FP electrode 6 diffuse into the gate insulating film 2 during heating of the first gate electrode film 3A. The diffusion of Al and other elements into the gate insulating film 2 causes the gate insulating film 2 to deteriorate. A semiconductor device with a deteriorated gate insulating film 2 will have a lower breakdown strength. Furthermore, because there is no second gate electrode film 3B, which is a film that relieves the thermal stress of the first gate electrode film 3A, a large film stress is generated due to the stress difference between the films in contact with the first gate electrode film 3A during heating. As a result, the gate insulating film 2 and the first gate electrode film 3A are prone to delamination after heating. When the gate insulating film 2 and the first gate electrode film 3A delaminate, the bias is lost, and the semiconductor device 100 cannot be turned off. Increasing the thickness of the first gate electrode film 3A increases the film stress, making it easier for the first gate electrode film 3A to delaminate from the gate insulating film 2.

[0092] During the alloying heat treatment, the presence of the second gate electrode film 3B prevents or reduces over-etching of the first gate electrode film 3A. By reducing over-etching, the barrier properties of the first gate electrode film 3A can be maintained at a high level, and degradation due to diffusion of Al and other elements from the gate FP electrode 6 into the gate insulating film 2 can be suppressed. Furthermore, since one of the first gate electrode film 3A and the second gate electrode film 3B has strong tensile stress and the other has strong compressive stress, the thermal stress of the first gate electrode film 3A can be relaxed, preventing delamination between the gate insulating film 2 and the first gate electrode film 3A.

[0093] During the heat treatment process for alloying, if some elements diffuse, the interface between the films may become unclear.

[0094] For example, compared to a configuration in which a single TiN film without the second gate electrode film 3B is provided on the SiN film (gate insulating film 2), the configuration in which a TiN and Ti multilayer film (TiN with a TiN thickness of 50 nm and Ti with a Ti thickness of 50 nm) is provided on the SiN film (gate insulating film 2) showed a reduction of more than 50% in the film stress [GPa] in the plane direction of the film after heat treatment. Furthermore, compared to a configuration in which a single TiN film is provided on the SiN film (gate insulating film 2) without using the second gate electrode film 3B, the configuration in which a TiN and Ti multilayer film (TiN with a TiN thickness of 50 nm and Ti with a Ti thickness of 10 nm) is provided on the SiN film (gate insulating film 2) also showed a reduction of more than 20% in the film stress [GPa] in the plane direction of the film after heat treatment.

[0095] By using both the first gate electrode film 3A and the second gate electrode film 3B, two factors that reduce reliability—degradation of the gate insulating film 2 and delamination between the gate insulating film 2 and the first gate electrode film 3A—can be minimized.

[0096] A modified version of the manufacturing method for the semiconductor device 100 will be described with reference to the schematic process diagrams in Figures 15 and 16. The modified version of the manufacturing method for the semiconductor device 100 differs from the previously described manufacturing method in that the first via V1, the second via V2, and the third via V3 are opened simultaneously, and the gate FP electrode 6X, the first source FP electrode 7X, and the drain FP electrode 8X are formed simultaneously.

[0097] Referring to the schematic process diagram in Figure 15, the process (S04) of forming the first via V1 by opening the first interlayer insulating film 9 on the second gate electrode film 3B will be described. The first via V1, second via V2, and third via V3 are opened simultaneously in member 104 to obtain member 111 as shown in Figure 15. The three vias can be processed appropriately by adjusting the etching conditions, the thickness of the gate insulating film 2, the thickness of the first gate electrode film 3A, the thickness of the second gate electrode film 3B, and the thickness of the first interlayer insulating film. For example, the three vias can be processed appropriately by setting conditions so that the second via V2 and third via V3 are processed to an appropriate depth, and the first gate electrode film 3A is not over-etched, or by reducing the thickness of the first gate electrode film 3A that is over-etched. Processing three vias in a single process can significantly reduce the number of steps.

[0098] Referring to the schematic diagram of the process in Figure 15, the process (S05) of forming the first field plate electrode (gate FP electrode) 6 in the first via V1 will be described. The gate FP electrode 6X, source electrode 4X, and drain electrode 5X are formed in the first via V1 and on the first interlayer insulating film 9 of member 111 to obtain member 112. Each electrode is formed by first forming a solid film and then processing it into the electrode shape. Processing multiple electrodes simultaneously also contributes to reducing the number of steps involved in electrode formation.

[0099] Even in modified versions of the manufacturing method for the semiconductor device 100, delamination between the gate insulating film 2 and the first gate electrode film 3A can be prevented, and degradation of the gate insulating film 2 can be prevented. By adopting a stacked structure of the first gate electrode film 3A and the second gate electrode film 3B, over-etching of the first gate electrode film 3A can be prevented, while the second via V2 of the source electrode 4 and the third via V3 of the drain electrode 5 are processed together with the gate FP electrode 6, thereby contributing to a reduction in the number of processes.

[0100] (Second Embodiment) The second embodiment relates to a semiconductor device and a method for manufacturing a semiconductor device. The semiconductor device of the second embodiment is a modified example of the semiconductor device 100 of the first embodiment. Details common to both the semiconductor device 200 of the second embodiment and the semiconductor device 100 of the first embodiment will not be explained. Furthermore, the details described in the second embodiment are applicable to the first embodiment.

[0101] Figures 16 and 17 show schematic cross-sectional views of the semiconductor device 200 of the second embodiment. The semiconductor device 200 includes a semiconductor layer 1, a first insulating film (gate insulating film) 2, a first electrode (gate electrode) 3, a second electrode (source electrode) 4, a third electrode (drain electrode) 5, a first field plate electrode (gate FP electrode) 6, a second field plate electrode (first source FP electrode) 7, a third field plate electrode (drain FP electrode) 8, a second insulating film (first interlayer insulating film) 9, a third insulating film (second interlayer insulating film) 10, a fourth field plate electrode (second source FP electrode) 11, and a conductive film 13. The element isolation region includes a high-resistance region 12 as shown in the schematic diagram of Figure 17.

[0102] Figure 16 is a schematic diagram of the semiconductor device 200 in the same position as in Figure 1. Figure 17 is a schematic cross-sectional view of the vicinity of the fourth field plate electrode 11 in the element isolation region located in the X direction from the cross-section of Figure 16.

[0103] The semiconductor device 200 differs from the semiconductor device 100 of the first embodiment in that it has a second source FP electrode 11 and a conductive film 13.

[0104] The second source FP electrode 11 is electrically connected to the source electrode 4. The second source FP electrode 11 is located between the gate electrode 3 and the drain electrode 5. The second source FP electrode 11 extends in the X direction and is aligned in the Y direction, similar to the first source FP electrode 7. By providing the second source FP electrode 11, electric field concentration on the electrodes can be mitigated.

[0105] The position and shape of the second source FP electrode 11 are not particularly limited. In the element region, the second source FP electrode 11 is not electrically connected to the source electrode 4 or the first source FP electrode 7, which are components electrically connected to the source electrode 4. In the high-resistance region 12, the second source FP electrode 11 is electrically connected to the source electrode 4 and the first source FP electrode 7 via the conductive film 13.

[0106] The second source FP electrode 11 is a conductor mainly composed of Al. The second source FP electrode 11 contains 80 wt% or more Al, preferably 90 wt% or more Al, more preferably 95% or more Al, and even more preferably 99 wt% or more Al. The second source FP electrode 11 is preferably an alloy or metal silicide containing one or more elements selected from the group consisting of Cu, Si, and Ti in addition to Al.

[0107] The conductive film 13 is provided on the semiconductor layer 1 in the element isolation region. The conductive film 13 has a first conductive film 13A and a second conductive film 13B. Except for the position where the first conductive film 13A is formed, the position where the second conductive film 13B is formed, and the fact that the first conductive film 13A and the second conductive film 13B are electrically connected to the second source FP electrode 11, the first conductive film 13A is the same as the first gate electrode film 3A and the second conductive film 13B is the same as the second gate electrode film 3B.

[0108] When the first conductive film 13A and the first gate electrode film 3A are formed by the same process, it is preferable that the elements contained in the first conductive film 13A and the first gate electrode film 3A are the same.

[0109] When the second conductive film 13B and the second gate electrode film 3B are formed by the same process, it is preferable that the elements contained in the second conductive film 13B and the second gate electrode film 3B are the same.

[0110] The minimum and maximum thickness of the first conductive film 13A is preferably 10 nm or more and 100 nm or less. If the thickness of the first conductive film 13A is too thick, the gate electrode 3 will have high resistance. Also, if the thickness of the first conductive film 13A is too thick, the first conductive film 13A and the gate insulating film 2 will be more likely to peel off. If the thickness of the first conductive film 13A is too thin, the metal contained in the second source FP electrode 11 will be more likely to diffuse into the gate insulating film 2 when the second source FP electrode 11 is alloyed. In other words, if the thickness of the first gate electrode film 3A is too thin, its function as a barrier metal will be reduced.

[0111] The thickness of the first conductive film 13A and the second gate electrode film 3B is the length of the first conductive film 13A in the stacking direction of the first conductive film 13A and the second conductive film 13B. The thickness of the first conductive film 13A can be determined from a cross-sectional view in the same direction as the schematic cross-sectional view in Figure 1.

[0112] The minimum thickness of the first conductive film 13A is the thickness of the thinnest part of the first conductive film 13A. When the second source FP electrode 11 is embedded in the first conductive film 13A, the minimum thickness of the first conductive film 13A is the thinnest part of the recessed portion of the first conductive film 13A where the second source FP electrode 11 is embedded.

[0113] The maximum thickness of the first conductive film 13A is the thickness of the thickest part of the first conductive film 13A. When the second source FP electrode 11 is embedded in the first conductive film 13A, the maximum thickness of the first conductive film 13A is the thickness of the thickest part of the first conductive film 13A excluding the recessed area where the second source FP electrode 11 is embedded.

[0114] The minimum thickness of the first conductive film 13A is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less.

[0115] The maximum thickness of the first conductive film 13A is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less.

[0116] If the difference between the minimum and maximum thickness of the first conductive film 13A is large, the stress difference within the first conductive film 13A may become large. The maximum thickness of the first conductive film 13A is preferably 0.3 times or more and 1.0 times or less than the minimum thickness of the first gate electrode film 3A, and more preferably 0.5 times or more and 1.0 times or less. When the above thickness relationship is satisfied, the minimum thickness of the first conductive film 13A is preferably 10 [nm] or more and 200 [nm] or less, and the maximum thickness of the first conductive film 13A is preferably 10 [nm] or more and 200 [nm] or less.

[0117] When the second source FP electrode 11 is embedded in the first conductive film 13A, a large difference between the minimum and maximum thicknesses of the first conductive film 13A can lead to a large stress difference within the first conductive film 13A. The maximum thickness of the first conductive film 13A is preferably 0.3 to 0.9 times, and more preferably 0.5 to 0.9 times, the minimum thickness of the first gate electrode film 3A. When the above thickness relationship is satisfied, the minimum thickness of the first conductive film 13A is preferably 10 nm to 200 nm, and the maximum thickness of the first conductive film 13A is preferably 10 nm to 200 nm.

[0118] The maximum thickness of the second conductive film 13B is preferably 10 nm or more and 100 nm or less. If the thickness of the second conductive film 13B is too thick, the electrode thickness increases, and the step difference of the gate electrode becomes larger, resulting in poor coverage of the insulating film deposited on top of it. If the thickness of the first conductive film 13A is too thin, the second source FP electrode 11 is more likely to penetrate the first conductive film 13A. If the thickness of the first conductive film 13A is too thin, the stress relaxation effect is reduced. The maximum thickness of the second conductive film 13B is preferably 10 nm or more and 200 nm or less, and more preferably 10 nm or more and 100 nm or less. The second conductive film 13B may be penetrated by the second source FP electrode 11 (minimum thickness of the second conductive film 13B is 0 nm).

[0119] The ratio of the maximum thickness of the first conductive film 13A to the maximum thickness of the second conductive film 13B (maximum thickness of the second conductive film 13B / maximum thickness of the first conductive film 13A) is preferably 0.3 or more and 2.0 or less, and more preferably 0.5 or more and 1.5 or less.

[0120] The area of ​​the first conductive film 13A (the area of ​​the surface of the first conductive film 13A facing the second conductive film 13B) is preferably 0.5 times or more and 1.5 times or less, and more preferably 0.8 times or more and 1.2 times or less, the area of ​​the second conductive film 13B (the area of ​​the surface of the second conductive film 13B facing the first conductive film 13A).

[0121] It is preferable that the second source FP electrode 11 and the second conductive film 13B are in ohmic contact. It is also preferable that the second conductive film 13B and the first conductive film 13A are in ohmic contact.

[0122] The length of the plate-shaped portion of the second source FP electrode 11 in the second direction (Y direction) is preferably greater than or equal to the length of the first conductive film 13A in the second direction, and more preferably 1.1 times or more and 2.5 times or less the length of the first conductive film 13A in the second direction.

[0123] Preferably, the end of the second source FP electrode 11 on the source electrode 4 side is located closer to the source electrode 4 than the end of the first conductive film 13A on the source electrode 4 side in the second direction. Preferably, the end of the second source FP electrode 11 on the drain electrode 5 side is located closer to the drain electrode 5 than the end of the first conductive film 13A on the drain electrode 5 side.

[0124] The length of the plate-shaped portion of the second source FP electrode 11 in the second direction (Y direction) is preferably greater than or equal to the length of the second conductive film 13B in the second direction, and more preferably 1.1 times or more and 2.5 times or less the length of the second conductive film 13B in the second direction.

[0125] Preferably, the end of the second source FP electrode 11 on the source electrode 4 side is located closer to the source electrode 4 than the end face of the second gate electrode film 3B on the source electrode 4 side in the second direction. Preferably, the end of the second source FP electrode 11 on the drain electrode 5 side is located closer to the drain electrode 5 than the end of the second conductive film 13B on the drain electrode 5 side.

[0126] The length of the columnar portion of the second source FP electrode 11 in the second direction (Y direction) is preferably less than the length of the first conductive film 13A in the second direction, and more preferably 0.2 times or more and 0.9 times or less the length of the first conductive film 13A in the second direction. The length of the first conductive film 13A in the second direction is preferably 150 [nm] or more longer than the length of the columnar portion of the second source FP electrode 11 in the second direction, and more preferably 150 [nm] or more and 1000 [nm] or less longer.

[0127] The length of the columnar portion of the second source FP electrode 11 in the second direction (Y direction) is preferably less than the length of the second gate electrode film 3B in the second direction, and more preferably 0.2 times or more and 0.9 times or less the length of the second conductive film 13B in the second direction. The length of the second conductive film 13B in the second direction is preferably 150 [nm] or more longer than the length of the columnar portion of the second source FP electrode 11 in the second direction, and more preferably 150 [nm] or more and 1000 [nm] or less longer.

[0128] If the semiconductor device 200 has a source FP electrode (not shown), it is preferable to provide a conductive film equivalent to the conductive film 13 between the source FP electrode (not shown) and the gate insulating film 2. The conductive film present between the source FP electrode (not shown) and the gate insulating film 2 is preferably electrically and directly connected to the conductive film 13 of the second source FP electrode 11, or a conductive film with a larger area than the conductive film 13 shown in Figure 17 is used, and the larger area conductive film is connected to the second source FP electrode 11 and the source FP electrode (not shown).

[0129] A method for manufacturing the semiconductor device 200 of the second embodiment will now be described. The conductive film 13 is formed in the step (S02) of forming the first gate electrode film 3A and the second gate electrode film 3B on the gate insulating film 2 by patterning such that the first gate electrode film 3A, the second gate electrode film 3B, the first conductive film 13A, and the second conductive film 13B of the gate electrode 3 remain. Then, the second source FP electrode 11 is formed on the second conductive film 13B in the same way as the first gate FP electrode 6, and the second source FP electrode 11 and the second conductive film 13B are alloyed by a heat treatment that causes alloying. Note that the gate electrode 3 and the conductive film 13 may be created separately in different steps.

[0130] A conductive film 13 with a configuration that is less susceptible to over-etching can also be provided beneath the second source FP electrode 11. Similar to the gate electrode 3, the conductive film 13 also suppresses the degradation of the gate insulating film 2 and the delamination between the conductive film 13 and the gate insulating film 2, contributing to improved reliability of the semiconductor device 200.

[0131] (Third embodiment) The third embodiment relates to a semiconductor device 300 and a method for manufacturing the semiconductor device 300. The semiconductor device 300 of the third embodiment is a modified example of the semiconductor device 100 of the first embodiment or the semiconductor device 200 of the second embodiment. Details common to the semiconductor device 100 of the first embodiment through the semiconductor device 300 of the third embodiment will not be explained. Furthermore, the details described in the third embodiment can be applied to the first or second embodiment.

[0132] Figure 19 shows a schematic cross-sectional view of the semiconductor device 300 of the third embodiment. In the semiconductor device 300 of the third embodiment, a trench is provided in the semiconductor layer 1 beneath the gate electrode 3, and the gate insulating film 2 and gate electrode 3 are provided along the shape of the trench. A first gate electrode film 3A is provided inside the trench, but a second gate electrode film 3B may be provided on the central side of the trench. By adopting a trench structure, the semiconductor device 300 becomes a normally-off type GaN-HEMT. The configuration of the gate electrode 3 of the embodiment can also be adopted in a normally-off type configuration.

[0133] A second source FP electrode 11 can also be formed on the gate insulating film 2 between the gate electrode 3 and the drain electrode 5. The second source FP electrode of the semiconductor device 300 does not include a columnar portion but includes a plate-like portion. The plate-like portion of the second source FP electrode 11 is in direct contact with the second conductive film 13B. If the second source FP electrode 11 is placed directly on the gate insulating film 2, the gate insulating film 2 may deteriorate. Even when the second source FP electrode 11 is placed on the gate insulating film 2, it is preferable to use the conductive film 13 to prevent deterioration of the gate insulating film 2.

[0134] In the specification, elements are represented by their element symbols.

[0135] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0136] 100: Semiconductor Device 1: Semiconductor layer 1A: Circuit board 1B: Buffer layer 1C: Channel layer 1D: Barrier layer 2: First insulating film (gate insulating film) 3: First electrode (gate electrode) 3A: First electrode film (first gate electrode film) 3B: Second electrode film (second gate electrode film) 3C: First electrode pad 4: Second electrode (source electrode) 4A: Second electrode pad 4X: Source electrode 5: Third electrode (drain electrode) 5A: Third electrode pad 5X: Drain electrode 6: First field plate electrode (gate FP electrode) 6X: Gate FP electrode 7: Second field plate electrode (first source FP electrode) 7X: First source FP electrode 8: Third field plate electrode (drain FP electrode) 8X: Drain FP electrode 9: Second insulating film (first interlayer insulating film) 10: Third insulating film (second interlayer insulating film) 11: Fourth field plate electrode (second source FP electrode) 12: High resistance region 13: Conductive film 13A: First conductive film 13B: Second conductive film 100: Semiconductor Device 101: Components 102: Components 103: Components 104: Components 105: Components 106: Components 107: Components 108: Components 109: Components 110: Components 111: Components 112: Components 200: Semiconductor equipment 300: Semiconductor equipment V1: First via V2: Second Via V3: Third Via V4: Fourth Via V5: Fifth Via

Claims

1. Semiconductor layer, A first insulating film provided on the semiconductor layer, A first electrode film provided on the first insulating film, A second electrode film provided on the first electrode film, The device comprises a first field plate electrode provided on the second electrode film, The lower end of the first field plate electrode is located on a second surface that contacts the second electrode film side rather than a first surface that contacts the first insulating film of the first electrode film. The first field plate electrode is a semiconductor device embedded in the second electrode film.

2. The semiconductor device according to claim 1, wherein the semiconductor layer includes a nitride semiconductor layer.

3. The semiconductor device according to claim 1, wherein one of the first electrode film and the second electrode film is subject to strong tensile stress and the other is subject to strong compressive stress.

4. The semiconductor device according to claim 1, wherein the first electrode film and the second electrode film are films with different compositions.

5. Semiconductor layer, A first insulating film provided on the semiconductor layer, A first electrode film provided on the first insulating film, A second electrode film provided on the first electrode film, The device comprises a first field plate electrode provided on the second electrode film, The lower end of the first field plate electrode is located on a second surface that contacts the second electrode film side rather than a first surface that contacts the first insulating film of the first electrode film. The first field plate electrode is a semiconductor device embedded in the first electrode film.

6. The semiconductor device according to claim 1, wherein the minimum and maximum thickness of the first electrode film is 10 nm or more and 200 nm or less.

7. Semiconductor layer, A first insulating film provided on the semiconductor layer, A first electrode film provided on the first insulating film, A second electrode film provided on the first electrode film, The device comprises a first field plate electrode provided on the second electrode film, A semiconductor device in which the first distance between the first interface between the first electrode film and the second electrode film and the second interface between the first field plate electrode and the second electrode film, which faces the semiconductor layer side, is smaller than the second distance between the surface of the second electrode film facing the first interface, excluding the second interface, and the first interface.

8. The semiconductor device according to claim 7, wherein the lower end of the first field plate electrode is located on a second surface that is in contact with the second electrode film side rather than a first surface that is in contact with the first insulating film of the first electrode film.

9. A step of providing a first insulating film on a semiconductor layer, A step of forming a first electrode film and a second electrode film on the first insulating film, A step of forming a second insulating film on the first insulating film and the second electrode film, A step of opening the second insulating film on the second electrode film to form a first via, The process involves forming a first field plate electrode on the first via, A step of heating the first field plate electrode and the second electrode film to alloy the first field plate electrode and the second electrode film, A method for manufacturing a semiconductor device having [a certain feature].

10. The method for manufacturing a semiconductor device according to claim 9, wherein the first via does not penetrate the first electrode film.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the minimum thickness of the first electrode film after the formation of the first via is 10 nm or more and 100 nm or less.

12. The semiconductor device according to claim 9, wherein the diameter of the first via is 100 nm or more and 1000 nm or less.

13. The second electrode film before heating contains Ti, The method for manufacturing a semiconductor device according to claim 9, wherein the first field plate electrode before heating comprises Al.

14. The method for manufacturing a semiconductor device according to claim 9, wherein the maximum thickness of the first electrode film after the formation of the first via is 10 nm or more and 100 nm or less.

15. A method for manufacturing a semiconductor device according to any one of claims 9 to 13, wherein the maximum thickness of the second electrode film is 10 nm or more and 100 nm or less.

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