Double-sided polishing method

Abstract

To provide a double-sided polishing method which can correct flatness of a wafer outer periphery.SOLUTION: There is provided a double-sided polishing method using a carrier for a double-sided polishing device which includes a carrier body that is arranged between upper and lower surface plates attached with a polishing cloth and is formed with a holding hole for holding a wafer sandwiched between the upper and lower surface plates during polishing; and a ring-shaped resin insert that is arranged along an inner periphery of the holding hole of the carrier body and has an inner peripheral surface that touches a periphery of the wafer. The method uses the insert which has a hook to fix a notch of the wafer, forms a wafer thickness pattern by transferring an anisotropic pattern to the insert in advance by polishing the anisotropic wafer while fixing it with the hook, and performs main polishing by fixing the wafer with the hook in such a state that the product wafer having a notch at an angle different from the notch of the anisotropic wafer is arranged in the holding hole.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a double-sided polishing method, a carrier for a double-sided polishing apparatus, and a double-sided polishing apparatus.

Background Art

[0002] When performing double-sided polishing to simultaneously polish both sides of a wafer by polishing or the like, the wafer is held by a carrier for a double-sided polishing apparatus as shown in Patent Document 1. FIG. 9 is a schematic explanatory diagram for explaining the polishing of a wafer by a conventionally used general double-sided polishing apparatus. As shown in FIG. 9, a carrier 101 for a double-sided polishing apparatus is formed to have a thickness thinner than that of the wafer W, and has a holding hole 104 for holding the wafer W at a predetermined position between an upper platen (not shown) and a lower platen of the double-sided polishing apparatus 120.

[0003] The wafer W is inserted into and held in this holding hole 104, and the upper and lower surfaces of the wafer W are sandwiched by polishing cloths provided on the opposing surfaces of the upper platen and the lower platen. This carrier 101 for a double-sided polishing apparatus is meshed with a sun gear 111 and an internal gear 112, and is rotated and revolved by the driving rotation of the sun gear 111. Then, while supplying a slurry containing abrasive grains to the polishing surface as an abrasive, the upper and lower platens are rotated in opposite directions to simultaneously polish both sides of the wafer W with the polishing cloths attached to the upper and lower platens.

[0004] The carrier body 102 of the carrier 101 for a double-sided polishing apparatus used in such a double-sided polishing process of the wafer W is mainly made of metal. Therefore, in order to protect the peripheral portion of the wafer W from damage by the metal carrier body 102, a resin insert 103 is attached along the inner peripheral portion of the holding hole 104 formed in the carrier body 102. Note that the wafer W is in a rotatable state within this holding hole 104.

[0005] In the double-sided polishing process, the main purpose is to planarize the wafer. In recent years, as miniaturization progresses, the requirement for this planarization has become higher, and the flatness of the wafer outer periphery has been emphasized.

[0006] ESFQR and ESFQD are indicators that represent the flatness of the wafer's outer edge. ESFQR (EdgeSiteFrontleastsQuaresRange) and ESFQD (EdgeSiteFrontleastsQuaresDeviation) are flatness indices that evaluate the vicinity of the edge, and are indices that evaluate site flatness in the outer perimeter.

[0007] ESFQR evaluates a fan-shaped cell configuration, for example, by using the average or maximum value of 72 cells at a 5-degree angle within a 35mm range from a point 1mm from the edge. ESFQD represents the maximum displacement from the virtual plane in ESFQR; a positive value indicates a larger displacement above the virtual plane, while a negative value indicates a larger displacement below the virtual plane. ESFQR is often used for wafer quality evaluation, while ESFQD is often used for shape analysis.

[0008] In recent years, along with miniaturization, improvements have been made to improve the flatness of the outer surface during double-sided polishing, such as using hard polishing cloths and ensuring a uniform load balance during polishing.

[0009] However, when evaluating using these indicators, a four-fold symmetrical pattern can sometimes be observed when looking at the circumferential direction of the wafer at different angles. A quadruple-symmetric pattern is a phenomenon in which ESFQR and ESFQD deteriorates at regular intervals when viewed circumferentially at different angles, occurring at 90° intervals, hence the term quadruple-symmetric.

[0010] The generation of a four-fold symmetric pattern has also been disclosed in Patent Document 2, among others. The occurrence rate of 4-fold symmetrical patterns varies depending on the model of the double-sided polishing machine and the polishing conditions. For example, it has been found that when the load distribution within the carrier is uniform and uneven loading is unlikely, the flatness level improves, but the occurrence rate of 4-fold symmetrical patterns increases.

[0011] This is thought to be because, if the wafer stops rotating within the carrier, there is insufficient rotational force to restart it. Conversely, under poor load balance conditions, the flatness level deteriorates slightly, but the occurrence of four-fold symmetrical patterns is less frequent. This is thought to be because, even if the wafer stops rotating, sufficient rotational force to restart it is obtained through uneven loading.

[0012] Patent Document 2 focuses on the slurry used for polishing and identifies that the crystal orientation dependence of the etching rate of the inorganic alkali contained in the slurry is one of the factors that cause a four-fold symmetric pattern. It discloses that by using an abrasive containing colloidal silica, containing only lithium hydroxide as the base alkali, and having a lithium hydroxide concentration of 0.02 wt% or more and less than 0.05 wt% of the total mass of the abrasive, it is possible to prevent the occurrence of variations in outer edge flatness that depend on the crystal orientation of the silicon wafer.

[0013] On the other hand, in double-sided polishing, a carrier 101 for a double-sided polishing apparatus is generally used, which consists of a carrier body 102 having a holding hole 104 for holding a wafer W, and a ring-shaped resin insert 103 that is arranged along the inner circumference of the holding hole 104 of the carrier body 102 and has an inner surface that contacts the peripheral edge of the wafer W being held.

[0014] Patent Document 1 describes that, before polishing the wafer, the angle θ between the inner surface of the resin insert 103 and the main surface of the carrier 101 for the double-sided polishing apparatus is inspected in advance, and only wafers W that satisfy the inspected angle θ of 88° ≤ θ ≤ 92° are used to polish the wafer. [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] Japanese Patent Publication No. 2011-25322 [Patent Document 2] Japanese Patent Publication No. 2017-92316 [Overview of the project] [Problems that the invention aims to solve]

[0016] As mentioned above, the demand for flatness is increasing even in the double-sided polishing process, and the flatness of the wafer's outer edge is considered important, with the occurrence of four-fold symmetrical patterns also becoming a problem. Polishing is required that can maintain high flatness while suppressing the occurrence of these patterns.

[0017] On the other hand, Patent Document 1 describes that wafer periphery sagging and nanotopology caused by distortion of the resin insert can be suppressed, and it is stated that the shape of the resin insert affects the shape of the wafer after polishing, but it does not describe that the occurrence of 4-fold symmetrical patterns can be suppressed or that the flatness of the wafer periphery can be improved.

[0018] On the other hand, as disclosed in Patent Document 2, while flatness can be improved by focusing on the slurry used for polishing and improving the crystal orientation dependence of the etching rate of the inorganic alkali contained in the slurry, it was not possible to sufficiently stabilize the flatness (reduce the occurrence rate of 4-fold symmetric patterns) when flatness deteriorated due to other factors.

[0019] The present invention has been made to solve the above problems, and aims to provide a double-sided polishing method that can improve the flatness of the outer edge of a wafer, a carrier for a double-sided polishing apparatus that can improve the flatness of the outer edge of a wafer, and a double-sided polishing apparatus. [Means for solving the problem]

[0020] The present invention has been made to achieve the above object, and is disposed between upper and lower surface plates to which polishing cloths are attached, and has a carrier body in which holding holes are formed for holding a wafer sandwiched between the upper and lower surface plates during polishing, and a ring-shaped resin insert disposed along the inner periphery of the holding hole of the carrier body and having an inner peripheral surface that contacts the peripheral edge of the wafer. A double-sided polishing method using a carrier for a double-sided polishing apparatus, the method using the insert having a hook for fixing the notch of the wafer, polishing while fixing the anisotropic wafer with the hook to transfer an anisotropic pattern to the insert in advance to create a wafer thickness pattern, and placing a product wafer having a notch at an angle different from the notch of the anisotropic wafer in the holding hole, and performing main polishing while fixing with the hook.

[0021] According to such a double-sided polishing method, an anisotropic wafer is fixed with a hook so that the wafer does not rotate with respect to the carrier body and the insert, and polishing is performed to transfer an anisotropic pattern to the insert in advance to create a wafer thickness pattern. Then, a product wafer having a notch angle different from that during the creation is fixed with a hook and main polishing is performed.

[0022] Thereby, during main polishing, among the thickness patterns created in the insert, the thick portion of the wafer thickness hits the thin portion of the insert thickness, and the thin portion of the wafer thickness hits the thick portion of the insert thickness, thereby preventing over-grinding of the thin portion of the outer periphery of the wafer and remaining un-grinded of the thick portion during main polishing, and suppressing the generation of a four-fold symmetric pattern. Therefore, the flatness of the wafer outer periphery can be improved.

[0023] At this time, the difference between the notch angle of the anisotropic wafer polished during the creation and the notch angle of the product wafer during the main polishing can be set to 45°. As a result, during this polishing process, the thickest part of the wafer contacts the thinnest part of the insert's plate thickness, and the thinnest part of the wafer contacts the thickest part of the insert's plate thickness. This reliably prevents excessive cutting of the thin part of the wafer's outer periphery and remaining uncut of the thick part during this polishing process, and suppresses the generation of a four-fold symmetric pattern. Therefore, the flatness of the wafer outer periphery can be more reliably improved.

[0024] At this time, as the polishing conditions in the pre-machining and the polishing conditions in this polishing, the load at the start of polishing is set to half of the final target load, and then the pressure is increased by 0.1 N or less per minute until the polishing progresses to the final target load. For example, the load at the start of polishing is 0.392 N (40 gf), and the pressure is increased by 0.098 N (10 gf) per minute as a gentle pressure increase, and finally the polishing can progress at a final target load of 同一荷重である最終目標荷重の0.784 N (80 gf) as in normal polishing. In this way, by making the initial load during polishing smaller than the load for final pressurization and increasing the pressure step by step up to the load for final pressurization, it is possible to reliably prevent the occurrence of crashes, etc., especially when creating a wafer thickness pattern. Also, it becomes difficult for the notch and hook to be loaded.

[0025] The present invention also provides a carrier for a double-sided polishing apparatus, which is disposed between upper and lower platen disks to which polishing cloths are attached, and has a carrier body in which holding holes are formed for holding a wafer sandwiched between the upper and lower platen disks during polishing, and a ring-shaped resin insert disposed along the inner periphery of the holding holes of the carrier body and having an inner peripheral surface that contacts the peripheral edge of the wafer. The insert has a hook for fixing the notch of the wafer.

[0026] According to such a carrier for a double-sided polishing apparatus, since it has a hook for fixing the notch of the wafer, the wafer does not rotate with respect to the carrier body and the insert during polishing. Therefore, by fixing an anisotropic wafer with a hook to prevent the wafer from rotating relative to the carrier body and insert, and then performing polishing, an anisotropic pattern can be transferred to the insert in advance to create a wafer thickness pattern. After that, a product wafer with a different notch angle than the one used for the initial creation can be fixed with a hook and the final polishing can be performed.

[0027] This ensures that during the polishing process, the thicker parts of the wafer come into contact with the thinner parts of the thickness pattern created in the insert, and the thinner parts of the wafer come into contact with the thicker parts, preventing over-polishing of the thin parts of the wafer and under-polishing of the thicker parts during the polishing process. Therefore, this carrier for the double-sided polishing machine can improve the flatness of the wafer's outer edge.

[0028] Furthermore, the present invention provides a double-sided polishing apparatus characterized by comprising the carrier for the double-sided polishing apparatus described above. Thus, since the double-sided polishing apparatus is equipped with a carrier for the double-sided polishing apparatus that can improve the flatness of the wafer periphery as described above, the flatness of the wafer periphery can be improved. [Effects of the Invention]

[0029] As described above, the double-sided polishing method of the present invention makes it possible to improve the flatness of the outer edge of the wafer. Furthermore, the carrier for the double-sided polishing apparatus and the double-sided polishing apparatus of the present invention also make it possible to improve the flatness of the outer edge of the wafer. [Brief explanation of the drawing]

[0030] [Figure 1] This shows a partial cross-sectional view of a double-sided polishing apparatus equipped with a carrier for a double-sided polishing apparatus according to an embodiment of the present invention. [Figure 2] Figure 1 is a plan view, with the upper base plate omitted. [Figure 3] Figure 1 shows a plan view of the carrier for the double-sided polishing apparatus and the wafer to be polished. [Figure 4]This shows the relationship between the circumferential angle and the outer thickness of an anisotropic wafer. [Figure 5] This shows a magnified cross-sectional view of the outer edge of the wafer and the area near the inner edge of the insert during polishing. [Figure 6] A flowchart of a double-sided polishing method according to an embodiment of the present invention is shown. [Figure 7] The example shows the relationship between the circumferential angle of the polished product wafer and the ESFQR displacement. [Figure 8] The comparative example shows the relationship between the circumferential angle and the ESFQR displacement of the polished product wafer. [Figure 9] This is a schematic diagram (plan view) illustrating the polishing of a wafer using a conventional double-sided polishing apparatus, with the upper polishing plate omitted. [Modes for carrying out the invention]

[0031] The present invention will be described in detail below, but the present invention is not limited to these descriptions.

[0032] As described above, there was a need for a double-sided polishing method that could improve the flatness of the wafer's outer edge. Furthermore, there was a need for a carrier for a double-sided polishing apparatus and a double-sided polishing apparatus that could improve the flatness of the wafer's outer edge.

[0033] As a result of diligent study on the above problems, the inventors have found that the flatness of the outer circumference of a wafer can be improved by using a double-sided polishing device carrier that includes a carrier body disposed between upper and lower platens to which a polishing cloth is attached, and which has a holding hole formed therein for holding a wafer sandwiched between the upper and lower platens during polishing, and a ring-shaped resin insert arranged along the inner circumference of the holding hole of the carrier body and having an inner surface that contacts the peripheral edge of the wafer, wherein the insert has a hook for fixing the notch of the wafer, an anisotropic wafer is polished while being fixed with the hook to transfer an anisotropic pattern to the insert in advance to create a wafer thickness pattern, and a product wafer having a notch at a different angle from the notch of the anisotropic wafer is placed in the holding hole, fixed with the hook, and polished, and the main polishing is performed, thereby improving the flatness of the outer circumference of the wafer. The inventors have found that the flatness of the outer circumference of the wafer can be improved by this double-sided polishing method.

[0034] Furthermore, the inventors have diligently studied the above problems and have found that a carrier for a double-sided polishing apparatus can improve the flatness of the outer circumference of a wafer, comprising a carrier body disposed between upper and lower platens to which a polishing cloth is attached, and having a holding hole formed therein for holding a wafer sandwiched between the upper and lower platens during polishing, and a ring-shaped resin insert arranged along the inner circumference of the holding hole of the carrier body and having an inner surface that contacts the peripheral edge of the wafer, wherein the insert has a hook for fixing the notch of the wafer, and thus the inventors have completed the present invention.

[0035] Furthermore, after diligently studying the above-mentioned problems, the inventors discovered that a double-sided polishing apparatus equipped with the carrier for the double-sided polishing apparatus described above can improve the flatness of the outer edge of the wafer, and thus completed the present invention.

[0036] The following explanation will be given with reference to the drawings. Hereinafter, a double-sided polishing apparatus 100 equipped with a carrier 1 for a double-sided polishing apparatus according to an embodiment of the present invention, and a double-sided polishing method according to an embodiment of the present invention will be described with reference to Figures 1 to 6.

[0037] First, with reference to Figures 1 to 5, a double-sided polishing apparatus 100 equipped with a carrier 1 for a double-sided polishing apparatus according to an embodiment of the present invention, and the carrier 1 for a double-sided polishing apparatus according to the present invention will be described. The double-sided polishing apparatus 100 shown in Figures 1 and 2 is an apparatus for polishing both the front and back surfaces of a wafer W, and comprises an upper platen 3, a lower platen 5, a sun gear 11, an internal gear 13, and a carrier 1 for a double-sided polishing apparatus.

[0038] The upper platen 3 and the lower platen 5 are disc-shaped plates that sandwich the wafer W from above and below, and are positioned opposite each other vertically. An upper polishing cloth 7, which is used to polish the upper surface of the wafer W, is attached to the lower surface of the upper platen 3, and a lower polishing cloth 9, which is used to polish the lower surface of the wafer W, is attached to the upper surface of the lower platen 5. The upper platen 3 is also provided with a slurry supply port 17, which is a hole that goes through from top to bottom, and during polishing, slurry containing abrasive grains is supplied as an abrasive from the slurry supply port 17. The sun gear 11 is a spur gear coaxially positioned between the upper platen 3 and the lower platen 5, and the internal gear 13 is an internal gear coaxially positioned on the periphery between the upper platen 3 and the lower platen 5.

[0039] The carrier 1 for the double-sided polishing apparatus is a component that holds the wafer W, and as shown in Figure 3, it comprises a carrier body 21 and an insert 25. The carrier body 21 is a metal spur gear positioned between the upper platen 3 to which the upper polishing cloth 7 is attached and the lower platen 5 to which the lower polishing cloth 9 is attached, and meshes with the sun gear 11 and the internal gear 13. The carrier body 21 has a holding hole 23 for holding the wafer W that is sandwiched between the upper platen 3 and the lower platen 5 during polishing. In addition to the holding hole 23, the carrier body 21 is also provided with a discard hole 27 for passing slurry through as needed.

[0040] The insert 25 is a component that prevents the wafer W from coming into contact with the carrier body 21 and damaging the wafer's peripheral edge. It is a ring-shaped resin component positioned along the inner circumference of the holding hole 23 of the carrier body 21 and having an inner surface that contacts the peripheral edge of the wafer W. The insert 25 is fixed to the carrier body 21 by fitting or adhesive.

[0041] The insert 25 has a hook 29 that secures the notch N of the wafer W when the wafer W is placed in the holding hole 23. The shape of the hook 29 is such that it can hook onto the notch N and secure the wafer W so that it does not rotate. As shown in Figure 3, if the shape of the notch N is a V-shaped groove, the shape of the hook 29 is a V-shaped projection that protrudes radially inward from the insert 25. It is preferable that the hook 29 be made of the same resin as the insert 25, as this reduces the possibility of the hook 29 scratching the wafer W. The hook 29 may be integrated with the insert 25 or be a separate part.

[0042] Because the insert 25 has a hook 29, the notch N is fixed by the hook 29 when the wafer W is placed in the holding hole 23, so the wafer W does not rotate relative to the carrier body 21 and the insert 25. Therefore, the wafer W does not rotate relative to the carrier 1 for the double-sided polishing apparatus during polishing.

[0043] During double-sided polishing of the wafer W, the upper platen 3 and lower platen 5 shown in Figure 1 are rotated by a drive source (not shown), and as shown in Figure 2, the carrier 1 for the double-sided polishing apparatus rotates on its own axis while revolving around the sun gear 11. Furthermore, a slurry containing abrasive grains is supplied as an abrasive to the upper polishing cloth 7 and lower polishing cloth 9 from the slurry supply port 17 shown in Figure 1.

[0044] As a result, the upper surface of the wafer W held in the holding hole 23 of the carrier 1 for the double-sided polishing apparatus is polished by the upper polishing cloth 7, and the lower surface is polished by the lower polishing cloth 9 simultaneously. However, since the wafer W is fixed by the hook 29 at the notch N as shown in Figure 3, the wafer W does not rotate relative to the insert 25.

[0045] The reason for providing the hook 29 on the insert 25 in this way, so that the wafer W does not rotate relative to the insert 25, is explained below.

[0046] Before double-sided polishing, wafers such as silicon wafers undergo surface treatments such as etching. However, since the etching rate differs depending on the crystal orientation, wafers become thinner in orientations with a fast etching rate, and thicker in orientations with a slow etching rate. For example, Figure 4 shows the outer thickness of a 45° notched wafer before double-sided polishing, measured using KLA Tencor's Wafersight1. As shown in Figure 4, the outer edge of the wafer W has an anisotropic pattern shape P1 in which thick and thin portions alternate in the circumferential direction.

[0047] Here, wafer anisotropy refers to the thickness of the wafer, and an anisotropic wafer is one in which there are thicker and thinner parts when viewed in the circumferential direction. The following explanation is similar.

[0048] When a wafer W with anisotropy as shown in Figure 4 is polished using a standard double-sided polishing device carrier 101 without hooks 29, as shown in Figure 9, a pattern shape with four-fold symmetry may occur despite the polishing.

[0049] However, the four-fold symmetrical pattern shape does not always occur when performing double-sided polishing, and is influenced by the polishing conditions and the state of the material. On the other hand, according to the inventor's findings, it has been found that the insert 25 of the carrier 1 for the double-sided polishing device is a factor that greatly increases the occurrence rate of this pattern. Therefore, there is a need for a double-sided polishing device that can improve flatness, such as the occurrence of four-fold symmetrical patterns, due to the influence of the resin of the carrier 1 for the double-sided polishing device, particularly the insert 25.

[0050] For example, as shown in Figure 9, a conventional carrier 101 for a double-sided polishing apparatus comprises a metal carrier body 102, a waste hole 105 for receiving polishing slurry, and a holding hole 104 for holding a wafer W. An insert 103 is formed on the inner circumference of the holding hole 104 to protect the edge of the wafer W.

[0051] Since most inserts 103 are made of resin, the inventors considered that as the lifespan of the carrier 101 for the double-sided polishing device progresses, the inner circumferential end surface of the insert 103 would be worn away by polishing, causing a depression in the insert 103.

[0052] Furthermore, the inventors believe that the wafer W may be held in place by the resulting depressions during polishing, preventing smooth rotation of the wafer W relative to the insert 25. As a result, the anisotropy of the wafer W cannot be corrected, and double-sided polishing proceeds, causing variations in the thickness of the wafer W's edge portion that are similar to the anisotropy, which manifests as a four-fold symmetrical pattern shape.

[0053] Therefore, in the carrier 1 for the double-sided polishing apparatus of the present invention shown in Figure 3, the wafer W is deliberately fixed with a hook 29 and not allowed to rotate relative to the carrier 1 for the double-sided polishing apparatus. If double-sided polishing is performed on the wafer W without it being able to rotate relative to the carrier 1 for the double-sided polishing apparatus, the anisotropy will not be corrected as the double-sided polishing proceeds. However, the anisotropy will be transferred to the insert 25, and the insert 25 will also acquire anisotropy corresponding to the wafer W. In the following explanation, the shape created by the transfer of anisotropy to the insert 25 will also be referred to as the wafer thickness pattern.

[0054] In a carrier 1 for a double-sided polishing apparatus having an insert 25 on which such anisotropy has been transferred, if another wafer having the same anisotropy and notch angle is processed, the anisotropy is transferred as is, further emphasizing the anisotropy and making it easy for quadruple symmetry to occur. However, if a wafer W with a different notch angle is polished, the anisotropy of the insert 25 and the anisotropy of the wafer W cancel each other out, making it less likely for abnormalities such as quadruple symmetry patterns to occur.

[0055] For example, if a wafer W having the pattern shape P1 shown in Figure 4 is polished using a carrier 1 for a double-sided polishing apparatus having an insert 25 onto which the pattern shape P2 has been transferred, the wafer W will be polished with a shifted crystal orientation compared to when the anisotropy was transferred. As a result, the thicker parts of the wafer W come into contact with the thinner parts of the thickness pattern created in the insert 25, and the thinner parts of the wafer W come into contact with the thicker parts, preventing over-polishing of the thin parts and under-polishing of the thicker parts of the outer edge of the wafer W during the polishing process.

[0056] Specifically, at angles of 0°, 90°, 180°, 270°, and 360° in Figure 4, as schematically shown in Figure 5, the thinner portion of the inner circumference 33 of the insert 25 comes into contact with the thicker portion of the outer circumference 31 of the wafer W. Due to the difference in thickness, the abrasive grains 35 in the slurry can easily get between the outer circumference 31 of the wafer W and the inner circumference 33 of the insert 25, increasing the polishing efficiency in that area and resulting in a generally flat wafer W.

[0057] Thus, the inventors have found that the presence of hooks 29 in the insert 25 allows for the transfer of the same anisotropic pattern described above to the insert 25, and that performing the polishing on a wafer W with a different notch angle from the transferred wafer suppresses the occurrence of a four-fold symmetric pattern on the polished wafer W, thereby improving the flatness of the wafer W.

[0058] In other words, by providing the hook 29, the wafer W does not rotate during polishing, allowing the shape of the insert portion to be fabricated initially using an anisotropic wafer W. Furthermore, by performing the final polishing of wafers W with different notch angles after fabrication, the occurrence of a four-fold symmetric pattern can be suppressed. As a result, the flatness of the outer edge of the wafer can be improved. The above explains why a hook 29 is provided on the insert 25 to prevent the wafer W from rotating relative to the insert 25.

[0059] Next, a double-sided polishing method according to an embodiment of the present invention will be described. First, an overview of the double-sided polishing method according to an embodiment of the present invention will be described. The present invention provides a double-sided polishing method that addresses the conventional problem of the insert shape changing over time, which prevents smooth wafer rotation and, in particular, makes it easier for quadruple symmetry to occur.

[0060] Specifically, the double-sided polishing method of the present invention involves first grinding the insert 25 to match the shape (anisotropy) of a wafer W with, for example, a 0° notch, and then holding a wafer W with a notch at a different angle than the pre-ground wafer, for example, a 45° notch, and performing polishing. Alternatively, the insert 25 may be pre-ground to match the shape (anisotropy) of a wafer W with, for example, a 45° notch, and then holding a wafer W with a 0° notch and performing polishing.

[0061] In this way, the thicker parts of the wafer W come into contact with the thinner parts of the insert 25, and the thinner parts of the wafer come into contact with the thicker parts of the insert 25, which helps to prevent over-machining of the thin outer edges of the wafer W and under-machining of the thicker parts.

[0062] In particular, the double-sided polishing method of the present invention is a double-sided polishing method in which polishing is performed while fixing the insert 25 and the wafer W so that the wafer W does not rotate relative to the carrier body 21 and the insert 25 during polishing.

[0063] To fix the insert 25 and the wafer W, a hook 29 is attached to the insert 25 so that it catches on the notch N of the wafer W. In the following explanation, a wafer W with a 0° notch will also be referred to as a 0° notch product, and a wafer W with a 45° notch will also be referred to as a 45° notch product. The above is an overview of the double-sided polishing method according to an embodiment of the present invention.

[0064] Next, the details of the double-sided polishing method according to an embodiment of the present invention will be described. The double-sided polishing method according to an embodiment of the present invention includes, for example, the following steps shown in Figure 6. S1: Set the wafer W1 for fabrication on carrier 1 for double-sided polishing machine with hook 29. S2: Perform polishing with the same load as during normal polishing to prepare for inserts. S3: Thickness measurement confirms that insert 25 has the same thickness distribution as the outer edge of the wafer. S4: Using the same double-sided polishing device carrier 1 with hook 29 used in S1 and S2, polish the product wafer W2, which is a wafer W with a different notch position than the one used during manufacturing.

[0065] In the following explanation, steps S1-S3 may be referred to as "preparation," and step S4 as "final polishing." The specific steps for each process are as follows:

[0066] S1: Set the wafer W1 for fabrication on carrier 1 for double-sided polishing machine with hook 29. In step S1, a carrier 1 for a double-sided polishing apparatus is used, which includes an insert 25 having a hook 29 for fixing a notch N of the wafer W. As shown in Figure 3, a fabrication wafer W1, which is an anisotropic wafer W to be polished during fabrication, is placed in the holding hole 23, and the notch N1 of the anisotropic fabrication wafer W1 is hooked onto the hook 29 to fix the fabrication wafer W1 to the insert 25 so that it does not rotate relative to the carrier body 21 and the insert 25 during polishing (S1 in Figure 6).

[0067] An anisotropic wafer W1 for fabrication only needs to have the anisotropy shown in Figure 4. However, it must have a different notch angle than the product wafer W2 shown in Figure 3. Since the fabrication wafer W1 in Figure 4 has a notch angle of 45°, unless otherwise specified, the following explanation will use the example of using a wafer W with a 45° notch angle as the anisotropic fabrication wafer W1.

[0068] S2: Perform polishing with the same load as during normal polishing to prepare for inserts. In step S2, the carrier 1 for the double-sided polishing device is engaged with the sun gear 11 and internal gear 13 of the double-sided polishing device 100, and the anisotropic wafer W1 for fabrication is polished by the double-sided polishing device 100 while being fixed to the insert 25 with the hook 29, thereby transferring the anisotropic pattern to the insert 25 in advance and creating the wafer thickness pattern (S2 in Figure 6).

[0069] For polishing in preparation for inserting, it is preferable to use polishing conditions that allow for faster transfer of the anisotropic pattern of the wafer W1 to the insert 25. On the other hand, in order to reduce the load on the notch N1 and the hook 29 caused by hooking and fixing the notch N1 with the hook 29, it is preferable to increase the pressure much more gradually than in a typical way of applying load.

[0070] Therefore, for example, it is preferable to set the initial load at the start of polishing to approximately half of the target load (final target load) during normal polishing, 0.392 N (40 gf), and then gradually increase the pressure at a rate of 0.1 N or less per minute, in this example 0.098 N (10 gf) per minute, until the polishing is completed at a final target load of 0.784 N (80 gf), which is the same load as during normal polishing.

[0071] In this way, by setting the initial pressure at the start of polishing to be smaller than the final pressure applied, and gradually increasing the pressure up to the final pressure, it is possible to reliably prevent crashes and other problems, especially when creating wafer thickness patterns. In addition, it is possible to reduce the load on notch N1 and hook 29.

[0072] The polishing time for S2 is such that the wafer thickness pattern of insert 25 has the same distribution as the thickness of the anisotropic fabrication wafer W1, which has had its shape transferred to it, as shown in Figure 4.

[0073] S3: Thickness measurement confirms that insert 25 has the same thickness distribution as the outer edge of the wafer. In S3, the outer thickness of the insert 25 into which the wafer thickness pattern has been fabricated is measured using a known thickness measuring instrument, and it is confirmed that it has the same thickness distribution as the anisotropic fabrication wafer W1 into which the shape has been transferred (S3 in Figure 6).

[0074] The carrier build-up, or fabrication, is considered complete when the thickness distribution of insert 25 matches the wafer thickness distribution shown in Figure 4. If the distributions are different, steps S1 and S2 are repeated until the distributions match.

[0075] S4: Using the same double-sided polishing device carrier 1 with hook 29 used in S1 and S2, product wafer W2, which is a wafer W with a different notch position than the one used during manufacturing, is polished. After confirming that insert 25 has been machined in S3, in S4, the actual polishing (product polishing) is performed on a notched part, which is different from the polishing done for insert preparation.

[0076] Specifically, in S4, as shown in Figure 3, the product wafer W2, which has a notch N2 at a different angle from the notch N1 of the anisotropic fabrication wafer W1, is placed in the holding hole 23 of the carrier 1 for the double-sided polishing apparatus, fixed with a hook 29, and the polishing is performed (S4 in Figure 6).

[0077] In particular, it is preferable to set the difference α between the notch angle of the anisotropic wafer W1 used for fabrication, which is polished during the fabrication process, and the notch angle of the product wafer W2, which is polished in the final product, to 45°, as shown in Figure 3.

[0078] For example, when manufacturing the insert 25, if a 45° notched wafer W1 is used as the wafer for manufacturing, it is preferable to use a 0° notched wafer W2 for the final product. Conversely, if the final product wafer W2 is a 45° notched wafer, it is preferable to manufacture the insert 25 using a 0° notched wafer W1 as the wafer for manufacturing. This is because by using wafers W1 and W2 with different notch positions, the anisotropy of the insert 25 and the anisotropy of the wafer W can be shifted and fixed in a state where they can be polished.

[0079] In particular, by setting the notch angle difference α to 45°, during the main polishing process, the thickest part of the product wafer W2 comes into contact with the thinnest part of the insert 25, and the thinnest part of the product wafer W2 comes into contact with the thickest part of the insert 25. This reliably prevents over-polishing of the thinnest parts and under-polishing of the thicker parts of the outer edge of the product wafer W2 during the main polishing process, thereby suppressing the generation of a four-fold symmetrical pattern. Therefore, the flatness of the wafer's outer edge can be corrected more reliably.

[0080] In the double-sided polishing method of the present invention, the insert 25 is pre-polished with the anisotropy of the product wafer W2 shifted, and the polishing is performed while fixing the insert 25 and the product wafer W2 so that the product wafer W2 does not rotate relative to the carrier body 21 and the insert 25.

[0081] In this way, by making the notch positions different between the wafer W1 used for fabrication to be transferred to the insert 25 and the product wafer W2 to be polished for the final product, the four-fold symmetrical pattern can be effectively eliminated.

[0082] Numerically, after double-sided polishing, a product wafer W2 can be produced in which the PV at each 90° interval is 10nm or less and there is no symmetrical pattern when viewed with ESFQR at different angles. [Examples]

[0083] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention. In one example, a double-sided polishing apparatus 100 of the present invention, equipped with a carrier 1 for double-sided polishing apparatus having a hook 29, was used to fabricate an anisotropic fabrication wafer W1 into an insert 25, and then a product wafer W2 with a different notch angle than the fabrication wafer W1 was polished. In a comparative example, a double-sided polishing apparatus 120 without a hook 29 was used, and the results of whether or not four-fold symmetry occurred in the product wafer W2 after polishing were compared. The specific procedure is as follows.

[0084] (Example: With custom-made inserts and a carrier with hooks) Before processing the product wafer W2, a wafer W1 (45° notched) for fabrication was set in the carrier 1 of the double-sided polishing apparatus 1 of the present invention, which is equipped with a carrier 1 for double-sided polishing apparatus having a hook 29. The insert 25 was removed by increased pressure polishing with the same load as during normal polishing, and it was confirmed that the distribution of the insert 25 was the same as the outer circumference shape of the wafer. Subsequently, a product wafer W2 with a 0° notch was polished on both sides by increased pressure polishing using the same double-sided polishing apparatus carrier 1 with a hook 29.

[0085] In this context, "pressure-enhanced polishing" refers to starting with a load of 0.392 N (40 gf), increasing the pressure by 0.098 N (10 gf) / min, and finally proceeding with polishing at 0.784 N (80 gf). The following explanations follow the same principle.

[0086] Regarding the fabrication of the insert 25, in order to intentionally mill the insert 25 to match the anisotropy of the wafer W, the insert 25 was polished in a carrier 1 for a double-sided polishing apparatus equipped with hooks 29 to prepare it for insertion, thereby giving the insert 25 the same thickness distribution as the outer edge of the wafer. The thickness variation of the insert 25 at this time was kept within 0.1 μm.

[0087] (Comparison example: No insert fabrication, no hooks used as carrier) In the comparative example, a conventional carrier 101 for double-sided polishing equipment, as shown in Figure 9, was used. No prior processing of the insert 103 using the fabrication wafer W1 was performed, and double-sided polishing of the product wafer W2 was carried out for more than 500 minutes using the carrier 101 for double-sided polishing equipment that was used for double-sided polishing.

[0088] The double-sided polishing apparatus used for processing insert 25 in the example (pressure polishing) and for processing the products in the example and comparative example (final polishing) was a 4-way double-sided polishing apparatus manufactured by Fujikoshi Machinery, model DSP-20B. A foamed urethane pad with a Shore A hardness of 90 was used as the polishing cloth, and the slurry used was a silica abrasive containing 35 nm average particle size, 1.0 wt% abrasive concentration, pH 10.5, and KOH-based. After processing, the wafers were cleaned using SC-1 cleaning under the conditions NH4OH:H2O2:H2O = 1:1:15. Polishing was performed using pressure polishing in all cases.

[0089] Measurement results: Whether or not a four-fold symmetric pattern occurred was determined by examining the PV and pattern at 90° intervals. For ESFQR, the wafer was measured using KLA Tencor's Wafersight1 after cleaning.

[0090] We compared the normal conditions (comparative example) using a carrier without insert fabrication and notch hooks, with the case where insert fabrication was performed and a carrier with notch hooks was used (example).

[0091] As shown in Figure 8, in the comparative example, the product wafer after double-sided polishing had PV of 20 nm or more at every 90° interval in the angle-specific ESFQR, indicating symmetry and resulting in a four-fold symmetric pattern. In contrast, as shown in Figure 7, the example obtained a flat wafer with PV of 10 nm or less in the same angle-specific ESFQR, lacking symmetry and suppressing the occurrence of a four-fold symmetric pattern.

[0092] These results show that by using a carrier 1 for a double-sided polishing apparatus equipped with hooks 29 for fixing the wafer W to fabricate an anisotropic wafer W into the insert 25, and then performing the final polishing of a wafer W with a different notch angle than the fabricated wafer W, the occurrence of a four-fold symmetric pattern can be suppressed.

[0093] In other words, it was found that the carrier 1 for the double-sided polishing apparatus and the double-sided polishing apparatus 100 of the present invention can be manufactured in a way that suppresses the occurrence of a four-fold symmetrical pattern in the insert 25, and can improve the flatness of the outer edge of the wafer. Furthermore, it was found that the double-sided polishing method of the present invention can suppress the occurrence of a four-fold symmetrical pattern and can improve the flatness of the outer edge of the wafer.

[0094] Thus, by preventing the wafer W from rotating relative to the carrier 1 for the double-sided polishing apparatus using the hook 29, and by pre-machining the insert 25 with an anisotropic wafer W1 having a different angle notch than the product wafer W2, it is possible to suppress the occurrence of four-fold symmetry and improve the flatness of the outer edge of the wafer.

[0095] In this embodiment, the thicker outer periphery of the 0° notched product wafer W2 overlaps the thinner portion of the insert 25. This makes it easier for the abrasive particles 35 of the slurry to penetrate this area during polishing, resulting in efficient grinding of the thicker outer periphery of the product wafer W2 and obtaining a generally flat product wafer W2. Numerically, when viewed using ESFQR at different angles, a product wafer W was obtained in which the PV at each 90° interval was 10 nm or less and there were no symmetrical patterns.

[0096] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative, and any configuration that is substantially identical to the technical idea described in the claims of the present invention and achieves similar effects is included within the technical scope of the present invention. [Explanation of symbols]

[0097] 1... Carrier for double-sided polishing machine, 3... Upper platen, 5... Lower platen, 7... Upper polishing cloth, 9... Lower polishing cloth, 11... Sun gear, 13... Internal gear, 17... Slurry supply port, 21... Carrier body, 23... Holding hole, 25... Insert, 27... Discard hole, 29... Hook, 31... Outer circumference, 33... Inner circumference, 35... Abrasive grain, 100... Double-sided polishing machine, 101... Carrier for double-sided polishing machine, 102... Carrier body, 103... Insert, 104... Holding hole, 105... Discard hole, 111... Sun gear, 112... Internal gear, 120... Double-sided polishing machine, N... Notch, N1... Notch, N2... Notch, P1... Pattern shape, P2... Pattern shape, W... Wafer, W1... Wafer for fabrication, W2…Product wafer.

Claims

1. A double-sided polishing method using a carrier for a double-sided polishing apparatus, comprising a carrier body disposed between upper and lower platens to which polishing cloth is attached, and having a holding hole formed therein for holding a wafer sandwiched between the upper and lower platens during polishing, and a ring-shaped resin insert arranged along the inner circumference of the holding hole of the carrier body and having an inner surface that contacts the peripheral edge of the wafer, wherein Using the insert having hooks for fixing the notches in the wafer, a wafer that has thicker and thinner parts when viewed in the circumferential direction is polished while being fixed with the hooks, thereby transferring the patterns of the thicker and thinner parts to the insert in advance and creating a wafer thickness pattern. A double-sided polishing method characterized by placing a product wafer having notches at a different angle from the notches of a wafer having thicker and thinner parts when viewed in the circumferential direction in the holding hole, fixing it with the hook, and performing the polishing.

2. The double-sided polishing method according to claim 1, characterized in that the difference between the notch angle of the wafer having thicker and thinner parts when viewed in the circumferential direction and being polished during the aforementioned manufacturing process, and the notch angle of the product wafer being polished is set to 45°.

3. The double-sided polishing method according to claim 1 or 2, characterized in that, as the polishing conditions in the preparation and the polishing conditions in the main polishing, the load at the start of polishing is set to half of the final target load, and then the pressure is increased by a load of 0.1 N or less per minute until the polishing is carried out to the final target load.

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