Memory device including phase-change memory cell and its operating method

Abstract

To provide a memory device including a phase change memory cell having improved lifetime and improved reliability, and an operation method for the same.SOLUTION: A memory device 100 includes: a first phase change memory cell that is connected between a first bit line and a first word line; an X-decoder that provides a voltage of a selection word line to the first word line during a reset write operation of changing a state of the first phase change memory cell from a set state to a reset state; a Y-decoder that provides a selection bit line voltage to the first bit line during the reset write operation; and a voltage bias circuit. The voltage bias circuit generates a selection word / bit on the basis of a first voltage bias in a first section of the reset write operation, generates a selection word / bit line voltage on the basis of a second voltage bias in a second section thereof, and generates the selection word / bit line voltage on the basis of a third voltage bias in a third section thereof.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor memory, and more particularly, to a memory device including a phase change memory cell and an operation method thereof.

Background Art

[0002] Semiconductor memories are classified into volatile memory devices in which stored data is lost when the power supply is cut off, such as SRAM and DRAM, and non-volatile memory devices that retain the stored data even when the power supply is cut off, such as flash memory devices, PRAM, MRAM, RRAM, and FRAM.

[0003] As an example, phase change memory (PCM: Phase Change Memory) stores data by utilizing the physical characteristics of a phase change material (GST). The phase change material has a crystalline state or an amorphous state, and the state of the phase change material may change by controlling the magnitude and time of the current supplied to the phase change material. To change the state of the phase change material from the crystalline state to the amorphous state, a large write current is required. Such a large write current is a factor that degrades the phase change memory or worsens the variation of high-speed cells.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

[0005] The present invention has been made in view of the problems of the prior art as described above, and the object of the present invention is to provide a memory device including a phase-change memory cell having improved lifespan and enhanced reliability, and a method for operating the same. [Means for solving the problem]

[0006] A memory device according to an embodiment of the present invention comprises: a first phase change memory cell connected between a first bit line and a first word line; an X-decoder configured to provide a selected word line voltage to the first word line during a reset write operation that changes the state of the first phase change memory cell from a set state to a reset state; a Y-decoder configured to provide a selected bit line voltage to the first bit line during the reset write operation; and a voltage bias circuit. The voltage bias circuit is configured to generate the selected word line voltage and the selected bit line voltage based on a first voltage bias within a first interval of the reset write operation; generate the selected word line voltage and the selected bit line voltage based on a second voltage bias greater than the first voltage bias within a second interval of the reset write operation; and generate the selected word line voltage and the selected bit line voltage based on a third voltage bias smaller than each of the first and second voltage biases within a third interval of the reset write operation.

[0007] A method for operating a memory device including a phase-change memory cell according to an embodiment of the present invention comprises the steps of: applying a first voltage bias to the bit line and word line connected to the phase-change memory cell within a first reset write operation that writes the phase-change memory cell to a reset state; applying a second voltage bias greater than the first voltage bias to the bit line and word line connected to the phase-change memory cell within a second reset write operation after the first period; and applying a third voltage bias less than or equal to the first voltage bias to the bit line and word line connected to the phase-change memory cell within a third reset write operation after the second period.

[0008] An operating method for a memory device including a phase-change memory cell according to an embodiment of the present invention includes the steps of turning on the phase-change memory cell, applying a reset write current to the phase-change memory cell, and applying at least one current pulse to the phase-change memory cell, wherein the voltage of the bit line and the word line connected to the phase-change memory cell are maintained constant while the at least one current pulse is applied to the phase-change memory cell.

[0009] An operation method for a memory device including a plurality of phase-change memory cells connected to a plurality of bit lines and a plurality of word lines according to an embodiment of the present invention comprises the steps of: selecting a target memory cell from among the plurality of phase-change memory cells; applying a first voltage bias to the target bit line connected to the target memory cell among the plurality of bit lines and the target word line connected to the target memory cell among the plurality of word lines within a first section of a reset write operation that changes the state of the target memory cell to a reset state; applying a second voltage bias higher than the first voltage bias to the target bit line and the target word line within a second section of the reset write operation after the first section; and applying a third voltage bias lower than or equal to the first voltage bias to the target bit line and the target word line within a third section of the reset write operation after the second section. [Effects of the Invention]

[0010] According to the present invention, a memory device can reset a target memory cell by applying at least one current pulse to the target memory cell. At this time, the at least one current pulse is a current pulse generated by the physical characteristics of a switching element (for example, OTS) included in the target memory cell. Therefore, since the application time of the reset write current is reduced, the deterioration of the phase change memory cells included in the memory device can be reduced, and since the threshold voltage of the phase change memory cells can be finely adjusted by the at least one current pulse, the reliability of the memory device can be improved.

Brief Description of Drawings

[0011] [Figure 1] It is a block diagram showing, as an example, a memory device according to an embodiment of the present invention. [Figure 2] It is a diagram showing, as an example, the memory cell array of FIG. 1. [Figure 3] It is a diagram showing, as an example, any one of the memory cells in the memory cells of FIG. 2. [Figure 4A] It is a diagram for explaining characteristics according to the state of the memory cell. [Figure 4B] It is a diagram for explaining characteristics according to the state of the memory cell. [Figure 5] It is a flowchart showing, as an example, the write operation of the memory device of FIG. 1. [Figure 6] It is a diagram for explaining the operation according to the flowchart of FIG. 5. [Figure 7] It is a timing diagram showing, as an example, the current flowing through the target memory cell according to the operation of the flowchart of FIG. 6. [Figure 8A] It is a timing diagram showing, as an example, the voltage bias according to the operation of the flowchart of FIG. 6. [Figure 8B] It is a timing diagram showing, as an example, the voltage bias according to the operation of the flowchart of FIG. 6. [Figure 8C] It is a timing diagram showing, as an example, a voltage bias corresponding to the operation of the flowchart of FIG. 6. [Figure 8D] It is a timing diagram showing, as an example, a voltage bias corresponding to the operation of the flowchart of FIG. 6. [Figure 9A] It is a scatter diagram (scatter plot), current-voltage graph, and timing diagram for explaining the operation of step S130 in FIG. 5. [Figure 9B] It is a scatter diagram (scatter plot), current-voltage graph, and timing diagram for explaining the operation of step S130 in FIG. 5. [Figure 9C] It is a scatter diagram (scatter plot), current-voltage graph, and timing diagram for explaining the operation of step S130 in FIG. 5. [Figure 10] It is a flowchart showing, as an example, the operation of the memory device in FIG. 1. [Figure 11] It is a timing diagram showing, as an example, a voltage bias corresponding to the operation of the flowchart of FIG. 10. [Figure 12] It is a circuit diagram showing, as an example, the current bias circuit in FIG. 1. [Figure 13] It is a timing diagram for explaining the operation of the current bias circuit in FIG. 12. [Figure 14] It is a block diagram showing, as an example, a memory device according to an embodiment of the present invention. [Figure 15] It is a circuit diagram showing, as an example, the three-dimensional structure of a memory device according to an embodiment of the present invention. [Figure 16] It is a block diagram showing, as an example, a memory system including a memory device according to the present invention. [Figure 17] It is a block diagram showing, as an example, a user system to which a memory device according to the present invention is applied.

Mode for Carrying Out the Invention

[0012] The embodiments of the present invention will be described below in such clarity and detail that a person with ordinary skill in the art of the present invention can easily implement the invention.

[0013] Figure 1 is a block diagram showing an example of a memory device according to an embodiment of the present invention. Referring to Figure 1, the memory device 100 may include a memory cell array 110, an X-decoder 120, a Y-decoder 130, a voltage bias circuit 140, a current bias circuit 150, and a control logic circuit 160.

[0014] The memory cell array 110 may include multiple memory cells. Each of the multiple memory cells may be connected to multiple word lines (WLs) and multiple bit lines (BLs).

[0015] The X-decoder 120 may be connected to the memory cell array 110 via multiple word lines (WLs). The X-decoder 120 is configured to control the levels of the multiple word lines (WLs). For example, the X-decoder 120 can select at least one word line from among the multiple word lines (WLs), provide a selected word line voltage (VWL_sel) to the selected word line, and provide an unselected word line voltage (VWL_unsel) to the unselected word line.

[0016] The Y-decoder 130 may be connected to the memory cell array 110 via multiple bit lines (BLs). The Y-decoder 130 is configured to control the levels of the multiple bit lines (BLs). For example, the Y-decoder 130 can select at least one bit line from the multiple bit lines (BLs), provide a selected bit line voltage (VBL_sel) to the selected bit line, and provide an unselected bit line voltage (VBL_unsel) to the unselected bit line.

[0017] The voltage bias circuit 140 is configured to generate a variety of voltages necessary for the operation of the memory device 100. For example, the voltage bias circuit 140 is configured to generate a variety of voltages such as the selected word line voltage (VWL_sel), the unselected word line voltage (VWL_unsel), the selected bit line voltage (VBL_sel), and the unselected bit line voltage (VBL_unsel). In an exemplary embodiment, the voltages described above may be used in write operations of the memory device 100 (in particular, operations that change a memory cell from a set state to a reset state, operations that write a memory cell to a reset state, or reset operations on a memory cell). However, the scope of the present invention is not limited thereto, and the circuit may be configured to generate a variety of voltages used in other operations such as read operations and set operations on a memory cell.

[0018] The current bias circuit 150 is configured to generate a current bias (CB). The current bias (CB) is configured to limit or control the magnitude of the current flowing through the bit line (BL) during write operations of the memory device 100 (particularly during reset write operations). For example, the Y-decoder 130 can limit the current flowing through a selected bit line to the magnitude of the current bias (CB). In an exemplary embodiment, the magnitude of the current bias (CB) may have a predetermined value depending on the physical characteristics of the memory cell. The current bias (CB) will be described in detail with reference to the following drawings.

[0019] The control logic circuit 160 is configured to control various operations of the memory device 100. For example, the control logic circuit 160 is configured to control the voltage bias circuit 140 and the current bias circuit 150 in order to write data to the memory cell array 110.

[0020] In an exemplary embodiment, the memory device 100 according to an embodiment of the present invention may be a phase-change memory (PCM) device. That is, the memory cells included in the memory cell array 110 may be phase-change memory (PCM) cells. However, the scope of the present invention is not limited thereto, and the memory device 100 may include memory elements that vary the threshold voltage or resistance value of memory cells using write current, such as in resistive memory (ReRAM). For the sake of convenience in the following explanation, we will assume that the memory device 100 includes phase-change memory.

[0021] A phase-change memory cell may have a set state or a reset state depending on the magnitude of the threshold voltage (Vth). In other words, by adjusting the magnitude of the threshold voltage of the phase-change memory cell, data can be written to the phase-change memory cell. In the following, in order to easily explain the technical concept of the present invention, it is assumed that the memory device 100 according to an embodiment of the present invention performs an operation to change the memory cell from a set state to a reset state (hereinafter referred to as a reset operation on the memory cell, or "reset write operation"). However, the scope of the present invention is not limited thereto.

[0022] Generally, reset write operations on memory cells use a large write current. This large current can degrade the memory cell. Conversely, if the write current and duration used in a reset operation are insufficient, the memory cell's threshold voltage may not be properly changed, resulting in insufficient read margin (i.e., the difference in threshold voltage variation between the set and reset states). This can reduce the reliability of the memory device.

[0023] In the memory device 100 according to an embodiment of the present invention, a reset write operation can apply multiple current pulses (or spike currents) to the target memory cell. In this case, since a large write current is not used over a long period of time, not only can degradation of the memory cell be reduced, but the read margin for the memory cell (i.e., the difference in threshold voltage variation between the set state and the reset state) is properly maintained. Thus, a memory device with improved reliability and an improved lifespan is provided. The write operation of the memory device according to an embodiment of the present invention (in particular, the reset write operation) will be described in more detail with reference to the following drawings.

[0024] Figure 2 is a diagram illustrating the memory cell array of Figure 1 as an example. Figure 3 is a diagram illustrating one of the memory cells from Figure 2 as an example. For the sake of brevity of the drawings and for ease of explanation, it is assumed that the memory cell array 110 includes nine memory cells (MC11 to MC33) arranged in a 3x3 configuration. However, the scope of the present invention is not limited thereto, and the number and arrangement of memory cells can be varied in many ways. Also, while one memory cell (e.g., MC22) is described with reference to Figure 3, the scope of the present invention is not limited thereto, and other memory cells may also have a structure similar to the memory cell (MC22) in Figure 3.

[0025] Referring to Figures 1 to 3, the memory cell array 110 may include multiple memory cells (MC11 to MC33). The multiple memory cells (MC11 to MC33) are connected to multiple word lines (WL1 to WL3) and multiple bit lines (BL1 to BL3).

[0026] Each of the multiple memory cells (MC11-MC33) may be a phase-change memory cell. For example, one of the multiple memory cells (MC11-MC33), e.g., MC22, is shown in Figure 3. As shown in Figure 3, the memory cell (MC22) may be coupled between the second word line (WL2) and the second bit line (BL2). The memory cell (MC22) may include an ovonic threshold switch (OTS) and a phase-change material (GST).

[0027] An ovonic threshold switch (OTS) can be a switching element having bidirectional characteristics. In an exemplary embodiment, an ovonic threshold switch (OTS) can be a switching element having nonlinear current-voltage characteristics (or snapback characteristics). In an exemplary embodiment, an ovonic threshold switch (OTS) can have a higher crystalline-amorphous phase transition temperature than a phase-change material (GST). In one example, the phase transition temperature of an ovonic threshold switch (OTS) can be about 350°C to about 450°C.

[0028] In an exemplary embodiment, the ovonic threshold switch (OTS) may include at least one of GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, and SnTe. In an exemplary embodiment, the ovonic threshold switch (OTS) may include at least one of GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe. In an exemplary embodiment, the ovonic threshold switch (OTS) may include at least one of GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAsSeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn, and GeAsTeZn.In an exemplary embodiment, the ovonic threshold switch (OTS) is made of GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeA sSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAs It may contain at least one of SeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSeAlSn, GeAsSeTlZn, GeAsSeTlSn, and GeAsSeZnSn.In an exemplary embodiment, the ovonic threshold switch (OTS) is made of GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSS n, GeAsSeTePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsS eInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGa Sn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl, It may contain at least one of the following: GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, and GeAsSeSAlSn.

[0029] Phase change materials (GSTs) are crystalline. (state) or amorphous state The phase change material (GST) may be in one of the following states. For example, if the phase change material (GST) is in a crystalline state, it may have a lower threshold voltage than if the phase change material (GST) is in an amorphous state. In an exemplary embodiment, if the phase change material (GST) is in a crystalline state, the memory cell (MC22) may be in a set state, and if the phase change material (GST) is in an amorphous state, the memory cell (MC22) may be in a reset state.

[0030] The state of a phase-change material (GST) (that is, the crystalline state (crystalline) state) or amorphous (non-crystalline) state (amorphous The state of the phase-change material (GST) is determined by temperature. In an example embodiment, the phase transition temperature between the crystalline and amorphous states of the phase-change material (GST) may be approximately 250°C to approximately 350°C. The temperature of the phase-change material (GST) can be determined by the magnitude and duration of the write current (Iwr) flowing through the memory cell (MC22). For example, if the write current (Iwr) is applied at a first level within a first time, the state of the phase-change material (GST) may be crystalline, and if the write current (Iwr) is applied at a second level greater than the first level within a second time shorter than the first time, the state of the phase-change material (GST) may be amorphous. In other words, the state of the memory cell (MC22) can change depending on the magnitude and duration of the write current (Iwr), thereby allowing data to be written to the memory cell (MC22). In an example embodiment, the magnitude and duration of the write current (Iwr) are determined according to the voltage difference between the second bit line (BL2) and the second word line (WL2) and the characteristics of the ovonic threshold switch (OTS).

[0031] In an example embodiment, the phase change material (GST) is formed in a compound in which at least one of the chalcogenide elements Te, Se, and S is combined with at least one selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C.

[0032] In an exemplary embodiment, the phase change material (GST) may include at least one of GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, Ysb, CeSb, DySb, and NdSb. In an exemplary embodiment, the phase change material (GST) may include at least one of GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, and NdSbS. In an example embodiment, the phase change material (GST) is GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn, G It may include at least one of the following: eSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe, and NdGeSbS.In the embodiment of the example, the phase change material (GST) is InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeSc SbSeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeSc SbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, GeSb It may include at least one of the following: SeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTeSIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl, GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGaSn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn, and GeSbSeZnSn.

[0033] In the embodiment shown in Figure 3, an ovonic threshold switch (OTS) is connected to a second bit line (BL2), and a phase change material (GST) is connected between the ovonic threshold switch (OTS) and a second word line (WL2), but the scope of the present invention is not limited thereto. For example, the ovonic threshold switch (OTS) may be a bidirectional switching element, and therefore the ovonic threshold switch (OTS) may be connected to a word line, and the phase change material (GST) may be connected between the ovonic threshold switch (OTS) and a bit line.

[0034] In an example embodiment, the write current (Iwr) is shown as flowing from the bit line to the word line in the embodiment of Figure 3, but the scope of the present invention is not limited thereto, and the direction of the write current (Iwr) or read current (not shown) can vary in various ways depending on the implementation method of the memory device (i.e., WL to BL or BL). (to WL). For the sake of explanation, we will assume below that the write current (in particular, the current for the reset write operation) flows from the bit line to the word line.

[0035] Figures 4A and 4B illustrate the characteristics of memory cells according to their state. Figure 4A shows the variation in the threshold voltage of memory cells, and Figure 4B shows the voltage-current curve according to the state of the memory cells. In Figure 4A, the horizontal axis of the variation graph represents the threshold voltage of the memory cells, and the vertical axis represents the number of memory cells. In Figure 4B, the horizontal axis of the graph represents the voltage applied to the memory cells (i.e., the voltage difference between the bit line and the word line), and the vertical axis represents the current flowing through the memory cells.

[0036] Referring to Figures 4A and 4B, as previously explained, a memory cell can be in either a set state (SET) or a reset state (RST). The threshold voltage (Vth) of a memory cell in the set state (SET) may be lower than the threshold voltage (Vth) of a memory cell in the reset state (RST). For example, the upper limit of the threshold voltage variation in the set state (SET) may be smaller than the lower limit of the threshold voltage variation in the reset state (RST). For example, as shown in Figure 4B, the threshold voltage of a memory cell in the set state (SET) may be a first threshold voltage (Vth1), and the threshold voltage of a memory cell in the reset state (RST) may be a second threshold voltage (Vth2) which is higher than the first threshold voltage (Vth2).

[0037] To read data stored in a specific memory cell, a read voltage (Vread) is applied between the bit line and word line of that memory cell. As shown in Figure 4B, if the memory cell is in the set state (SET), it is turned on, and if it is in the reset state (RST), it is turned off. In other words, by applying a read voltage (Vread) between the bit line and word line connected to the memory cell, the data stored in that memory cell is read by reading whether the memory cell is turned on or off.

[0038] Figure 5 is a flowchart illustrating the write operation of the memory device shown in Figure 1 as an example. Figure 6 is a diagram illustrating the operation shown in the flowchart of Figure 5. For the sake of explanation, it is assumed that the memory device 100 performs a reset write operation on the memory cell (MC22). In other words, the memory device 100 can change the state of the memory cell (MC22) from the set state (SET) to the reset state (RST) through the write method described below. Hereinafter, the memory cell (MC22) will be referred to as the target memory cell, and the second bit line (BL2) and the second word line (WL2) will be referred to as the target bit line and the target word line, respectively.

[0039] Below, we will discuss voltage bias (voltage bias). The terms voltage bias and current bias are used. Voltage bias can refer to the voltage difference between the corresponding bit line and word line. Current bias can refer to the limiting current flowing through the corresponding bit line. In this case, it should be understood that the limiting current due to the current bias is not absolute, and even if the current is limited by the current bias, a higher current than the current bias can momentarily flow depending on other voltage biases or the physical state of the target memory cell.

[0040] Referring to Figures 1, 5, and 6, in step S101, the memory device 100 can select a target memory cell. For example, the memory device 100 can receive an address and data from an external device (e.g., a memory controller) and select a target memory cell based on the received address and data. In this case, the target memory cell may refer to a memory cell that is changed from the set state (SET) to the reset state (RST).

[0041] As a more detailed example, as shown in Figure 6, a memory cell (MC22) (hereinafter referred to as the "target memory cell") may be selected as the target memory cell. The target memory cell (MC22) can refer to a memory cell that is changed from the set state (SET) to the reset state (RST).

[0042] In step S110, the memory device 100 can turn on the target memory cell by controlling the target bit line (BL) and target word line (WL) corresponding to the target memory cell. For example, the memory device 100 can apply a first voltage bias (VB1) between the target bit line (BL2) and the target word line (WL2) connected to the target memory cell (MC22). In a more detailed example, as shown in Figure 6, a selected bit line voltage (VBL_sel) is applied to the target bit line (BL2) connected to the target memory cell (MC22), and a selected word line voltage (VWL_sel) is applied to the target word line (WL2) connected to the target memory cell (MC22). At this time, the difference between the selected word line voltage (VWL_sel) and the selected bit line voltage (VBL_sel) may be the first voltage bias (VB1).

[0043] The memory device 100 can apply a first current bias (CB1) to the target bit line (BL2) connected to the target memory cell (MC22). The first current bias (CB1) limits the current flowing through the target bit line (BL2).

[0044] In an example embodiment, the first voltage bias (VB1) may be at a voltage level higher than the threshold voltage of the memory cell in the reset state (SET). That is, when the first voltage bias (VB1) is applied to the target bit line (BL2) and target word line (WL2) of the target memory cell (MC22), the target memory cell (MC22) should be turned on. The first current bias (CB1) may be the set write current (described with reference to Figure 7 below).

[0045] In an example embodiment, an unselected word line voltage (VWL_unsel) may be applied to unselected word lines (e.g., WL1, WL3), and an unselected bit line voltage (VBL_unsel) may be applied to unselected bit lines (BL1, BL3). The unselected word line voltage (VWL_unsel) and the unselected bit line voltage (VBL_unsel) may be set so that the remaining memory cells (MC11~MC13, MC21, MC23, MC31~MC33) are not turned on, excluding the target memory cell (MC22).

[0046] For example, memory cell (MC11) may not be turned on due to the unselected word line voltage (VWL_unsel) of the first word line and the unselected bit line voltage (VBL_unsel) of the first bit line (BL1). Memory cell (MC12) may not be turned on due to the unselected word line voltage (VWL_unsel) of the first word line and the selected bit line voltage (VBL_unsel) of the second bit line (BL2). Memory cell (MC21) may not be turned on due to the selected word line voltage (VWL_sel) of the second word line (WL2) and the unselected bit line voltage (VBL_unsel) of the first bit line (BL1).

[0047] In step S120, the memory device 100 can control the bit line (BL2) and word line (WL2) corresponding to the target memory cell (MC22) to provide a reset write current to the target memory cell (MC22). For example, the memory device 100 can control the selected bit line voltage (VBL_sel) and selected word line voltage (VWL_sel) so that a second voltage bias (VB2) is applied to the target bit line (BL2) and target word line (WL2) of the target memory cell (MC22). The memory device 100 can also apply a second current bias (CB2) to the target bit line (BL2) of the target memory cell (MC22).

[0048] The operation of step S120 is similar to that of step S110, except that the voltage and current biases between the target bit line (BL) and the target word line connected to the target memory cell are different; therefore, a detailed explanation of this is omitted. In the exemplary embodiment, the second voltage bias (CB2) may be greater than the first voltage bias (CB1), and the second current bias (CB2) may be greater than the first current bias (CB1). In the exemplary embodiment, the second current bias (CB2) may correspond to the magnitude of the reset write current.

[0049] In step S130, the memory device 100 can control the second bit line (BL2) and second word line (WL2) corresponding to the target memory cell (MC22) to provide a spike current (or current pulse) to the target memory cell (MC22). For example, the memory device 100 can control the selected bit line voltage (VBL_sel) and selected word line voltage (VWL_sel) so that a third voltage bias (VB3) is applied to the second bit line (BL2) and second word line (WL2) of the target memory cell (MC22). The memory device 100 can also apply a third current bias (CB3) to the second bit line (BL2) of the target memory cell (MC22).

[0050] The operation of step S130 is similar to that of step S110, except that the voltage and current biases between the second bit line (BL2) and the second word line (WL2) of the target memory cell (MC22) are different, so a detailed explanation of this is omitted. In the exemplary embodiment, the third current bias (CB3) may be smaller than the first and second current biases (CB1, CB2), respectively. In the exemplary embodiment, the third current bias (CB3) may be smaller than or equal to the hold current (Ihold) depending on the current-voltage characteristics of the target memory cell (MC22). In the exemplary embodiment, the hold current (Ihold) may represent the magnitude of the minimum current required for the target memory cell (MC22) to maintain the turn-on state.

[0051] In an exemplary embodiment, when a third voltage bias (VB3) and a third current bias (CB3) are applied to the target memory cell through the operation of step S130, at least one spike current (or at least one current pulse) may be generated due to the physical characteristics of the target memory cell. In an exemplary embodiment, at least one spike current may be generated by the repetitive switching operation of the target memory cell.

[0052] At least one spike current (or at least one current pulse) can fine-tune (or increase) the threshold voltage of the target memory cell. In other words, as the threshold voltage of the target memory cell increases due to at least one spike current (or at least one current pulse), a read margin is ensured. Write operation using at least one spike current (or at least one current pulse) is described in more detail with reference to the following diagram.

[0053] As described above, according to embodiments of the present invention, the memory device 100 can turn on the target memory cell based on the first voltage bias (VB1). Thereafter, the memory device 100 can increase the threshold voltage of the target memory cell by applying a reset write current to the target memory cell based on the second voltage bias (VB2). Thereafter, the memory device 100 can gradually increase the threshold voltage of the target memory cell by applying at least one spike current or at least one current pulse to the target memory cell based on the third voltage bias (VB3).

[0054] In an exemplary embodiment, the memory device 100 according to an embodiment of the present invention can generate at least one current pulse while maintaining a constant voltage bias between the target bit line and the target word line of the target memory cell.

[0055] In an exemplary embodiment, the time during which a reset write current is applied in the memory device 100 according to an embodiment of the present invention may be shorter than the time during which a reset write current is applied in a conventional phase-change memory. However, in the present invention, data can be successfully written to the target memory cell by gradually or progressively increasing the threshold voltage of the target memory cell via at least one spike current or at least one current pulse. Therefore, the lifespan and reliability of the memory device can be improved.

[0056] Figure 7 is a timing diagram illustrating the current flowing through the target memory cell as an example, in accordance with the operation of the flowchart in Figure 6. In the timing diagram of Figure 7, the horizontal axis represents time, and the vertical axis represents the current flowing through the target memory cell (MC22).

[0057] Referring to Figures 6 and 7, the memory device 100 can change the state of the target memory cell (MC22) from the set state (SET) to the reset state (RST) via the first to third sections (PR1 to PR3). The first section (PR1) corresponds to stage S110 in Figure 6, the second section (PR2) corresponds to stage S120 in Figure 6, and the third section (PR3) corresponds to stage S130 in Figure 6.

[0058] Firstly, in the interval (PR1) from time zero (t0) to time one (t1), a first voltage bias (VB1) may be applied to the second bit line (BL2) and second word line (WL2) of the target memory cell (MC22). In this case, a current can flow through the target memory cell as shown in the first interval (PR1) of Figure 7. As a more detailed example, at time zero (t0), the target memory cell (MC22) may be in a set state (SET). The first voltage bias (VB1) may be higher than the upper limit of the threshold voltage variation of the set state (SET). Therefore, if the first voltage bias (VB1) is applied at time zero (t0), the target memory cell is turned on, and a momentary peak current (Isp) can flow. Thereafter, the magnitude of the current is maintained at the set write current (Iset), while the current decreases according to the current-voltage characteristics (i.e., snapback characteristics) of the target memory cell.

[0059] In the exemplary embodiment, the first current bias (CB1) applied from the first section (PR1) corresponds to the set-write current (ISET). In the exemplary embodiment, if the set-write current (ISET) is continuously maintained, the target memory cell may be in a set state (SET). That is, if the target memory cell must be changed from a reset state (RST) to a set state (SET), the current flowing through the target memory cell is maintained at the set-write current (ISET).

[0060] Thereafter, a second voltage bias (VB2) may be applied to the second bit line (BL2) and second word line (WL2) of the target memory cell (MC22) within the second interval (PR2) from the first time point (t1) to the second time point (t2). In this case, a reset write current (Irst) may flow through the target memory cell as shown in the second interval (PR2) of Figure 7. The reset write current (Irst) may be greater than the set write current (Iset). The reset write current (Irst) may be the current that causes the phase change material (GST) of the target memory cell to become amorphous. In an example embodiment, the second current bias (CB2) applied from the second interval (PR2) corresponds to the reset write current (Irst).

[0061] Subsequently, during the third interval (PR3) from the second time point (t2) to the third time point (t3), a third voltage bias (VB3) may be applied to the second bit line (BL2) and the second word line (WL2) of the target memory cell (MC22). At this time, the third voltage bias (VB3) may be lower than the second voltage bias (CB2), and may be lower than or the same as the first voltage bias (CB1).

[0062] As a third voltage bias (VB3) is applied to the second bit line (BL2) and second word line (WL2) of the target memory cell (MC22) within the third section (PR3), multiple spike currents (or multiple current pulses) as shown in Figure 7 can flow through the target memory cell. In this example embodiment, the peak value of the multiple spike currents may have an Isp value or vary depending on the number of current pulses generated. The peak value of the multiple spike currents is determined based on the current state or physical characteristics of the target memory cell.

[0063] In an exemplary embodiment, the number of multiple spike currents can vary depending on the current state or physical characteristics of the target memory cell.

[0064] In the example embodiment, the time of the first interval (PR1) (i.e., t0~t1), the time of the second interval (PR2) (i.e., t1~t2), and the time of the third interval (PR3) (i.e., t2~t3) can each be a predetermined time. In the example embodiment, the time of each of the first to third intervals (PR1 to PR3) may have the relationship PR2 > PR3 ≥ PR1.

[0065] Figures 8A to 8D are timing diagrams illustrating voltage bias as an example, corresponding to the operation of the flowchart in Figure 6. In the timing diagrams of Figures 8A to 8D, the horizontal axis represents time, and the vertical axis represents voltage. For the sake of simplicity in the diagrams, in each timing diagram, the selected word line voltage (VWL_sel) is shown by a dashed line, and the selected bit line voltage (VBL_sel) is shown by a solid line. The selected bit line voltage (VBL_sel) and selected word line voltage (VWL_sel), as described with reference to Figures 8A to 8D, are generated by or regulated by the voltage bias circuit 150, as described with reference to Figure 1.

[0066] As shown in Figure 8A, during a reset write operation, the selected word line voltage (VWL_sel) can maintain a constant level, while the selected bit line voltage (VBL_sel) can vary in the first to third intervals (PR1 to PR3). For example, in the first interval (PR1), the selected bit line voltage (VBL_sel) can be increased so that the voltage difference between it and the selected word line voltage (VWL_sel) becomes the first voltage bias (VB1). Subsequently, in the second interval (PR2), the selected bit line voltage (VBL_sel) can be increased so that the voltage difference between it and the selected word line voltage (VWL_sel) becomes the second voltage bias (VB2). Then, in the third interval (PR3), the selected bit line voltage (VBL_sel) can be decreased so that the voltage difference between it and the selected word line voltage (VWL_sel) becomes the third voltage bias (VB3). In an example embodiment, the selected word line voltage (VWL_sel) may be the ground voltage or a predetermined voltage.

[0067] Next, as shown in Figure 8B, during a reset write operation, the selected word line voltage (VWL_sel) and the selected bit line voltage (VBL_sel) can be changed in the first to third intervals (PR1 to PR3). For example, in the first interval (PR1), the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) can each be increased or decreased from voltage (Va) so that the difference between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) becomes the first voltage bias (VB1). Subsequently, in the second interval (PR2), the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) can each be increased or decreased so that the difference between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) becomes the second voltage bias (VB2). Subsequently, in the third section (PR3), the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) can be decreased and increased respectively, such that the difference between them becomes the third voltage bias (VB3). In an example embodiment, the voltage (Va) may be the ground voltage or a predetermined voltage.

[0068] Next, as shown in Figure 8C, during a reset write operation, the selected word line voltage (VWL_sel) and the selected bit line voltage (VBL_sel) can be changed in the first to third intervals (PR1 to PR3). For example, in the first interval (PR1), the selected word line voltage (VWL_sel) can be maintained at a voltage (Va), and the selected bit line voltage (VBL_sel) can be increased so that the voltage difference between it and the selected word line voltage (VWL_sel) becomes the first voltage bias (VB1). Subsequently, in the second interval (PR2), the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) can be increased and decreased respectively so that the voltage difference between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) becomes the second voltage bias (VB2). Subsequently, in the third section (PR3), the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) can be decreased and increased respectively, such that the difference between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) becomes the third voltage bias (VB3). In an exemplary embodiment, the selected word line voltage (VWL_sel) in the first and third sections (PR1, PR3) may be the same as the voltage (Va). The voltage (Va) may be the ground voltage or a predetermined voltage.

[0069] Next, as shown in Figure 8D, during a reset write operation, the selected bit line voltage (VBL_sel) can be maintained at a constant level, while the selected word line voltage (VWL_sel) can be varied in the first to third intervals (PR1 to PR3). For example, in the first interval (PR1), the selected word line voltage (VWL_sel) can be decreased so that the voltage difference between it and the selected bit line voltage (VBL_sel) becomes the first voltage bias (VB1). Subsequently, in the second interval (PR2), the selected word line voltage (VWL_sel) can be decreased so that the voltage difference between it and the selected bit line voltage (VBL_sel) becomes the second voltage bias (VB2). Then, in the third interval (PR3), the selected word line voltage (VBL_sel) can be increased so that the voltage difference between it and the selected bit line voltage (VBL_sel) becomes the third voltage bias (VB3). In an example embodiment, the selected bit line voltage (VBL_sel) may be the ground voltage or a predetermined voltage.

[0070] The bit line and word line control methods described above are examples only, and the scope of the present invention is not limited thereto. For example, a memory device 100 according to an embodiment of the present invention can control the bit line and word line of a target memory cell by various methods during a reset write operation. In this case, the memory device 100 can control the bit line and word line of a target memory cell so that the voltage difference between the bit line and word line of the target memory cell becomes the first to third voltage biases (VB1, VB2, VB3) within the first to third intervals (PR1 to PR3).

[0071] In an exemplary embodiment, the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) are controlled in various ways depending on the method of driving the selected bit line voltage (VBL_sel) and selected word line voltage (VWL_sel). For example, the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) may have intermediate values ​​between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) in each interval. For example, referring to the timing diagram in Figure 8A, in the first interval (PR1), the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) may be higher than the selected word line voltage (VWL_sel) by half of the first voltage bias (VB1) (i.e., VB1 / 2), in the second interval (PR2), the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) may be higher than the selected word line voltage (VWL_sel) by half of the second voltage bias (VB2) (i.e., VB2 / 2), and in the third interval (PR3), the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) may be higher than the selected word line voltage (VWL_sel) by half of the third voltage bias (VB3) (i.e., VB3 / 2). Furthermore, when the selected bit line voltage (VBL_sel) and selected word line voltage (VWL_sel) are driven as shown in Figure 8B, the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) may be a specific voltage (Va).

[0072] In this case, the voltage difference between the unselected word line and the unselected bit line is 0V, and the voltage difference between the selected bit line and the unselected word line, as well as the voltage difference between the unselected bit line and the unselected word line, is at most VB2 / 2. Therefore, memory cells connected to the unselected word line or unselected bit line (for example, MC11, MC12, MC13, MC21, MC23, MC31, MC32, MC33 in Figure 6) may not be turned on.

[0073] The configurations of the unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) described above are simple examples, and the scope of the present invention is not limited thereto. The unselected bit line voltage (VBL_unsel) and unselected word line voltage (VWL_unsel) can be controlled in a variety of ways.

[0074] Figures 9A to 9C are a scatter plot, current-voltage graph, and timing diagram illustrating the operation of step S130 in Figure 5. In the scatter plots in Figures 9A to 9C, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. In the current-voltage graphs in Figures 9A to 9C, the horizontal axis represents the voltage applied to the memory cell (i.e., the voltage between the bit line and the word line), and the vertical axis represents the current flowing through the memory cell. In the timing diagrams in Figures 9A to 9C, the horizontal axis represents time, and the vertical axis represents the current flowing through the memory cell.

[0075] For the sake of simplicity and ease of explanation, the diagrams illustrate memory cell variations (scatter plots), current-voltage graphs, and timing diagrams corresponding to specific moments in time, but the scope of the present invention is not limited thereto.

[0076] Referring to Figures 5 and 9A, after the operation of step S120 is completed, the target memory cell may have a first threshold voltage (Vth1), as shown in the variation in Figure 9A. In other words, the threshold voltage of the target memory cell has risen compared to the set state (SET), but the threshold voltage of the target memory cell may not reach the intended reset state (RST).

[0077] At this time, a third voltage bias (VB3) may be applied between the bit line and word line of the target memory cell. The third voltage bias (VB3) may be higher than the upper limit of the threshold voltage variation for the set state (SET) and lower than the lower limit of the threshold voltage variation for the reset state (RST). In the example embodiment, the third voltage bias (VB3) corresponds to the read voltage (Vread) described with reference to Figures 4A and 4B. The third voltage bias (VB3) also corresponds to the lower limit of the threshold voltage variation for the reset state (RST) of the memory cell.

[0078] When a third voltage bias (VB3) is applied between the bit line and word line of the target memory cell, the third voltage bias (VB3) is higher than the first threshold voltage (Vth1) of the target memory cell, as shown in the current-voltage graph of Figure 9A, and therefore a first peak current (Isp1) can flow through the target memory cell ((1)).

[0079] Since a third current bias (CB3) is applied through the bit line of the target memory cell, after the operation of (1), the current flowing through the target memory cell can be gradually reduced to the third current bias (CB3) ((2)). In an exemplary embodiment, the third current bias (CB3) may be less than or equal to the hold current (Ihold) of the target memory cell. The hold current (Ihold) may refer to the minimum current required for the target memory cell to maintain the turn-on state. In this case, if the current flowing through the target memory cell drops below the hold current (Ihold), the target memory cell may be turned off ((3)).

[0080] The current flowing through the target memory cell due to the operations (1), (2), and (3) described above may be the same as the timing diagram in Figure 9A. That is, when a third voltage bias (VB3) is applied between the bit line and word line of the target memory cell, and a third current bias (CB3) is applied to the target memory cell, the turn-on / turn-off of the target memory cell (in particular the ovonic threshold switch (OTS)) generates a spike current (or current pulse) with a first peak current (Isp1).

[0081] In an exemplary embodiment, a spike current (or current pulse) can raise the threshold voltage of a target memory cell by a predetermined level, as shown in Figure 9B. For example, a spike current (or current pulse) described with reference to Figure 9A can raise the threshold voltage of a target memory cell from a first threshold voltage (Vth1) to a second threshold voltage (Vth2). In this case, the current-voltage characteristics of the target memory cell are illustrated by the dashed line in the current-voltage graph of Figure 9B.

[0082] At this time, the memory device 100 will maintain the voltage difference between the bit line and word line of the target memory cell at a third voltage bias (VB3). In this case, as previously described, since the third voltage bias (VB3) is higher than the second peak voltage (Vth2), the target memory cell is turned on, and a second peak current (Isp2) can flow through the target memory cell ((4)). In an exemplary embodiment, the second peak current (Isp2) may be greater than the first peak current (Isp1) described with reference to Figure 9A. However, the scope of the present invention is not limited thereto, and depending on the physical characteristics of the memory cell, the peak values ​​for multiple spike currents may be the same or different from one another.

[0083] Thereafter, as explained earlier, the current flowing through the target memory cell can be gradually reduced to the third current bias (CB3) ((5)), and the target memory cell is turned off when the current flowing through the target memory cell falls below the hold current (Ihold) ((6)).

[0084] As described above, when a third voltage bias (VB3) is applied between the bit line and word line of the target memory cell, and a third current bias (CB3) is applied to the target memory cell, the physical characteristics of the target memory cell (e.g., current-voltage snapback characteristics) can cause the target memory cell (in particular, an ovonic threshold switch (OTS)) to be repeatedly turned on and turned off. Repeated turning on and turning off of the target memory cell (in particular, an ovonic threshold switch (OTS)) can generate spike currents or current pulses, which can cause the threshold voltage of the target memory cell to gradually increase.

[0085] In an exemplary embodiment, the repeated turning on and turning off of the target memory cell (in particular, the ovonic threshold switch (OTS)) described above is performed until the threshold voltage of the target memory cell increases to a specific value (e.g., a third voltage bias (VB3) or a reset threshold voltage (Vth_RST)).

[0086] For example, as shown in Figure 9C, when a third voltage bias (VB3) is applied to the bit line and word line of the target memory cell, and a third current bias (CB3) is applied to the target memory cell, repeated turn-on and turn-off operations on the target memory cell can generate spike currents or current pulses. The generated spike currents or current pulses gradually increase the threshold voltage of the target memory cell, allowing it to reach the reset threshold voltage (Vth_RST).

[0087] In this case, the current-voltage characteristics of the target memory cell are represented by a solid line in the current-voltage graph of Figure 9C. As shown in the current-voltage graph of Figure 9C, the target memory cell should remain in the turn-off state because the threshold voltage of the target memory cell (i.e., Vth_RST) is higher than the third voltage bias (VB3). Therefore, no spike current or current pulses as described earlier are generated.

[0088] As described above, the memory device 100 according to an embodiment of the present invention can increase the threshold voltage of a target memory cell by applying a reset write current (Irst) to the target memory cell during a reset write operation. Subsequently, the memory device 100 can apply a third voltage bias (VB3) to the bit line and word line of the target memory cell and apply a third current bias (CB3) to the target memory cell. At this time, the target memory cell is repeatedly turned on and turned off, causing multiple spike currents or multiple current pulses to flow through the target memory cell. Through multiple spike currents or multiple current pulses, the threshold voltage of the target memory cell can be gradually increased to an intended threshold voltage (e.g., Vth_RST). In an exemplary embodiment, the target memory cell is repeatedly turned on and turned off until the threshold voltage of the target memory cell becomes equal to or greater than the intended threshold voltage. The number of turns on and off cycles of the target memory cell or the number of spike currents may vary depending on the physical characteristics of the target memory cell or its current state and current threshold voltage.

[0089] Figure 10 is a flowchart illustrating the operation of the memory device shown in Figure 1 as an example. Referring to Figures 1 and 10, the memory device 100 can perform the operations in stages S201, S210, S220, and S230. The operations in stages S201, S210, S220, and S230 are similar to the operations in stages S101, S110, S120, and S130 in Figure 5, so a detailed explanation of these will be omitted.

[0090] After step S230, in step S240, the bit line (BL) and word line (WL) corresponding to the target memory cell can be controlled to stabilize the threshold voltage of the target memory cell. For example, the memory device 100 can apply a fourth voltage bias (VB4) between the bit line (BL) and word line (WL) connected to the target memory cell, and apply a fourth current bias (CB4) to the bit line (BL) connected to the target memory cell. In an exemplary embodiment, the fourth voltage bias (VB4) may be lower than the lower limit of the threshold voltage variation of the set state (SET) of the memory cell. Through the operation of step S240, an electric field (electrical) is applied to the target memory cell having a reset state (RST). A field is added, which stabilizes the change in threshold voltage of the target memory cell having a reset state (RST).

[0091] As described above, immediately after the reset write operation on the target memory cell is completed, a fourth voltage bias (VB4) may be applied to the bit line and word line of the target memory cell. In this case, the change in the threshold voltage of the target memory cell is stabilized through the electric field formed by the fourth voltage bias (VB4).

[0092] Figure 11 is a timing diagram illustrating the voltage bias corresponding to the operation of the flowchart in Figure 10 as an example. In the timing diagram of Figure 11, the horizontal axis represents time and the vertical axis represents voltage. For the sake of simplicity in the diagram, in a single timing diagram, the selected word line voltage (VWL_sel) is shown as a dashed line and the selected bit line voltage (VBL_sel) is shown as a solid line.

[0093] Referring to Figures 1, 10, and 11, the memory device 100 can perform a reset write operation by controlling the bit line and word line of the target memory cell, as shown in Figure 11. For example, the memory device 100 can control the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) via the first to third intervals (PR1 to PR3). The first to third intervals (PR1 to PR3) are the same as those described with reference to Figure 8A, so a detailed explanation of them is omitted.

[0094] After the third interval (PR3), during the fourth interval (PR4) (i.e., t3~t4), the memory device 100 can lower the selected bit line voltage (VBL_sel) so that the difference between the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) becomes the fourth voltage bias (VB4). In other words, by providing the fourth voltage bias (VB4) to the bit line and word line of the target memory cell during the fourth interval (PR4), the change in the threshold voltage of the target memory cell is stabilized.

[0095] In an exemplary embodiment, the fourth voltage bias (VB4) applied in the fourth interval (PR4) may be at a level lower than the first threshold voltage (Vth1) (see Figure 4B) which refers to the threshold voltage of the memory cell in the set state (SET). In an exemplary embodiment, the fourth voltage bias (VB4) applied in the fourth interval (PR4) may be controlled in a multi-step manner. That is, the fourth voltage bias (VB4) may be controlled to decrease or increase stepwise or progressively within the fourth interval (PR4). The maximum value of the multi-step controlled fourth voltage bias (VB4) may be at a level lower than the first threshold voltage (Vth1) (see Figure 4B) which refers to the threshold voltage of the memory cell in the set state (SET).

[0096] In an exemplary embodiment, a configuration for controlling the selected bit line voltage (VBL_sel) and the selected word line voltage (VWL_sel) was described with reference to Figure 11, but the scope of the present invention is not limited thereto. For example, based on the methods described with reference to Figures 8A to 8D, or on various other methods, the memory device 100 can control the voltages applied to the bit line and word line of a target memory cell. In this case, the voltage difference between the bit line and the word line is controlled by first to fourth voltage biases (VB1 to VB4) depending on the section.

[0097] Figure 12 is a circuit diagram illustrating the current bias circuit of Figure 1 as an example. Figure 13 is a timing diagram illustrating the operation of the current bias circuit of Figure 12. In the timing diagram of Figure 13, the horizontal axis represents time, and the vertical axis represents the current flowing through the target memory cell. For ease of explanation, one spike current (or one current pulse) is shown in Figure 13. Referring to Figures 1, 12, and 13, the current bias circuit 150 may include a plurality of switches (SW1 to SWn) and a plurality of capacitors (C1 to Cn). Each of the plurality of switches (SW1 to SWn) is connected in series between the current bias node (CB) and a specific voltage node to each of the plurality of capacitors (C1 to Cn).

[0098] Each of the multiple switches (SW1 to SWn) is turned on or turned off based on the control of the control logic circuit 160. As the number of switches that are turned on increases, the combined capacitance value formed by the multiple capacitors (C1 to Cn) can be increased. As the combined capacitance value increases, the duration for which a single spike current or a single current pulse is maintained can be increased.

[0099] For example, as shown in Figure 13, if a switches out of a group of switches (SW1 to SWn) are turned on, one spike current may be maintained within the first time (p1). In other words, one spike current may decrease from its peak value to zero within the first time (p1). If b switches out of a group of switches (SW1 to SWn) (where b is greater than a) are turned on, one spike current may be maintained for a second time (p2), which is longer than the first time (p1). If all switches (SW1 to SWn) (i.e., n switches) are turned on, one spike current will be maintained for an nth time (pn), which is longer than the second time (p2).

[0100] As described above, the combined capacitance value of the current bias circuit 150 is adjusted by controlling multiple switches in the current bias circuit 150, and the time that a single spike current is maintained and the time that it decreases from its peak value to zero are controlled by the adjusted combined capacitance value.

[0101] Figure 14 is a block diagram showing an example of a memory device according to an embodiment of the present invention. Referring to Figure 14, the memory device 200 may include a memory cell array 210, an X-decoder 220, a Y-decoder 230, a voltage bias circuit 240, a current bias circuit 250, a control logic circuit 260, and a compensation circuit 270. The memory cell array 210, X-decoder 220, Y-decoder 230, voltage bias circuit 240, current bias circuit 250, and control logic circuit 260 have been described previously, so a detailed explanation of them will be omitted.

[0102] The memory device 200 in Figure 14 may further include a compensation circuit 270. The compensation circuit 270 can perform a variety of compensation operations on the memory device 200. For example, the compensation circuit 270 may be configured to control the voltage bias or current bias applied to the target memory cell depending on the temperature of the memory device 200. In an exemplary embodiment, the voltage bias is controlled during compensation by controlling the selected word line voltage (VWL_sel), the unselected word line voltage (VWL_unsel), the selected bit line voltage (VBL_sel), and the unselected bit line voltage (VBL_unsel). In an exemplary embodiment, the current bias is controlled during compensation by controlling the combined capacitance value of the current bias circuit 250.

[0103] For example, the compensation circuit 270 can perform compensation operations for the voltage bias based on the temperature of the memory device 200. If the temperature of the memory device 200 increases, the resistance in the path through which the write current flows will increase. In this case, the compensation circuit 270 can control the voltage bias based on the temperature compensation of the PTC (positive temperature coefficient). That is, temperature compensation for the voltage bias is performed by increasing the magnitude of the voltage bias (e.g., the voltage difference between the word line and the bit line) as the temperature of the memory device 200 increases. The current bias may also be affected by the offset due to temperature changes, as the magnitude of the reset write current of the memory cell can be varied with temperature.

[0104] In an example embodiment, the temperature information of the memory device 200 may be provided in the form of temperature data or temperature codes from another temperature detector, and the compensation circuit 270 is configured to determine the offsets applied to the voltage bias and current bias based on the temperature data or temperature codes.

[0105] In an exemplary embodiment, the compensation circuit 270 may be configured to control the voltage bias or current bias by performing position compensation according to the position of the target memory cell on the memory cell array 210. For example, if the physical position of the target memory cell is far from the X-decoder 120 and Y-decoder 150, the magnitude of the current flowing through the target memory cell or the voltage or current affecting the target memory cell will be smaller, even if the same voltage bias and current bias are applied. In other words, if the physical position of the target memory cell is far from the X-decoder 120 and Y-decoder 150, position compensation is performed by reflecting an offset in the voltage bias and current bias, respectively.

[0106] As a more detailed example, referring to the memory cell array 110 shown in Figure 2, the memory cell MC31 may be the closest memory cell to the X-decoder 120 and Y-decoder 130 among the shown memory cells, and the memory cell MC13 may be the furthest memory cell from the X-decoder 120 and Y-decoder 130 among the shown memory cells. The distance between the memory cell and the X-decoder 120 and Y-decoder 130 (i.e., the distance or physical location of the memory cell) may correspond to the sum of the length of the word line between the memory cell and the X-decoder 120 and the length of the bit line between the memory cell and the Y-decoder 120. In this example embodiment, the distance or physical location of the memory cell is determined based on address information.

[0107] As the distance to the target memory cell increases, the voltage bias offset can be increased. In other words, position compensation is performed by reflecting the increased offset in the voltage bias as the distance to the target memory cell increases. In an exemplary embodiment, with respect to the nearest memory cell, the value of the offset reflected as the distance increases can correspond to the product of the magnitude of the current flowing through the memory cell and the change in resistance due to the increase in the length of the word line and bit line.

[0108] As described above, the memory device 200 according to the embodiment of the present invention is configured to control the voltage bias or current bias by performing various compensation operations (e.g., temperature compensation, position compensation, or a combination thereof). This improves the reliability of the memory device.

[0109] Figure 15 is a circuit diagram illustrating an example of a three-dimensional structure of a memory device according to an embodiment of the present invention. Referring to Figure 15, the memory device is mounted in a three-dimensional stacked structure. For example, the memory device may include first to fourth memory cell array layers (MCA1 to MCA4). Each of the first to fourth memory cell array layers (MCA1 to MCA4) may include a plurality of memory cells (MC1, MC2, MC3, MC4).

[0110] The first to fourth memory cell array layers (MCA1 to MCA4) are stacked along the third direction (D3), and between each of the first to fourth memory cell array layers (MCA1 to MCA4), conductive lines (CL1, CL2) extending along the first and second directions (D1, D2) can be formed alternately. For example, the first conductive line (CL1) extends along the first direction (D1), and the second conductive line (CL2) extends along the second direction (D2). The first memory cell array layer (MCA1) is formed above the first conductive line (CL1), and the second conductive line (CL2) is formed between the first and second memory cell array layers (MCA1, MCA2). The first conductive line (CL1) is formed between the second and third memory cell array layers (MCA2, MCA3), and the second conductive line (CL2) is formed between the third and fourth memory cell array layers (MCA3, MCA4). A first conductive line (CL1) is formed on the upper part of the fourth memory cell array layer (MCA4). Each of the first and second conductive lines (CL1, CL2) is electrically connected to an adjacent memory cell along the third direction (D3).

[0111] In an exemplary embodiment, the first conductive line (CL1) may be a bit line or a word line as described with reference to Figures 1 to 14, and the second conductive line (CL2) may be a word line or a bit line as described with reference to Figures 1 to 14. For example, if the first conductive line (CL1) is a word line and the second conductive line is a bit line, the first and second memory cell array layers (MCA1, MCA2) may share a bit line with each other, the second and third memory cell array layers (MCA2, MCA3) may share a word line with each other, and the third and fourth memory cell array layers (MCA3, MCA4) may share a bit line with each other.

[0112] In an exemplary embodiment, the target bit line and target word line can be determined based on the location of the target memory cell. For example, if the first memory cell (MC1) of the first memory cell array layer (MCA1) is the target cell, the conductive lines (CL1a, CL2a) are selected as the target lines, and the selected target lines (CL1a, CL2a) are controlled based on the method described with reference to Figures 1 to 14. If the second memory cell (MC2) of the second memory cell array layer (MCA2) is the target cell, the conductive lines (CL2a, CL1b) are selected as the target lines, and the selected target lines (CL2a, CL1b) are controlled based on the method described with reference to Figures 1 to 14. If the third memory cell (MC3) of the third memory cell array layer (MCA3) is the target cell, the conductive lines (CL1b, CL2b) are selected as the target lines, and the selected target lines (CL1b, CL2b) are controlled based on the method described with reference to Figures 1 to 14. In other words, the target line is determined based on the location of the target memory cell, and the selected target line can then become a bit line or a word line, depending on the location of the selected target memory cell. However, the scope of the present invention is not limited to this.

[0113] The three-dimensional memory device shown in Figure 15 is an example, and the scope of the present invention is not limited thereto. For example, the number of memory cell array layers, the number of conductive lines, and the number of memory cells can each be increased or decreased depending on the mounting method.

[0114] Figure 16 is a block diagram illustrating an example of a memory system including a memory device according to the present invention. Referring to Figure 16, the memory system 1000 may include a controller 1100 and a memory device 1200. The controller 1100 can store data (DATA) in the memory device 1200 or read data (DATA) stored in the memory device 1200. For example, the controller 1100 can store data (DATA) in the memory device 1200 or read data (DATA) stored in the memory device 1200 by transferring an address (ADDR) and a command (CMD) to the memory device 1200.

[0115] In an exemplary embodiment, the memory device 1200 may be the memory devices (100, 200) described with reference to Figures 1 to 15, or it may operate based on the operating methods described with reference to Figures 1 to 15. In an exemplary embodiment, the controller 1100 may provide bias information (BS) to the memory device 1200. The bias information (BS) may include information related to various voltage biases and current biases described with reference to Figures 1 to 15. The memory device 1200 may be configured to store data (DATA) based on the bias information (BS).

[0116] In an exemplary embodiment, the memory system 1000 may be implemented in a memory module or storage device and can store data based on the control of an external host. In this case, the controller 1100 can communicate with the external host via a predetermined host interface. The host interface may include at least one of various interface conventions such as SATA (Serial ATA) interface, PCIe (Peripheral Component Interconnect Express) interface, SAS (Serial Attached SCSI) interface, NVMe (Nonvolatile Memory Express) interface, and UFS (Universal Flash Storage).

[0117] In an example embodiment, the controller 1100 can communicate with the memory device 1200 via a predetermined memory interface. The predetermined memory interface may include a high-speed interface such as a DDR4.0 interface or a DDR-T interface.

[0118] Figure 17 is a block diagram illustrating an example of a user system to which the memory device according to the present invention is applied. Referring to Figure 17, the user system 2000 may include a processor 2001 and a plurality of memory devices (2110 to 2140).

[0119] The processor 2001 may include a memory controller 2002. The memory controller 2002 can communicate with multiple memories (2110-2140) via a bus 2003. In an exemplary embodiment, the bus 2003 may include a dedicated bus connected to each of the multiple memories (2110-2140), or a shared bus shared by the multiple memories (2110-2140).

[0120] In an example embodiment, at least some of the multiple memories (2110 to 2140) are memory devices described with reference to Figures 1 to 16, and can operate based on the operating methods described with reference to Figures 1 to 16.

[0121] In an exemplary embodiment, at least some of the multiple memories (2110-2140) include phase-change memories as described with reference to Figures 1-16, while the remaining portion may include other types of memories (e.g., DRAM, NAND flash, MRAM, etc.).

[0122] The above-described content is a specific embodiment for carrying out the present invention. The present invention will also include not only the embodiments described above, but also embodiments that can be simply redesigned or easily modified. Furthermore, the present invention will also include techniques that can be easily modified and carried out using the embodiments. Therefore, the scope of the present invention should not be limited to the embodiments described above, but should be defined not only by the claims described later, but also by something equivalent to the claims of this invention.

Claims

1. A first phase-change memory cell is connected between the first bit line and the first word line, An X-decoder is configured to provide a selected word line voltage to the first word line during a reset write operation that changes the state of the first phase-change memory cell from a set state to a reset state, During the reset write operation, a Y-decoder is configured to provide a selected bit line voltage to the first bit line, The system includes a voltage bias circuit configured to generate the selected word line voltage and the selected bit line voltage based on a first voltage bias within a first interval of the reset write operation, generate the selected word line voltage and the selected bit line voltage based on a second voltage bias greater than the first voltage bias within a second interval of the reset write operation, and generate the selected word line voltage and the selected bit line voltage based on a third voltage bias smaller than each of the first and second voltage biases within a third interval of the reset write operation. A memory device in which, during the third interval of the reset write operation, a plurality of current pulses flowing through the first phase change memory cell are generated by the third voltage bias.

2. The memory device according to claim 1, further comprising a current bias circuit configured to provide a first current bias to the first bit line within a first interval of the reset write operation, a second current bias to the first bit line within a second interval of the reset write operation, and a third current bias to the first bit line within a third interval of the reset write operation.

3. The current bias circuit described above is Multiple switches, Includes multiple capacitors, The memory device according to claim 2, wherein each of the plurality of switches and each of the plurality of capacitors is connected in series between an output node from which each of the first to third current biases is output and a specific voltage.

4. The memory device according to claim 3, further comprising a control logic circuit configured to control the plurality of switches.

5. The first current bias corresponds to the magnitude of the set-write current, The second current bias corresponds to the magnitude of the reset write current. The memory device according to claim 2, wherein the third current bias is less than or equal to the magnitude of the hold current, which is the minimum current that maintains the turn-on state of the first phase-change memory cell.

6. The first phase-change memory cell is An ovonic threshold switch (OTS) connected to the first bit line, A memory device according to any one of claims 1 to 5, comprising a phase change material (GST) connected between the ovonic threshold switch and the first word line.

7. The first phase-change memory cell is An ovonic threshold switch (OTS) connected to the first word line, A memory device according to any one of claims 1 to 5, comprising a phase change material (GST) connected between the ovonic threshold switch and the first bit line.

8. The memory device according to any one of claims 1 to 7, wherein the first bit line extends in a first direction, and the first word line extends in a second direction perpendicular to the first direction.

9. The memory device according to claim 8, further comprising: a second phase-change memory cell stacked on top of the first phase-change memory cell in a direction perpendicular to the plane formed by the first and second directions, and connected to the first bit line and the second word line extending in the second direction.

10. The memory device according to any one of claims 1 to 9, further comprising a compensation circuit configured to reflect an offset based on the temperature of the memory device or the physical position of the first phase-change memory cell in each of the first to third voltage biases.

11. A method for operating a memory device including a phase-change memory cell, Within the first section of a reset write operation that writes the phase-change memory cell to a reset state, the steps include applying a first voltage bias to the bit line and word line connected to the phase-change memory cell, Within the second section of the reset write operation following the first section, a step is to apply a second voltage bias greater than the first voltage bias to the bit line and the word line connected to the phase change memory cell. The third section of the reset write operation, from the second section onward, includes the step of applying a third voltage bias, which is less than or equal to the first voltage bias, to the bit line and the word line connected to the phase change memory cell. An operating method wherein, during the third interval of the reset write operation, a plurality of current pulses flowing through the phase change memory cell are generated by the third voltage bias.

12. Within the first section, the steps include applying a first current bias to the bit line, Within the second section, the step of applying a second current bias greater than the first current bias to the bit line, The operating method according to claim 11, further comprising the step of applying a third current bias smaller than the first current bias to the bit line within the third section.

13. The first current bias corresponds to the magnitude of the set-write current of the phase-change memory cell. The second current bias corresponds to the magnitude of the reset write current of the phase-change memory cell. The operating method according to claim 12, wherein the third current bias is less than or equal to the magnitude of the hold current, which is the minimum current required to maintain the turn-on state of the phase-change memory cell.

14. The operating method according to claim 12, wherein the third voltage bias refers to the voltage difference between the bit line and the word line, and the third voltage bias is maintained constant within the third interval.

15. The operating method according to claim 11, wherein the peak value of the at least one current pulse is greater than or equal to the peak value of the reset write current.

16. The phase-change memory cell includes an ovonic threshold switch connected between the bit line and the word line, and a phase-change material. The operation method according to claim 12, wherein the ovonic threshold switch is repeatedly turned on and turned off until the threshold voltage of the phase-change memory cell becomes greater than the third voltage bias.

17. The operating method according to any one of claims 11 to 16, wherein the length of the first section is shorter than the length of the second section, and the length of the third section is shorter than the length of the first section.

18. The operating method according to any one of claims 11 to 17, further comprising the step of applying a fourth voltage bias smaller than the third voltage bias to the bit line and the word line within a fourth section of the reset write operation, from the third section onward.

19. The operating method according to any one of claims 11 to 18, further comprising the step of applying the third voltage bias to the bit line and the word line of the phase change memory cell to read the data written to the phase change memory cell.

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