Semiconductor structure with two-dimensional channels

Abstract

Semiconductor structure having a two-dimensional channel. A semiconductor structure is disclosed that includes a semiconductor device having a thin multi-layer channel stack. In one example, the semiconductor structure includes a gate structure including a multi-layer channel stack. The multi-layer channel stack includes a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further includes a first source / drain region disposed on a first side of the gate structure and in electrical contact with a first end of the multi-layer channel stack, and a second source / drain region disposed on a second side of the gate structure and in electrical contact with a second end of the multi-layer channel stack.

Description

Background Art

[0001] Due to the continuous innovation of semiconductor process technology, higher integration density and device scaling have become possible. As semiconductor field-effect transistor (FET) device structures are scaled to smaller dimensions and provide an increased device width per footprint area, non-planar FET devices such as nanosheet devices have become a viable option for continuous complementary metal-oxide semiconductor (CMOS) scaling. Generally, a nanosheet device has a device channel that includes one or more nanosheet layers in a stack configuration. In a nanosheet device, a common gate structure is formed above and below each nanosheet layer in the stack configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area. However, nanosheet devices exhibit scalability limitations beyond 40 nm contact poly pitch (CPP) due to the risk of pinch-off between gates in the formation of inner spacers. One means of enabling a CPP below 40 nm is to scale the gate length below the current effective anchor point of 12 nm. However, current hardware with a 5 nm thick silicon (Si) sheet may face the limit of short channel effects below the 12 nm gate work function metal (WFM) width, while reducing the thickness of the Si sheet below 5 nm improves electrostatic control but performance begins to degrade due to the quantum confinement effect, which is also not desirable.

Summary of the Invention

[0002] The disclosed embodiments include a semiconductor structure including a thin multi-layer channel stack, and a technique for manufacturing a semiconductor structure including a thin multi-layer channel stack.

[0003] For example, one embodiment includes a semiconductor structure comprising a gate structure including a multilayer channel stack. The multilayer channel stack includes a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The semiconductor structure further includes a first source / drain region located on the first side of the gate structure and electrically in contact with the first end of the multilayer channel stack, and a second source / drain region located on the second side of the gate structure and electrically in contact with the second end of the multilayer channel stack.

[0004] Another embodiment includes a semiconductor structure comprising a gate structure including a first multilayer channel stack and a second multilayer channel stack separated by an inner spacer. Each of the first and second multilayer channel stacks includes a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first and second dielectric layers. The channel layer of the first multilayer channel stack includes a first material configured for use with either an n-type field-effect transistor or a p-type field-effect transistor, and the channel layer of the second multilayer channel stack, which includes a second material, is configured for use with either an n-type field-effect transistor or a p-type field-effect transistor.

[0005] Another embodiment includes a method for manufacturing a semiconductor structure, comprising the steps of forming a sacrificial stack structure including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer positioned between the first and second sacrificial layers. The method further comprises the steps of removing the third sacrificial layer and forming a multilayer channel stack on the surfaces of the first and second sacrificial layers exposed by the removal of the third sacrificial layer. Each multilayer channel stack includes a first dielectric layer, a second dielectric layer, and a channel layer formed between the first and second dielectric layers. The method further comprises the steps of forming a fourth sacrificial layer between the multilayer channel stacks and recessing the fourth sacrificial layer from the edges of the multilayer channel stacks by etching the fourth sacrificial layer laterally. The method further comprises the steps of forming sidewall spacers in the recessed portion between the multilayer channel stacks and forming metallic source / drain regions that electrically contact the channel layers of the multilayer channel stacks.

[0006] Other embodiments are described in the following detailed description of embodiments, which should be read in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view of a semiconductor structure according to a first exemplary embodiment.

[0008] [Figure 2] Figure 1 is a schematic cross-sectional view of the semiconductor structure after the removal of the sacrificial layer, deposition of the inner dielectric layer, deposition of the channel layer, deposition of the outer dielectric layer, and deposition of the sacrificial layer.

[0009] [Figure 3] Figure 2 is a schematic cross-sectional view of the semiconductor structure after trimming the sacrificial layer in the channel between the gate structures.

[0010] [Figure 4]Figure 3 is a schematic cross-sectional view of the semiconductor structure after etching the inner dielectric layer, channel layer, outer dielectric layer, and sacrificial layer based on the pattern defined by the sidewall spacers.

[0011] [Figure 5] Figure 4 is a schematic cross-sectional view of the semiconductor structure after the sacrificial layer has been removed, additional material has been formed for the sacrificial layer, and the additional sacrificial layer has been etched based on the patterning defined by the sidewall spacers.

[0012] [Figure 6] Figure 5 is a schematic cross-sectional view of the semiconductor structure after forming an etching mask, removing the sacrificial layer by resetting the etching mask below it, and then removing the sacrificial layer.

[0013] [Figure 7] Figure 6 is a schematic cross-sectional view of the semiconductor structure after the etching mask has been removed, additional material for the sacrificial layer has been formed, and the additional sacrificial layer has been etched based on the pattern defined by the sidewall spacers.

[0014] [Figure 8] Figure 7 is a schematic cross-sectional view of the semiconductor structure after the sacrificial layer has been removed to form an inner spacer and the contact layer has been formed.

[0015] [Figure 9A] Figure 8 is a schematic cross-sectional view of the semiconductor structure after forming source / drain regions, resetting the source / drain regions, and forming an interlayer dielectric (ILD) on the reset source / drain regions. [Figure 9B] Figure 8 is a schematic cross-sectional view of the semiconductor structure after forming source / drain regions, resetting the source / drain regions, and forming an interlayer dielectric (ILD) on the reset source / drain regions. [Figure 9C]Schematic cross-sectional view of the semiconductor structure of FIG. 8 after forming source / drain regions, recessing the source / drain regions, and forming an interlayer dielectric (ILD) over the recessed source / drain regions.

[0016] [Figure 10A] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10B] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10C] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10D] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10E] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10F] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10G] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10H] �D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10I] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process. [Figure 10J] 3D projection views of the semiconductor structures of FIGS. 9A - 9C showing the semiconductor structure at various stages of the gate replacement process.

[0017] [Figure 11A]Figures 9A to 9C show schematic cross-sectional views of the semiconductor structure after the dummy gate electrode and dummy gate insulator layer have been removed, and the inner dielectric layer, channel layer, and outer dielectric layer have been indented to expose the sacrificial layer contained within them. [Figure 11B] Figures 9A to 9C show schematic cross-sectional views of the semiconductor structure after the dummy gate electrode and dummy gate insulator layer have been removed, and the inner dielectric layer, channel layer, and outer dielectric layer have been indented to expose the sacrificial layer contained within them. [Figure 11C] Figures 9A to 9C show schematic cross-sectional views of the semiconductor structure after the dummy gate electrode and dummy gate insulator layer have been removed, and the inner dielectric layer, channel layer, and outer dielectric layer have been indented to expose the sacrificial layer contained within them.

[0018] [Figure 12A] Figures 11A to 11C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed according to an embodiment of the first embodiment, which includes removal of the sacrificial layer, formation of a gate dielectric layer, and formation of a gate conductor layer, gate contacts, and a sacrificial gate cap. [Figure 12B] Figures 11A to 11C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed according to an embodiment of the first embodiment, which includes removal of the sacrificial layer, formation of a gate dielectric layer, and formation of a gate conductor layer, gate contacts, and a sacrificial gate cap. [Figure 12C] Figures 11A to 11C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed according to an embodiment of the first embodiment, which includes removal of the sacrificial layer, formation of a gate dielectric layer, and formation of a gate conductor layer, gate contacts, and a sacrificial gate cap.

[0019] [Figure 13A] These are schematic cross-sectional views of the semiconductor structure shown in Figures 11A to 11C after a gate replacement process has been performed according to another embodiment of the first embodiment, in which the gate dielectric layer is formed before the sacrificial layer is replaced with a gate conductor layer, gate contacts, and a sacrificial gate cap. [Figure 13B] These are schematic cross-sectional views of the semiconductor structure shown in Figures 11A to 11C after a gate replacement process has been performed according to another embodiment of the first embodiment, in which the gate dielectric layer is formed before the sacrificial layer is replaced with a gate conductor layer, gate contacts, and a sacrificial gate cap. [Figure 13C] These are schematic cross-sectional views of the semiconductor structure shown in Figures 11A to 11C after a gate replacement process has been performed according to another embodiment of the first embodiment, in which the gate dielectric layer is formed before the sacrificial layer is replaced with a gate conductor layer, gate contacts, and a sacrificial gate cap.

[0020] [Figure 14] This is a schematic cross-sectional view of a semiconductor structure of a second exemplary embodiment in a manufacturing stage similar to that shown in Figure 4 of the first embodiment.

[0021] [Figure 15] Figure 14 is a schematic cross-sectional view of the semiconductor structure after forming an etching mask, removing the sacrificial layer by resetting the etching mask below it, and then removing the sacrificial layer.

[0022] [Figure 16] Figure 15 is a schematic cross-sectional view of the semiconductor structure after the etching mask has been removed, additional material for the sacrificial layer has been formed, and the additional sacrificial layer has been etched based on the pattern defined by the sidewall spacers.

[0023] [Figure 17] This is a schematic cross-sectional view of the semiconductor structure shown in Figure 16 after the sacrificial layer has been removed to form an inner spacer.

[0024] [Figure 18] This is a schematic cross-sectional view of the semiconductor structure shown in Figure 17 after the sacrificial layer has been removed.

[0025] [Figure 19] Figure 18 is a schematic cross-sectional view of the semiconductor structure after the inner dielectric layer, channel layer, and outer dielectric layer, which were exposed by the removal of the sacrificial layer, have been removed.

[0026] [Figure 20] Figure 19 is a schematic cross-sectional view of the semiconductor structure after the formation of the lower dielectric insulation (BDI), ILD, and contact layer.

[0027] [Figure 21A] Figure 20 is a schematic cross-sectional view of the semiconductor structure after forming source / drain regions, resetting the source / drain regions, and forming ILDs on the reset source / drain regions. [Figure 21B] Figure 20 is a schematic cross-sectional view of the semiconductor structure after forming source / drain regions, resetting the source / drain regions, and forming ILDs on the reset source / drain regions. [Figure 21C] Figure 20 is a schematic cross-sectional view of the semiconductor structure after forming source / drain regions, resetting the source / drain regions, and forming ILDs on the reset source / drain regions.

[0028] [Figure 22A] Figures 21A to 21C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed, which includes the removal of the dummy gate electrode, the removal of the dummy gate insulator layer, the removal of the sacrificial layer, and replacement with a gate conductor layer, gate contacts, and sacrificial gate cap. [Figure 22B] Figures 21A to 21C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed, which includes the removal of the dummy gate electrode, the removal of the dummy gate insulator layer, the removal of the sacrificial layer, and replacement with a gate conductor layer, gate contacts, and sacrificial gate cap. [Figure 22C] Figures 21A to 21C show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed, which includes the removal of the dummy gate electrode, the removal of the dummy gate insulator layer, the removal of the sacrificial layer, and replacement with a gate conductor layer, gate contacts, and sacrificial gate cap.

[0029] [Figure 23] This is a schematic top view of a semiconductor structure according to a third exemplary embodiment.

[0030] [Figure 24] This is a schematic cross-sectional view of the semiconductor structure in Figure 23 during an intermediate stage of manufacturing.

[0031] [Figure 25] Figure 24 (A) to (D) are schematic cross-sectional views of the semiconductor structure after removal of the sacrificial layer, deposition of the inner dielectric layer, deposition of the channel layer, deposition of the outer dielectric layer, deposition of the sacrificial layer, and trimming of the sacrificial layer.

[0032] [Figure 26] Figures 25(A) to (D) show schematic cross-sectional views of the semiconductor structure after etching the inner dielectric layer, channel layer, outer dielectric layer, and sacrificial layer based on the pattern defined by the sidewall spacers.

[0033] [Figure 27] Figure 26 (A) to (D) are schematic cross-sectional views of the semiconductor structure after removal of the sacrificial layer, deposition of the inner dielectric layer, deposition of the channel layer, deposition of the outer dielectric layer, deposition of additional material on the sacrificial layer, and trimming of additional material on the sacrificial layer.

[0034] [Figure 28] Figures 27(A) to (D) show schematic cross-sectional views of the semiconductor structure after etching the inner dielectric layer, channel layer, outer dielectric layer, and sacrificial layer based on the pattern defined by the sidewall spacers.

[0035] [Figure 29] Figure 28 (A) to (D) are schematic cross-sectional views of the semiconductor structure after the sacrificial layer has been replaced with additional material for the sacrificial layer.

[0036] [Figure 30]Figures 29(A) to (D) show schematic cross-sectional views of the semiconductor structure after the sacrificial layer has been removed, the inner spacer 530 has been formed, and the contact layer has been formed.

[0037] [Figure 31] Figures 30(A) to (D) are top views of the semiconductor structures after forming an etching mask with patterned channels. [Figure 32] These are schematic cross-sectional views of the semiconductor structures shown in Figure 30(A) to (D) after forming an etching mask with patterned channels.

[0038] [Figure 33] Figure 32 (A) to (D) are schematic cross-sectional views of the semiconductor structure after removal of the exposed embedded power rail (BPR) capping layer and formation of source / drain regions that electrically contact the BPR.

[0039] [Figure 34] Figure 33 (A) to (D) shows schematic cross-sectional views of the semiconductor structure after the contact layer and source / drain region have been reset to a level below the inner dielectric layer, channel layer, and outer dielectric layer, forming a source / drain spacer, forming an ILD, and then resetting the ILD.

[0040] [Figure 35] These are schematic cross-sectional views of the semiconductor structure shown in Figure 34 (A) to (D) after the source / drain spacer has been reset below the level of the bottom three-layer stack of the inner dielectric layer, channel layer, and outer dielectric layer, exposing the portion of the inner spacer located between the bottom three-layer stack of the inner dielectric layer, channel layer, and outer dielectric layer, and the top three-layer stack of the inner dielectric layer 520, channel layer, and outer dielectric layer.

[0041] [Figure 36]Figures 35(A) to (D) show schematic cross-sectional views of the semiconductor structure after the removal of ILD542 and the formation of an etching mask patterned to protect the other side of the gate structure while exposing one side of the gate structure.

[0042] [Figure 37] Figure 36 (A) to (D) shows schematic cross-sectional views of the semiconductor structure after removing the source / drain spacer portion on the gate structure side exposed by the etching mask, removing the etching mask, forming a contact layer on the semiconductor structure (including the remaining portion of the source / drain spacer and the source / drain region exposed by the removal of the source / drain spacer portion on that side of the gate structure) and on the sidewall of the gate structure (including the inner spacer, inner dielectric layer, channel layer, and outer dielectric layer and sidewall spacer), etching the contact layer to expose the source / drain spacer and source / drain region, and removing the source / drain region.

[0043] [Figure 38] Figures 37(A) to (D) are top views of the semiconductor structures after an etching mask with patterned channels has been formed. [Figure 39] These are schematic cross-sectional views of the semiconductor structures shown in Figure 37(A) to (D) after forming an etching mask with patterned channels.

[0044] [Figure 40] Figure 39 (A) to (D) shows schematic cross-sectional views of the semiconductor structure after removing the exposed BPR capping layer, forming a source / drain region that electrically contacts the BPR, and resetting the contact layer and source / drain region to a level above the top three layers of the inner dielectric layer, channel layer, and outer dielectric layer, and below the sidewall spacers.

[0045] [Figure 41]Figure 40 (A) to (D) are schematic cross-sectional views of the semiconductor structure after the ILD and capping layer have been formed and the dummy gate electrode has been removed.

[0046] [Figure 42] Figures 41(A) to (D) show schematic cross-sectional views of the semiconductor structure after a gate replacement process has been performed, which includes removing the dummy gate insulator layer and removing the sacrificial layer and replacing it with a gate conductor layer, gate contacts, and sacrificial gate cap.

[0047] [Figure 43] Figure 42(A) shows a schematic cross-sectional view of a semiconductor structure, illustrating an inverter complementary FET (CFET) circuit formed by a semiconductor structure.

[0048] [Figure 44] Figures 42(A) to (D) are top views of the semiconductor structures after the formation of middle-of-line (MOL) contacts. [Figure 45] Figures 42(A) to (D) show schematic cross-sectional views of the semiconductor structure after the formation of a middle-of-line (MOL) contact. [Figure 46] Figures 42(A) to (D) show schematic cross-sectional views of the semiconductor structure after the formation of a middle-of-line (MOL) contact. [Figure 47] Figures 42(A) to (D) show schematic cross-sectional views of the semiconductor structure after the formation of a middle-of-line (MOL) contact.

[0049] [Figure 48] This is a schematic top view of a semiconductor structure according to a fourth exemplary embodiment. [Figure 49] Figure 48 is a schematic cross-sectional view of the semiconductor structure in an intermediate manufacturing stage similar to the manufacturing stage for the semiconductor structure of the third embodiment shown in Figure 31.

[0050] [Figure 50]Figures 49(A) to (D) show schematic cross-sectional views of the semiconductor structure after removing the exposed portion of the BPR capping layer and forming source / drain regions that electrically contact the BPR.

[0051] [Figure 51] Figure 50(A)-(D) shows schematic cross-sectional views of the semiconductor structure after the contact layer and source / drain region are reset to a level below the inner dielectric layer, channel layer, and outer dielectric layer, a source / drain spacer is formed, a contact layer is formed, an additional source / drain region is formed, an ILD and capping layer is formed, a dummy gate electrode is removed, a dummy gate insulator layer is removed, a sacrificial layer is removed and replaced with a gate conductor layer, gate contact, and sacrificial gate cap, and in some embodiments, the dielectric layer is formed before the gate conductor layer is formed.

[0052] [Figure 52] This is a schematic cross-sectional view of the semiconductor structure shown in Figure 51(A), which illustrates a CFET circuit formed by the semiconductor structure of the fourth embodiment.

[0053] [Figure 53] Figures 51(A) to (D) are top views of the semiconductor structure after the formation of the MOL contacts. [Figure 54] These are schematic cross-sectional views of the semiconductor structures shown in Figure 51 (A) to (D) after the formation of the MOL contacts. [Figure 55] These are schematic cross-sectional views of the semiconductor structures shown in Figure 51 (A) to (D) after the formation of the MOL contacts. [Figure 56] These are schematic cross-sectional views of the semiconductor structures shown in Figure 51 (A) to (D) after the formation of the MOL contacts. [Modes for carrying out the invention]

[0054] Herein, embodiments of the invention are described in further detail below. A device and method are provided for fabricating a nanosheet field-effect transistor device having an embedded power rail beneath an active device, utilizing a diffusion break contact.

[0055] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic diagrams and not drawn to scale. Furthermore, for the sake of simplicity, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not mean that any layers, structures, and regions not explicitly shown are omitted from actual semiconductor device structures. Furthermore, please understand that the embodiments discussed herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor process steps, it should be emphasized that the descriptions provided herein are not intended to encompass all process steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain process steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity.

[0056] Furthermore, identical or similar reference numbers are used throughout the drawings to indicate identical or similar features, elements, or structures, and therefore, detailed descriptions of identical or similar features, elements, or structures are not repeated for each drawing. It should be understood that the terms “approximately” or “substantially” used herein with respect to thickness, width, percentage, range, etc., mean that they are not exact but close or approximate. For example, the terms “approximately” or “substantially” used herein mean that there is a slight error, such as less than 1% of the stated quantity.

[0057] When used herein, the terms “electrically contacted” and “telecommunication” refer to direct contact between two elements or an electrical connection between two elements via one or more intermediary structures.

[0058] Figures 1 to 14 schematically illustrate an exemplary method for manufacturing a semiconductor structure 100 according to a first exemplary embodiment.

[0059] Figure 1 is a schematic cross-sectional view of the semiconductor structure 100 in an intermediate stage of manufacturing. The semiconductor structure 100 comprises a semiconductor substrate 102, a nanosheet stack structure including sacrificial layers 104-1 and 104-2, sacrificial layers 106-1, 106-2, and 106-3, and sacrificial layers 108-1 and 108-2, a dummy gate insulator layer 110, a dummy gate electrode 112, and a sidewall spacer 114. Although not shown, a gate capping layer (not shown) may also be placed on the dummy gate electrode 112.

[0060] Although the semiconductor substrate 102 is shown as a general substrate layer, it should be understood that the semiconductor substrate 102 may include one of several different types of semiconductor substrate structures and materials. For example, in one embodiment, the semiconductor substrate 102 may be a bulk semiconductor substrate (e.g., a wafer) formed from silicon (Si) or germanium (Ge), or other types of semiconductor substrate materials commonly used in bulk semiconductor manufacturing processes, such as silicon-germanium alloys, composite semiconductor materials (e.g., III-V). In another embodiment, the semiconductor substrate 102 may be an SOI (silicon on an insulator) substrate, a GeOI (germanium on an insulator) substrate, or an active semiconductor layer of a semiconductor substrate on an insulator, including an insulating layer (e.g., an oxide layer) placed between a base substrate layer (e.g., a silicon substrate) and an active semiconductor layer (e.g., Si, Ge, etc.) on which active circuit components are formed as part of a substrate process (FEOL) structure.

[0061] Sacrificial layers 104-1 and 104-2 are also referred to collectively and individually as sacrificial layer 104. Sacrificial layers 106-1 to 106-3 are also referred to collectively and individually as sacrificial layer 106. Sacrificial layers 108-1 and 108-2 are also referred to collectively and individually as sacrificial layer 108. Sacrificial layers 104, 106, and 108 of the nanosheet stack structure contain epitaxial layers that are grown continuously.

[0062] In one embodiment, the epitaxial sacrifices 104, 106 and 108 include a single-crystal semiconductor material epitaxially grown using a known method such as chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), reduced-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), organometallic molecular beam epitaxy (MOMBE), rapid thermochemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), liquid-phase epitaxy (LPE), metal-organic chemical vapor deposition (MOCVD), or other known epitaxial growth techniques suitable for a given process flow. The type of material used to form the epitaxial sacrificial layers 104, 106, and 108 depends on various factors, such as the desired level of etching selectivity between the sacrificial layers, and provides sufficient lattice matching between the sacrificial layer materials to ensure proper (e.g., defect-free) epitaxial growth of the crystalline sacrificial layers 104, 106, and 108.

[0063] For example, in one embodiment, one of the sacrificial layers 104, 106, and 108 is formed from epitaxial silicon (Si), and the other sacrificial layers 106 and 108 are formed from an epitaxial silicon-germanium (SiGe) alloy having a variable concentration of Ge. This allows the sacrificial layers 104, 106, and 108 to be selectively etched from one another. In some embodiments, sacrificial layer 104 comprises a SiGe alloy having Ge in the range of about 25% to 40%, sacrificial layer 106 comprises a SiGe alloy having Ge in the range of about 50% to about 90%, and sacrificial layer 108 comprises Si or It contains Ge in the range of approximately 5% to 15%. This includes SiGe alloys. In exemplary embodiments, sacrificial layer 104 contains a SiGe alloy having about 25% Ge, sacrificial layer 106 contains a SiGe alloy having about 60% Ge, and sacrificial layer 108 contains Si. In some embodiments, other materials selectively etchable to each other may be used for sacrificial layers 104, 106, and 108.

[0064] While the nanosheet stack structure has been shown to include two sacrificial layers 104, three sacrificial layers 104, and two sacrificial layers 104, in other embodiments the nanosheet stack structure may be manufactured to have more or fewer than two sacrificial layers 104, three sacrificial layers 104, and two sacrificial layers 104.

[0065] Continuing to refer to Figure 1, the sacrificial layers 104, 106, and 108 may be formed with thicknesses that define the spacing size at which the high-k dielectric material and work function metal are formed. In one embodiment, the thickness of sacrificial layer 104 is in the range of about 4 nm to about 8 nm, the thickness of sacrificial layer 106 is in the range of about 8 nm to about 15 nm, and the thickness of sacrificial layer 108 is in the range of about 4 nm to about 8 nm. In some embodiments, other thicknesses may be used for each of the sacrificial nanosheet layers 104, 106, and 108.

[0066] The dummy gate dielectric 110, dummy gate electrode 112, and sidewall spacer 114 can be formed using standard deposition and lithography processes.

[0067] For example, a conformal layer of silicon oxide may be deposited on a semiconductor structure 100 to form a dummy gate insulator layer, followed by blanket deposition of a sacrificial material such as polysilicon or amorphous silicon material to form a dummy gate electrode layer. In some embodiments, a CMP process is performed to planarize one or both of the deposited materials. A hard mask layer is formed on the planarized surface of the polysilicon layer by depositing a layer of dielectric material such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), or other similar materials commonly used to form a gate capping layer.

[0068] The hard mask layer is then patterned to form a gate capping layer (not shown) that defines the image of the dummy gate structure. The gate capping layer is then used as an etching hard mask for anisotropic etching (e.g., RIE) of the sacrificial polysilicon layer and the silicon oxide layer, thereby forming the dummy gate dielectric 110 and dummy gate electrode 112 of the gate structure. In exemplary embodiments, the etching chemical action for patterning the dummy gate dielectric 110 and dummy gate electrode 112 is selective for the gate capping layer and the sacrificial layer 104-2.

[0069] Next, the sidewall spacers 114 are formed by depositing a conformal layer of dielectric material over the entire surface of the semiconductor structure 100. The conformal layer of dielectric material is formed from SiN, SiCN, SiON, BN, SiBN, SiBCN, SiOC, SiCN, or any other type of dielectric material commonly used to form insulating sidewall spacers for FET devices, and can be deposited using known techniques such as atomic layer deposition (ALD), CVD, and PVD. The conformal layer of dielectric material is then patterned by performing an anisotropic dry etching process such as RIE, etching the conformal layer of dielectric material vertically downward. This etching process is performed selectively on the materials of the sacrificial layer 104-2 and the gate capping layer (not shown). As a result of the etching process, the sidewall spacers 114 are formed on the dummy gate dielectric 110 and the dummy gate electrode 112, surrounding the sidewall surfaces of the dummy gate dielectric 110 and the dummy gate electrode 112. In one embodiment, the thickness of the sidewall spacer 114 is in the range of about 3 nm to about 10 nm, but the sidewall spacer 114 can be formed in other thickness ranges. During the etching process for forming the sidewall spacer 114, for example, a portion (not shown) of the conformal layer of dielectric material on the side of the semiconductor structure 100, on the upper surface of the sacrificial layer 104-2 and the gate capping layer, is etched, exposing the upper surfaces of the sacrificial layer 104-2 and the gate capping layer (not shown).

[0070] An etching process is used to reset the exposed portions of the nanosheet stack structure into the semiconductor substrate 102 according to a patterning defined by the sidewall spacers 114 and the gate capping layer (not shown). For example, dry or wet etching techniques may be used to reset the exposed portions of the nanosheet stack structure and the semiconductor substrate 102 according to the patterning in one or more steps. The etching chemical action used to perform the resetting may be selective to one or more of the materials of the gate capping layer and the sidewall spacers 114. In some embodiments, a directional RIE process is used to reset the exposed portions of the nanosheet stack structure into the semiconductor substrate 102 according to the patterning, using a chemical action that is selective to the materials of the gate capping layer and the sidewall spacers 114.

[0071] Figure 2 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 1 after the sacrificial layer 106 has been removed, the inner dielectric layer 120 has been deposited, the channel layer 122 has been deposited, the outer dielectric layer 124 has been deposited, and the sacrificial layer 126 has been deposited.

[0072] One or more etching processes are used to remove the sacrificial layer 106. In some embodiments, dry or wet etching processes may be used to etch the sacrificial layer 106 without removing other layers of the nanosheet stack structure. For example, the etching chemicals and processes may be selective for the materials of the semiconductor substrate 102, sacrificial layers 104 and 108, gate capping layer (not shown), and sidewall spacer 114. For example, the etching chemicals may be selective for the sacrificial layer 104. exist Lower concentrations of Ge, for example, about 25% to 40% Ge, and sacrificial layer 108 ofThe etching process may be configured to remove a SiGe alloy concentration, e.g., about 50% to about 90% Ge, from the sacrificial layer 106, while being selective to Si or about 5% to about 15% Ge. In some embodiments, a dry vapor-phase etching process may be used to remove the sacrificial layer 106. In one embodiment, the SiGe material of the sacrificial layer 106 may be selectively etched (with high etching selectivity) by using vapor-phase HCl (hydrochloric acid) or a wet etching solution to selectively etch the SiGe material of the sacrificial layer 106 laterally with respect to the Si and SiGe materials of the sacrificial layers 104 and 108. For example, if the sacrificial layers 104 and 108 are Si or Lower Ge concentration than the SiGe material of sacrificial layer 106 S When formed from iGe, gas-phase HCl (hydrochloric acid) provides high etching selectivity.

[0073] The inner dielectric layer 120 includes, but is not limited to, a high-k dielectric layer containing, for example, HfO2 (hafnium oxide), ZrO2 (zirconium dioxide), hafnium zirconium oxide, Al2O3 (aluminum oxide), and Ta2O5 (tantalum pentoxide) or other electronic grade (EG) oxides. Examples of high-k materials also include, but are not limited to, metal oxides such as hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In one embodiment, the dielectric material of the inner dielectric layer 120 is conformally deposited using a highly conformable deposition process such as ALD. Other deposition methods such as CVD and PVD may be used to deposit a highly conformable layer of dielectric material onto the semiconductor structure 100. In some embodiments, the inner dielectric layer 120 is deposited as a thin layer having a thickness in the range of, for example, about 0.5 nm to about 2 nm, and in exemplary embodiments, about 1 nm to about 1.5 nm.

[0074] In some embodiments, the channel layer 122 includes, but is not limited to, titanium (Ti)-based materials, tungsten (W)-based materials, molybdenum (Mo)-based materials, graphene-based materials, III-V-based materials, or other materials. Some exemplary materials include tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten ditelluride (WTe2), and molybdenum ditelluride (MoTe2), indium tin oxide (ITO), indium aluminum-doped zinc oxide (IAZO), or other materials deposited or formed in thin layers having a thickness ranging from about 0.3 nm to less than 2 nm, for example, in two-dimensional (2D) layers such as single-layer or double-layer deposits. In some embodiments, the material used for the channel layer 122 may be selected based on the type of semiconductor structure 100, for example, nFET or pFET. In one embodiment, the material for the channel layer 122 is conformally deposited using a highly conformal deposition process such as ALD. Other deposition methods such as CVD and PVD may be used to deposit a highly conformal thin layer of the channel material on the inner dielectric layer 120.

[0075] The outer dielectric layer 124 includes a high-k dielectric layer containing, but not limited to, HfO2 (hafnium oxide), ZrO2 (zirconium dioxide), hafnium zirconium oxide, Al2O3 (aluminum oxide), and Ta2O5 (tantalum pentoxide) or other electronic grade (EG) oxides. Examples of high-k materials also include, but are not limited to, metal oxides such as hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In one embodiment, the dielectric material of the outer dielectric layer 124 is conformally deposited using a highly conformal deposition process such as ALD. Other deposition methods such as CVD may be used to deposit a highly conformal layer of dielectric material to cover the exposed portion of the channel layer 122. In some embodiments, the outer dielectric layer is deposited as a thin layer having a thickness in the range of, for example, about 0.5 nm to about 2 nm, and in exemplary embodiments, about 1 nm to about 1.5 nm.

[0076] In an exemplary embodiment, the combined thickness of the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124 is approximately 3 nm to less than 4 nm.

[0077] The sacrificial layer 126 includes, for example, a material that is selectively etchable relative to the outer dielectric layer 124. In some embodiments, non-limiting examples of materials that may be used for the sacrificial layer 126 include Al2O3, AlN, La2O3, TiO2, GaN, SiO2, GeO2, Ge2N3, or other materials that can be conformally deposited and are resistant to selective etching of the sacrificial layers 104 and 108. In one embodiment, the material for the sacrificial layer 126 is conformally deposited using a highly conformable deposition process such as ALD to ensure that the recess is sufficiently filled with dielectric material. Other deposition methods such as CVD and PVD may be used to deposit a highly conformable layer of the sacrificial material to fill the recess.

[0078] Figure 3 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 2 after trimming the sacrificial layer 126 in the channel between the gate structures. The sacrificial layer 126 is trimmed using known etching techniques and etching chemicals. For example, the sacrificial layer 126 may be trimmed using directional RIE or wet etching, which is selective for the outer dielectric layer 124, for example. As can be seen from Figure 3, the trimming leaves the sacrificial layer 126 in a nanosheet stack structure between the outer dielectric layers 124.

[0079] Figure 4 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 3 after etching the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 based on a pattern defined by the sidewall spacer 114. Etching may be performed in one or more etching processes. For example, dry or wet etching techniques may be used to remove the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 according to a pattern in one or more steps, while leaving the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 beneath the gate structure. The etching chemical action used to perform the etching may be selective for one or more of the materials of the gate capping layer and the sidewall spacer 114. In some embodiments, a directional RIE process is used to remove the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 according to a pattern, using a chemical action that is selective to the gate capping layer, sidewall spacer 114, and semiconductor substrate 102 material.

[0080] Figure 5 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 4 after removing the sacrificial layer 104, forming additional material for the sacrificial layer 126, and etching the additional sacrificial layer 126 based on the pattern defined by the sidewall spacers 114.

[0081] One or more etching processes are used to remove the sacrificial layer 104. In some embodiments, dry or wet etching processes may be used to etch the sacrificial layer 104 without removing other layers of the nanosheet stack structure. For example, the etching chemicals and processes may be selective to the materials of the semiconductor substrate 102, the sacrificial layer 108, the gate capping layer (not shown), and the sidewall spacer 114. For example, the etching chemicals may be configured to remove a SiGe alloy concentration of about 25% to 40% Ge in the sacrificial layer 104, while being selective to lower concentrations of Ge found in the sacrificial layer 108, e.g., Si, or about 5% to about 15% Ge. In some embodiments, a dry vapor-phase etching process may be used to remove the sacrificial layer 104. In one embodiment, the SiGe material of the sacrificial layer 104 can be selectively etched (with high etching selectivity) by selectively etching the SiGe material of the sacrificial layer 104 laterally with respect to the Si or SiGe material of the sacrificial layer 108 using gas-phase HCl (hydrochloric acid) or a wet etching solution. Gas-phase HCl (hydrochloric acid) provides high etching selectivity, for example, when the sacrificial layer 108 is formed from Si or SiGe having a lower Ge concentration than the SiGe material of the sacrificial layer 104.

[0082] High-conformal deposition processes such as ALD are used to ensure that additional sacrificial material for the sacrificial layer 126 is conformally deposited, and that the recess exposed by the removal of the sacrificial layer 104 is adequately filled with dielectric material. Other deposition methods such as CVD and PVD may be used to deposit a highly conformal layer of sacrificial material to fill the recess.

[0083] The sacrificial layer 126 is trimmed in a manner similar to that described above, using known etching techniques and etching chemicals. For example, the sacrificial layer 126 may be trimmed according to the pattern defined by the sidewall spacers 114, using, for example, directional RIE or wet etching that is selective for the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the semiconductor substrate 102, and the sidewall spacers 114.

[0084] Figure 6 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 5 after forming an etching mask 128, removing the etching mask 128 below the sacrificial layer 108 to expose the sacrificial layer 108, and then removing the sacrificial layer 108.

[0085] An OPL may be coated onto a semiconductor structure 100, followed by an etching process to etch the OPL down to a desired level, forming an etching mask 128 as shown in Figure 6. The OPL may include, for example, a resin material that is applied and baked by spin coating to enhance planarization. The OPL is reset so that the etching mask 128 exposes the sacrificial layer 108. A time-controlled directional etching process, such as a directional RIE process, may be used to etch the OPL down to a desired level. For example, the etching chemistry may be selective for the materials of the gate capping layer (not shown), sidewall spacer 112, inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126. In some embodiments, the OPL may be reset using, for example, a plasma etching process or an ashing process.

[0086] One or more etching processes are used to remove the sacrificial layer 108. In some embodiments, dry or wet etching processes may be used to etch the sacrificial layer 108 without removing other layers of the nanosheet stack structure. For example, the etching chemistry and process may be selective for the materials of the gate capping layer (not shown), sidewall spacer 114, inner dielectric layer 120, channel layer 122, outer dielectric layer 124, sacrificial layer 126, and etching mask 128. In some embodiments, a dry vapor-phase etching process may be used to remove the sacrificial layer 108. In one embodiment, the sacrificial layer 108 may be selectively etched (with high etching selectivity) by etching the material of the sacrificial layer 108 laterally using vapor-phase HCl (hydrochloric acid) or a wet etching solution.

[0087] Figure 7 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 6 after the etching mask 128 is removed, additional material for the sacrificial layer 126 is formed, and the additional sacrificial layer 126 is etched based on the pattern defined by the sidewall spacers 114.

[0088] The etching mask 128 can be removed, for example, using a plasma etching process or an ashing process.

[0089] High-conformal deposition processes such as ALD are used to ensure that additional sacrificial material for the sacrificial layer 126 is conformally deposited, and that the recess exposed by the removal of the sacrificial layer 108 is adequately filled with dielectric material. Other deposition methods such as CVD and PVD may be used to deposit a highly conformal layer of sacrificial material to fill the recess.

[0090] The sacrificial layer 126 is trimmed in a manner similar to that described above, using known etching techniques and etching chemicals. For example, the sacrificial layer 126 may be trimmed according to the pattern defined by the sidewall spacers 114, using, for example, directional RIE or wet etching that is selective for the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the semiconductor substrate 102, and the sidewall spacers 114.

[0091] Figure 8 is a schematic cross-sectional view of the semiconductor structure 100 of Figure 7 after the sacrificial layer 126 has been reset to form the inner spacer 130 and the contact layer 132 has been formed. In one embodiment, the inner spacer 130 is formed by a process that includes laterally resetting the exposed sidewall surface of the sacrificial layer 126 of the nanosheet stack structure to form a recess in the sidewall of the nanosheet stack structure. As shown in Figure 8, the exposed sidewall surface of the sacrificial layer 130 is laterally reset to a predetermined depth. The amount of laterally resetting is controlled through time-controlled etching. In one embodiment, the resetting depth is substantially equal to the thickness of the adjacent sidewall spacer 114. In some embodiments, the resetting depth may be about 4 nm to about 8 nm, and in exemplary embodiments, about 6 nm.

[0092] The lateral etching process can be performed by using an isotropic wet etching process with an etching solution suitable for selectively etching the material of the sacrificial layer 126 with respect to the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the semiconductor substrate 102, the sidewall spacer 114, and other exposed elements. In another embodiment, an isotropic dry plasma etching process can be performed to selectively laterally etch the exposed sidewall surface of the sacrificial layer 130 with respect to the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the semiconductor substrate 102, the sidewall spacer 114, and other exposed elements.

[0093] The recess is then filled with dielectric material to form an inner spacer 130 (or embedded spacer) on the sidewall of the nanosheet stack structure. In one embodiment, the inner spacer 130 is formed by depositing a conformal layer of dielectric material on the semiconductor structure 100 until the recess is filled with dielectric material, and then removing the excess dielectric material by etching. The inner spacer 130 may be formed from SiN, SiBCN, SiOCN, SiOC, SiO2, SiW, or any other type of dielectric material (e.g., low-k dielectric material with k less than 5) commonly used to form insulating gate sidewall spacers for FET devices. In some embodiments, the dielectric material used to form the inner spacer 130 includes an oxide in which the 2D channel material can be functionalized. In one embodiment, the dielectric material is conformally deposited using a highly conformal deposition process such as ALD to ensure that the recess is sufficiently filled with dielectric material. Other deposition methods such as CVD and PVD may be used to deposit a highly conformal layer of dielectric material to fill the recess. The conformal layers of the dielectric material may be etched using an isotropic wet etching process to remove excess dielectric material on the sidewalls of the nanosheet stack structure, exposing the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124, while leaving dielectric material in the recesses, thereby forming the inner spacer 130. The wet etching process may include, but is not limited to, buffered hydrofluoric acid (BHF), dilute hydrofluoric acid (DHF), nitrate hydrofluoric acid (HNA), phosphoric acid, HF diluted with ethylene glycol (HF / EG), hydrochloric acid (HCl), or any combination thereof.

[0094] The contact layer 132 comprises a contact material configured to electrically connect the channel layer 122 to a metallic source / drain region with the smallest possible amount of contact resistance. In some embodiments, the contact layer 132 comprises a bismuth (Bi)-based material, an antimony-based material, or another metallic material. The contact layer 132 is formed using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, sputtering, and / or plating. In an exemplary embodiment, as can be seen, for example from Figure 8, the contact material is deposited on a semiconductor structure 100 including a semiconductor substrate 102, a sidewall spacer 114, an inner dielectric layer 120, a channel layer 122, an outer dielectric layer 124, and the exposed surface of the inner spacer 130 to form a contact layer 132 that electrically contacts the channel layer 122.

[0095] In some embodiments, the contact material used to form the contact layer 132 may be selected based on the type of semiconductor structure 100, for example, an n-type or p-type semiconductor structure 100. The contact layer 132 provides a low-resistance contact between the source / drain region 134 and the channel layer 122. In some embodiments, the contact layer 132 is formed as a two-layer contact, for example, comprising a layer of the same material used for the channel layer 122 and a layer of semimetallic contact, such as bismuth or antimony. In other embodiments, the contact layer 132 comprises a single material layer, for example, a layer of channel material only or a layer of semiconductor material. In addition, the contact layer is blood Channel layer 122 and Later formed Reduces the Schottky barrier between metallic source / drain regions.

[0096] Figures 9A to 9C are schematic cross-sectional views of the semiconductor structure 100 of Figure 8 after forming the source / drain region 134, resetting the source / drain region 134, and forming the interlayer dielectric (ILD) 136 on the reset source / drain region 134. Figure 9B is obtained along the cross-sectional line BB of Figure 9A, and Figure 9C is obtained along the cross-sectional line CC of Figure 9A.

[0097] The source / drain region 134 includes a metallic material formed using a standard deposition technique. In exemplary embodiments, the source / drain region 134 includes a metallic material for either an nFET device or a pFET device. For nFET devices, the metallic material may include titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or a combination of Ti and Al alloys, and its stack includes a barrier layer (e.g., titanium nitride (TiN) or another suitable material), followed by one or more of the above-mentioned WFM materials. For pFET devices, the metallic material may include TiN, tantalum nitride (TaN), or another suitable material. In some embodiments, the pFET metallic material may include a metal stack, where a thicker barrier layer (e.g., TiN, TaN, etc.) is formed, followed by a metallic material such as Ti, Al, TiAl, TiAlC, or any combination of Ti and Al alloys. Other metallic materials that may be used in either the nFET or pFET device may include, but are not limited to, W, Co, Bi, Sb, Al, Sn, In, Mo, or other metallic materials. It should be understood that a variety of other materials may be used in the source / drain region 134 as appropriate.

[0098] The source / drain region 134 is formed using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, sputtering, and / or plating. In exemplary embodiments, the source / drain region 134 is deposited on the contact layer 132, as can be seen, for example, from Figures 9A to 9C. Excess metallic material can be removed, for example, by etching or a CMP process.

[0099] The source / drain region 134 can be reset downward to the bottom of the sidewall spacer 114, for example, by using one or more etching processes. For example, an isotropic wet etching process may be used to reset the source / drain region 134.

[0100] ILD136 is, for example, SiO x The ILD 136 may be formed by depositing dielectric material, including but not limited to low-temperature oxides (LTO), high-temperature oxides (HTO), fluid oxides (FOX), or several other dielectrics, onto the source / drain region 134. The ILD 136 may be deposited using deposition techniques, including but not limited to CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, and / or LSMCD sputtering and / or plating. Planarization, such as chemical mechanical polishing (CMP), may be performed to remove excess material from the ILD 136 and planarize the resulting structure. Planarization may be performed down to the dummy gate electrode 112 so that the gate capping layer (not shown) is removed and the dummy gate electrode 112 is exposed. According to an exemplary embodiment, the ILD 136 electrically insulates different gate structures from each other.

[0101] Figures 10A to 10J are three-dimensional projections of semiconductor structure 100 shown in Figures 9A to 9C, illustrating the semiconductor structure during various stages of the gate replacement process. Figures 10A to 10J are explained here with reference to Figures 9A to 13C.

[0102] Figure 10A corresponds to the manufacturing stages shown in Figures 9A to 9C and shows a dummy gate electrode 112 placed between the side wall spacers 114.

[0103] Figures 11A to 11C are schematic cross-sectional views of the semiconductor structure 100 shown in Figures 9A to 9C after the dummy gate electrode 112 and dummy gate insulator layer 110 have been removed, and the inner dielectric layer 120, channel layer 122, and outer dielectric layer 124 have been indented to expose the portion of the sacrificial layer 126 encapsulated within them. Figure 11B is obtained along the cross-sectional line BB of Figure 11A, and Figure 11C is obtained along the cross-sectional line CC of Figure 11A. Figures 10B to 10G correspond to the process stages associated with the manufacturing stages shown in Figures 11A to 11C.

[0104] The dummy gate electrode 112 is etched using known etching techniques and etching chemicals. For example, the dummy gate material can be removed using selective dry etching or wet etching processes with suitable etching chemicals including ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), or SF6 plasma. Etching of the dummy gate electrode 112 is selective for, for example, the ILD 136, the dummy gate insulator layer 110, the sidewall spacer 114, and the semiconductor substrate 102. Etching of the dummy gate electrode 112 exposes the dummy gate insulator layer 110. Figure 10B shows the semiconductor structure 100 with the dummy gate electrode 112 removed, while Figure 10C shows the same manufacturing stage, but with the sidewall spacer 114 removed to show the exposed dummy gate insulator layer 110.

[0105] The dummy gate insulator layer 110 can be removed using a selective dry etching or wet etching process with a suitable etching chemical action that is selective to the ILD 136, sidewall spacer 114, semiconductor substrate 102, inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126. Figure 10D shows the semiconductor structure 100 with the dummy gate insulator layer 110 removed, while Figure 10E shows the same manufacturing stage, but with the inner dielectric layer 120, channel layer 122, and outer dielectric layer 124 removed to show the sacrificial layer 126.

[0106] As can be seen from Figures 11C and 10F, the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124 are indented in areas exposed by removing the dummy gate insulator layer 110, for example, using one or more isotropic RIE, dry etching, or wet etching processes. For example, as can be seen from Figure 10F, the sides of the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124 are etched to expose the sacrificial layer 126 surrounded by the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124. The etching chemical action may be selective for the ILD 136, the sidewall spacer 114, and the semiconductor substrate 102.

[0107] Figures 12A to 12C are schematic cross-sectional views of the semiconductor structure 100 shown in Figures 11A to 11C after a gate replacement process has been performed according to an embodiment of the first embodiment, which includes removing the inner dielectric layer 120, channel layer 122, and outer dielectric layer 124 from the sacrificial layer 126, forming a gate dielectric layer 138 in the recess to seal the exposed portion of the channel layer 122, removing the sacrificial layer 126, and forming gate conductor layers 140 and 144, gate contacts 142 and 146, and a sacrificial gate cap 148. Figure 12B is obtained along the cross-sectional line BB of Figure 12A, and Figure 12C is obtained along the cross-sectional line CC of Figure 12A. Figures 10H and 10I correspond to process stages associated with the manufacturing stages shown in Figures 12A to 12C.

[0108] For example, as shown in Figure 10G, a further etching process is performed on the sacrificial layer 126 to remove the inner dielectric layer 120, the channel layer 122, and the outer dielectric layer 124. The further etching process may utilize the same etching chemical action as the initial indentation shown in Figure 11C.

[0109] In this embodiment of the first embodiment, the gate dielectric layer 138 is formed before the removal of the sacrificial layer 126. The gate dielectric layer 138 includes a high-k dielectric layer that includes, but is not limited to, HfO2 (hafnium oxide), ZrO2 (zirconium dioxide), hafnium zirconium oxide, Al2O3 (aluminum oxide), and Ta2O5 (tantalum pentoxide) or other electronic grade (EG) oxides. Examples of high-k materials also include, but are not limited to, metal oxides such as hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In one embodiment, the dielectric material of the gate dielectric layer 138 is conformally deposited using a highly conformal deposition process such as ALD. Other deposition methods, such as CVD and PVD, can be used to deposit a highly conformal layer of dielectric material to cover the exposed portion of the gate structure. Excess material can be removed using standard techniques. As shown in Figures 12C and 10J, for example, the exposed channel layer 122 is covered by the gate dielectric layer 138.

[0110] The sacrificial layer 126 is selectively etched, freeing the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, and the gate dielectric layer 138, thereby allowing the open gate structure to extend into the adjacent space between the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, and the gate dielectric layer 138.

[0111] The sacrificial layer 126 can be selectively etched with respect to the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the gate dielectric layer 138, the sidewall spacer 114, the inner spacer 130, and the semiconductor substrate 102 using a wet etching process that is selective for the inner dielectric layer 120, the channel layer 122, the outer dielectric layer 124, the gate dielectric layer 138.

[0112] The gate conductor layers 140 and 144 may include a metallic gate or a work function metal (WFM). In exemplary embodiments, the gate conductor layers 140 and 144 include a WFM for either an nFET device or a pFET device. For nFET devices, the WFM for the gate conductor may include titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or a combination of Ti and Al alloys, and the stack may include a barrier layer (e.g., titanium nitride (TiN) or another suitable material), followed by one or more of the above-mentioned WFM materials. For pFET devices, the WFM for the gate conductor may include TiN, tantalum nitride (TaN), or another suitable material. In some embodiments, the pFET WFM may include a metallic stack, where a thicker barrier layer (e.g., TiN, TaN, etc.) is formed following a WFM such as Ti, Al, TiAl, TiAlC, or any combination of Ti and Al alloys. It should be understood that various other materials may be used as appropriate for the gate conductor layers 140 and 144. In exemplary embodiments, the material of the gate conductor layer 140 is different from the material of the gate conductor layer 144. In exemplary embodiments, the gate conductor layers 140 and 144 are deposited on the semiconductor structure 100 and within the nanosheet stack structure, as can be seen, for example, from Figures 12A and 12B.

[0113] The gate structure further includes gate contacts 142 and 146, which include, but are not limited to, metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum-magnesium carbide, or combinations thereof, deposited in channels etched within the gate conductor layers 140 and 144. For example, a lithography process may be used to pattern the gate conductor layers 140 and 144 and to etch the channels for the gate contacts 142 and 146.

[0114] The sacrificial gate cap 148 is formed by depositing a layer of dielectric material such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), or other similar materials commonly used to form a gate capping layer.

[0115] The gate conductor layers 140 and 144, gate contacts 142 and 146, and sacrificial gate cap 148 may be deposited using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP.

[0116] Figures 13A to 13C are schematic cross-sectional views of the semiconductor structure 100 of Figures 11A to 11C in another embodiment of the first embodiment after the gate replacement process has been performed. In this embodiment, the same process as in the embodiments of Figures 12A to 12C is performed, except that the sacrificial layer 126 is etched before the formation of the gate dielectric layer 138, and the gate dielectric layer 138 is formed on the exposed surfaces of the inner and outer dielectric layers 120 and 124, on the channel layer 122, on the inner spacer 130, on the semiconductor substrate 102, and on the sidewall spacer 114 before the formation of the gate conductor layers 140 and 144, the gate contacts 142 and 146, and the sacrificial gate cap 148. Figure 13B is obtained along the cross-sectional line BB of Figure 13A, and Figure 13C is obtained along the cross-sectional line CC of Figure 13A.

[0117] The sacrificial layer 126 is removed using the processes and techniques described above, and the gate dielectric layer 138 is then formed in the same manner as described above, except that the gate dielectric layer 138 in this embodiment is deposited on the exposed surfaces of the inner and outer dielectric layers 120 and 124, the channel layer 122, the inner spacer 130, the semiconductor substrate 102, and the sidewall spacer 114. The gate conductor layers 140 and 144, the gate contacts 142 and 146, and the sacrificial gate cap 148 are then formed as described above. As shown in Figures 13A to 13C and Figure 10J, for example, in this embodiment of the first embodiment, the outer spacer layer 124 and the inner spacer layer 122 in the gate channel have increased thickness due to the addition of the gate dielectric layer 138.

[0118] Figures 14 to 22C schematically illustrate an exemplary method for manufacturing a semiconductor structure 300 according to a second exemplary embodiment. In the second exemplary embodiment, features similar to those seen in the first exemplary embodiment have the same numbering and will be described by reference to the description of those features seen above in the first embodiment.

[0119] Figure 14 is a schematic cross-sectional view of semiconductor structure 300 in a similar manufacturing stage to Figure 4 of the first embodiment, and is formed using techniques similar to those described above with reference to semiconductor structure 100. Semiconductor structure 300 includes a nanosheet stack structure comprising a semiconductor substrate 302, sacrificial layer 304, sacrificial layers 308-1, 308-2, and 308-3, dummy gate insulator layer 310, dummy gate electrode 312, sidewall spacer 314, inner dielectric layer 320, channel layer 322, outer dielectric layer 324, and sacrificial layer 126. Although not shown, a gate capping layer (not shown) may also be placed on the dummy gate electrode 312.

[0120] As can be seen from Figure 14, in the second exemplary embodiment, only one sacrificial layer 304 is present at the bottom, and additional sacrificial layers 308-3 but , the second sacrificial layer 104-2 of the first exemplary embodiment is placed tree exchange I understand For example, in a second exemplary embodiment, there may be one sacrificial layer 304 and three sacrificial layers 308. Sacrifice Corresponds to sacrificial layers 106-1 to 106-3 In the manufacturing stage shown in Figure 14, the sacrificial layer has already been replaced by the sacrificial layer 326. In addition, the semiconductor substrate 302 shown in Figure 14 has not been reset, unlike in the first embodiment.

[0121] Figure 15 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 14 after forming an etching mask 328, resetting the etching mask 328 below the sacrificial layer 308 to expose the sacrificial layer 308, and removing the sacrificial layer 308 using the process described above with reference to Figure 6, for example. In the second embodiment, the etching mask 328 protects the sacrificial layer 304 while exposing the sacrificial layer 308. In particular, in the second embodiment, the sacrificial layer 308 is removed before the removal of the sacrificial layer 304.

[0122] Figure 16 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 15 after removing the etching mask 328 and forming additional material for the sacrificial layer 326, and etching the additional sacrificial layer 326 based on the pattern defined by the sidewall spacers 314 using, for example, the process described above with reference to Figure 7. As can be seen from a comparison of Figure 7 and Figure 16, the sacrificial layer 304 is still present.

[0123] Figure 17 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 16 after the sacrificial layer 326 has been reset to form the inner spacer 330 using the process described above, for example with reference to Figure 8. At this stage of the manufacturing process, the contact layer 332 (Figure 20) has not yet been formed in the second embodiment.

[0124] Figure 18 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 17 after the sacrificial layer 304 has been removed using the process described above with reference to Figure 5, for example.

[0125] Figure 19 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 18 after the removal of the inner dielectric layer 320, channel layer 322, and outer dielectric layer 324, which were exposed by the removal of the sacrificial layer 304. For example, one or more wet or dry etching processes may be used to etch the inner dielectric layer 320, channel layer 322, and outer dielectric layer 324 that were exposed by the removal of the sacrificial layer 304. In some embodiments, the exposed portions of the inner dielectric layer 320, channel layer 322, and outer dielectric layer 324 located between portions of the sacrificial layer 126 may be slightly etched. As a non-limiting example, if the inner and outer dielectric layers 320 and 324 contain HfO2, an HCl-based wet chemistry may be used to etch the inner and outer dielectric layers 320 and 324. If the channel layer contains MoS2, it may be etched using a dry isotropic SF6+N2 or XeF2 type etching chemistry. Because the exposed edges of the three-layer stack consisting of the inner dielectric layer 320, the channel layer 322, and the outer dielectric layer 324 have a small area, their etching is minimal compared to the exposed layers at the bottom.

[0126] Figure 20 is a schematic cross-sectional view of the semiconductor structure 300 of Figure 19 after the formation of the lower dielectric insulation (BDI) 350, ILD 352, and contact layer 332.

[0127] The dielectric layer for BDI350 is formed on the semiconductor structure 300 on the semiconductor substrate 302, the sidewall spacer 314, the inner spacer 330, the sacrificial layer 304 and the adjacent inner dielectric layer 320, the channel layer 322 and the portion of the sacrificial layer 326 exposed by the removal of the outer dielectric layer 324, and the exposed portions of the inner dielectric layer 320, the channel layer 322 and the outer dielectric layer 324. For example, the dielectric layer may be formed by depositing one or more conformal layers of dielectric material on the exposed surface of the semiconductor structure 300, including the exposed surface of the nanosheet stack structure. In some embodiments, the dielectric layer is formed from a low-k dielectric material. For example, the dielectric layer may be formed from SiN, SiBCN, SiOCN, SiOC, SiO2, or any other type of dielectric material (e.g., a low-k dielectric material with k less than 5) which is commonly used to form insulating gate sidewall spacers in FET devices. In one embodiment, the dielectric material is conformally deposited using a highly conformal deposition process such as ALD to ensure that the recess is sufficiently filled with the dielectric material. Other deposition methods such as CVD and PVD may be used to deposit a highly conformal layer of the dielectric material to fill the recess.

[0128] SiO x A dielectric material for ILD352, including but not limited to low-temperature oxides (LTO), high-temperature oxides (HTO), fluid oxides (FOX), or several other dielectrics, is deposited on a dielectric layer for BDI350 using deposition techniques including but not limited to CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, and / or LSMCD, sputtering, and / or plating.

[0129] The dielectric layers for BDI350 and the dielectric material for ILD352 are then etched in one or more etching processes to a level below the bottom three-layer stack of the inner dielectric layer 320, channel layer 322, and outer dielectric layer 324. For example, the dielectric material for ILD352 may be etched using an etching process such as a directional RIE process that is selective for the material for the sidewall spacer 314 and the dielectric layer for BDI350 to form ILD352. The dielectric layers for BDI350 may be etched using an etching process such as a directional RIE process that is selective for the material for the sidewall spacer 314, inner spacer 330, inner dielectric layer 320, channel layer 322, and outer dielectric layer 324 to form BDI350. One or both of the etching processes may be time-adjusted, and in some embodiments, etching for forming both BDI350 and ILD352 may be performed as part of the same etching process. As shown in Figure 20, for example, BDI350 and ILD352 can be etched to a level between the upper and lower surfaces of the bottom inner spacer 330. Etching to form BDI350 and ILD352 exposes the side wall spacer 314, the inner spacer 330, and the inner dielectric layer 320, the channel layer 322, and the outer dielectric layer 324.

[0130] The contact layer 332 is formed on the BDI 350, ILD 352, exposed sidewall spacer 314, inner spacer 330, and inner dielectric layer 320, channel layer 322, and outer dielectric layer 324, for example, using the process described above for the formation of the contact layer 132 in Figure 8.

[0131] Figures 21A to 21C are schematic cross-sectional views of the semiconductor structure 300 of Figure 20 after forming the source / drain region 334, resetting the source / drain region 334, and forming the interlayer dielectric (ILD) 336 on the reset source / drain region 334. Figure 21B is obtained along the cross-sectional line BB of Figure 21A, and Figure 21C is obtained along the cross-sectional line CC of Figure 21A. The source / drain region 334 and ILD 336 are formed, for example, using the process described above for the formation of the source / drain region 134 and ILD 136 in Figures 9A to 9C.

[0132] Figures 22A to 22C are schematic cross-sectional views of the semiconductor structure 300 shown in Figures 21A to 21C after a gate replacement process has been performed, which includes removing the dummy gate electrode 312, removing the dummy gate insulator layer 310, forming a gate dielectric layer 338, removing the sacrificial layer 326 and replacing it with gate conductor layers 340 and 344, gate contacts 342 and 346, and sacrificial gate cap 348 by using a process similar to that described above for removal, and replacing the sacrificial layer 126 with gate conductor layers 140 and 144, gate contacts 142 and 146, and sacrificial gate cap 148 of Figure 12A. Figure 22B is obtained along the cross-sectional line BB of Figure 22A, and Figure 22C is obtained along the cross-sectional line CC of Figure 22A. The gate dielectric layer 338 may be formed according to any aspect of the first embodiment described above for the dielectric layer 138.

[0133] Figures 23-24 7 isThe third exemplary embodiment schematically illustrates an exemplary method for manufacturing a semiconductor structure 500 according to an exemplary embodiment. In the exemplary embodiment, the semiconductor structure 500 is a stacked CFET including both nFETs and pFETs formed in a stacked array according to the process described below. In some embodiments, the CFETs of the semiconductor structure 500 are formed as inverter CFETs. In the third exemplary embodiment, features similar to those seen in the first exemplary embodiment have similar numbers and are described by reference to the description of those features seen above in the first embodiment. In the following figures, figures with the reference numeral "A" are obtained along cross-section XX, figures with the reference numeral "B" are obtained along cross-section Y1-Y1 of Figure 23, figures with the reference numeral "C" are obtained along cross-section Y2-Y2 of Figure 23, and figures with the reference numeral "D" are obtained along cross-section Y3-Y3 of Figure 23. For example, Figure 2 4(A)~(D) Therefore, see Figure 2 4(A) is Obtained along cross-section XX, Figure 2 4(B) is Obtained along the cross-section Y1-Y1 in Figure 23, and Figure 2 4(C) is Obtained along the cross-section Y2-Y2 in Figure 23, Figure 2 4(D) is This is obtained along the Y3-Y3 section in Figure 23. Note that without any material or structure formed in the planes defined by the Y1-Y1 and Y3-Y3 sections, these sections show the underlying structure when viewed toward the Y2-Y2 section, as indicated by the translucent plane.

[0134] Figure 23 is a schematic top view of semiconductor structure 500. Figure 2 4(A)~(D) This is a schematic cross-sectional view of the semiconductor structure 500 in Figure 23 at an intermediate stage of manufacturing, obtained along the cross-sections XX, Y1-Y1, Y2-Y2, and Y3-Y3 described above.

[0135] The semiconductor structure 500 includes a dielectric layer 502 disposed on a semiconductor substrate (not shown), a nanosheet stack structure formed on the dielectric layer 502 and including sacrificial layers 504, 506, and 508-1 to 508-3, an active gate including a dummy gate insulator layer 510 and a dummy gate electrode 512, a sidewall spacer 514, inert gates 516-1 and 516-2, embedded power rail (BPR) capping layers 518-1 and 518-2, and embedded power rails 520-1 and 520-2. Although not shown, a gate capping layer (not shown) may also be disposed on the dummy gate electrode 512.

[0136] The semiconductor substrate may be formed using a process similar to that described above for the semiconductor substrate 102, and the dielectric layer 502 may be formed on the semiconductor substrate using standard deposition techniques such as ALD, CVD, and PVD, and planarized to a desired thickness using a process such as CMP or etching. The dielectric layer 502 may contain dielectric materials such as those described above.

[0137] Sacrificial layers 504, 506, 508-1 to 508-3, dummy gate insulator layer 510, dummy gate electrode 512, and sidewall spacer 514 may be formed using a process similar to that described above for sacrificial layers 104-1 and 104-2, sacrificial layers 106-1, 106-2, and 106-3, sacrificial layers 108-1 and 108-2, dummy gate insulator layer 110, dummy gate electrode 112, and sidewall spacer 114. In exemplary embodiments, sacrificial layer 504 comprises a SiGe alloy having Ge in the range of about 25% to 40%, sacrificial layer 506 comprises a SiGe alloy having Ge in the range of about 50% to about 90%, and sacrificial layers 508-1 to 508-3 are Si or It contains Ge in the range of approximately 5% to 15%. S Includes iGe alloy.

[0138] Sacrificial layers 504, 506, and 508 may be formed with thicknesses that define the spacing size at which the high-k dielectric material and work function metal are formed. In one embodiment, the thickness of sacrificial layer 504 is in the range of about 8 nm to about 15 nm, the thickness of sacrificial layer 506 is in the range of about 8 nm to about 15 nm, and the thickness of sacrificial layer 508 is in the range of about 4 nm to about 8 nm. In some embodiments, other thicknesses may be used for each of the sacrificial nanosheet layers 104, 106, and 108.

[0139] Inert gates 516-1 and 516-2 can be formed by etching the dummy gate electrode and other gate materials and replacing them with, for example, a dielectric material, using known processes and techniques.

[0140] For example, channels for BPR capping layers 518-1 and 518-2, and BPR520-1 and 520-2, can be formed by etching the dielectric layer 502 before the formation of the nanosheet stack structure, for example, by patterning the dielectric layer 502 using a lithography technique.

[0141] BPR520-1 and 520-2 may include metallic materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, and / or copper. BPR520-1 and 520-2 may be formed in the channel by conformal deposition using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, sputtering, and / or plating. In some embodiments, the metallic materials of BPR520-1 and 520-2 are deposited to fill the channel. CMP may be used to planarize the semiconductor structure 500 and etch any undesirable metallic materials, followed by a metal resetting process to reset BPR520-1 and 520-2 in the channel.

[0142] The BPR capping layers 518-1 and 518-2 may contain dielectric materials such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), or other similar dielectric materials commonly used to form capping layers, and may be deposited using known techniques such as atomic layer deposition (ALD), CVD, and PVD. CMP may be used to planarize the semiconductor structure 500, etch any undesirable dielectric materials, and expose the dielectric layer 502.

[0143] Figure 2 5(A)~(D) , the sacrificial layer 506 is removed, the inner dielectric layer 520 is deposited, the channel layer 522 is deposited, the outer dielectric layer 524 is deposited, the sacrificial layer 526 is deposited, the outer sacrificial layer 526 is deposited, the sacrificial layer 526 is trimmed using the process described above with reference to Figures 2 and 3 for the removal of the outer sacrificial layer 106, the inner dielectric layer 120 is deposited, the channel layer 122 is deposited, the outer dielectric layer 124 is deposited, the sacrificial layer 126 is deposited, and the sacrificial layer 126 is trimmed (Figure 2) 4(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0144] Figure 2 6(A)~(D) For example, using the process described above with reference to Figure 4, to etch the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 based on the pattern defined by the sidewall spacer 114, Figure 2 shows the inner dielectric layer 520, channel layer 522, outer dielectric layer 524, and sacrificial layer 526 after etching based on the pattern defined by the sidewall spacer 514. 5(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0145] Figure 2 7(A)~(D), remove sacrificial layer 504, deposit inner dielectric layer 620, deposit channel layer 622, deposit outer dielectric layer 624, deposit additional material for sacrificial layer 526, trim the additional material for sacrificial layer 526 using the process described above with reference to Figures 2 and 3 for the removal of sacrificial layer 106, deposit inner dielectric layer 120, deposit channel layer 122, deposit outer dielectric layer 124, deposit sacrificial layer 126, and Figure 2 after trimming sacrificial layer 126 6(A)~(D) This is a schematic cross-sectional view of the semiconductor structure 500. In some embodiments, the channel material used for channel layer 622 is different from the channel material used for channel layer 522. For example, if channel layer 522 is used in an nFET semiconductor device and channel layer 622 is used in a pFET semiconductor device, the materials of channel layers 522 and 622 may be different. In other embodiments, the same material may be used for both channel layer 522 and channel layer 622.

[0146] Figure 2 8(A)~(D) For example, using the process described above with reference to Figure 4 for etching the inner dielectric layer 120, channel layer 122, outer dielectric layer 124, and sacrificial layer 126 based on the pattern defined by the sidewall spacer 114, Figure 2 shows the inner dielectric layer 620, channel layer 622, outer dielectric layer 624, and sacrificial layer 526 after etching based on the pattern defined by the sidewall spacer 514. 7(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0147] Figure 2 9(A)~(D) For example, using the process described above with reference to Figures 6 and 7, the sacrificial layer 508 is replaced with additional material for sacrificial layer 526, sacrificial layer 108 is removed, and additional material for sacrificial layer 126 is formed, as shown in Figure 2. 8(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0148] Figure 3 (A) to (D) of 0 are, the sacrificial layer 526 is reset, the inner spacer 530 is formed, the contact layer 532 is formed using the process described above with reference to Figure 8 for resetting the sacrificial layer 126, the inner spacer 130 is formed, the contact layer 132 is formed, and then the contact layer 532 is directionally etched to expose the dielectric layer 502, as shown in Figure 2 9(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0149] The contact layer 532 may be etched using a directional RIE or other directional process that is selective for, for example, the dielectric layer 502, the sidewall spacer 514, and the gate capping layer (not shown), thereby removing the contact layer 532 from the surface of the dielectric layer 502, while remaining on the sidewalls of the inner spacer 530, the inner dielectric layers 520 and 620, the channel layers 522 and 622, and the outer dielectric layers 524 and 624.

[0150] Figure 31 shows the etching mask 534 after it has been formed, which has a patterned channel 536. 0 (A)~(D) This is a top view of semiconductor structure 500, as shown in Figure 3. 2(A)~(D) This is a schematic cross-sectional view thereof. For example, an OPL may be coated onto a semiconductor structure 500, followed by a lithography process to pattern the OPL and form an etching mask 534. The OPL may include, for example, a resin material that is applied and baked by spin coating to enhance planarization. The patterned portion of the OPL is removed to form a channel 536, thereby exposing a portion of the BPR capping layer 518-2 in the Y3-Y3 cross section of the etching mask 534.

[0151] Figure 3 3(A)~(D) Figure 3 shows the result after removing the exposed BPR capping layer 518-2 in the Y3-Y3 cross section and forming a source / drain region 538 that electrically contacts the BPR 520-2. 2(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0152] The exposed BPR gate capping layer 518-2 can be removed using, for example, a RIE, wet, or dry etching process that is selective for the materials of the etching mask 534, dielectric layer 502, contact layer 532, and BPR 520-2.

[0153] The source / drain region 538 can be formed, for example, using the processes and techniques described above for the formation of the source / drain region 134. Figure 3 3(A)~(D) As can be seen, the source / drain region 134 is in contact with the BPR 520-2 in the Y3-Y3 cross section, where a portion of the BPR gate capping layer 518-2 has been removed.

[0154] Figure 3 4(A)~(D) Figure 3 shows the state after the contact layer 532 and source / drain region 538 are reset to the level below the inner dielectric layer 620, channel layer 622, and outer dielectric layer 624, forming the source / drain spacer 540, forming the ILD 542, and then resetting the ILD 542. 3(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0155] The contact layer 532 and the source / drain region 538 are, for example, etched using one or more etching processes, such as directional RIE having an etching chemical action that is selective for the sidewall spacer 514, as shown in Figure 3. 4(A) The inner dielectric layer 620, channel layer 622, and outer dielectric layer 624 may be reset to a level below as shown. For example, an anisotropic wet etching process may be used to reset the contact layer 532 and source / drain region 538. In an exemplary embodiment, for example, the contact layer 532 and source / drain region 538 may be etched along the inner spacer 530 between the bottom three-layer stack of the inner dielectric layer 620, channel layer 622, and outer dielectric layer 624 and the top three-layer stack of the inner dielectric layer 520, channel layer 522, and outer dielectric layer 524 for a distance of about three-quarters or more, without exposing the inner dielectric layer 520, channel layer 522, and outer dielectric layer 524.

[0156] The source / drain spacer 540 is formed on a semiconductor structure 500, which includes a resetted source / drain region 538, a sidewall spacer 514, an exposed inner spacer 530, an inner dielectric layer 620, a channel layer 622, and an outer dielectric layer 624. Non-limiting examples of materials for the source / drain spacer 540 include, for example, SiN, AlN, Al2O3, or other similar dielectric materials that are selectively etchable with respect to the material of the sidewall spacer 514. In some embodiments, the source / drain spacer 540 is conformally deposited using deposition techniques including, but not limited to, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, sputtering, and / or plating.

[0157] ILD542 is, for example, SiO x The ILD542 may be formed by depositing dielectric materials, including but not limited to low-temperature oxides (LTO), high-temperature oxides (HTO), fluid oxides (FOX), or several other dielectrics, onto the source / drain spacer 540. The ILD542 may be deposited using deposition techniques, including but not limited to CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, and / or LSMCD sputtering and / or plating. Planarization, such as chemical mechanical polishing (CMP), may be performed to remove excess material from the ILD542 and planarize the resulting structure. Etching processes, such as those described above, which are selective for the source / drain spacer 540, are shown in Figure 3. 4(A) This can be done to reset the ILD542 shown.

[0158] Figure 3 5(A)~(D)Figure 3 shows the source / drain spacer 540 after being reset below the level of the bottom three-layer stack of the inner dielectric layer 620, channel layer 622, and outer dielectric layer 624, exposing the portion of the inner spacer 530 located between the bottom three-layer stack of the inner dielectric layer 620, channel layer 622, and outer dielectric layer 624, and the top three-layer stack of the inner dielectric layer 520, channel layer 522, and outer dielectric layer 524. 4(A)~(D) This is a schematic cross-sectional view of the semiconductor structure 500. For example, the source / drain spacer 540 may be reduced in height by approximately one-quarter of a distance along the inner spacer 530, which is located below the bottom three-layer stack of the inner dielectric layer 620, the channel layer 622, and the outer dielectric layer 624. Figure 3 5(A) As can be seen, the reset source / drain spacer 540 includes portions 540-1 and 540-2 on either side of the gate structure, and ILD 542 acts as an etching mask for portions 540-1 and 540-2 of the source / drain spacer 540 to prevent the source / drain region 538 from being exposed by etching of the source / drain spacer 540.

[0159] Figure 3 6(A)~(D) Figure 3 shows the result after removing ILD542 and forming a patterned etching mask 544 to expose one side of the gate structure, for example, corresponding to cross section Y1-Y1, while protecting the other side of the gate structure, for example, corresponding to cross section Y3-Y3. 5(A)~(D) This is a schematic cross-sectional view of the semiconductor structure 500. Etching processes such as those described above, which are selective for the source / drain spacer 540, inner dielectric layer 620, channel layer 622, and outer dielectric layer 624, inner spacer 530, and sidewall spacer 514, may be performed to remove the remainder of the ILD 542.

[0160] Next, the OPL may be coated onto the semiconductor structure 500, followed by a lithography process to pattern the OPL and form an etching mask 544. The OPL may include, for example, a resin material that is applied and baked by spin coating to enhance planarization. The patterned portion of the OPL is removed, exposing the side of the gate structure corresponding to the Y1-Y1 cross section.

[0161] Figure 3 7(A)~(D) Figure 3 shows the following steps: removing portion 540-1 of the source / drain spacer 540 on the side of the gate structure corresponding to the Y1-Y1 cross section exposed by the etching mask 544, removing the etching mask 544, forming a contact layer 546 on the semiconductor structure 500 including the remaining portion 540-2 of the source / drain spacer 540, the source / drain region 538 corresponding to the Y1-Y1 cross section exposed by the removal of portion 540-1 of the source / drain spacer 540 on that side of the gate structure, and on the sidewall of the gate structure including the inner spacer 530, the inner dielectric layer 620, the channel layer 622, the outer dielectric layer 624, and the sidewall spacer 514, etching the contact layer 546 to expose the source / drain spacer 540 corresponding to the Y3-Y3 cross section and portion 540-2 of the source / drain region 538 corresponding to the Y1-Y1 cross section, and removing the source / drain region 538 corresponding to the Y1-Y1 cross section. 6(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0162] A portion 540-1 of the source / drain spacer 540 may be removed, for example, using an etching process, such as a RIE process, to expose the source / drain region 538. For example, a RIE process may utilize an etching chemical action that is selective for the material of the source / drain region 538.

[0163] The etching mask 544 can be removed, for example, by using a plasma etching process or an ashing process.

[0164] The contact layer 546 may be formed on the semiconductor structure 500, including the remaining source / drain spacer 540, the source / drain region 538 corresponding to the Y1-Y1 cross-section exposed by the removal of the source / drain spacer 540 on that side of the gate structure, and the gate structure including the inner spacer 530, the inner dielectric layer 620, the channel layer 622, and the outer dielectric layer 624, and the sidewall of the sidewall spacer 514, in a manner similar to that described above for the contact layer 532. In some embodiments, the material selected for use with the contact layer 546 may depend on the material used for the channel layer 622, for example, whether the channel layer 622 is used in an nFET or pFET semiconductor device, and may include a bilayer material made from both the channel layer 622 and the semimetallic contact layer material, such as bismuth or antimony or other similar material, or a monolayer containing either the channel layer material or the semiconductor material. In some embodiments, doping treatment may be performed on the contact layer 546 to reduce the Schottky barrier of the upper FET.

[0165] The contact layer 546 may be etched using a directional RIE or other directional process that is selective for, for example, the source / drain region 538, the sidewall spacer 514, the gate capping layer (not shown), and portion 540-2 of the source / drain spacer 540, thereby removing the contact layer 546 from the surface of the source / drain region 538 and portion 540-2 of the source / drain spacer 540, while remaining on the inner spacer 530, the inner dielectric layer 620, the channel layer 622, the outer dielectric layer 624, and the lateral sidewalls of the sidewall spacer 514.

[0166] The exposed source / drain region 538 can be removed using one or more etching processes, such as directional RIE, which have an etching chemical action that is selective to the sidewall spacers 514, contact layer 532, and contact layer 546. For example, anisotropic or isotropic dry or wet etching processes can be used to remove the exposed source / drain region 538 and expose the dielectric layer 502.

[0167] Figure 38 shows the etching mask 548 having patterned channels 550 after forming Figure 3 7(A)~(D) This is a top view of semiconductor structure 500, as shown in Figure 3. 9(A)~(D) This is a schematic cross-sectional view. For example, an OPL may be coated onto a semiconductor structure 500, and then the OPL is patterned by a lithography process to form an etching mask 548. The OPL may include, for example, a resin material that is applied and baked by spin coating to enhance planarization. The patterned portion of the OPL is removed to form a channel 550 so that the etching mask 548 exposes a portion of the BPR capping layer 518-1 in the Y1-Y1 section.

[0168] Figure 4 (A) to (D) of 0 are Figure 3 shows the result after removing the exposed BPR capping layer 518-1 in the Y1-Y1 section, forming a source / drain region 552 that electrically contacts the BPR 520-1, and then resetting the contact layer 546 and the source / drain region 552 to the level above the top three-layer stack of the inner dielectric layer 620, channel layer 622, and outer dielectric layer 624 and below the sidewall spacer 514. 9(A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0169] The exposed BPR gate capping layer 518-1 can be removed, for example, using a RIE wet or dry etching process that is selective for the materials of the etching mask 548, dielectric layer 502, contact layers 532 and 546, and BPR 520-1.

[0170] The source / drain region 552 may be formed, for example, using the processes and techniques described above for the formation of the source / drain region 134. In some embodiments, the source / drain region 552 is formed from a different material than the source / drain region 538, where, for example, the materials of the source / drain region 538 and the source / drain region 552 depend on the respective types of semiconductor devices of the corresponding channel layers 522 and 622. Figure 4 0 (A)~(D) As can be seen, the source / drain region 552 is in contact with the BPR 520-1 in the Y1-Y1 section, where a portion of the BPR gate capping layer 518-1 has been removed. In addition, the source / drain region 552 is also formed on portion 540-2 of the source / drain spacer 540 in the Y3-Y3 section.

[0171] The contact layer 546 and the source / drain region 552 may be reset using one or more etching processes, for example, directional RIE having an etching chemical action selective to the sidewall spacer 514. For example, an anisotropic wet etching process may be used to reset the contact layer 546 and the source / drain region 552. In exemplary embodiments, for example, the contact layer 546 and the source / drain region 552 may be etched down to a level between the top three layers stack of the inner dielectric layer 620, the channel layer 622, and the outer dielectric layer 624, and the bottom of the sidewall spacer 514, without exposing the inner dielectric layer 620, the channel layer 622, and the outer dielectric layer 624. For example, in some embodiments, the contact layer 546 and the source / drain region 552 may be etched down to the bottom of the sidewall spacer 514 and about halfway between the top three layers stack of the inner dielectric layer 620, the channel layer 622, and the outer dielectric layer 624.

[0172] Figure 4 1(A)~(D) Figure 4 shows the result after forming ILD554, capping layer 556, and removing the dummy gate electrode 512. 0 (A)~(D) This is a schematic cross-sectional view of semiconductor structure 500.

[0173] ILD554 is, for example, SiO x The ILD554 may be formed by depositing dielectric materials, including but not limited to low-temperature oxides (LTO), high-temperature oxides (HTO), fluid oxides (FOX), or several other dielectrics, onto the source / drain spacer 540. The ILD554 may be deposited using deposition techniques, including but not limited to CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, and / or LSMCD sputtering and / or plating. Planarization, such as chemical mechanical polishing (CMP), may be performed to remove excess material from the ILD554 and planarize the resulting structure. Etching processes, such as those described above, which are selective for the sidewall spacer 514, are shown in Figure 4. 1(A) This can be done to reset ILD554 as shown.

[0174] The capping layer 556 may be formed by depositing a layer of dielectric material, such as a material similar to those used for SiN, SiCN, SiON, BN, SiBN, SiOC, ILD554 but with a higher density, or other similar materials commonly used to form a capping layer that is selectively etchable against the sidewall spacers 514. The dielectric material may be deposited using known techniques such as atomic layer deposition (ALD), CVD, and PVD, and then planarized, for example, using CMP to remove excess material.

[0175] The dummy gate electrode 512 is etched using known etching techniques and etching chemicals, such as those described above for the removal of the dummy gate electrode 112.

[0176] Figure 4 2(A)~(D)Figure 4 shows the gate after a gate replacement process has been performed, which includes removing the dummy gate insulator layer 510, removing the sacrificial layer 526 using a process similar to that described above for removing the dummy gate insulator layer 110 and replacing it with the gate conductor layer 560, gate contact 562, and sacrificial gate cap 564, and removing the sacrificial layer 126 and replacing it with the gate conductor layer 140, gate contact 142, and sacrificial gate cap 148 in Figure 12A. 1 (A)~(D) This is a schematic cross-sectional view of the semiconductor structure 500. In some embodiments, a dielectric layer 558 is formed before the gate conductor layer 560 is formed with respect to the dielectric layer 138 described above in a manner similar to that described above.

[0177] Figure 43 shows an inverter CFET circuit formed by the semiconductor structure 500. 2(A) This is a schematic cross-sectional view of the semiconductor structure 500 described. For example, as can be seen from Figure 43, the source / drain region 538 is the V of the inverter circuit. S Corresponding to this, the source / drain region 552 on the gate structure side corresponding to the Y3-Y3 cross section is the V of the inverter circuit. DD Corresponding to this, the source / drain region 552 on the gate structure side corresponding to the Y1-Y1 cross section is the V of the inverter circuit. Out Corresponding to this, gate contact 562 is the V of the inverter circuit. In It corresponds to.

[0178] Figure 44 shows a non-restrictive example of Figure 4 Figures 5-47 as well Refer to Figure 4, which shows the formation of the middle of line (MOL) contact. 2(A) This is a top view of the semiconductor structure 500. As part of the MOL process, a MOL dielectric layer 566 is formed on the semiconductor structure 500 using conformal deposition, for example, as described above for various dielectric layers. Contact channels are etched into the MOL dielectric layer 566, exposing the gate contact 562, the source / drain region 552 on the side of the gate structure corresponding to the Y3-Y3 cross section, and the BPRs 520-1 and 520-2, respectively.

[0179] For example, Figure 4 5(A) and (C) As shown, the contact channel may be etched into the MOL dielectric layer 566, the sidewall spacer 514, and the sacrificial gate cap 564, exposing the gate contact 562 using one or more lithography or etching processes, such as those described above. The MOL contact material, which includes but is not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, is deposited into the channel using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form the MOL contact 568 for the gate contact 562.

[0180] Figure 4 6(A) and (D) As shown, on the side of the gate structure corresponding to the Y3-Y3 cross section, the contact channel may be etched into the MOL dielectric layer 566, the capping layer 556, and the ILD 554, for example, by using one or more lithography or etching processes such as those described above to expose the source / drain region 552 on the side of the gate structure corresponding to the Y3-Y3 cross section. The MOL contact material, which includes but is not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, is deposited in the channel using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form the MOL contact 570 for the exposed source / drain region 552.

[0181] Figure 4 7(B) and (D)As shown, the contact channels may be etched into the MOL dielectric layer 566 above BPR520-1 and 520-2, exposing BPR520-1 and 520-2 by, for example, one or more lithography or etching processes such as those described above. The MOL contact material, which includes but is not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, is deposited in the channels using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form MOL contact 572 for the exposed BPR520-1 and MOL contact 574 for the exposed BPR520-2.

[0182] Figures 48 to 5 6 is The fourth exemplary embodiment schematically illustrates an exemplary method for manufacturing a semiconductor structure 700 according to an exemplary embodiment. In the exemplary embodiment, the semiconductor structure 700 is a stacked CFET including both nFETs and pFETs formed in a stacked array according to the process described below, and is formed in a similar manner to the semiconductor structure 500, except that it is described differently below. In the fourth exemplary embodiment, features similar to those seen in the third exemplary embodiment have similar numbers and are described by reference to the description of those features seen above in the first embodiment. In the following figures, figures with the reference numeral "A" are obtained along cross-section XX of Figure 48, figures with the reference numeral "B" are obtained along cross-section Y1-Y1 of Figure 48, figures with the reference numeral "C" are obtained along cross-section Y2-Y2 of Figure 48, and figures with the reference numeral "D" are obtained along cross-section Y3-Y3 of Figure 48. For example, Figure 4 9(A)~(D) Therefore, see Figure 4 9(A) is Obtained along cross-section XX, Figure 4 9(B) is Obtained along the cross-section Y1-Y1 in Figure 48, and Figure 4 9(C) is Obtained along the cross-section Y2-Y2 in Figure 48, and Figure 4 9(D) isThis is obtained along the Y3-Y3 section in Figure 48. Note that without any material or structure formed in the planes defined by the Y1-Y1 and Y3-Y3 sections, these sections show the underlying structure when viewed toward the Y2-Y2 section, as indicated by the translucent plane.

[0183] Figure 48 is a schematic top view of semiconductor structure 700, and Figure 4 9(A)~(D) Figure 48 is a schematic cross-sectional view of semiconductor structure 700 in an intermediate manufacturing stage similar to the manufacturing stages for semiconductor structure 500 shown in Figure 31. For example, Figure 5 (A) to (D) of 0 as well For reference, the semiconductor structure 700 includes a nanosheet stack structure comprising a dielectric layer 702 disposed on a semiconductor substrate (not shown), an inner dielectric layer 720 formed on the dielectric layer 702, a channel layer 722, an outer dielectric layer 724, a sacrificial layer 726, an inner dielectric layer 820, a channel layer 822, an outer dielectric layer 824, a sidewall spacer 730, a contact layer 732, an active gate including a dummy gate insulator layer 710 and a dummy gate electrode 712, a sidewall spacer 714, inert gates 716-1 and 716-2, embedded power rail (BPR) capping layers 718-1 and 718-2, and embedded power rails 720-1 and 720-2. Although not shown, the gate capping layer (not shown) may also be disposed on the dummy gate electrode 712. Each of these layers may be formed using the processes, techniques, and materials described above, for example, to form the dielectric layer 502, inner dielectric layer 520, channel layer 522, outer dielectric layer 524, sacrificial layer 526, inner dielectric layer 620, channel layer 622, outer dielectric layer 624, sidewall spacer 530, contact layer 532, dummy gate insulator layer 510 and dummy gate electrode 512, sidewall spacer 514, inert gates 516-1 and 516-2, embedded power rail (BPR) capping layers 518-1 and 518-2 and embedded power rails 520-1 and 520-2.

[0184] Again, see Figures 48 and 4 9(A)~(D)With reference, in the fourth embodiment, an etching mask 734 having patterned channels 736 and 750 is formed and patterned in a manner similar to, for example, the formation of etching masks 534 and 548 described above. Channel 736 exposes a portion of the BPR capping layer 718-2 in the Y3-Y3 cross section, and channel 750 exposes a portion of the BPR capping layer 718-1 in the Y1-Y1 cross section. It is important to note that in the fourth exemplary embodiment, channels 736 and 750 are opened in the same stage of the manufacturing process, exposing BPR capping layers 718-1 and 718-2 for both BPR 720-1 and 720-2, compared to the third embodiment in which the channels are opened in different stages of the manufacturing process.

[0185] Figure 5 (A) to (D) of 0 are Figure 4 shows the result after removing the exposed portions of the BPR capping layers 718-1 and 718-2 and forming source / drain regions 738-1 and 738-2 that electrically contact BPR 720-1 and BPR 720-2, respectively. 9(A)~(D) This is a schematic cross-sectional view of semiconductor structure 700.

[0186] The exposed BPR gate capping layers 718-1 and 718-2 can be removed, for example, using the processes and techniques described above for the removal of gate capping layers 518-1 and 518-2.

[0187] Source / drain regions 738-1 and 738-2 can be formed, for example, using the processes and techniques described above for the formation of source / drain regions 538-1 and 538-2. Figure 5 0 (A)~(D) As can be seen, the source / drain region 738-1 is in contact with BPR720-1 in the Y1-Y1 cross section, where the portion of the BPR gate capping layer 718-2 has been removed, and the source / drain region 738-1 is in contact with BPR720-2 in the Y3-Y3 cross section, where the portion of the BPR gate capping layer 718-2 has been removed.

[0188] Figure 5 1(A)~(D) , the contact layer 732 and source / drain regions 738-1 and 738-2 are reset to the level below the inner dielectric layer 820, channel layer 822, and outer dielectric layer 824, source / drain spacers 740-1 and 740-2 are formed, the contact layer 746 is formed, source / drain regions 752-1 and 752-2 are formed, ILD 754 and capping layer 756 are formed, the dummy gate electrode 712 is removed, the dummy gate insulator layer 710 is removed, the sacrificial layer 726 is removed and replaced with the gate conductor layer 760, gate contact 762, and sacrificial gate cap 764, and in some embodiments, the dielectric layer 758 is formed before the gate conductor layer 760 is formed using a process similar to that described above for the third embodiment, as shown in Figure 5. 0 (A)~(D) This is a schematic cross-sectional view of semiconductor structure 700.

[0189] Figure 52 shows a CFET circuit formed by the semiconductor structure 700. 1(A) This is a schematic cross-sectional view of the semiconductor structure 700. For example, as can be seen from Figure 52, the source / drain region 738-1 corresponds to the nFET drain, the source / drain region 738-2 corresponds to the nFET source, the source / drain region 752-1 corresponds to the pFET drain, the source / drain region 752-2 corresponds to the pFET source, and the gate contact 762 corresponds to the gate.

[0190] Figure 5 1(A)~(D) To refer again, source / drain region 738-1 is electrically in contact with BDR720-1, and source / drain region 738-2 is electrically in contact with BDR720-2. Source / drain regions 752-1 and 752-2 are, for example, in Figures 53 and 5. Figures 4-56 As shown, it connects to the contact during the MOL process.

[0191] Figure 53 shows Figure 5 in a non-restrictive example. Figure 4 5 6 Refer to Figure 5, which shows the middle of line (MOL) contact after it has been formed. 1(A)This is a top view of the semiconductor structure 700. As part of the MOL process, for example, using the processes and techniques described above for the semiconductor structure 500 in the third embodiment, a MOL dielectric layer 766 is formed on the semiconductor structure 700, contact channels are etched into the MOL dielectric layer 766, exposing the gate contact 762, the source / drain regions 752-1 and 752-2, and the BPRs 720-1 and 720-2, respectively.

[0192] For example, MOL contact materials, which include but are not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, are deposited in the channel using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form the MOL contact 768 for the gate contact 762.

[0193] Figure 5 5(A) and (D) As shown, the contact channels may be etched into the MOL dielectric layer 766, the capping layer 756, and the ILD 754, exposing the source / drain regions 552-1 and 552-2, for example, by one or more lithography or etching processes such as those described above. The MOL contact material, which includes but is not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, is deposited into the channels using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form the MOL contacts 770 and 778 for the exposed source / drain regions 752-1 and 752-2.

[0194] Figure 5 6(B) and (D) As shown, the contact channels may be etched into the MOL dielectric layer 766 above BPR720-1 and 720-2, exposing BPR720-1 and 720-2 by, for example, one or more lithography or etching processes such as those described above. The MOL contact material, which includes but is not limited to metals such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminides, tantalum carbide, titanium carbide, tantalum magnesium carbide, or combinations thereof, may be deposited in the channels using, for example, CVD, PECVD, RFCVD, PVD, ALD, MLD, MBD, PLD, LSMCD, and / or sputtering, and then planarized by, for example, CMP to form the MOL contact 772 for the exposed BPR720-1 and the MOL contact 774 for the exposed BPR720-2.

[0195] By using standard Si-based nanosheet layers as a framework for forming 2D channel layers in semiconductor structures 100, 300, 500, and 700 of the embodiments described above, for example, all of these channels are etched in the sacrificial layer, thus limiting the impact of channel defects in Si-based growth, and enabling the use of standard manufacturing processes in forming 2D channel layers. In addition, 2D materials enable the use of metallic source / drain regions, enhancing the ease of placement of source / drain regions, because they no longer need to be grown from a silicon substrate or base of another material, but can rather be deposited. The use of 2D channel materials enables higher drive current densities than Si-based CFETs and allows for higher performance from CFETs with lower aspect ratios. N / P performance matching can also be achieved through the selection of channel layer materials.

[0196] It should be understood that the methods for manufacturing semiconductor structures discussed herein can be readily incorporated into semiconductor process flows, semiconductor devices, and integrated circuits having various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be manufactured from various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, and inductors. Integrated circuits according to the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the techniques herein.

[0197] While exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to these exact embodiments, and various other changes and modifications can be made herein by those skilled in the art without departing from the scope of the appended claims.

[0198] In a preferred embodiment of the invention described herein, a semiconductor structure is provided which includes a gate structure comprising a first multilayer channel stack and a second multilayer channel stack spaced apart by an inner spacer, each of the first and second multilayer channel stacks comprising a first dielectric layer; a second dielectric layer; and a channel layer disposed between the first and second dielectric layers, wherein the channel layer of the first multilayer channel stack comprises a first material configured for use with one of an n-type field-effect transistor and a p-type field-effect transistor, and the channel layer of the second multilayer channel stack comprises a second material configured for use with the other of an n-type field-effect transistor and a p-type field-effect transistor. The first material is preferably different from the second material. The semiconductor structure further preferably includes a first metallic source / drain region located on the first side of the gate structure and electrically in contact with the first end of the first multilayer channel stack, and a second metallic source / drain region located on the first side of the gate structure and electrically in contact with the second end of the second multilayer channel stack. The first metallic source / drain region is preferably made of a different material from the second metallic source / drain region. The first and second multilayer channel stacks preferably extend into a first metallic source / drain region through an inner spacer. The semiconductor structure further preferably includes a first contact layer electrically connecting the channel layer of the first multilayer channel stack to the first metallic source / drain region, the first contact layer being located between the sidewall spacer and the first metallic source / drain region; and a second contact layer electrically connecting the channel layer of the second multilayer channel stack to the second metallic source / drain region, the second contact layer being located between the sidewall spacer and the second metallic source / drain region. The material of the first contact layer is preferably different from the material of the second contact layer. The gate structure is preferably located on a dielectric material.

Claims

1. A semiconductor substrate and A gate structure disposed on the semiconductor substrate and including a multilayer channel stack, wherein the multilayer channel stack includes a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first dielectric layer and the second dielectric layer, A first source / drain region located on the first side of the gate structure, which is in electrical contact with the first end of the multilayer channel stack, A semiconductor structure comprising: a second source / drain region located on the second side of the gate structure, which is in electrical contact with the second end of the multilayer channel stack, The multilayer channel stack extends through the first inner spacer to the first source / drain region, and through the second inner spacer to the second source / drain region. The aforementioned semiconductor structure is A contact layer that electrically connects the channel layer to the first source / drain region and the second source / drain region, the contact layer further comprising a contact layer disposed between the first inner spacer and the first source / drain region, and between the second inner spacer and the second source / drain region, A semiconductor structure in which the first source / drain region and the second source / drain region are recessed into the semiconductor substrate, and the contact layer is disposed between the first source / drain region and the second source / drain region and the semiconductor substrate.

2. The semiconductor structure according to claim 1, wherein the multilayer channel stack includes a thickness in the range of about 2 nm to about 4 nm.

3. The semiconductor structure according to claim 1 or 2, wherein the first source / drain region and the second source / drain region include a metallic material.

4. The semiconductor structure according to claim 1 or 2, wherein the channel layer includes a metallic material.

5. The semiconductor structure according to claim 1 or 2, wherein the channel layer includes a two-dimensional layer.

6. The semiconductor structure according to claim 1, further comprising a lower dielectric insulating layer, wherein the gate structure is disposed on the lower dielectric insulating layer, and the contact layer is disposed between the first source / drain region and the lower dielectric insulating layer.

7. The semiconductor structure according to claim 6, further comprising a second dielectric insulating layer disposed between a part of the lower dielectric insulating layer and the first source / drain region, wherein the contact layer is disposed between the first source / drain region and the second dielectric insulating layer.

8. A gate structure comprising a multilayer channel stack, wherein the multilayer channel stack comprises a first dielectric layer, a second dielectric layer, and a channel layer disposed between the first dielectric layer and the second dielectric layer, A first source / drain region located on the first side of the gate structure, which is in electrical contact with the first end of the multilayer channel stack, A semiconductor structure comprising: a second source / drain region located on the second side of the gate structure, which is in electrical contact with the second end of the multilayer channel stack, The multilayer channel stack extends through the first inner spacer to the first source / drain region, and through the second inner spacer to the second source / drain region. The aforementioned semiconductor structure is A contact layer electrically connects the channel layer to the first source / drain region and the second source / drain region, wherein the contact layer is disposed between the first inner spacer and the first source / drain region, and between the second inner spacer and the second source / drain region. A lower dielectric insulating layer, wherein the gate structure is disposed on the lower dielectric insulating layer, The system further comprises a second dielectric insulating layer disposed between a portion of the lower dielectric insulating layer and the first source / drain region, The semiconductor structure wherein the contact layer is disposed between the first source / drain region and the lower dielectric insulating layer, and also between the first source / drain region and the second dielectric insulating layer.

9. In the step of forming a sacrificial stack structure, the sacrificial stack structure includes a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer disposed between the first and second sacrificial layers; Step of removing the third sacrificial layer; In the step of forming a multilayer channel stack on the surfaces of the first and second sacrificial layers exposed by the removal of the third sacrificial layer, each multilayer channel stack is: First dielectric layer; Second dielectric layer; and channel layer formed between the first dielectric layer and the second dielectric layer including; The step of forming a fourth sacrificial layer between the multilayer channel stacks; A step of etching the fourth sacrificial layer laterally to remove the fourth sacrificial layer from the edges of the multilayer channel stack; The step of forming an inner spacer in the recess between the multilayer channel stacks; The step of forming a contact layer between the inner spacer and the metallic source / drain region; and The step of forming the metallic source / drain region that electrically contacts the channel layer of the multilayer channel stack via the contact layer. A method for manufacturing a semiconductor structure, comprising the following features.

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