Battery voltage monitoring device

Abstract

To provide a battery voltage monitoring device that can be incorporated into a battery system.SOLUTION: A battery voltage monitoring device includes a clock generation circuit, and a switch circuit that includes a first N-type transistor (hereinafter referred to as Tr), a second N-type Tr, a first P-type Tr, and a second P-type Tr, in which a source (hereinafter referred to as S) and a back gate are connected to each other, and in which the drain (hereinafter referred to as D) of one of the first N-type Tr and the first P-type Tr is connected to the other S, one S is connected to a signal input portion, and the other D is connected to the signal output portion, and one D of the second N-type Tr and the second P-type Tr is connected to the other S, one S is connected to the signal input portion, and the other D is connected to the signal output portion, a first generation circuit that generates a first control signal for the first P-type Tr and a second control signal for the second P-type Tr, and a second generation circuit that generates a third control signal for the first N-type Tr and a fourth control signal for the second N-type Tr.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a battery voltage monitoring device.

Background Art

[0002] In a battery system, a battery pack in which battery cells are connected in series or parallel is used. The voltages of individual battery cells are monitored by a battery voltage monitoring device such as a battery voltage monitoring IC (Integrated Circuit) that measures the respective voltages. Also, individual battery cells of the battery pack are physically connected by screws connecting bus bars. When the screws connecting the bus bars loosen, problems such as voltage abnormalities and heat generation may occur, so a circuit for monitoring the voltages at both ends of the bus bar is provided. In a battery system, a technique for monitoring the voltages at both ends of a bus bar is known (see, for example, Patent Document 1). According to this technique, the battery system has a voltage detection unit that monitors the voltages at both ends of the bus bar. The circuit of the voltage detection unit is configured as discrete components outside the IC, not included in the battery voltage monitoring IC and the control IC.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Miniaturization is required for the battery system. However, in the above-described technique, since the circuit for monitoring the voltages at both ends of the bus bar is configured outside the IC, it is difficult to meet the requirement for miniaturization. An object of the present invention is to provide a battery voltage monitoring device that can be built into a battery system.

Means for Solving the Problems

[0005] The battery voltage monitoring device of the present invention comprises a signal input section having an input terminal into which the voltages across a busbar are input, and an analog-to-digital conversion circuit that measures the differential voltage of the voltages across the busbar, and monitors the voltages across the busbar, and includes a clock generation circuit that generates a plurality of clocks based on an input reference clock, including a first clock, a second clock having the opposite polarity to the first clock, a third clock that is at a low level during the period when the first clock is at a high level, and a fourth clock that is at a high level during the period when the second clock is at a low level, and a first N-type transfer transistor and a second N-type transfer transistor which are N-type field-effect transistors with their source and back gate connected, and a first P-type transfer transistor and a second P-type transfer transistor which are P-type field-effect transistors with their source and back gate connected, wherein one of the first N-type transfer transistor and the first P-type transfer transistor A switch circuit comprising: a switch circuit in which the drain of one transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to a first signal input terminal, the drain of the other transfer transistor is connected to a first signal output terminal, and of the second N-type transfer transistor and the second P-type transfer transistor, the drain of one transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to the first signal input terminal, and the drain of the other transfer transistor is connected to a second signal output terminal; a first control signal generation circuit configured to generate a first control signal for controlling the on and off states of the first P-type transfer transistor based on the voltage of the first signal input terminal and the second clock, and configured to generate a second control signal for controlling the on and off states of the second P-type transfer transistor based on the voltage of the first signal input terminal and the fourth clock;The battery voltage monitoring device is characterized by comprising: a battery voltage monitoring device [Effects of the Invention]

[0006] According to the present invention, a battery voltage monitoring device that can be built into a battery system can be provided. [Brief explanation of the drawing]

[0007] [Figure 1] This figure shows an example configuration of a battery system according to an embodiment of the present invention. [Figure 2] This figure shows an example of a second ADC in the battery system according to this embodiment. [Figure 3] This figure shows an example of a first switch included in the battery voltage monitoring IC of the battery system according to this embodiment. [Figure 4] This diagram shows the details of the first switch. [Figure 5] This figure shows an example of a timing chart for the first switch of the battery system according to this embodiment. [Modes for carrying out the invention]

[0008] Next, the battery voltage monitoring device of this embodiment will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments. In all the figures used to illustrate the embodiments, components with the same function are given the same reference numerals, and repeated explanations are omitted. Furthermore, in this application, "based on XX" means "based on at least XX," and includes cases where it is based on another element in addition to XX. Also, "based on XX" is not limited to cases where XX is used directly, but also includes cases where it is based on something that has been calculated or processed from XX. "XX" is any element (for example, any information).

[0009] (Embodiment) (Battery system) Figure 1 shows an example configuration of a battery system according to an embodiment of the present invention. In Figure 1, the battery system 1 comprises a battery cell 10-1, a battery cell 10-2, a busbar 20, a battery voltage monitoring IC 30-1, and a battery voltage monitoring IC 30-2. The battery voltage monitoring IC 30-1 and the battery voltage monitoring IC 30-2 are examples of battery voltage monitoring devices. Battery cell 10-1 is, for example, a series connection of n batteries (where n is an integer n > 0). Battery cell 10-2 is, for example, a series connection of n batteries. An example of a battery is a lithium battery. Busbar 20 is an electrode that connects battery cell 10-1 and battery cell 10-2. The battery voltage monitoring IC30-1 has terminals C0 to Cn, each of which is input via resistor R: voltages VC0 and VCn across the battery cell 10-1, and voltages VC1 to VCn-1 between each of the n batteries contained in the battery cell 10-1. Resistor R is a protective resistor.

[0010] The battery voltage monitoring IC30-1 includes terminals VSS and VDD, to which the voltages VC0 and VCn across the battery cell 10-1 are input. The battery voltage monitoring IC30-1 is fabricated, for example, on a P-type semiconductor substrate. The battery voltage monitoring IC 30-1 includes a multiplexer 32-1 connected to each of terminals C0 through Cn, a first analog-to-digital converter (ADC) 34-1 connected to the multiplexer 32-1, terminals BB and TB to which the voltages VBB and VTB across the busbar 20 are input via resistor R, and a second ADC 36-1 connected to terminals BB and TB to measure the differential voltage between voltage VBB and voltage VTB.

[0011] The battery voltage monitoring IC30-2 has terminals C0 to Cn, each of which is input via resistor R, the voltages VC0 and VCn across the battery cell 10-2, and the voltages VC1 to VCn-1 between each of the n batteries contained in the battery cell 10-2. The battery voltage monitoring IC30-2 has terminals VSS and VDD to which the voltages VC0 and VCn across the battery cell 10-2 are input. The battery voltage monitoring IC30-2 includes a multiplexer 32-2 connected to each of terminals C0 through Cn, a first ADC34-2 connected to the multiplexer 32-2, terminals BB and TB to which the voltages VBB and VTB across the busbar (not shown) are input via resistor R, and a second ADC36-2 connected to terminals BB and TB to measure the differential voltage between voltage VBB and voltage VTB.

[0012] Since battery voltage monitoring IC30-1 and battery voltage monitoring IC30-2 have the same configuration, the following explanation will mainly focus on battery voltage monitoring IC30-1. Figure 2 shows an example of a second ADC in the battery system according to this embodiment. The second ADC 36-1 measures the voltage between terminals BB and TB, to which the voltages VBB and VTB across the busbar 20 are input via resistor R. Since charging current and discharging current flow through the bus bar 20, the second ADC 36-1 needs to measure positive and negative voltages. Therefore, the second ADC 36-1 has a different input switch configuration compared to the first ADC 34-1. The second ADC 36-1 can apply an oversampling ADC. FIG. 2 shows an example of an integration circuit at the first stage of the oversampling ADC.

[0013] The second ADC 36-1 includes a first switch SW1, a second switch SW2, a third switch SW3-1, a third switch SW3-2, a first sample capacitor Cs-1, a second sample capacitor Cs-2, a first capacitor Cd-1, a second capacitor Cd-2, an amplifier AMP, a first integration capacitor Cint-1, a second integration capacitor Cint-2, a reset switch SW-1, and a reset switch SW-2.

[0014] The first switch SW1 includes a switch SW1-11, a switch SW1-12, a switch SW1-21, and a switch SW1-22. The terminal BB and the first sample capacitor Cs-1 are connected via the switch SW1-11. The terminal BB and the second sample capacitor Cs-2 are connected via the switch SW1-22. The terminal TB and the first sample capacitor Cs-1 are connected via the switch SW1-21. The terminal TB and the second sample capacitor Cs-2 are connected via the switch SW1-12. The second switch SW2 includes a switch SW2-11, a switch SW2-12, a switch SW2-21, and a switch SW2-22. The third switch SW3-1 includes a switch SW3-11 and a switch SW3-12. The third switch SW3-2 includes a switch SW3-21 and a switch SW3-22.

[0015] The terminal RFP to which the reference voltage Vrfp is applied and the first capacitor Cd-1 are connected via the switches SW2-11 and SW3-12, and the terminal RFP and the second capacitor Cd-2 are connected via the switches SW2-11 and SW3-21. The terminal RFP and the first capacitor Cd-1 are connected via the switches SW2-22 and SW3-11, and the terminal RFP and the second capacitor Cd-2 are connected via the switches SW2-22 and SW3-22.

[0016] The terminal RFN to which the reference voltage Vrfn is applied and the first capacitor Cd-1 are connected via the switches SW2-12 and SW3-11, and the terminal RFN and the second capacitor Cd-2 are connected via the switches SW2-12 and SW3-22. The terminal RFN and the first capacitor Cd-1 are connected via the switches SW2-21 and SW3-12, and the terminal RFN and the second capacitor Cd-2 are connected via the switches SW2-21 and SW3-21.

[0017] The first sample capacitor Cs-1 and the second capacitor Cd-2 are grounded via the switch SWIC-2. The first sample capacitor Cs-1 and the second capacitor Cd-2 are connected to the non-inverting input terminal of the amplifier AMP via the switch SWI-1. The second sample capacitor Cs-2 and the first capacitor Cd-1 are grounded via the switch SWIC-1. The second sample capacitor Cs-2 and the first capacitor Cd-1 are connected to the inverting input terminal of the amplifier AMP via the switch SWI-2. The first integration capacitor Cint-1, the second integration capacitor Cint-2, the reset switch SW-1, and the reset switch SW-2 are connected to the input and output terminals of the amplifier AMP. The output of the amplifier AMP is input to the quantizer QUA via, for example, the next-stage amplifier. The output of the quantizer QUA is input to the second switch SW2.

[0018] The operation of the second ADC36-1 will be described. First, in order to short-circuit both ends of each of the first integration capacitor Cint-1 and the second integration capacitor Cint-2 and discharge (reset), each of the reset switch SW-1 and the reset switch SW-2 is once closed and then opened after a predetermined time. The open state is maintained for a predetermined period.

[0019] During this initial period, the clock signal Φcko turns on switches SW1-11 and SW1-12 of the first switch SW1, switch SW3-11 of the third switch SW3-1, switch SW3-21 of the third switch SW3-2, and switches SWIC-1 and SWIC-2. The clock signal Φcko will be described later.

[0020] During this initial period, the clock signal Φcko turns off switches SW1-21 and SW1-22 of the first switch SW1, switch SW3-12 of the third switch SW3-1, switch SW3-22 of the third switch SW3-2, and switches SWI-1 and SWI-2. The terminal voltage VBB of busbar 20 is applied to the first sample capacitor Cs-1, and charge is stored in the first sample capacitor Cs-1. The terminal voltage VTB of busbar 20 is applied to the second sample capacitor Cs-2, and charge is stored in the second sample capacitor Cs-2.

[0021] The quantizer QUA is reset to its initial value. Depending on the initial value of the quantizer QUA, the second switch SW2 selects either switches SW2-12 and SW2-21, or switches SW2-11 and SW2-22. By selecting either switch SW2-12 and switch SW2-21, or switch SW2-11 and switch SW2-22, a reference voltage Vrfp or reference voltage Vrfn is applied to the first capacitor Cd-1 and the second capacitor Cd-2, and charge is stored in the first capacitor Cd-1 and the second capacitor Cd-2.

[0022] Furthermore, for both the first sample capacitor Cs-1 and the second capacitor Cd-2, the other end opposite to switches SW1-11 and SW3-21 is biased by turning on switch SWIC-2 to the input common. For both the second sample capacitor Cs-2 and the first capacitor Cd-1, the other end opposite to switches SW1-12 and SW3-11 is biased by turning on switch SWIC-1 to the input common.

[0023] Next, as the clock signal Φcko changes, switches SW1-11 and SW1-12 of the first switch SW1, switch SW3-11 of the third switch SW3-1, switch SW3-21 of the third switch SW3-2, and switches SWIC-1 and SWIC-2 are turned off. When the clock signal Φcko changes, switches SW1-21 and SW1-22 of the first switch SW1, switch SW3-12 of the third switch SW3-1, switch SW3-22 of the third switch SW3-2, and switches SWI-1 and SWI-2 are turned on.

[0024] When input common switches SWIC-1 and SWIC-2 are turned off, the first sample capacitor Cs-1, the second sample capacitor Cs-2, the first capacitor Cd-1, and the second capacitor Cd-2, which are biased to the input common, are disconnected from the input common. When switch SWIC-1 is turned on, the first sample capacitor Cs-1, the second sample capacitor Cs-2, the first capacitor Cd-1, and the second capacitor Cd-2 are connected to the amplifier AMP.

[0025] The terminal voltage VTB of busbar 20 is applied to the first sample capacitor Cs-1, and charge is stored in the first sample capacitor Cs-1. The charge stored in the first sample capacitor Cs-1, along with the previously stored charge, is transferred to the integrating capacitor Cint-2 located between the input and output of amplifier AMP, and the voltage is integrated. Furthermore, the charge stored in the second capacitor Cd-2 is transferred to the integrating capacitor Cint-2 located between the input and output of amplifier AMP, and the voltage is integrated.

[0026] The terminal voltage VBB of busbar 20 is applied to the second sample capacitor Cs-2, and charge is stored in the second sample capacitor Cs-2. The charge stored in the second sample capacitor Cs-2, along with the previously stored charge, is transferred to the integrating capacitor Cint-1 located between the input and output of amplifier AMP, and the voltage is integrated. Furthermore, the charge stored in the first capacitor Cd-1 is transferred to the integrating capacitor Cint-1 located between the input and output of amplifier AMP, and the voltage is integrated, thereby performing an integral operation.

[0027] The integral operation changes the output of the quantizer QUA. This change in the output of the quantizer QUA causes the second switch SW2 to switch between either switch SW2-12 and switch SW2-21, or switch SW2-11 and switch SW2-22. By switching between switches SW2-12 and SW2-21, and switches SW2-11 and SW2-22, a reference voltage Vrfp or Vrfn is applied to the first capacitor Cd-1 and the second capacitor Cd-2, and charge is stored in the first capacitor Cd-1 and the second capacitor Cd-2. This process is repeated for a predetermined period each time the clock signal Φcko changes. By repeating the above operations, an analog-to-digital conversion value corresponding to the input busbar voltage Vbb can be obtained from a series of stream data output by the quantizer QUA. Since an analog-to-digital conversion value corresponding to the busbar voltage Vbb can be obtained, the voltage across the busbar 20 can be monitored.

[0028] Let's explain the first switch SW1. Since the polarity of the terminal voltages VTB and VBB of the busbar 20 is reversed, the first switch SW1 is configured to prevent current from flowing backward. Figure 3 shows an example of a first switch included in the battery voltage monitoring IC of the battery system according to this embodiment. The first switch SW1 comprises a first clock bootstrap circuit 40-1, a second clock bootstrap circuit 40-2, a first switch 41-1, a second switch 41-2, and a non-overlap clock generation circuit 42. The first switch 41-1 and the second switch 41-2 are examples of switch circuits, and the non-overlap clock generation circuit 42 is an example of a clock generation circuit. The non-overlap clock generation circuit 42 has a clock input terminal 42-1 and eight clock output terminals 42-21, 42-22, 42-23, 42-24, 42-25, 42-26, 42-27, and 42-28.

[0029] The first clock bootstrap circuit 40-1 includes a first buck circuit 40-11 and a first boost circuit 40-12. The first buck circuit 40-11 is an example of a first control signal generation circuit, and the first boost circuit 40-12 is an example of a second control signal generation circuit. The first clock bootstrap circuit 40-1 is configured to generate control signals that control the on and off states of the FETs (Field Effect Transistors) included in the first buck circuit 40-11 and the first boost circuit 40-12, respectively.

[0030] The first switch 41-1 is a first MOS (metal-oxide-semiconducting) r) It has a switch 41-11 and a second MOS switch 41-12. The first MOS switch 41-11 has at least one N-type FET, which is an NMOS transistor Mns11 (first N-type transfer transistor Mns11), and at least one P-type FET, which is a PMOS transistor Mps11 (first P-type transfer transistor Mps11). Figure 3 shows an example where the first MOS switch 41-11 has one NMOS transistor Mns11 and one PMOS transistor Mps11.

[0031] The second MOS switch 41-12 has at least one N-type FET, which is an NMOS transistor Mns21 (second N-type transfer transistor Mns21), and at least one P-type FET, which is a PMOS transistor Mps21 (second P-type transfer transistor Mps21). Figure 3 shows an example where the second MOS switch 41-12 has one NMOS transistor Mns21 and one PMOS transistor Mps21.

[0032] The second clock bootstrap circuit 40-2 includes a second buck circuit 40-21 and a second boost circuit 40-22. The second buck circuit 40-21 is an example of a third control signal generation circuit, and the second boost circuit 40-22 is an example of a fourth control signal generation circuit. The second clock bootstrap circuit 40-2 is configured to generate control signals that control the on and off states of the FETs included in the second buck circuit 40-21 and the second boost circuit 40-22, respectively. The second switch 41-2 has a first MOS switch 41-21 and a second MOS switch 41-22.

[0033] The first MOS switch 41-21 has at least one N-type FET, which is an NMOS transistor Mns12 (third N-type transfer transistor Mns12), and at least one P-type FET, which is a PMOS transistor Mps12 (third P-type transfer transistor Mps12). Figure 3 shows an example where the first MOS switch 41-21 has one NMOS transistor Mns12 and one PMOS transistor Mps12.

[0034] The second MOS switch 41-22 has at least one N-type FET, which is an NMOS transistor Mns22 (the fourth N-type transfer transistor Mns22), and at least one P-type FET, which is a PMOS transistor Mps22 (the fourth P-type transfer transistor Mps22). Figure 3 shows an example where the second MOS switch 41-22 has one NMOS transistor Mns22 and one PMOS transistor Mps22.

[0035] The non-overlap clock generation circuit 42 is connected to the first clock bootstrap circuit 40-1. The first clock bootstrap circuit 40-1 is connected to the first switch 41-1. More specifically, the first buck converter circuit 40-11 is connected to the clock output terminals 42-21 and 42-22. Furthermore, the first buck converter circuit 40-11 is connected to the gate of the PMOS transistor Mps11 included in the first MOS switch 41-11 and to the gate of the PMOS transistor Mps21 included in the second MOS switch 41-12. The first boost circuit 40-12 is connected to the clock output terminals 42-23 and 42-24. Furthermore, the first boost circuit 40-12 is connected to the gate of the NMOS transistor Mns11 included in the first MOS switch 41-11 and to the gate of the NMOS transistor Mns21 included in the second MOS switch 41-12.

[0036] The first step-down circuit 40-11 includes two capacitors Ccn and CcnH, two P-type field-effect transistors (FETs) called PMOS transistors Mp21 and Mp11, and two Zener diodes ZD-1 and ZD-2. Capacitor Ccn is an example of the first capacitor, and capacitor CcnH is an example of the second capacitor. PMOS transistor Mp21 is an example of the first P-type FET, and PMOS transistor Mp11 is an example of the second P-type FET. Zener diode ZD-1 is an example of the first Zener diode, and Zener diode ZD-2 is an example of the second Zener diode. Capacitor Ccn has one end connected to clock output terminal 42-21. Capacitor CcnH has one end connected to clock output terminal 42-22. The other end of capacitor Ccn is connected to the drain of PMOS transistor Mp21 and the gate of PMOS transistor Mp11. This connection point is referred to as node N1.

[0037] The source of PMOS transistor Mp21 is connected to the source of PMOS transistor Mp11. PMOS transistors Mp11 and Mp21 are connected to their own sources and back gates, respectively. That is, the source and back gate of PMOS transistor Mp21 are connected to the source and back gate of PMOS transistor Mp11. This connection point is called node N3. The drain of PMOS transistor Mp11 is connected to the other end of capacitor CcnH and the gate of PMOS transistor Mp21. This connection point is called node N2.

[0038] A Zener diode ZD-2 is further connected between node N1 and node N3. The Zener diode ZD-2 includes an anode connected to node N1 and a cathode connected to node N3.

[0039] Furthermore, a Zener diode ZD-1 is connected between node N2 and node N3. The Zener diode ZD-1 includes an anode connected to node N2 and a cathode connected to node N3.

[0040] The first buck converter circuit 40-11, configured in this way, operates as a buck converter that reduces the input voltage and outputs it. The first buck converter circuit 40-11 is configured to output control signals that control the operating state of the PMOS transistor from nodes N1 and N2, respectively. The withstand voltage of capacitors Ccn and CcnH is selected considering the voltage input to the first buck converter circuit 40-11.

[0041] The first boost circuit 40-12 has two capacitors Ccp and CcpL, two N-type field-effect transistors, NMOS transistors Mn21 and Mn11, and two Zener diodes ZD-3 and ZD-4. Capacitor Ccp is an example of a third capacitor, and capacitor CcpL is an example of a fourth capacitor. NMOS transistor Mn21 is the 2 This is an example of an N-type FET, and the NMOS transistor Mn11 is an example of a first-type N-FET. Zener diode ZD-3 is an example of a third-type Zener diode, and Zener diode ZD-4 is an example of a fourth-type Zener diode. Capacitor Ccp has one end connected to clock output terminal 42-23. Capacitor CcpL has one end connected to clock output terminal 42-24. The other end of capacitor Ccp is connected to the drain of NMOS transistor Mn21 and the gate of NMOS transistor Mn11. This connection point is referred to as node N4.

[0042] The source of NMOS transistor Mn21 is connected to the source of NMOS transistor Mn11. NMOS transistors Mn21 and Mn11 each have their own source and back gate connected. That is, the source and back gate of NMOS transistor Mn21 are connected to the source and back gate of NMOS transistor Mn11. This connection point is called node N6. The drain of NMOS transistor Mn11 is connected to the other end of capacitor CcpL and the gate of NMOS transistor Mn21. This connection point is called node N5.

[0043] A Zener diode ZD-4 is further connected between node N4 and node N6. Zener diode ZD-4 includes an anode connected to node N6 and a cathode connected to node N4. Additionally, a Zener diode ZD-3 is further connected between node N5 and node N6. Zener diode ZD-3 includes an anode connected to node N6 and a cathode connected to node N5.

[0044] The first boost circuit 40-12, configured in this way, operates as a boost circuit that increases the input voltage and outputs it. The first boost circuit 40-12 is configured to output control signals that control the operating state of the NMOS transistor from nodes N4 and N5, respectively. The withstand voltage of capacitors Ccp and CcpL is selected considering the voltage input to the first boost circuit 40-12.

[0045] Furthermore, the first step-down circuit 40-11 and the first step-up circuit 40-12 are connected at nodes N3 and N6. In addition, nodes N3 and N6 are connected to terminal BB and the connection point between the source of the NMOS transistor Mns11 of the first MOS switch 41-11 and the source of the NMOS transistor Mns21 of the second MOS switch 41-12. Thus, node N3, node N6, terminal BB, the source of the NMOS transistor Mns11, and the source of the NMOS transistor Mns21 form the same node.

[0046] In the first switch 41-1, the first MOS switch 41-11 includes one NMOS transistor Mns11 and one PMOS transistor Mps11. In the first MOS switch 41-11, the NMOS transistor Mns11 and the PMOS transistor Mps11 are connected. Furthermore, the source and back gate of the NMOS transistor Mns11 and the PMOS transistor Mps11 are connected to each other.

[0047] The source of NMOS transistor Mns11 is connected to terminal BB and the back gate of NMOS transistor Mns11. The drain of NMOS transistor Mns11 is connected to the source of PMOS transistor Mps11. The drain of PMOS transistor Mps11 is connected to signal output terminal To1. The gate of NMOS transistor Mns11 is connected to the cathode of Zener diode ZD-3, the drain of NMOS transistor Mn11, the gate of NMOS transistor Mn21, and the other end of capacitor CcpL. The gate of PMOS transistor Mps11 is connected to the anode of Zener diode ZD-1, the drain of PMOS transistor Mp11, the gate of PMOS transistor Mp21, and the other end of capacitor CcnH.

[0048] The non-overlap clock generation circuit 42 is connected to the second clock bootstrap circuit 40-2. The second clock bootstrap circuit 40-2 is connected to the second switch 41-2. More specifically, the second step-down circuit 40-21 is connected to the clock output terminals 42-27 and 42-28. Furthermore, the second step-down circuit 40-21 is connected to the gate of the PMOS transistor Mps12 (the third P-type transfer transistor Mps12) included in the first MOS switch 41-21, and to the gate of the PMOS transistor Mps22 (the fourth P-type transfer transistor Mps22) included in the second MOS switch 41-22. The second boost circuit 40-22 is connected to the clock output terminals 42-25 and 42-26. The second boost circuit 40-22 is also connected to the gate of the NMOS transistor Mns12 (third N-type transfer transistor Mns12) included in the first MOS switch 41-21 and to the gate of the NMOS transistor Mns22 (fourth N-type transfer transistor Mpn22) included in the second MOS switch 41-22.

[0049] The second step-down circuit 40-21 includes two capacitors Ccn and CcnH, two P-type field-effect transistors (FETs) called PMOS transistors Mp12 and Mp22, and two Zener diodes ZD-7 and ZD-8. Capacitor Ccn is an example of the first capacitor, and capacitor CcnH is an example of the second capacitor. PMOS transistor Mp22 is an example of the first P-type FET, and PMOS transistor Mp12 is an example of the second P-type FET. Zener diode ZD-7 is an example of the first Zener diode, and Zener diode ZD-2 is an example of the second Zener diode. Capacitor Ccn has one end connected to clock output terminal 42-28. Capacitor CcnH has one end connected to clock output terminal 42-27. The other end of capacitor Ccn is connected to the drain of PMOS transistor Mp22 and the gate of PMOS transistor Mp12. This connection point is referred to as node N7.

[0050] The source of PMOS transistor Mp22 is connected to the source of PMOS transistor Mp12. PMOS transistors Mp12 and Mp22 are connected to their own sources and back gates, respectively. That is, the source and back gate of PMOS transistor Mp22 are connected to the source and back gate of PMOS transistor Mp12. This connection point is called node N9. The drain of PMOS transistor Mp12 is connected to the other end of capacitor CcnH and the gate of PMOS transistor Mp22. This connection point is called node N8. A Zener diode ZD-8 is further connected between node N7 and node N9. The Zener diode ZD-8 includes an anode connected to node N7 and a cathode connected to node N9.

[0051] Furthermore, a Zener diode ZD-7 is connected between node N8 and node N9. The Zener diode ZD-7 includes an anode connected to node N8 and a cathode connected to node N9.

[0052] The second step-down circuit 40-21, configured in this way, operates as a step-down circuit that steps down the input voltage and outputs it. The second step-down circuit 40-21 is configured to output control signals that control the operating state of the PMOS transistor from nodes N7 and N8, respectively. The withstand voltage of capacitors Ccn and CcnH is selected considering the voltage input to the second step-down circuit 40-21.

[0053] The second boost circuit 40-22 includes two capacitors Ccp and CcpL, two N-type field-effect transistors (NMOS transistors) Mn12 and Mn22, and two Zener diodes ZD-5 and ZD-6. Capacitor Ccp is an example of a third capacitor, and capacitor CcpL is an example of a fourth capacitor. NMOS transistor Mn22 is an example of a first N-type FET, and NMOS transistor Mn12 is an example of a second N-type FET. Zener diode ZD-5 is an example of a third Zener diode, and Zener diode ZD-8 is an example of a fourth Zener diode.

[0054] Capacitor Ccp has one end connected to clock output terminal 42-26. Capacitor CcpL has one end connected to clock output terminal 42-25. The other end of capacitor Ccp is connected to the drain of NMOS transistor Mn22 and the gate of NMOS transistor Mn12. This connection point is referred to as node N10.

[0055] The source of NMOS transistor Mn22 is connected to the source of NMOS transistor Mn12. NMOS transistors Mn12 and Mn22 each have their own source and back gate connected. That is, the source and back gate of NMOS transistor Mn22 are connected to the source and back gate of NMOS transistor Mn12. This connection point is referred to as node N12. The drain of NMOS transistor Mn12 is connected to the other end of capacitor CcpL and the gate of NMOS transistor Mn22. This connection point is referred to as node N11.

[0056] A Zener diode ZD-5 is further connected between node N11 and node N12. The Zener diode ZD-5 includes a cathode connected to node N11 and an anode connected to node N12. Furthermore, a Zener diode ZD-6 is connected between node N10 and node N12. The Zener diode ZD-6 includes a cathode connected to node N10 and an anode connected to node N12.

[0057] The second boost circuit 40-22, configured in this way, operates as a boost circuit that increases the input voltage and outputs it. The second boost circuit 40-22 is configured to output control signals that control the operating state of the NMOS transistor from nodes N10 and N11, respectively. The withstand voltage of capacitors Ccp and CcpL is selected considering the voltage input to the second boost circuit 40-22.

[0058] Furthermore, the second step-down circuit 40-21 and the second step-up circuit 40-22 are connected at nodes N9 and N12. In addition, nodes N9 and N12 are connected to terminal TB and the connection point between the source of the NMOS transistor Mns12 of the first MOS switch 41-21 and the source of the NMOS transistor Mns22 of the second MOS switch 41-22. Thus, node N9, node N12, terminal TB, the source of the NMOS transistor Mns12, and the source of the NMOS transistor Mns22 form the same node.

[0059] In the second switch 41-2, the first MOS switch 41-21 includes one NMOS transistor Mns12 and one PMOS transistor Mps12. In the first MOS switch 41-21, the NMOS transistor Mns12 and the PMOS transistor Mps12 are connected. Furthermore, the source and back gate of the NMOS transistor Mns12 and the PMOS transistor Mps12 are connected to each other, respectively.

[0060] The source of NMOS transistor Mns12 is connected to terminal TB and the back gate of NMOS transistor Mns12. The drain of NMOS transistor Mns12 is connected to the source of PMOS transistor Mps12. The drain of PMOS transistor Mps12 is connected to signal output terminal To2. The gate of NMOS transistor Mns12 is connected to the cathode of Zener diode ZD-5, the drain of NMOS transistor Mn12, the gate of NMOS transistor Mn22, and the other end of capacitor CcpL. The gate of PMOS transistor Mps12 is connected to the anode of Zener diode ZD-7, the drain of PMOS transistor Mp12, the gate of PMOS transistor Mp22, and the other end of capacitor CcnH.

[0061] Figure 4 shows the details of the first switch. As an example, the first MOS switch 41-11 included in the first switch 41-1 will be described. As mentioned above, the first MOS switch 41-11 has an NMOS transistor Mns11 and a PMOS transistor Mps11. Furthermore, the first MOS switch 41-11 has parasitic diodes Diod1 and Diod2. In the first MOS switch 41-11, the NMOS transistor Mns11 and the PMOS transistor Mps11 are connected. The NMOS transistor Mns11 has its source and back gate connected to the anode of the parasitic diode Diod1, and its drain connected to the cathode of the parasitic diode Diod1. The PMOS transistor Mps11 has its source and back gate connected to the cathode of the parasitic diode Diod2, and its drain connected to the anode of the parasitic diode Diod2.

[0062] I will explain the case when the switch is on and the case when the switch is off. When the switch is on, equations (1) and (2) hold true. ΦnH = VBB + vd (1) ΦpL = VBB - vd (2) In equations (1) and (2), vd is the desired voltage, and vd >> |vth| (where vth is the threshold voltage of the MOS transistor (NMOS transistor Mns11, PMOS transistor Mps11)). The NMOS transistor Mns11 and the PMOS transistor Mps11 become conductive and switch on. As a result, Vil = VBB.

[0063] When the switch is off, equation (3) holds true. ΦnH = ΦpL = VBB (3) Therefore, MOS is turned off. Since the state before being turned off was on, it becomes CSS~VBB. After the switch is turned off, Vil becomes VTB. (1) When Vil = VTB < VBB, the PMOS transistor Mps11 is in a non-conducting state and the switch is off. (2) When Vil = VTB > VBB, the parasitic diode Diod2 is forward-biased, and the terminal Vil and CSS are conducting. CSS has a voltage higher than VBB, but the parasitic diode Diod1 is reverse-biased and there is no conduction between VBB and CSS. Since there is no conduction between VBB and Vil, the switch is off.

[0064] Returning to FIG. 3, the operation of the first switch SW1 will be described. The first switch SW1 generates four types of non-overlapping clocks from the clock signal Φcko in the non-overlap clock generation circuit 42. The first switch 41-1 and the second switch 41-2 switch and output the voltages VBB and VTB at both ends of the bus bar 20 to the output terminal Vi1 and the output terminal Vi2. The first clock bootstrap circuit 40-1 boosts or降压 the voltage vd with respect to the voltage VBB of the bus bar 20 to generate gate signals for on / off control of the NMOS transistor Mns11, PMOS transistor Mps11, NMOS transistor Mns21, and PMOS transistor Mps21 included in the first switch 41-1. The second clock bootstrap circuit 40-2 boosts or降压 the voltage vd with respect to the voltage VTB of the bus bar 20 to generate gate signals for on / off control of the NMOS transistor Mns12, PMOS transistor Mps12, NMOS transistor Mns22, and PMOS transistor Mps22 included in the second switch 41-2.

[0065] FIG. 5 is a diagram showing an example of the timing chart of the first switch of the battery system according to the present embodiment. The non-overlap clock generation circuit 42 receives a reference clock signal Φcko from the clock input terminal 42-1. Based on the input clock signal Φcko received from the clock input terminal 42-1, the non-overlap clock generation circuit 42 generates several different clocks, including clock signals Φnck, ΦnckH, Φpck, and ΦpckL. Clock signal ΦnckH is an example of the first clock, clock signal ΦpckL is an example of the second clock, clock signal Φnck is an example of the third clock, and clock signal Φpck is an example of the fourth clock. The clock signals Φnck, ΦnckH, Φpck, and ΦpckL transition between high level (hereinafter referred to as "H level") and low level (hereinafter referred to as "L level") at the timings shown in Figure 5.

[0066] Specifically, clock signals Φnck and ΦnckH are generated at times when they do not reach the H level during the same period. That is, while clock signal Φnck is at the H level, clock signal ΦnckH is at the L level. Clock signals Φpck and ΦpckL are generated at times when they do not reach the L level during the same period. That is, while clock signal Φpck is at the L level, clock signal ΦpckL is at the H level. Furthermore, clock signals Φnck and Φpck are generated at timings where they have opposite polarities. Additionally, clock signals ΦnckH and ΦpckL are generated at timings where they have opposite polarities. The voltage difference between the high level and low level of input clock signals Φcko, Φnck, ΦnckH, Φpck, and ΦpckL is voltage vd.

[0067] The non-overlap clock generation circuit 42 outputs the generated clock signals Φpck, ΦpckL, Φnck, and ΦnckH to clock output terminals 42-21, 42-22, 42-23, and 42-24, respectively. The clock signals Φpck input to clock output terminal 42-21, ΦpckL input to clock output terminal 42-22, Φnck input to clock output terminal 42-23, and ΦnckH input to clock output terminal 42-24 are applied to the gates of the PMOS transistor Mps21 of the second MOS switch 41-12, the PMOS transistor Mps11 of the first MOS switch 41-11, the NMOS transistor Mns21 of the second MOS switch 41-12, and the NMOS transistor Mns11 of the first MOS switch 41-11, respectively.

[0068] In the first step-down circuit 40-11, the voltage VBB at terminal BB is applied to the source and back gate of PMOS transistors Mp21 and Mp11, respectively. PMOS transistors Mp21 and Mp11 operate exclusively according to the input clock signals Φpck and ΦpckL. That is, when PMOS transistor Mp21 is ON, PMOS transistor Mp11 is OFF, and when PMOS transistor Mp11 is ON, PMOS transistor Mp21 is OFF. It is permissible for PMOS transistors Mp21 and Mp11 to be OFF for the same period.

[0069] Through the above operation, the voltages at nodes N1 and N2 are controlled between a voltage VBB, which is the reference voltage, and a voltage lowered from this reference voltage (hereinafter referred to as the "down-adjustment voltage"). That is, the first step-down circuit 40-11 generates a signal based on the voltage VBB and the clock signals Φpck and ΦpckL, setting the reference voltage VBB to a high level and the down-adjustment voltage to a low level. The generated signals are output from nodes N1 and N2, respectively, as control signals to control the on / off states of PMOS transistors Mps21 and Mps11. The signal Φp1 output from node N1 is input to the gate of PMOS transistor Mps21. The signal ΦpL1 output from node N2 is input to the gate of PMOS transistor Mps11.

[0070] In the first boost circuit 40-12, the voltage VBB at terminal BB is applied to the source and back gate of NMOS transistors Mn21 and Mn11, respectively. NMOS transistors Mn21 and Mn11 operate exclusively according to the input clock signals Φnck and ΦnckH. That is, when NMOS transistor Mn21 is ON, NMOS transistor Mn11 is OFF, and when NMOS transistor Mn11 is ON, NMOS transistor Mn21 is OFF. It is permissible for NMOS transistors Mn21 and Mn11 to be OFF for the same period.

[0071] Through the above operation, the voltages at nodes N4 and N5 are controlled between a voltage VBB, which is the reference voltage, and a voltage that is boosted above this reference voltage (hereinafter referred to as the "boost adjustment voltage"). That is, the first boost circuit 40-12 generates a signal based on the voltages of the voltage VBB and the clock signals Φnck and ΦnckH, setting the reference voltage VBB to a low level and the boost adjustment voltage to a high level. The generated signals are output from nodes N4 and N5, respectively, as control signals to control the on / off states of NMOS transistors Mns11 and Mns21. The signal Φn1 output from node N4 is input to the gate of NMOS transistor Mns21. The signal ΦnH1 output from node N5 is input to the gate of NMOS transistor Mns11.

[0072] The first switch 41-1 functions as a switching device that can switch between an on state and an off state based on the signals Φp1, ΦpL1, Φn1, and ΦnH1 input from the first clock bootstrap circuit 40-1. In the on state, the voltage VBB input to terminal BB is output from the signal output terminal To1. On the other hand, in the off state, the voltage VBB input to terminal BB is output from the signal output terminal To1 It is not output.

[0073] The first switch 41-1 conducts between terminal BB and signal output terminal To1 during the period when the clock signal ΦpckL is at a low level and the clock signal ΦnckH is at a high level. The first switch 41-1 conducts between terminal BB and signal output terminal To2 during the period when the clock signal Φpck is at a low level and the clock signal Φnck is at a high level. The state in which terminal BB and signal output terminal To1 or signal output terminal To2 are conductive is the ON state of the first switch 41-1. The first switch 41-1 is OFF during periods other than those described above, specifically, during periods when a voltage equal to the voltage VBB is applied to the gates of the NMOS transistors Mns11 and Mns21 and the PMOS transistors Mps11 and Mps21.

[0074] The non-overlap clock generation circuit 42 outputs the generated clock signals Φpck, ΦpckL, Φnck, and ΦnckH to clock output terminals 42-28, 42-27, 42-26, and 42-25, respectively. The clock signals Φpck input to clock output terminal 42-28, ΦpckL input to clock output terminal 42-27, Φnck input to clock output terminal 42-26, and ΦnckH input to clock output terminal 42-25 are applied to the gates of the PMOS transistor Mps22 of the second MOS switch 41-22, the PMOS transistor Mps12 of the first MOS switch 41-21, the NMOS transistor Mns22 of the second MOS switch 41-22, and the NMOS transistor Mns12 of the first MOS switch 41-21, respectively.

[0075] In the second step-down circuit 40-21, the voltage VTB at terminal TB is applied to the source and back gate of PMOS transistors Mp22 and Mp12, respectively. PMOS transistors Mp22 and Mp12 operate exclusively according to the input clock signals Φpck and ΦpckL. That is, when PMOS transistor Mp22 is ON, PMOS transistor Mp12 is OFF, and when PMOS transistor Mp12 is ON, PMOS transistor Mp22 is OFF. It is permissible for PMOS transistors Mp22 and Mp12 to be OFF for the same period.

[0076] Through the above operation, the voltages at nodes N7 and N8 are controlled between the reference voltage VTB and a voltage lowered from this reference voltage (hereinafter referred to as the "down-adjustment voltage"). That is, the second step-down circuit 40-21 generates a signal that sets the reference voltage VTB to a high level and the down-adjustment voltage to a low level, based on the voltages of the voltage VTB and the clock signals Φpck and ΦpckL. The generated signal is output from nodes N7 and N8, respectively, as a control signal to control the on / off state of the PMOS transistors Mps22 and Mps12. The signal Φp2 output from node N7 is input to the gate of the PMOS transistor Mps22. The signal ΦpL2 output from node N8 is input to the gate of the PMOS transistor Mps12.

[0077] In the second boost circuit 40-22, the voltage VTB at terminal TB is applied to the source and back gate of NMOS transistors Mn22 and Mn12, respectively. NMOS transistors Mn22 and Mn12 operate exclusively according to the input clock signals Φnck and ΦnckH. That is, when NMOS transistor Mn22 is ON, NMOS transistor Mn12 is OFF, and when NMOS transistor Mn12 is ON, NMOS transistor Mn22 is OFF. It is permissible for NMOS transistors Mn22 and Mn12 to be OFF for the same period.

[0078] Through the above operation, the voltages at nodes N10 and N11 are controlled between a voltage VTB, which is the reference voltage, and a voltage that is boosted above this reference voltage (hereinafter referred to as the "boost adjustment voltage"). That is, the second boost circuit 40-22 generates a signal based on the voltage VTB and the clock signals Φnck and ΦnckH, setting the reference voltage VTB to a low level and the boost adjustment voltage to a high level. The generated signals are output from nodes N10 and N11, respectively, as control signals to control the on / off states of NMOS transistors Mns12 and Mns22. The signal Φn2 output from node N10 is input to the gate of NMOS transistor Mns22. The signal ΦnH2 output from node N11 is input to the gate of NMOS transistor Mns12.

[0079] The second switch 41-2 functions as a switching device that can switch between an on state and an off state based on the signals Φp2, ΦpL2, Φn2, and ΦnH2 input from the second clock bootstrap circuit 40-2. In the on state, the voltage VTB input to terminal TB is output from signal output terminal To2. On the other hand, in the off state, the voltage VTB input to terminal TB is not output from signal output terminal T02.

[0080] The second switch 41-2 conducts between terminal TB and signal output terminal To2 during the period when the clock signal ΦpckL is at a low level and the clock signal ΦnckH is at a high level. The second switch 41-2 conducts between terminal TB and signal output terminal To1 during the period when the clock signal Φpck is at a low level and the clock signal Φnck is at a high level. The state in which terminal TB and either signal output terminal To1 or signal output terminal To2 conduct is the ON state of the second switch 41-2. The second switch 41-2 is OFF during periods other than those described above, specifically, during the period when a voltage equal to voltage VTB is applied to the gates of the NMOS transistors Mns12 and Mns22 and the PMOS transistors Mps12 and Mps22.

[0081] As explained above, the battery voltage monitoring device according to this embodiment can be configured so that current does not flow backward even when the switch circuit is off and a voltage difference is applied between the input and output of the switch, and can therefore be built into the battery system. The current flowing through the busbar is in opposite directions during charging and discharging, so the voltages generated across the ends of the busbar are in opposite directions. In other words, the polarity is reversed during charging and discharging. The polarity of the terminal voltages VTB and VBB of the busbar 20 is reversed, but this makes it possible to configure the switch circuit so that current does not flow backward.

[0082] Although embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and design modifications and the like are also included within the scope of the gist of the present invention. For example, we have described a case where the second ADC36-1 of the battery voltage monitoring IC30-1 is manufactured to a higher voltage than the first ADC34-1, but this is not the only example. For example, the second ADC36-1 of the battery voltage monitoring IC may be manufactured to a lower voltage than the first ADC34-1. [Explanation of symbols]

[0083] 1…Battery system, 10-1, 10-2…Battery cell, 20…Busbar, 30-1, 30-2…Battery voltage monitoring IC, 32-1, 32-2…Multiplexer, 34-1, 34-2…First ADC, 36-1, 36-2…Second ADC, 40-1…First clock bootstrap circuit, 40-2…Second clock bootstrap circuit, 40-11…First buck circuit, 40-12…First boost circuit, 40-21…Second buck circuit, 40-22…Second boost circuit, 41-1…First switch, 41-2…Second switch, 41-11, 41-21…First MOS switch, 41-12, 41-22…Second MOS switch, 42…Non-overlap clock generation circuit, 42-1…Clock input terminal, 42-21~42-28…Clock output terminals

Claims

1. A battery voltage monitoring device comprising a signal input section having an input terminal to which the voltages across the busbar are input, and an analog-to-digital conversion circuit that measures the differential voltage of the voltages across the busbar, wherein the device monitors the voltages across the busbar, A clock generation circuit that generates a plurality of clocks based on an input reference clock, including a first clock, a second clock having the opposite polarity to the first clock, a third clock that is at a low level during the period when the first clock is at a high level, and a fourth clock that is at a high level during the period when the second clock is at a low level. A switch circuit comprising: a first N-type transfer transistor and a second N-type transfer transistor, both N-type field-effect transistors with their source and back gate connected; and a first P-type transfer transistor and a second P-type transfer transistor, both P-type field-effect transistors with their source and back gate connected, wherein the drain of one of the first N-type transfer transistors and the first P-type transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to a first signal input terminal, and the drain of the other transfer transistor is connected to a first signal output terminal; and the drain of one of the second N-type transfer transistors and the second P-type transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to the first signal input terminal, and the drain of the other transfer transistor is connected to a second signal output terminal. A first control signal generation circuit is configured to generate a first control signal for controlling the on and off states of the first P-type transfer transistor based on the voltage of the first signal input terminal and the second clock, and a second control signal for controlling the on and off states of the second P-type transfer transistor based on the voltage of the first signal input terminal and the fourth clock, A second control signal generation circuit is configured to generate a third control signal for controlling the on and off states of the first N-type transfer transistor based on the voltage of the first signal input terminal and the first clock, and a fourth control signal for controlling the on and off states of the second N-type transfer transistor based on the voltage of the first signal input terminal and the third clock, A battery voltage monitoring device characterized by comprising the following features.

2. The clock generation circuit includes a clock input terminal into which the reference clock is input, a first clock output terminal that outputs the first clock, a second clock output terminal that outputs the second clock, a third clock output terminal that outputs the third clock, and a fourth clock output terminal that outputs the fourth clock. The first control signal generation circuit includes: a first P-type FET which is a P-type field-effect transistor with its source and back gate connected; a second P-type FET whose source is connected to the source and back gate of the first P-type FET and its own back gate; a first capacitor including one end connected to the fourth clock output terminal and the other end connected to the drain of the second P-type FET and the gate of the first P-type FET; a second capacitor including one end connected to the second clock output terminal and the other end connected to the drain of the first P-type FET and the gate of the second P-type FET; a first Zener diode including an anode connected to the drain of the first P-type FET and a cathode connected to the source and back gate of the second P-type FET; and a second Zener diode including an anode connected to the drain of the second P-type FET and a cathode connected to the source and back gate of the first P-type FET. The second control signal generation circuit includes a first N-type FET, which is an N-type field-effect transistor with its source and back gate connected; a second N-type FET, whose source is connected to the source and back gate of the first N-type FET and its own back gate; a third capacitor, which includes one end connected to the third clock output terminal and the other end connected to the drain of the second N-type FET and the gate of the first N-type FET; a fourth capacitor, which includes one end connected to the first clock output terminal and the other end connected to the drain of the first N-type FET and the gate of the second N-type FET; a third Zener diode, which includes a cathode connected to the drain of the first N-type FET and an anode connected to the source and back gate of the first N-type FET; and a fourth Zener diode, which includes a cathode connected to the drain of the second N-type FET and an anode connected to the source and back gate of the second N-type FET. The connection point between the first signal input terminal and the source of the one transfer transistor is connected to the first node and the second node, The first node is a node to which the source and back gate of the first P-type FET, the source and back gate of the second P-type FET, the cathode of the first Zener diode, and the cathode of the second Zener diode are connected. The battery voltage monitoring device according to claim 1, wherein the second node is the connection point between the source and back gate of the first N-type FET, the source and back gate of the second N-type FET, the anode of the third Zener diode, and the anode of the fourth Zener diode.

3. The first control signal generation circuit has a third node and a fourth node, The second control signal generation circuit has a fifth node and a sixth node, The third node is the connection point between the drain of the first P-type FET of the first control signal generation circuit, the gate of the second P-type FET, the other end of the second capacitor, and the anode of the first Zener diode. The fourth node is the connection point between the drain of the second P-type FET of the first control signal generation circuit, the gate of the first P-type FET, the other end of the first capacitor, and the anode of the second Zener diode. The fifth node is the connection point between the drain of the first N-type FET of the second control signal generation circuit, the gate of the second N-type FET, the other end of the fourth capacitor, and the cathode of the third Zener diode. The sixth node is the connection point between the drain of the second N-type FET of the second control signal generation circuit, the gate of the first N-type FET, the other end of the third capacitor, and the cathode of the fourth Zener diode. The first P-type transfer transistor includes a gate connected to the third node, The second P-type transfer transistor includes a gate connected to the fourth node, The first N-type transfer transistor includes a gate connected to the fifth node, The battery voltage monitoring device according to claim 2, wherein the second N-type transfer transistor includes a gate connected to the sixth node.

4. A third control signal generation circuit having the same configuration as the first control signal generation circuit, which generates a fifth control signal that is the same as the first control signal and a sixth control signal that is the same as the second control signal, The system further comprises a fourth control signal generation circuit having the same configuration as the second control signal generation circuit, and generating a seventh control signal which is in the opposite polarity to the fifth control signal and is at a low level when the fifth control signal is at a high level, and an eighth control signal which is in the opposite polarity to the sixth control signal and is at a low level when the sixth control signal is at a high level. The third control signal generation circuit has a seventh node and an eighth node, The fourth control signal generation circuit has a ninth node and a tenth node, The seventh node is the connection point between the drain of the second P-type FET of the third control signal generation circuit, the gate of the first P-type FET, the other end of the first capacitor, and the anode of the first Zener diode. The eighth node is the connection point between the drain of the first P-type FET of the third control signal generation circuit, the gate of the second P-type FET, the other end of the second capacitor, and the anode of the second Zener diode. The ninth node is the connection point between the drain of the second N-type FET of the fourth control signal generation circuit, the gate of the first N-type FET, the other end of the third capacitor, and the cathode of the third Zener diode. The tenth node is the connection point between the drain of the first N-type FET of the fourth control signal generation circuit, the gate of the second N-type FET, the other end of the fourth capacitor, and the cathode of the fourth Zener diode. The aforementioned signal input section further has a second signal input terminal, The switch circuit further comprises a third N-type transfer transistor and a fourth N-type transfer transistor, the source and back gate of which are connected, and a third P-type transfer transistor and a fourth P-type transfer transistor, the source and back gate of which are connected. Of the third N-type transfer transistor and the third P-type transfer transistor, the drain of one transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to the second signal input terminal, and the drain of the other transfer transistor is connected to the drain of one of the second N-type transfer transistor and the second P-type transfer transistor and to the second signal output terminal. Of the fourth N-type transfer transistor and the fourth P-type transfer transistor, the drain of one transfer transistor is connected to the source of the other transfer transistor, the source of one transfer transistor is connected to the second signal input terminal, and the drain of the other transfer transistor is connected to the drain of one of the first N-type transfer transistor and the first P-type transfer transistor and the first signal output terminal. The third P-type transfer transistor includes a gate connected to the seventh node if the first P-type FET includes a gate connected to the fourth node, and includes a gate connected to the eighth node if the first P-type FET includes a gate connected to the third node. The third N-type transfer transistor includes a gate connected to the seventh node if the first P-type FET includes a gate connected to the third node, and includes a gate connected to the eighth node if the first P-type FET includes a gate connected to the fourth node. The fourth P-type transfer transistor includes a gate connected to the ninth node if the first N-type FET includes a gate connected to the sixth node, and includes a gate connected to the tenth node if the first N-type FET includes a gate connected to the fifth node. The battery voltage monitoring device according to claim 3, wherein the fourth N-type transfer transistor includes a gate connected to the ninth node if the first N-type FET includes a gate connected to the fifth node, and includes a gate connected to the tenth node if the first P-type FET includes a gate connected to the sixth node.

5. The battery voltage monitoring device according to any one of claims 1 to 4, wherein the first control signal generation circuit is configured to generate a first control signal and a second control signal, the first of which includes a first level having the same voltage as the first signal input terminal and a second level having a lower voltage than the first level.

6. The battery voltage monitoring device according to any one of claims 1 to 5, wherein the second control signal generation circuit is configured to generate a third control signal and a fourth control signal, which include a first level having the same voltage as the first signal input terminal and a third level having a higher voltage than the first level.

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