Method for forming a FinFET structure

Abstract

A method for fabricating a FET semiconductor structure includes providing a substrate with at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a dummy gate of the at least one FET. A TiSi2 film having a C54 structure is selectively deposited on a vertical sidewall of a gate spacer between the at least one source / drain contact and the dummy gate, directly on and completely covering the at least one source / drain contact. The dummy gate is replaced with a replacement metal gate.

Description

Technical Field

[0001] Cross - reference to Related Applications This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 179,092, filed on April 23, 2021, which is hereby incorporated by reference in its entirety.

[0002] The present invention generally relates to the field of semiconductors, and more particularly to a method of fabricating FET semiconductor devices.

Background Art

[0003] Advances in semiconductor technology rely on continuous improvements in manufacturing techniques. Innovations in semiconductor technology have led to the introduction of new types of structures such as Fin field - effect transistor (FinFET) devices and stacked structures (e.g., 3D NAND devices). In conventional FinFET process flows, the inventors have recognized that source / drain damage, etch - stop layer residues formed on the source / drain, and thermal budget limitations for forming metal gates can result in poor contacts on the source / drain and uncontrolled variations in the electrical performance of the device. Additionally, in aggressive device scaling at the 5nm and beyond nodes, the inventors have recognized that the low contact resistance requirements using conventional integration methods cannot meet the device performance requirements due to the increasingly diminished contact area.

Summary of the Invention

Means for Solving the Problems

[0004] This disclosure relates to semiconductor devices and a method of manufacturing semiconductor devices.

[0005] Embodiment (1) provides a method for manufacturing an FET semiconductor structure, the method comprising providing a substrate including at least one source / drain contact of at least one FET, the at least one source / drain contact being formed adjacent to a dummy gate of at least one FET. A TiSi2 film having a C54 structure is selectively deposited on the at least one source / drain contact, directly and completely covering the at least one source / drain contact, against the vertical sidewall of the gate spacer between the at least one source / drain contact and the dummy gate. The dummy gate is then replaced with a replacement metal gate.

[0006] Embodiment (2) includes the method of Embodiment (1), wherein the TiSi2 film is selectively deposited before the dummy gate is replaced with a substitution metal gate.

[0007] Embodiment (3) includes the method according to Embodiment (1), wherein selective deposition of the TiSi2 film comprises exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas.

[0008] Embodiment (4) includes the method according to Embodiment (3), wherein the titanium-containing precursor gas includes TiCl4.

[0009] Embodiment (5) includes the method according to Embodiment (3), wherein the silicon-containing precursor gas comprises at least one of SiH4, SiH2Cl2, SiHCl3, and SiCl4.

[0010] Embodiment (6) includes the method according to Embodiment (3), wherein the process gas comprises TiCl4 and SiH4.

[0011] Embodiment (7) includes the method according to Embodiment (3), wherein the process gas further comprises H2 gas.

[0012] Embodiment (8) further includes the method according to Embodiment (3), which further includes maintaining the gas pressure at approximately 1 mTorr to approximately 50 mTorr or approximately 5 mTorr to approximately 20 mTorr, and maintaining the substrate temperature at approximately 700°C to approximately 800°C.

[0013] Embodiment (9) further comprises the method according to Embodiment (1), wherein, after depositing the TiSi2 film, at least one source / drain contact, a dummy gate, a gate spacer, and an etch stop layer are deposited on top of the TiSi2 film.

[0014] Embodiment (10) includes the method of embodiment (9), further comprising depositing a dielectric on an etch stop layer.

[0015] Embodiment (11) further comprises the method of embodiment (1), wherein the cleaning process is used to clean at least one source / drain contact before selectively depositing the TiSi2 film.

[0016] Embodiment (12) includes the method according to Embodiment (11), wherein the cleaning process includes exposing the source / drain contacts to a hot H2 gas for a period of about 10 seconds to about 60 seconds at a substrate temperature of about 600°C to about 800°C at a gas pressure of about 100 mTorr to about 700 mTorr.

[0017] Embodiment (13) includes the method according to Embodiment (11), wherein the cleaning process includes exposing the source / drain contacts to thermal NH3 and HF gases for a period of about 10 seconds to about 60 seconds at a substrate temperature of about 35°C to about 100°C at a gas pressure of about 1 Torr to about 3 Torr.

[0018] Embodiment (14) includes the method according to Embodiment (11), wherein the cleaning process includes exposing the source / drain contacts to thermal NF3 and H2 gas for a period of about 10 seconds to about 60 seconds at a substrate temperature of about 20°C to about 100°C at a gas pressure of about 1 Torr to about 3 Torr.

[0019] Embodiment (15) includes the method of Embodiment (1), wherein no annealing step is performed between the selective deposition step and the replacement step.

[0020] Embodiment (16) further includes the method of Embodiment (1), comprising an annealing step performed between the selective deposition step and the replacement step.

[0021] Embodiment (17) includes an FET semiconductor device comprising a substrate including at least one source / drain contact of at least one FET, wherein the at least one source / drain contact is formed adjacent to the gate of at least one FET and includes an upper portion which is a line of site from the top of the substrate and a lower portion which is a line of site from the bottom of the substrate. A TiSi2 film having a C54 structure conformally covers both the upper and bottom portions of the at least one source / drain contact.

[0022] Embodiment (18) includes the FET described in Embodiment (17), wherein the source / drain contacts include epitaxial Si.

[0023] Embodiment (19) includes the FET described in Embodiment (17), further comprising a gate spacer between at least one source / drain contact and the gate.

[0024] Embodiment (20) includes the FET described in Embodiment (19), wherein the gate spacer contains SiN.

[0025] It should be noted that this “Summary of the Invention” section does not specify all embodiments and / or progressively novel aspects of the disclosure or the claims. Rather, the “Summary of the Invention” provides only a preliminary description of various embodiments and their corresponding novelties to the prior art. For further details and / or anticipated aspects of the disclosure and embodiments, readers should refer to the “Modes for Carrying Out the Invention” section and corresponding drawings of the disclosure, which are discussed further below.

[0026] Aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that various features are not drawn to scale in accordance with standard industry practice. In fact, the dimensions of various features may be enlarged or reduced to clarify the discussion.

Brief Description of the Drawings

[0027] [Figure 1] Shows a comparison of a conventional method for manufacturing a FinFET with a FinFET manufacturing method according to an exemplary embodiment of the present disclosure. [Figure 2] Shows a schematic diagram of a FinFET structure according to an exemplary embodiment of the present disclosure. [Figure 3A-3J] Shows various process steps of a conventional method for manufacturing a FinFET. [Figure 4A-4H] Shows various process steps of a novel method for manufacturing a FinFET according to an exemplary embodiment of the present disclosure. [Figure 5A-5B] Shows a comparison of a conventional FinFET structure with a FinFET structure according to an exemplary embodiment of the present disclosure.

Modes for Carrying Out the Invention

[0028] The following disclosure provides numerous diverse embodiments or examples for realizing various features of the subject matter provided. For the sake of brevity, specific examples of components and arrangements are described below. Naturally, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, or it may include embodiments in which an additional feature is formed between the first and second features so that they are not in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various embodiments. This repetition is for the sake of brevity and clarity and does not in itself refer to the relationships between the various embodiments and / or configurations discussed. Furthermore, for the sake of simplicity, this specification may use spatially relative terms such as “top,” “bottom,” “down,” “below,” “lower,” “above,” and “up” to describe the relationship of one element or feature to another, as shown in the figures. Spatially relative terminology is intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figure. The device may be in other orientations (rotated 90 degrees or otherwise), and spatially relative descriptors used herein may be interpreted accordingly.

[0029] The present invention will be described in terms of various exemplary processes for fabricating FET semiconductor structures on a circuit support substrate. These fabrication processes can be used to fabricate planar FET semiconductor devices, FinFET semiconductor devices, or both types of semiconductor devices on the circuit support substrate.

[0030] Figure 1 shows a comparison of the process flow for a conventional gate-first FinFET manufacturing process 300 with a FinFET manufacturing method 400 according to one embodiment of the present invention. Conventional FinFET manufacturing is represented by steps 3A to 3J and includes the formation of a substituted metal gate (RMG) in step 3D before forming a titanium silicide (TiSi2) film on the source / drain contacts in steps 3G to 3I. The formation of the TiSi2 film is achieved by non-selective physical deposition (PVD) of Ti metal onto epitaxial Si of the source / drain contacts in step 3G, followed by the deposition of a TiN liner on the Ti metal in step 3H, and then annealing in step 3I, which causes the Ti metal to react with Si on the source / drain contacts to form a low-resistance titanium silicide (i.e., TiSi2 having a C54 structure). Ti metal PVD is a line-of-site deposition method, and therefore, Ti metal deposition cannot be used for wrap-around deposition on the source / drain contacts. Additional details related to conventional FinFETs are discussed with reference to Figures 3A to 3J, which are numbered accordingly.

[0031] Conventional FinFET manufacturing methods have several potentially troublesome issues that can lead to poor quality TiSi2 formation, including residual contact etch stop layer (CESL) SiN, damaged epitaxial Si after reactive ion etching (RIE), reduced metal contact area, and partial formation of TiSi2 by thermal annealing due to the thermal budget of the (WF) material.

[0032] In contrast, embodiments of the present disclosure provide a FinFET manufacturing method in which a titanium silicide film is formed on the source / drain contacts followed by the formation of an RMG, as shown in the exemplary process steps 4A–4H of Figure 1. Additional details related to these steps are discussed with reference to correspondingly numbered Figures 4A–4H. The titanium silicide can be deposited as a fully formed TiSi2 film having a C54 structure, thereby making subsequent annealing optional. The titanium silicide can be selectively deposited on the source / drain contacts by exposing the substrate to a process gas containing, for example, a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the process gas may include SiH4 and TiCl4.

[0033] Embodiments of this disclosure provide a one-step wrap-around TiSi2 film formation on source / drain contacts with significantly improved interface quality compared to conventional methods. The TiSi2 film is formed completely with low electrical resistance and does not depend on Si diffusion from the source / drain contacts. This method enables a novel, integrated process flow that eliminates damage to the epitaxial Si source / drain contacts, eliminates the formation of etch-stop layer residue on the source / drain contacts, and reduces source / drain contact resistance.

[0034] Figure 2 schematically shows a FinFET. The FinFET includes a fin 201, an epitaxial Si source / drain (S / D) contact 203 on the fin 201, a gate dielectric 205 on the fin 201, and a metal gate 207 on the gate dielectric 205. Fin cross section A-A' is shown traversing the epitaxial Si source / drain 203 and the fin 201, and gate cross section B-B' is shown along the length of the fin 201. Fin and gate cross sections traversing the FinFET are shown in Figures 3A-3J and 4A-4H, and are described later herein.

[0035] Figures 3A to 3J schematically illustrate a conventional method for forming a FinFET by a gate-first process. Each of Figures 3A to 3J includes an upper gate cross-sectional view, such as B-B' in Figure 2, and a lower fin cross-sectional view, such as A-A' in Figure 2. Unlike the FinFET in Figure 2, the gate cross-sectional views in Figures 3A to 3J show three adjacent gates, and the fin cross-sectional views show two adjacent S / D contacts. Figure 3A shows an S / D contact 301, a gate spacer 303, a dummy gate 305, a contact hole 306, and a fin 307. For example, the S / D contact 301 may contain epitaxial Si, the fin 307 may contain Si, the gate spacer 303 may contain SiN, and / or the dummy gate 305 may contain polySi. The fin cross-sectional views in Figures 3A to 3J show that the S / D contacts 301 are physically connected to each other to form a common S / D for two fin devices, while the S / D contacts 301 may be separated from each other and associated with a single corresponding fin device.

[0036] Figure 3B shows the FinFET after the deposition of a conformal etch stop layer (ESL) 309. As shown, the ESL 309 is deposited on the downward-facing surface of the S / D contact 301, except for an intermediate region that is not exposed to the deposition gas due to the physical connection of the S / D contact 301 to the common S / D as described above. In embodiments including a single S / D contact or adjacent S / D contacts that are physically separated from each other, the ESL 309 is deposited on all downward-facing surfaces exposed to the gaseous environment for depositing the ESL. In one embodiment, the ESL 309 may contain SiN.

[0037] Figure 3C shows the FinFET after blanket deposition of the dielectric layer 311 on the ESL 309, which fills the contact holes 306.

[0038] Figure 3D shows the FinFET after planarization and replacement of the dummy gate 305 with a replacement metal gate (RMG) 313.

[0039] Figure 3E shows the FinFET after anisotropic oxide etching, exposing the ESL 309 within the contact hole 306.

[0040] Figure 3F shows the FinFET after anisotropic nitride etching, exposing the S / D contact 301 within the contact hole 306.

[0041] Figure 3G shows the FinFET after the deposition of Ti metal 315 into the contact hole 306 by PVD, where Ti metal 315 is deposited only on the S / D contact 301 and not on the sidewall.

[0042] Figure 3H shows the FinFET after conformal deposition of the TiN layer 317 into the contact hole 306.

[0043] Figure 3I shows the FinFET after annealing, in which a TiSi 2-layer 319 is formed by the reaction of Ti metal 315 with Si in the epitaxial Si S / D contact 301.

[0044] Figure 3J shows the FinFET after the contact hole 306 has been filled with metal 321.

[0045] Figures 4A to 4H schematically illustrate a method for forming a FinFET by a gate-last process according to one embodiment of the present disclosure. Each of Figures 4A to 4H includes an upper gate cross-sectional view, such as B-B' in Figure 2, and a lower fin cross-sectional view, such as A-A' in Figure 2. Unlike the FinFET in Figure 2, the gate cross-sectional views in Figures 4A to 4J show three adjacent gates, and the fin cross-sectional views show two adjacent S / D contacts. Figure 4A shows an S / D contact 401, a gate spacer 403, a dummy gate 405, a contact hole 406, and a fin 407. For example, the S / D contact 401 may contain epitaxial Si, the fin 407 may contain Si, the gate spacer 403 may contain SiN, and / or the dummy gate 405 may contain polySi. The fin cross-sectional views in Figures 4A to 4H show that the S / D contacts 401 are physically connected to each other to form a common S / D for two fin devices, while the S / D contacts 401 may be separated from each other and associated with a single corresponding fin device.

[0046] The surface of the epitaxial Si S / D contact 401 may be cleaned using a cleaning process to remove any SiO2. A cleaning process that provides good selectivity between SiO2 and the SiN gate spacer 403 may be used. The cleaning process facilitates the subsequent good deposition of the TiSi2 film on the epitaxial Si. In one embodiment, the cleaning process may include exposure to thermal H2 gas at a gas pressure of about 600 mTorr to about 700 mTorr, a substrate temperature of about 700°C to about 800°C, and a period of about 10 seconds to about 30 seconds. In another embodiment, the cleaning process may include exposure to thermal H2 gas at a gas pressure of about 100 mTorr to about 700 mTorr, a substrate temperature of about 600°C to about 800°C, and a period of about 10 seconds to about 60 seconds. In another embodiment, the cleaning process may include exposure to thermal NH3 and HF gases at a gas pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 35°C to about 100°C, and a period of about 10 seconds to about 30 seconds, or alternatively, a period of about 10 seconds to about 60 seconds. In yet another embodiment, the cleaning process may include exposure to thermal NF3 and H2 gases at a gas pressure of about 1 Torr to about 3 Torr, a substrate temperature of about 20°C to about 100°C, and a period of about 10 seconds to about 30 seconds, or alternatively, a period of about 10 seconds to about 60 seconds.

[0047] Figure 4B shows the FinFET after selective deposition of a TiSi2 film 409 having a C54 structure directly onto the S / D contact 401 and completely covering it, against the vertical sidewall of the gate spacer 403 between the S / D contact 401 and the dummy gate 405. Importantly, the TiSi2 film 419 can be deposited as a fully formed TiSi2 film 419 having a C54 structure, thereby making subsequent annealing optional. The TiSi2 film 419 wraps around the S / D contact 401, including the underside which is not a line of site from above the substrate. Selective deposition may involve exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas. For example, the titanium-containing precursor gas may include TiCl4. For example, the silicon-containing precursor gas may include SiH4, SiH2Cl2, SiHCl3, or SiCl4. In one embodiment, the process gas may include SiH4 and TiCl4. The process gas may further contain H2 gas. The gas pressure may be, for example, about 1 mTorr to about 50 mTorr, or about 5 mTorr to about 20 mTorr. The substrate temperature may be, for example, about 700°C to about 800°C.

[0048] Figure 4C shows the FinFET after the deposition of a conformal etch stop layer (ESL) 409. As shown, the ESL 409 is deposited on the downward-facing surface of the S / D contact 401, except for an intermediate region that is not exposed to the deposition gas due to the physical connection of the S / D contact 401 to the common S / D as described above. In embodiments including a single S / D contact or adjacent S / D contacts that are physically separated from each other, the ESL 409 is deposited on all downward-facing surfaces exposed to the gaseous environment for depositing the ESL. In one embodiment, the ESL 409 may contain SiN.

[0049] Figure 4D shows the FinFET after blanket deposition of the dielectric layer 411 that fills the contact holes 406.

[0050] Figure 4E shows the FinFET after the dummy gate 405 has been replaced with a replacement metal gate (RMG) 413. In one embodiment, the replacement may be carried out by planarizing the structure to the ESL 409 using chemical mechanical planarization (CMP), forming a patterned mask that exposes the dummy gate 405, forming a concave feature by removing the dummy gate 405 (e.g., polySi) by a plasma etching process, depositing a conformal high-k dielectric layer (not shown) within the concave feature, partially filling the concave feature with tungsten (W) metal, and filling the remaining portion of the concave feature with SiN.

[0051] Figure 4F shows the FinFET after anisotropic etching, exposing the ESL 409 within the contact hole 406.

[0052] Figure 4G shows the FinFET after anisotropic etching, exposing the TiSi2 film 419 on the S / D contact 401 within the contact hole 406.

[0053] Figure 4H shows the FinFET after the contact holes 406 have been filled with metal 415. As can be seen from the figure, after the TiSi2 film 409 is deposited, the dummy gate 405 is replaced with RMG 414, so that the FinFET has the TiSi2 film 409 deposited around all of the periphery of the S / D contact 401 (except for the peripheral portion that contacts the fin 407). This direct formation of the TiSi2 film 409 on the S / D contact 401 improves interface quality, reduces contact resistance due to the increased contact area, and may alleviate concerns about the thermal budget due to the high thermal stability of the TiSi2 film 409.

[0054] Therefore, it can be understood that the devices and their variations discussed herein can be considered as systems. In one embodiment, the FET semiconductor device comprises a substrate including at least one source / drain contact of at least one FET, wherein the at least one source / drain contact is formed adjacent to the gate of at least one FET, and a TiSi2 film having a C54 structure that is directly present on the at least one source / drain contact and completely covers the at least one source / drain contact, with respect to the vertical sidewall of the gate spacer between the at least one source / drain contact and the gate. An embodiment of such a system is shown in Figure 4H.

[0055] Figure 5A is a schematic diagram of a structure resulting from a conventional FinFET manufacturing method. As shown, the structure includes a remaining contact etch stop layer (CESL) SiN 387 and damaged epitaxial Si 381 after a reactive ion etching (RIE) process. The TiSi2 layer 385 is only partially formed due to the low thermal budget of the (WF) material. Furthermore, the TiSi2 has a reduced metal contact area 383. Figure 5B is a schematic diagram of a structure resulting from a FinFET manufacturing method according to embodiments disclosed herein, where the RMG is formed after a titanium silicide film is formed on the source / drain contacts, as discussed in Figures 4A-4H. As shown, the TiSi2 film 419 is fully formed from the top of the substrate, including the lower 419' which is not line-of-sight. This allows for low electrical resistance and is not dependent on Si diffusion from the source / drain contacts. Furthermore, the disclosed method eliminates damage to the epitaxial Si source / drain contacts, eliminates the formation of etch stop layer residue on the source / drain contacts, and reduces source / drain contact resistance.

[0056] The preceding description has included specific details, such as the particular shape of the processing system and the various components and processes used therein. However, it should be understood that the technology of the present invention may be implemented in other embodiments different from these specific details, and that such details are for illustrative purposes only and do not limit the invention. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes and to ensure a complete understanding, specific numbers, materials, and configurations have been described. Nevertheless, embodiments may be implemented without such specific details. Components having substantially the same functional structure are denoted by similar reference numerals, and therefore any redundant descriptions may be omitted.

[0057] To facilitate understanding of various embodiments, various techniques have been described as multiple separate operations. The order of the descriptions should not be interpreted as suggesting that these operations necessarily depend on the order in which they are performed. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in a different order than in the embodiments described. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0058] As used herein, “substrate” or “wafer” refers collectively to the object processed according to the present invention. A substrate may include any material portion or structure of a device, in particular a semiconductor device or other electronic device, such as a base substrate structure, reticle, or layer on or superimposed on a base substrate structure, such as a thin film. Thus, a substrate is not limited to any particular base structure, underlay or coating layer, whether patterned or not, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to specific types of substrates, but these are for illustrative purposes only.

[0059] Those skilled in the art will also understand that even with many modifications to the operation of the techniques described above, the same objectives of the present invention can still be achieved. Such modifications are intended to be included within the scope of this disclosure. Therefore, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations on embodiments of the present invention are presented in the following claims.

Claims

1. A method for manufacturing an FET semiconductor structure, A step of providing a substrate having at least one source / drain contact of at least one FET, wherein the at least one source / drain contact is formed adjacent to a dummy gate of the at least one FET, A TiSi having a C54 structure is provided on the vertical side wall of the gate spacer between the at least one source / drain contact and the dummy gate, directly on the at least one source / drain contact and completely covering the at least one source / drain contact. ２ A step of selectively depositing a film, The steps include replacing the dummy gate with a replacement metal gate, It has, The TiSi ２ A method comprising the step of selectively depositing a film, wherein the step of exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas, wherein the gas pressure of the process gas is maintained between 1 mTorr and 50 mTorr, and the substrate temperature is maintained between 700°C and 800°C.

2. The TiSi ２ The method according to claim 1, wherein the step of selectively depositing a film is performed before the step of replacing the dummy gate with the substitution metal gate.

3. The titanium-containing precursor gas is TiCl ４ The method according to claim 1, including the method described in claim 1.

4. The silicon-containing precursor gas is SiH ４ , SiH ２ Cl ２ , SiHCl ３ , and SiCl ４ The method according to claim 1, comprising at least one of them.

5. The process gas is TiCl ４ and SiH ４ The method according to claim 1, including the method described in claim 1.

6. The aforementioned process gas is H ２ The method according to claim 1, further comprising a gas.

7. The TiSi ２ After the step of depositing the film, the at least one source / drain contact, the dummy gate, the gate spacer, and the TiSi ２ The method according to claim 1, further comprising the step of depositing an etch-stop layer on the film.

8. The method according to claim 7, further comprising the step of depositing a dielectric on the etch stop layer.

9. The TiSi ２ The method according to claim 1, further comprising the step of cleaning the at least one source / drain contact using a cleaning process before the step of selectively depositing the film.

10. The method according to claim 9, wherein the cleaning process comprises the step of exposing the source / drain contact to a hot H2 gas for a period of time between 10 seconds and 60 seconds, at a gas pressure between 100 mTorr and 700 mTorr and a substrate temperature between 600°C and 800°C.

11. The method according to claim 9, wherein the cleaning process comprises the step of exposing the source / drain contacts to hot NH3 and HF gases for a period of time between 10 seconds and 60 seconds, at a gas pressure between 1 Torr and 3 Torr, and a substrate temperature between 35°C and 100°C.

12. The method according to claim 9, wherein the cleaning process comprises the step of exposing the source / drain contacts to thermal NF3 and H2 gases for a period of time between 10 seconds and 60 seconds, at a gas pressure between 1 Torr and 3 Torr and a substrate temperature between 20°C and 100°C.

13. The method according to claim 1, wherein no annealing step is performed between the selective deposition step and the substitution step.

14. The method according to claim 1, further comprising an annealing step performed between the selective deposition step and the substitution step.

15. A method for manufacturing an FET semiconductor structure, A step of providing a substrate having at least one source / drain contact of at least one FET, wherein the at least one source / drain contact is formed adjacent to a dummy gate of the at least one FET, The steps include selectively depositing a TiSi2 film having a C54 structure onto the vertical sidewall of the gate spacer between the at least one source / drain contact and the dummy gate, so as to directly cover the at least one source / drain contact, and completely cover the at least one source / drain contact. The steps include replacing the dummy gate with a replacement metal gate, Prior to the step of selectively depositing the TiSi2 film, the step of cleaning the at least one source / drain contact using a cleaning process, It has, The cleaning process described above is The step of exposing the source / drain contact to hot H2 gas for a period of time between 10 seconds and 60 seconds, at a gas pressure between 100 mTorr and 700 mTorr, and a substrate temperature between 600°C and 800°C. The steps include exposing the source / drain contacts to thermal NH3 and HF gases for a period of time between 10 seconds and 60 seconds, at a gas pressure between 1 Torr and 3 Torr, and a substrate temperature between 35°C and 100°C, or The step of exposing the source / drain contacts to thermal NF3 and H2 gases for a period of time between 10 seconds and 60 seconds, at a gas pressure between 1 Torr and 3 Torr, and a substrate temperature between 20°C and 100°C. A method having

16. The method according to claim 15, wherein the step of selectively depositing the TiSi2 film comprises the step of exposing the substrate to a process gas containing a titanium-containing precursor gas and a silicon-containing precursor gas.

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