Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device in which the injection of charges from a bit line to a readout transistor and a floating gate at an operation of writing in a memory can be suppressed.SOLUTION: A semiconductor device includes a semiconductor substrate and a first memory cell provided on the semiconductor substrate. The first memory cell includes a first writing and erasing transistor that controls writing and erasing of data, a first readout transistor that controls readout of data, and a first charge transfer suppressing transistor that suppresses the injection of charges to the first writing and erasing transistor and the first readout transistor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, particularly a semiconductor device constituting a single-layer polysilicon type non-volatile memory and a method for manufacturing the same.

Background Art

[0002] As a non-volatile storage device, a non-volatile memory that writes and erases data by changing the charge accumulation state in a floating gate, which is an electrically insulated floating electrode layer constituting a write and erase transistor, is known. As such a non-volatile memory, a single-layer polysilicon type non-volatile memory configured using a single layer of polysilicon is known (for example, Patent Document 1).

[0003] In a single-layer polysilicon type non-volatile memory, for example, a first well region that functions as a write active region, a second well region that functions as a read active region, and a third well region that functions as an erase active region are formed near the surface layer portion of a semiconductor substrate. On the substrate surface, a floating gate composed of a tunnel oxide film and a single layer of polysilicon is formed so as to overlap from the first well region to the third well region. Further, a read transistor is formed on the surface of the second well region.

[0004] In such a non-volatile memory, a plurality of memory cells are arranged, and the write and erase transistors of a pair of adjacent memory cells are formed in a common active region, and each read transistor is formed in a common active region.

[0005] The write active region is connected to a word line WL via a contact. The active region for reading is connected to the bit line BL via a contact. The active region for erasing is connected to the wiring TL via a contact. The gate of the read transistor is connected to the lead wire RL via a contact.

[0006] During data writing, for example, a voltage of 9.5V is applied to the word line WL, and a voltage of 0V is applied to the bit line BL and lead line RL. In addition, 0V is applied to the wiring TL of the cell selected for writing (hereinafter referred to as the "selected cell for writing"), and the writing operation is performed by injecting electrons from the active region to the floating gate in the portion located on the active region for erasing the floating gate due to the potential difference between WL and TL. On the other hand, for cells not selected for writing (hereinafter referred to as the "non-selected cell for writing"), writing is prevented by applying 2.5V to the wiring TL. Furthermore, by applying a voltage of, for example, 3.5V to the source line SL connected to the active region for reading via a contact, electrons generated on the silicon substrate are prevented from injecting electrons from the active region to the floating gate in the formation region of the read transistor. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2019-62065 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] When writing to the selectable cell under the voltage conditions described above, some of the electrons generated in the area where contact is formed with the bit line BL of the read active region due to the potential difference between BL and SL (the BL portion) move and are accelerated in the direction of extension of the source line SL, and electrons are injected into the gate insulating film of the read transistor and floating gate. This caused a problem in which the characteristics of the semiconductor memory would change.

[0009] One possible solution to suppress electron injection into the gate insulating film is to increase its thickness. However, this has drawbacks, such as slower writing speeds and reduced read current. Furthermore, if the voltage applied to the source line SL is reduced, electrons are injected from the substrate into the floating gate via the gate insulating film, making such countermeasures difficult.

[0010] This invention has been made in view of the above-mentioned problems, and aims to provide a semiconductor device that can suppress the injection of charge into the read transistor and the write and erase transistors during a write operation to memory. [Means for solving the problem]

[0011] The semiconductor device according to the present invention comprises a semiconductor substrate and a first memory cell provided on the semiconductor substrate, wherein the first memory cell includes a first write and erase transistor for controlling the writing and erasing of data, a first read transistor for controlling the reading of data, and a first charge transfer suppression transistor for suppressing the injection of charge into the first write and erase transistor and the first read transistor. [Effects of the Invention]

[0012] According to the semiconductor device of the present invention, it is possible to suppress the injection of charge into the read transistor and the write and erase transistors during a write operation to the memory. [Brief explanation of the drawing]

[0013] [Figure 1] This is a top view showing the configuration of the semiconductor memory according to Embodiment 1 of the present invention. [Figure 2] This is a cross-sectional view of the semiconductor memory along line 2-2 in Figure 1. [Figure 3] This is a cross-sectional view of the semiconductor memory along line 3-3 in Figure 1. [Figure 4] This is a cross-sectional view of the semiconductor memory along line 4-4 in Figure 1. [Figure 5] This is a flowchart showing the manufacturing procedure for semiconductor devices. [Figure 6] This diagram shows the positional relationship between the floating gate and the charge transfer suppression gate. [Figure 7] This is a top view showing the configuration of the semiconductor memory according to Embodiment 2 of the present invention. [Figure 8] This diagram shows the arrangement of memory cells in semiconductor memory. [Figure 9] This figure shows an example of voltage application to each memory cell when 0V is applied to the bit line and lead line during data writing and erasure. [Figure 10A] This figure schematically illustrates the injection of electrons into a non-selective cell when the voltage shown in Figure 9 is applied. [Figure 10B] This figure shows the decrease in cell current when adjacent cells are repeatedly written to using the voltage shown in Figure 9 under high-temperature conditions. [Figure 11] This figure shows an example of voltage application to each memory cell when 1.5V is applied to the bit line and lead line during data writing and erasure. [Figure 12A] This figure schematically illustrates how electron injection into non-selective cells is suppressed when the voltage shown in Figure 11 is applied. [Figure 12B] This figure shows the decrease in cell current when adjacent cells are repeatedly written to using the voltage shown in Figure 11 under high-temperature conditions. [Figure 13] This is a top view showing the configuration of a semiconductor memory that does not have a charge transfer suppression transistor.

Best Mode for Carrying Out the Invention

[0014] Preferred embodiments of the present invention will be described in detail below. In the following descriptions of each embodiment and the accompanying drawings, the same reference numerals are assigned to substantially identical or equivalent parts.

Embodiment

[0015] FIG. 1 is a top view of a semiconductor memory 100 according to Embodiment 1 of the present invention as viewed from above the device formation surface. The semiconductor memory 100 is a semiconductor device that constitutes a memory cell of a single-layer polysilicon type non-volatile semiconductor memory. The semiconductor memory 100 has a structure in which a plurality of memory cells are arranged. Here, a pair of first memory cells M1 and second memory cells M2 that are arranged adjacent to each other among the plurality of memory cells constituting the semiconductor memory 100 are shown. Here, the first memory cell M1 is a write selection cell, and the second memory cell M2 is a non-write selection cell. Although not shown in FIG. 1, in the semiconductor memory 100 of the present embodiment, a plurality of similar configurations are further continuously formed in the direction in which the first memory cell M1 and the second memory cell M2 are adjacent. In the following description, among the semiconductor substrates constituting the semiconductor memory 100, the region where the first memory cell M1 indicated by the two-dot chain line in FIG. 1 is formed is referred to as the first memory cell region A1, and the region where the second memory cell M2 is formed is referred to as the second memory cell region A2.

[0016] In the semiconductor substrate constituting the semiconductor memory 100, a first active region 11, a second active region 12, a third active region 13A, and a fourth active region 13B are formed.

[0017] The first active region 11 is formed to extend across the first memory cell region A1 and the second memory cell region A2 in a top view, that is, to extend in the direction in which the first memory cell M1 and the second memory cell M2 are arranged adjacent to each other. The first active region 11 is composed of an N-type well region which is a first conductivity type. The first active region 11 is a writing active region to which a first voltage (e.g., 9.5V) is applied when data is written. Multiple contact CTs made of a conductor such as tungsten are provided on the surface of the first active region 11.

[0018] The second active region 12 is formed to extend across the first memory cell region A1 and the second memory cell region A2 in a top view, that is, to extend in the direction in which the first memory cell M1 and the second memory cell M2 are arranged adjacent to each other. The second active region 12 is composed of a P-type well region, which is a second conductivity type opposite to the first conductivity type. The second active region 12 is an active region for data reading. Multiple contact CTs made of a conductor such as tungsten are provided on the surface of the second active region 12.

[0019] The third active area 13A has a rectangular shape when viewed from above and is provided in two locations within the first memory cell area A1. The third active area 13A is composed of an N-type well area, which is the first conductivity type. The third active area 13A is an active area for data erasure, and its surface is provided with a contact CT made of a conductor such as tungsten.

[0020] The fourth active region 13B has the same shape as the third active region 13A and is provided in two locations in the second memory cell region A2. The fourth active region 13B is composed of an N-type well region which is the first conductivity type. The fourth active region 13B is an active region for data erasure, similar to the third active region 13A, and a contact CT made of a conductor such as tungsten is provided on its surface.

[0021] The first memory cell M1 has a write and erase transistor 21A, a read transistor 22A, and a charge transfer suppression transistor 23A. The second memory cell M2 has a write and erase transistor 21B, a read transistor 22B, and a charge transfer suppression transistor 23B.

[0022] The write and erase transistor 21A is formed in the first memory cell region A1, spanning the first active region 11, the second active region 12, and the third active region 13A. The write and erase transistor 21A is a transistor for writing data and erasing data.

[0023] The write and erase transistor 21A has a floating gate on the surface of the first memory cell region A1. The floating gate is a single-layer conductive layer made of a polysilicon film. The floating gate is positioned to extend across the upper surfaces of the first active region 11, the second active region 12, and the third active region 13A, and to expose a portion of each surface. The floating gate consists of a portion having a rectangular shape in a top view that covers a portion of the surface of the first active region 11 (hereinafter referred to as the write region WC), a portion having a rectangular shape in a top view that covers a portion of the surface of the third active region 13A (hereinafter referred to as the erase region EC), and a strip-shaped portion connecting the write region WC and the erase region EC so as to traverse the surface of the second active region 12 (hereinafter referred to as the strip-shaped region).

[0024] The read transistor 22A is located adjacent to the write and erase transistor 21A in the first memory cell region A1 and is formed traversing the second active region 12 in a direction that intersects with the extension direction of the second active region 12. The read transistor 22A is a transistor for reading data.

[0025] The read transistor 22A has a read gate on the surface of the first memory cell region A1. The read gate is a single-layer conductive layer made of a polysilicon film. The read gate has a rectangular shape, and its longitudinal direction is perpendicular to the stretching direction of the second active region 12 and is positioned to traverse the surface of the second active region 12. The read gate is positioned parallel to the strip-shaped region of the floating gate at a predetermined interval.

[0026] Furthermore, the charge transfer suppression transistor 23A is located adjacent to the read transistor 22A in the first memory cell region A1, and is formed so as to sandwich the read transistor 22A between it and the write and erase transistor 21A. It is also formed to traverse the second active region 12 in a direction intersecting the extension direction of the second active region 12.

[0027] The charge transfer suppression transistor 23A has a charge transfer suppression gate on the surface of the first memory cell region A1. The charge transfer suppression gate, like the read gate, is composed of a single-layer conductive layer made of polysilicon film, has a rectangular shape, and is positioned so that its longitudinal direction is perpendicular to the extension direction of the second active region 12 and crosses the surface of the second active region 12. The charge transfer suppression gate is positioned parallel to the read gate of the read transistor 22A at a predetermined distance.

[0028] The charge transfer suppression transistor 23A is provided to suppress the injection of charge from the second active region 12 into the floating gate strip region of the read transistor 22A and the write and erase transistor 21A during data writing operations to the semiconductor memory 100 (hereinafter simply referred to as "writing operations"). In other words, although the charge transfer suppression gate is similar to the read gate of the read transistor 22A in that it receives voltage during data writing and reading, it is a so-called dummy gate that does not directly participate in the writing, reading, and erasing operations.

[0029] The write and erase transistor 21B is formed in the second memory cell region A2, spanning the first active region 11, the second active region 12, and the fourth active region 13B. The write and erase transistor 21B also has a floating gate on the surface of the second memory cell region A2, having a shape similar to the floating gate of the write and erase transistor 21A. The floating gate of the write and erase transistor 21B is positioned to extend across the upper surfaces of the first active region 11, the second active region 12, and the fourth active region 13B, with a portion of each surface exposed. The first active region 11 contains the write region WC, and the fourth active region 13B contains the erase region EC.

[0030] The read transistor 22B has the same configuration as the read transistor 22A provided in the first memory cell region A1, in the second memory cell region A2. Furthermore, the read transistor 22B has a read gate on the surface of the second memory cell region A2 that has the same configuration and shape as the read gate of the read transistor 22A.

[0031] The charge transfer suppression transistor 23B has the same configuration as the charge transfer suppression transistor 23A provided in the first memory cell region A1, in the second memory cell region A2. Furthermore, the charge transfer suppression transistor 23B has a charge transfer suppression gate on the surface of the second memory cell region A2 that has the same configuration and shape as the charge transfer suppression gate of the charge transfer suppression transistor 23A.

[0032] The first memory cell M1 and the second memory cell M2 are formed symmetrically in the second active region 12 with respect to the boundary between the first memory cell M1 and the second memory cell M2. Specifically, in the second active region 12, the write and erase transistor 21A, the read transistor 22A, the charge transfer suppression transistor 23A, the write and erase transistor 23B, the read transistor 22B, and the charge transfer suppression transistor 23B are formed in the direction of extension of the second active region 12.

[0033] The element mounting surface of the semiconductor memory 100 is provided with word lines WL, lead lines RL1 and RL2, source lines SL, bit lines BL, wiring lines TL1 and TL2, and pseudo-lead lines DL.

[0034] The word line WL is routed along the extension direction of the first active region 11, i.e., in the row direction of the figure. The word line WL is connected to the first active region 11 via contact CT provided in the first active region 11.

[0035] Furthermore, lead wires RL1 and RL2 are routed parallel to the word wire WL in the row direction. Lead wire RL1 is connected via a contact to the read transistor 22A of the first memory cell M1. Lead wire RL2 is connected via a contact to the read transistor 22B of the second memory cell M2.

[0036] Furthermore, the source wire SL is routed on the second active region 12 in its extension direction, i.e., in the row direction. The source wire SL is connected to the second active region 12 via a plurality of contacts.

[0037] The bit line BL is wired on the upper surface of the boundary between the first memory cell M1 and the second memory cell M2. The bit line BL is wired parallel to the direction in which the strip-shaped regions of the floating gates of the write and erase transistors 21A and 21B extend, i.e., in the column direction shown in the figure. The bit line BL is connected to the second active region 12 via a contact. In the following description, the predetermined region of the second active region 12 including the connection portion with the bit line BL will be referred to as the BL section 24. Also, the predetermined region of the second active region 12 including the connection portion with the source line SL will be referred to as the SL sections 25A and 25B.

[0038] The BL section 24 is a first region located at the boundary between the first memory cell region A1 and the second memory cell region A2 of the second active region 12. The SL section 25A is a second region provided in the first memory cell region A1 of the second active region 12, and the SL section 25B is a third region provided in the second memory cell region A2 of the second active region 12. The BL section 24 and the SL section 25A are located opposite each other, straddling the formation positions of the write and erase transistor 21A, the read transistor 22A, and the charge transfer suppression transistor 23A. The BL section 24 and the SL section 25B are also located opposite each other, straddling the formation positions of the write and erase transistor 21B, the read transistor 22B, and the charge transfer suppression transistor 23B.

[0039] Furthermore, wirings TL1 and TL2 are routed parallel to the bit line BL, i.e., in the column direction of the figure. Wiring TL1 is connected via a contact to the third active area 13A of the first memory cell area A1. Wiring TL2 is connected via a contact to the fourth active area 13B of the second memory cell area A2.

[0040] Furthermore, the pseudo-lead wire DL is wired parallel to the lead wires RL1 and RL2, i.e., in the row direction of the figure. The pseudo-lead wire DL is connected via contacts to the charge transfer suppression transistor 23A of the first memory cell M1 and the charge transfer suppression transistor 23B of the second memory cell M2.

[0041] Figure 2 is a cross-sectional view along line 2-2 in Figure 1. Figure 3 is a cross-sectional view along line 3-3 in Figure 1.

[0042] As shown in Figure 2, the semiconductor memory 100 is composed of a first well region 31, a second well region 32, and a third well region 33 formed on the semiconductor substrate 30. In Figures 2, 3, and 4, the portion of the semiconductor substrate 30 constituting the semiconductor memory 100 in which no well regions are formed is shown as the silicon substrate 40.

[0043] The first well area 31 is an N-type well area that constitutes the first active area 11, which is an active area for data writing. The second well area 32 is a P-type well area that constitutes the second active area 12, which is an active area for data reading. The third well area 33 is an N-type well area that constitutes the third active area 13A and the fourth active area 13B, which are active areas for data erasure.

[0044] An element isolation layer (insulating layer) 34 is formed in the region between the surface layers of each well region. The element isolation layer 34 has an STI (Shallow Trench Isolation) structure, which is formed by embedding an oxide film in a groove provided between adjacent well regions.

[0045] A tunnel oxide film (not shown) made of silicon oxide is formed between the surfaces of the first well region 31, the second well region 32, and the third well region 33 and the floating gate of the write and erase transistor 21A, the read gate of the read transistor 22A, and the charge transfer suppression gate of the charge transfer suppression transistor 23A and the charge transfer suppression transistor 23B.

[0046] The write and erase transistor 21A is a conductive layer that constitutes the floating gate of the first memory cell M1. The portion of the first well region 31 covered by the floating gate of the write and erase transistor 21A is a well region that functions as a control gate when writing and erasing data to the first memory cell M1. The portion of the third well region 33 covered by the floating gate of the write and erase transistor 21A is a well region that functions as a tunnel gate when writing and erasing data to the first memory cell M1. The second well region 32 is a well region that functions as a read transistor when reading data from the first memory cell M1.

[0047] An insulating layer 35 is formed on the surface of the semiconductor substrate 30. For example, as shown in Figure 3, the insulating layer 35 is formed to cover the floating gate of the write and erase transistor 21A and the charge transfer suppression gate of the charge transfer suppression transistor 23A, as well as the portion of each well region exposed on the surface of the semiconductor substrate 30.

[0048] Figure 4 is a cross-sectional view along line 4-4 in Figure 1.

[0049] The planar portion of the second well region 32 exposed on the surface of the semiconductor substrate 30 constitutes a second active region 12, which is an active region for data reading. Multiple contact CTs for voltage application are provided on the surface of the second well region 32. On the surface of the second well region 32 in the first memory cell region A1, a strip-shaped region of the floating gate of the write and erase transistor 21A, the read gate of the read transistor 22A, and the charge transfer suppression gate of the charge transfer suppression transistor 23A are provided. In addition, on the surface of the second well region 32 in the second memory cell region A2, a strip-shaped region of the floating gate of the write and erase transistor 21B, the read gate of the read transistor 22B, and the charge transfer suppression gate of the charge transfer suppression transistor 23B are provided.

[0050] Next, the manufacturing method of the semiconductor memory 100 in this embodiment will be explained in accordance with the manufacturing flow shown in Figure 5.

[0051] First, a resist film patterned by photolithography is formed on the surface of a second-conductivity semiconductor substrate, for example, a P-type Si substrate. Then, by ion implantation, a first-conductivity impurity, in this embodiment, an N-type impurity such as P+ (phosphorus) or As+ (arsenic), is implanted onto the surface of the semiconductor substrate. This forms the first well region 31 and the third well region 33, which are N-type well regions (STEP 101).

[0052] Next, a resist film is formed on the first well region 31 and the third well region 33 on the surface of the semiconductor substrate, and a second conductivity type, in this embodiment, P-type impurity is implanted. This forms the second well region 32, which is a P-type well region (STEP 102).

[0053] Next, etching is performed on the surface of the semiconductor substrate on which the first well region 31, the second well region 32, and the third well region 33 are formed to form grooves (STEP 103).

[0054] Next, an insulating film such as SiO2 is formed on the entire surface of the semiconductor substrate, including the grooves, by the CVD (Chemical Vapor Deposition) method. This forms the element isolation layer (STEP 104).

[0055] Next, a silicon oxide film is formed by thermal oxidation to cover the exposed portions of the surfaces of the first well region 31, the second well region 32, and the third well region 33. This forms a tunnel oxide film in those portions (STEP 105).

[0056] Next, a polysilicon film is formed by CVD to cover the surface of the element isolation layer and the tunnel oxide film. This forms the floating gates of the write and erase transistors 21A and 21B, the read gates of the read transistors 22A and 22B, and the charge transfer suppression gates of the charge transfer suppression transistors 23A and 23B (STEP 106).

[0057] Next, a resist film patterned by photolithography is formed on the surface of the wafer that has undergone the above process. Then, by ion implantation, a second conductivity type, in this embodiment, P-type impurity is implanted into the surfaces of the first well region 31 and the third well region 33. This forms a P-type diffusion region consisting of a diffusion layer of the second conductivity type (STEP 107).

[0058] After the above process, the contact CT is formed, and the semiconductor memory 100 of this embodiment is manufactured.

[0059] Next, we will explain the voltage applied to each wire when writing data.

[0060] When writing data to the first memory cell M1, a first voltage (for example, 9.0) is applied to the word line WL. A voltage of 5V is applied, and a second voltage (e.g., 0V) is applied to the wiring TL1 connected to the third active region 13A, which is the erase region EC of the first memory cell M1. Due to this potential difference between WL and TL1, electrons are injected into the floating gate of the write and erase transistor 21A. When erasing data, the opposite of when writing data occurs: a second voltage is applied to the word line WL, and a first voltage is applied to the wiring TL1, causing electrons to move from the floating gate to the second well region 32.

[0061] Furthermore, during data writing, a second voltage is applied to the bit line BL and lead line RL1, and a third voltage (e.g., 3.5V), which is between the first and second voltages, is applied to the source line SL. Then, 0V, which is the same second voltage as the voltage applied to lead line RL, is applied to the pseudo-lead line DL. As a result, 0V is applied to the charge transfer suppression gate of the charge transfer suppression transistor 23A.

[0062] The charge transfer suppression transistor 23A suppresses the injection of charge from the second active region 12 to the read transistor 22A and the write and erase transistor 21A. In other words, the charge transfer suppression transistor 23A in this embodiment plays a role in suppressing the injection of charge to the read transistor 22A and the write and erase transistor 21A.

[0063] If a charge transfer suppression transistor like the present invention were not present, during data writing, electrons would be generated in the BL section 24 due to the potential difference between BL and SL, and these electrons would move along the direction of extension of the source line SL, injecting electrons into the gate insulating film of the read transistor 22A and the write and erase transistor 21A, causing characteristic fluctuations.

[0064] In contrast, in the semiconductor memory 100 of this embodiment, electrons generated in the BL section 24 move to the charge transfer suppression transistor 23A, thereby suppressing the injection of charge into the read transistor 22A and the write and erase transistor 21A in the first memory cell M1. Similarly, in the second memory cell M2, the charge transfer suppression transistor 23B suppresses the injection of electrons generated in the BL section 24 into the read transistor 22B and the write and erase transistor 21B.

[0065] Furthermore, to prevent data from being written to the second memory cell M2, which is a non-write-selected cell, a fourth voltage (e.g., 2.5V), which is the voltage between the first voltage and the second voltage, is applied to the wiring TL2 during data writing.

[0066] Furthermore, in the semiconductor memory 100 of this embodiment, as shown in Figure 6, the distance L2 from the end of the strip portion of the floating gate of the write and erase transistor 21A on the second active region 12 to the end of the charge transfer suppression gate of the charge transfer suppression transistor 23A is shorter than the length L1 of the portion of the floating gate of the write and erase transistor 21A that protrudes from the strip portion of the write region WC. That is, the distance L2 is shorter than the length from the boundary between the rectangular region of the write region WC and the strip portion to the end of the write region WC in the extending direction of the first active region 11. Therefore, charge injection from the second active region 12 to the read transistor 22A and the write and erase transistor 21A can be suppressed without increasing the cell size compared to the case without a charge transfer suppression transistor.

[0067] Note that the placement of charge transfer suppression transistors 23A and 23B is not limited to that shown in Figure 1. Furthermore, additional charge transfer suppression transistors with similar functions may be provided separately from charge transfer suppression transistors 23A and 23B. [Examples]

[0068] Figure 7 is a top view of the semiconductor memory 200 of Embodiment 2, which was made in view of the above points, as seen from above the element formation surface.

[0069] The first memory cell M1 has a charge transfer suppression transistor 26A in addition to the charge transfer suppression transistor 23A. The charge transfer suppression transistor 26A is formed in the first memory cell region A1, as shown in Figure 7, for example, on either side of the write and erase transistor 21A, opposite the read transistor 22A and the charge transfer suppression transistor 23A. It is formed traversing the second active region 12 in a direction intersecting the extension direction of the second active region 12.

[0070] The charge transfer suppression transistor 26A has a charge transfer suppression gate on the surface of the first memory cell region A1, similar to the charge transfer suppression transistor 23A. The charge transfer suppression gate, like the charge transfer suppression gate of the charge transfer suppression transistor 23A, is composed of a single-layer conductive layer made of polysilicon film. The charge transfer suppression gate of the charge transfer suppression transistor 26A has a rectangular shape, and its longitudinal direction is perpendicular to the extension direction of the second active region 12 and is positioned to traverse the surface between the first region 24 and the second region 25A of the second active region 12. In the second active region 12, the charge transfer suppression gate of the charge transfer suppression transistor 26A is positioned parallel to the floating gate of the write and erase transistor 21A at a predetermined distance.

[0071] Furthermore, the charge transfer suppression gate of charge transfer suppression transistor 26A is connected to a pseudo-lead wire DL, similar to the charge transfer suppression gate of charge transfer suppression transistor 23A, and a voltage equivalent to the voltage applied to read transistor 22A is applied during data writing.

[0072] The charge transfer suppression transistor 26A, like the charge transfer suppression transistor 23A, has the function of suppressing the injection of charge from the second active region 12 to the write and erase transistor 21A and the read transistor 22A during data writing.

[0073] Furthermore, since the charge transfer suppression transistor 26A is positioned closer to the SL section 25A than to the BL section 24, for example, when applying voltage in the opposite logic to that described in Embodiment 1 during data writing, such as applying 3.5V to the bit line BL and 0V to the source line SL, electrons generated in the SL section 25A are injected into the charge transfer suppression transistor 26A due to the potential difference between BL and SL. Therefore, compared to the case without the charge transfer suppression transistor 26A, charge injection into the read transistor 22A and the write and erase transistors 21A can be suppressed more effectively regardless of the wiring voltage.

[0074] The second memory cell M2 has a charge transfer suppression transistor 26B in addition to the charge transfer suppression transistor 23B. The charge transfer suppression transistor 26B has the same configuration as the charge transfer suppression transistor 26A in the second memory cell region A2, as shown in Figure 7. The charge transfer suppression transistor 26B also has a charge transfer suppression gate on the surface of the second memory cell region A2 that has the same shape as the charge transfer suppression gate of the charge transfer suppression transistor 26A. The charge transfer suppression gate of the charge transfer suppression transistor 26B is positioned so that its longitudinal direction is perpendicular to the extension direction of the second active region 12 and crosses the surface between the first region 24 and the third region 25B of the second active region 12. The charge transfer suppression gate of the charge transfer suppression transistor 26B is positioned in the second active region 12 parallel to the floating gate of the write and erase transistor 21B at a predetermined interval. The charge transfer suppression transistor 26B has the same function as the charge transfer suppression transistor 26A.

[0075] Since the charge transfer suppression transistor 26B is positioned closer to the SL section 25B than to the BL section 24, electrons generated in the SL section 25B are injected into the charge transfer suppression transistor 26B due to the potential difference between BL and SL, similar to the above. Therefore, the charge transfer suppression transistor 26B, like the charge transfer suppression transistor 26A, can more effectively suppress the injection of charge into the readout transistor 22B and the write and erase transistors 21B, regardless of the wiring voltage.

[0076] As described above, the semiconductor memory 100 of this embodiment makes it possible to suppress the injection of charge into the read transistor and the write and erase transistors during a write operation to the memory.

[0077] Furthermore, as a modification of Example 2, the charge transfer suppression transistor 23A may be omitted, and only the charge transfer suppression transistor 26A may be provided. Since the charge transfer suppression transistor 26A is located closer to the SL section 25A than the BL section 24, for example, when writing data, if 3.5V is applied to the bit line BL and 0V to the source line SL, the potential difference between BL and SL causes electrons generated in the SL section 25A to be injected into the charge transfer suppression transistor 26A. Therefore, the injection of charge into the read transistor 22A and the write and erase transistor 21A in the first memory cell M1 is suppressed. Similarly, in the second memory cell M2, the charge transfer suppression transistor 23B may be omitted, and only the charge transfer suppression transistor 26B may be provided. With this configuration, the injection of electrons generated in the BL section 24 into the read transistor 22B and the write and erase transistor 21B is suppressed.

[0078] It should be noted that the present invention is not limited to those shown in the above embodiments. For example, the top view shapes of the first active region 11, the second active region 12, the third active region 13A, and the fourth active region 13B are not limited to those shown in the above embodiments.

[0079] Furthermore, in the above embodiment, the floating gates of the write and erase transistors 21A and 21B, the read gates of the read transistors 22A and 22B, and the charge transfer suppression gates of the charge transfer suppression transistors 23A and 23B were described as being composed of conductive layers made of polysilicon. However, the invention is not limited to this, and these may be composed of conductive layers made of other conductive materials other than polysilicon.

[0080] Furthermore, the voltage values ​​shown in the above embodiment during data writing are merely examples, and the actual voltage values ​​are not limited to those shown in the above embodiment. That is, it is sufficient that the system is configured such that a second voltage is applied to the read transistor 22A and the charge transfer suppression transistor 23A when a first voltage is applied to the first active region 11, a second voltage is applied to the first region of the second active region 12, and a third voltage is applied to the second region of the second active region 12 during data writing. Also, it is sufficient that the system is configured such that a second voltage is applied to the read transistor 22A and the charge transfer suppression transistor 26A when a first voltage is applied to the first active region 11, a third voltage is applied to the first region of the second active region 12, and a second voltage is applied to the second region of the second active region 12 during data writing.

[0081] [Example of changing the applied voltage] In the above embodiment, as an example of voltage application during data erasure, the case in which 0V (i.e., a second voltage) is applied to the bit line BL and lead line RL1, and a third voltage is applied to the source line SL was described. Since the semiconductor memory in each of the above embodiments is provided with a charge transfer suppression gate, even when such voltages are applied, it is usually possible to suppress the injection of charge into the read transistor and the write and erase transistors.

[0082] However, the inventors discovered that when data is repeatedly written to and erased from a memory cell, charge is injected from the source line into the floating gate of the write and erase transistor. In particular, the charge injection becomes larger when repeated writing and erasing are performed in a high-temperature environment (for example, 85°C).

[0083] To suppress the injection of charge into such floating gates, it is conceivable to apply a predetermined voltage (fourth voltage) that is higher than the third voltage but lower than the first voltage, rather than the third voltage, to the source line SL during data erasure. This will be explained below.

[0084] Figure 8 shows the arrangement of memory cells in the semiconductor memory 100. Multiple memory cells are arranged in a matrix along the respective extension directions of the word line WL and the bit line BL.

[0085] For example, memory cells MC0A, MC1A, MC0B, and MC1B are connected to a common source line SLA and arranged in a single row along the direction of extension of the source line SLA. Also, memory cells MC2A, MC3A, MC2B, and MC3B are connected to a common source line SL and arranged in a single row along the direction of extension of the source line SL. Memory cells MC4A, MC5A, MC4B, and MC5B are connected to a common source line SLB and arranged in a single row along the direction of extension of the source line SLB. Memory cells MC6A, MC7A, MC6B, and MC7B are connected to a common source line SLC and arranged in a single row along the direction of extension of the source line SLC. Memory cells MC0A, MC2A, MC4A, and MC6A are arranged in a single row along the direction of extension of the bit line BL. Memory cells MC1A, MC3A, MC5A, and MC7A are arranged in a single row along the direction of extension of the bit line BL. Memory cells MC0B, MC2B, MC4B, and MC6B are arranged in a single line along the direction of extension of bit line BL2. Memory cells MC1B, MC3B, MC5B, and MC7B are arranged in a single line along the direction of extension of bit line BL2.

[0086] The first memory cell M1 and the second memory cell M2 shown in Figure 1 correspond to memory cells MC2A and MC3A in Figure 8, respectively. Memory cells MC2A and MC3A are connected to a common bit line BL, word line WL, and source line SL. Memory cell MC3B is a complementary cell to memory cell MC3A, connected to the same word line WL, lead line RL2, and source line SL as memory cell MC3A. Memory cell MC5A is connected to the same bit line BL and wiring TL2A as memory cell MC3A.

[0087] Figure 9 shows examples of voltage application to memory cells MC3A, MC3B, MC2A, and MC5A when a second voltage is applied to the bit line BL and lead line RL1, and a third voltage is applied to the source line SL, before the applied voltage is changed, i.e., during data writing and erasing. Here, the selected cells for writing and erasing are memory cells MC3A, MC2A, and MC3B, and the unselected cell not for writing and erasing is memory cell MC5A. Also, the selected cells for reading are memory cells MC3A and MC3B, and the unselected cells not for reading are memory cells MC2A and MC5A.

[0088] Furthermore, the figures show the case where the gate insulating film (oxide film) thickness of the write and erase transistor is approximately 70 Å, and the first voltage, which is the write voltage, is 9.1 V. The second voltage is 0 V, and the third voltage is 4.5 V.

[0089] [During data writing (before changing applied voltage)] 0V is applied to the bit line BL, wiring TL2A, and lead line RL2 connected to memory cell MC3A, which is the selected cell for data writing. 9.1V is applied to the word line WL and 4.5V to the source line SL. 0V is applied to the wiring TL1A and lead line RL1 connected to memory cell MC2A, which is the selected cell. 0V is applied to the bit line BL2 and wiring TL2B connected to memory cell MC3B, which is the selected cell and the complementary cell to memory cell MC3A. The word line WL2 connected to memory cell MC5A, which is not the selected cell, is controlled to an open state, and 4.5V is applied to the source line SLB and 0V to the lead line RLC.

[0090] [During data erasure (before changing applied voltage)] 0V is applied to the bit line BL, word line WL, and lead line RL2 connected to memory cell MC3A, which is the selected cell for data erasure; 9.1V is applied to wiring TL2A; and 4.5V is applied to source line SL. 9.1V is applied to wiring TL1A connected to memory cell MC2A, which is the selected cell; and 0V is applied to lead line RL1. 0V is applied to the bit line BL2 connected to memory cell MC3B, which is the selected cell and complementary cell to memory cell MC3A; and 9.1V is applied to wiring TL2B. 9.1V is applied to the word line WL2, 4.5V to source line SLB, and 0V is applied to lead line RLC connected to memory cell MC5A, which is the non-selected cell.

[0091] [When reading data (before changing applied voltage)] 1.5V is applied to the bit line BL, word line WL, and lead line RL2 connected to memory cell MC3A, which is the selected cell for data reading, while 0V is applied to the wiring TL2A and source line SL. 0V is applied to the wiring TL1A and lead line RL1 connected to memory cell MC2A, which is the unselected cell. 1.5V is applied to the bit line BL2 and 0V to the wiring TL2B connected to memory cell MC3B, which is the selected cell and complementary cell to memory cell MC3A. 1.5V is applied to the word line WL2 connected to memory cell MC5A, which is the unselected cell, the source line SLB is controlled to an open state, and 0V is applied to the lead line RLC.

[0092] When data is repeatedly written and erased by applying such a voltage, electrons are injected from the source line into the floating gate of the write and erase transistors in non-selected cells. Such electron injection causes characteristic variations in semiconductor memory.

[0093] Figure 10A is a simplified diagram showing the circuit configuration and electron injection of memory cell MC5A, which is a non-selected cell when memory cells MC3A, MC2A, and MC3B are selected for data erasure. The applied voltage during data erasure is shown here.

[0094] Due to the large voltage difference between the source line SL (4.5V) and the floating gate FG (9.1V), electrons from the source line SL are injected into the floating gate FG, as indicated by the arrows in the diagram. As a result, the decrease in cell current increases with repeated data writing and erasing. Furthermore, as a high voltage is applied to the source line SL, and the voltage difference between it and the bit line BL and lead line RL increases, the leakage current increases.

[0095] Figure 10B shows the decrease in cell current when repeated writing and erasing is performed in a high-temperature environment (e.g., 85°C). Here, the state before voltage application for data writing and erasing, the state after 10,000 data writing and erasing, the state after 50,000 data writing and erasing, and the state after 100,000 data writing and erasing are compared. As data writing and erasing are repeated, the decrease in cell current due to electron injection from the source line SL to the floating gate FG becomes larger.

[0096] In contrast, by changing the applied voltage as described below, electron injection into the floating gate FG can be suppressed, thereby preventing a decrease in cell current caused by repeated data writing and erasing. Furthermore, an increase in leakage current can be suppressed.

[0097] Figure 11 shows examples of changing the applied voltage for each of the memory cells MC3A, MC3B, MC2A, and MC5A.

[0098] [During data writing (after changing applied voltage)] A voltage of 1.5V is applied to the bit line BL and lead line RL2 connected to memory cell MC3A, which is the selected cell for data writing. Additionally, a voltage of 1.5V is applied to the lead line RL1 connected to memory cell MC2A, which is the selected cell; the lead line RL2 and bit line BL2 connected to memory cell MC3B, which is the selected cell and complementary cell; and the lead line RLC connected to memory cell MC5A, which is the non-selected cell.

[0099] [During data erasure (after changing applied voltage)] 1.5V is applied to the bit line BL and lead line RL2 connected to memory cell MC3A, which is the selected cell for data erasure, and 6V is applied to the source line SL. Additionally, 1.5V is applied to the lead line RL1 connected to memory cell MC2A, which is the selected cell, the lead line RL2 and bit line BL2 connected to memory cell MC3B, which is the selected cell and complementary cell, and the lead line RLC connected to memory cell MC5A, which is the unselected cell. Furthermore, 6V is applied to the source line SLB connected to memory cell MC5A, which is the unselected cell.

[0100] In this way, by setting the voltage applied to the source line to 6V during data erasure and reducing the voltage difference with the word line WL and wiring TL, the injection of electrons from the source line to the floating gate can be suppressed. Furthermore, by increasing the voltage applied to the source line during data erasure and setting the voltage applied to the bit line and lead line to 1.5V, and not increasing the voltage difference with the voltage applied to the source line, the increase in leakage current can be suppressed.

[0101] Figure 12A shows the circuit configuration and applied voltage during data erasure of memory cell MC5A, which is a non-selected cell when memory cells MC3A, MC2A, and MC3B are selected for data erasure.

[0102] In this case, the voltage difference between the source line SL (6V) and the floating gate FG (9.1V) is smaller compared to the case shown in Figure 10A. Therefore, electron injection from the source line SL to the floating gate FG is suppressed. Consequently, the decrease in cell current due to electron injection is suppressed. In addition, the voltage difference between the source line SL (6V) and the bit line BL (1.5V) and lead line RL (1.5V) remains unchanged. Therefore, the increase in leakage current is suppressed.

[0103] Figure 12B shows the decrease in cell current when repeated writing and erasing are performed in a high-temperature environment (e.g., 85°C). Unlike the example shown in Figure 10B, electron injection from the source wire to the floating gate is suppressed, so there is no fluctuation in cell current due to repeated data writing and erasing.

[0104] As described above, for example, if the applied voltage to the word line WL is 9.1V, by setting the applied voltage to the source line SL to 6V and reducing the voltage difference between the applied voltages to the word line WL and wiring TL and the applied voltage to the source line SL, the injection of electrons from the source line SL to the floating gate FG during data erasure can be suppressed. Also, for example, if the applied voltage to the source line SL is 6V, by setting the applied voltage to the bit line BL and lead line RL to 1.5V and not increasing the voltage difference between the source line SL and the bit line BL and lead line RL, the increase in leakage current can be suppressed.

[0105] Therefore, by changing the applied voltage in this way, in addition to suppressing charge injection into the write and erase transistors by the charge transfer suppression gate as in Examples 1 and 2 above, it is also possible to further suppress charge injection into the floating gate in non-selected cells and suppress the increase in leakage current when data writing and erasing are repeatedly performed.

[0106] In the explanation using Figures 11 and 12A, the example was given where the applied voltage to the word line WL and wiring TL is approximately 9.1V, the applied voltage to the source line SL is 6V, and the applied voltage to the bit line BL and lead line RL is 1.5V. However, the specific voltage values ​​are not limited to these. The source line SL should be supplied with a voltage such that the voltage difference between it and the applied voltages to the word line WL and wiring TL is at least 4.5V, preferably 3.1V or less. The bit line BL and lead line RL should be supplied with a voltage approximately 4.5V lower than that of the source line SL. Furthermore, the voltage values ​​of each applied voltage include an error of about 0.1V. In addition, these specific voltage values ​​are based on the assumption that the thickness of the gate insulating film (oxide film) is approximately 70Å. If a gate insulating film of a different thickness is used, the voltage applied to each line will be a different voltage value.

[0107] In other words, when erasing data, a first voltage is applied to the word line WL, a first voltage is applied to the erasure wiring TL, and a fourth voltage is applied to the source line SL that is higher than the third voltage (the voltage between the first and second voltages applied during data writing) and lower than the first voltage. Furthermore, a fifth voltage is applied to the bit line BL and lead line RL when erasing data that is higher than the second voltage and lower than the third voltage.

[0108] Furthermore, the effect of suppressing charge injection into the floating gate by changing the applied voltage can also be obtained in semiconductor memories that are not provided with charge transfer suppression gates, such as those in Examples 1 and 2 described above.

[0109] Figure 13 is a top view showing the configuration of semiconductor memory 100A, which is obtained by removing the charge transfer suppression transistors 23A and 23B from the semiconductor memory 100 shown in Figure 1. In semiconductor memory 100A with this configuration, by applying voltages similar to the above-mentioned voltage change example during erasure, it is possible to suppress the injection of charge from the source line SL of the non-selected cell to the floating gate and to suppress the increase in leakage current. For example, if the second memory cell MC2 is a selected cell and the first memory cell MC1 is a non-selected cell, by applying 9V to the word line WL and wiring TL, 1.5V to the lead lines RL1 and RL2, and 6V to the source line SL during data erasure, it is possible to suppress the injection of charge from the source line SL to the floating gate and to suppress the increase in leakage current.

[0110] Furthermore, the manufacturing method shown in the above examples is just one example, and the manufacturing process may be carried out using a different procedure than described above. [Explanation of symbols]

[0111] 100 Semiconductor memory 200 Semiconductor Memory 11. First Active Region 12. Second Active Area 13A Third Active Area 13B Fourth Active Region 21A Write and erase transistor 21B Write and erase transistor 22A Readout Transistor 22B Readout Transistor 23A Charge Transfer Suppression Transistor 23B Charge Transfer Suppression Transistor 24 BL section, 1st area 25A SL section, 2nd area 25B SL section, 3rd area 26A Charge Transfer Suppression Transistor 26B Charge Transfer Suppression Transistor 31. First well area 32 Second well area 33 Third Well Area 34-element isolation layer 35 Insulating layer

Claims

1. Semiconductor substrate and A first memory cell provided on the semiconductor substrate, A first active region of a first conductivity type is formed on the semiconductor substrate, to which a first voltage is applied when data is written, A second active region of a second conductivity type different from the first conductivity type, having a first region formed on the semiconductor substrate and spaced apart from the first active region, to which a second voltage different from the first voltage is applied when data is written, and a second region to which a third voltage between the first voltage and the second voltage is applied when data is written, A third active region of the first conductivity type is formed on the semiconductor substrate, spaced apart from the second active region, and to which the second voltage is applied when data is written. Equipped with, The first memory cell is A first write and erase transistor that controls the writing and erasing of data, A first readout transistor that controls the reading of data, A first charge transfer suppression transistor that suppresses the injection of charge into the first write and erase transistor and the first read transistor, It has, The first write and erase transistor, the first read transistor, and the first charge transfer suppression transistor are provided in the second active region between the first region and the second region. The first charge transfer suppression transistor is provided between the first region of the second active region and the first readout transistor. A semiconductor device characterized in that the first write and erase transistor is provided between the second region of the second active region and the first read transistor.

2. A bit line extends in a direction intersecting the extension directions of the first active region and the second active region, is connected to the first region via a contact provided in the first region of the second active region, and receives the second voltage when data is written. A source line extends along the extension direction of the second active region, is connected to the second region via a contact provided in the second region of the second active region, and receives the third voltage when data is written. A pseudo-lead wire extends along the extension direction of the second active region, is connected to the first charge transfer suppression transistor via a contact provided on the first charge transfer suppression transistor, and receives the second voltage when data is written. The semiconductor device according to claim 1, characterized by having the following features.

3. The first memory cell further includes a second charge transfer suppression transistor that suppresses the injection of charge into the first write and erase transistor and the first read transistor. The semiconductor device according to claim 1, characterized in that the second charge transfer suppression transistor is provided between the second region of the second active region and the first write and erase transistor.

4. A bit line extends in a direction intersecting the extension directions of the first active region and the second active region, is connected to the first region via a contact provided in the first region of the second active region, and receives the second voltage when data is written. A source line extends along the extension direction of the second active region, is connected to the second region via a contact provided in the second region of the second active region, and receives the third voltage when data is written. A pseudo-lead wire extends along the extension direction of the second active region, is connected to the first charge transfer suppression transistor and the second charge transfer suppression transistor via contacts provided on the first charge transfer suppression transistor and the second charge transfer suppression transistor, and receives the second voltage when data is written. The semiconductor device according to claim 3, characterized by having the following features.

5. The first write and erase transistor has a first floating gate formed extending on the semiconductor substrate across the first active region, the second active region, and the third active region. The first readout transistor has a first readout gate that is spaced apart from the first floating gate and is formed across the second active region in a direction intersecting the extension direction of the second active region. The semiconductor device according to claim 2 or 4, characterized in that the first charge transfer suppression transistor has a first charge transfer suppression gate formed spaced apart from the first read gate and traversing the second active region in a direction intersecting the extension direction of the second active region.

6. The first floating gate has a first rectangular portion positioned on the first active region, a second rectangular portion positioned on the third active region, and a first strip-shaped portion that traverses the second active region and connects the first rectangular portion and the second rectangular portion. The semiconductor device according to claim 5, characterized in that the distance from the first strip-shaped portion of the first floating gate to the end of the first charge transfer suppression gate on the second active region is shorter than the distance from the boundary between the first rectangular portion and the first strip-shaped portion to the end of the first rectangular portion in the extending direction of the first active region.

7. A first active region of a first conductivity type is formed on the semiconductor substrate, to which a first voltage is applied when data is written, A second active region of a second conductivity type different from the first conductivity type is formed on the semiconductor substrate, spaced apart from the first active region, and having a first region to which a third voltage is applied during data writing, which is a voltage between the first voltage and a second voltage different from the first voltage, and a second region to which the second voltage is applied during data writing, A third active region of the first conductivity type is formed on the semiconductor substrate, spaced apart from the second active region, and to which the second voltage is applied when data is written. The semiconductor device according to claim 1, characterized by having the following features.

8. The first write and erase transistor, the first read transistor, and the first charge transfer suppression transistor are provided in the second active region between the first region and the second region. The first charge transfer suppression transistor is provided between the second region of the second active region and the first write and erase transistor. The semiconductor device according to claim 7, characterized in that the first read transistor is provided between the first region of the second active region and the first write and erase transistor.

9. A bit line extends in a direction intersecting the extension directions of the first active region and the second active region, is connected to the first region via a contact provided in the first region of the second active region, and receives the application of the third voltage when data is written. A source line extends along the extension direction of the second active region, is connected to the second region via a contact provided in the second region of the second active region, and receives the second voltage when data is written. A pseudo-lead wire extends along the extension direction of the second active region, is connected to the first charge transfer suppression transistor via a contact provided on the first charge transfer suppression transistor, and receives the second voltage when data is written. The semiconductor device according to claim 8, characterized by having the following features.

10. The first memory cell further includes a second charge transfer suppression transistor that suppresses the injection of charge into the first write and erase transistor and the first read transistor. The semiconductor device according to claim 8, characterized in that the second charge transfer suppression transistor is provided between the first region of the second active region and the first readout transistor.

11. A bit line extends in a direction intersecting the extension directions of the first active region and the second active region, is connected to the first region via a contact provided in the first region of the second active region, and receives the application of the third voltage when data is written. A source line extends along the extension direction of the second active region, is connected to the second region via a contact provided in the second region of the second active region, and receives the second voltage when data is written. A pseudo-lead wire extends along the extension direction of the second active region, is connected to the first charge transfer suppression transistor and the second charge transfer suppression transistor via contacts provided on the first charge transfer suppression transistor and the second charge transfer suppression transistor, and receives the second voltage when data is written. The semiconductor device according to claim 10, characterized by having the following features.

12. The first write and erase transistor has a first floating gate formed extending on the semiconductor substrate across the first active region, the second active region, and the third active region. The first readout transistor has a first readout gate that is spaced apart from the first floating gate and is formed across the second active region in a direction intersecting the extension direction of the second active region. The semiconductor device according to claim 11, wherein the second charge transfer suppression transistor has a second charge transfer suppression gate that is spaced apart from the first readout gate and is formed across the second active region in a direction intersecting the extension direction of the second active region.

13. The first floating gate has a first rectangular portion positioned on the first active region, a second rectangular portion positioned on the third active region, and a first strip-shaped portion that traverses the second active region and connects the first rectangular portion and the second rectangular portion. The semiconductor device according to claim 12, characterized in that the distance from the first strip-shaped portion of the first floating gate to the end of the second charge transfer suppression gate on the second active region is shorter than the distance from the boundary between the first rectangular portion and the first strip-shaped portion to the end of the first rectangular portion in the extending direction of the first active region.

14. A word line extends along the extension direction of the first active region, is connected to the first active region via a contact provided in the first active region, and receives the first voltage when data is written. A first lead wire extends along the extension direction of the second active region, is connected to the first read transistor via a contact provided on the first read transistor, and receives the second voltage when data is written, A semiconductor device according to any one of 1 to 13, characterized by having the following features.

15. The semiconductor substrate is provided with a second memory cell, The second memory cell is A second write and erase transistor controls the writing and erasing of data, A second readout transistor controls the reading of data, A third charge transfer suppression transistor that suppresses the injection of charge into the second write and erase transistor and the second read transistor, A fourth charge transfer suppression transistor that suppresses the injection of charge into the second write and erase transistor and the second read transistor, The semiconductor device according to claim 6 or 13, further comprising the above.

16. The second active region includes a third region that is separated from the first and second regions and to which the third voltage is applied when data is written. The second write and erase transistor, the second read transistor, the third charge transfer suppression transistor, and the fourth charge transfer suppression transistor are provided in the second active region between the first region and the third region. The third charge transfer suppression transistor is provided between the first region of the second active region and the second readout transistor. The fourth charge transfer suppression transistor is provided between the third region of the second active region and the second write and erase transistor. The semiconductor device according to claim 15, characterized in that the second readout transistor is provided between the second write and erase transistor and the third charge transfer suppression transistor.

17. The second lead wire extends along the extension direction of the second active region, is connected to the second read transistor via a contact provided on the second read transistor, and receives the second voltage when data is written, The source line is connected to a contact provided in the third region of the second active region. The semiconductor device according to claim 16, characterized in that the pseudo-lead wire is connected to contacts provided on the third charge transfer suppression transistor and the fourth charge transfer suppression transistor.

18. The semiconductor substrate includes a fourth active region of the first conductivity type, which is formed spaced apart from the second active region and the third active region, and to which the second voltage is applied when data is written. The second write and erase transistor has a second floating gate formed extending on the semiconductor substrate across the first active region, the second active region, and the fourth active region. The second readout transistor has a second readout gate formed across the second active region in a direction intersecting the extension direction of the second active region, The semiconductor device according to any one of 15 to 17, characterized in that the third charge transfer suppression transistor has a third charge transfer suppression gate that is spaced apart from the second read gate and is formed across the second active region in a direction intersecting the extension direction of the second active region.

19. The second floating gate has a third rectangular portion positioned on the first active region, a fourth rectangular portion positioned on the fourth active region, and a second strip-shaped portion that traverses the second active region and connects the third rectangular portion and the fourth rectangular portion. The semiconductor device according to claim 18, characterized in that the distance from the second strip-shaped portion of the second floating gate to the end of the third charge transfer suppression gate on the second active region is shorter than the distance from the boundary between the third rectangular portion and the second strip-shaped portion to the end of the third rectangular portion in the extending direction of the first active region.

20. A first wiring extends in a direction intersecting the extending directions of the first and second active regions, is connected to the third active region via a contact provided in the third active region, and receives the second voltage when data is written. A second wiring extends in a direction intersecting the extending directions of the first and second active regions, is connected to the fourth active region via a contact provided in the fourth active region, and receives a fourth voltage, which is the voltage between the second voltage and the third voltage, when data is written. The semiconductor device according to claim 18 or 19, characterized by having the following features.

21. A first active region of the first conductivity type formed on the semiconductor substrate, A second active region of a second conductivity type different from the first conductivity type is formed at a position separated from the first active region of the semiconductor substrate and has a first region and a second region to which different voltages are applied when data is written, A third active region of the first conductivity type is formed at a position separated from the second active region of the semiconductor substrate, A word line extending in direction 1 on the upper surface of the semiconductor substrate and connected to the first active region, A bit line extending in a direction intersecting the direction of 1 on the upper surface of the semiconductor substrate and connected to the first region of the second active region, A source line extending in the direction of 1 on the upper surface of the semiconductor substrate and connected to the second region of the second active region, A lead wire extending in the direction of 1 on the upper surface of the semiconductor substrate and connected to the first readout transistor, An erase wiring extending in a direction intersecting the direction of 1 on the upper surface of the semiconductor substrate and connected to the third active region, It has, The first write and erase transistor is provided on the upper surface of the semiconductor substrate so as to extend from the upper surface of the first active region to the upper surface of the third active region, straddling the upper surface of the second active region. The first readout transistor is provided on the upper surface of the second active region, A first voltage is applied to the word line when erasing data to the first memory cell. The erasure wiring is subjected to the first voltage when erasing data from the first memory cell. The semiconductor device according to claim 1, characterized in that a third voltage, which is between the first voltage and a second voltage lower than the first voltage, is applied to the source line when writing data to the first memory cell, and a fourth voltage higher than the third voltage and lower than the first voltage is applied when erasing data.

22. The semiconductor device according to claim 21, characterized in that a fifth voltage higher than the second voltage and lower than the third voltage is applied to each of the bit line and the lead line when writing data to the first memory cell and when erasing data.

23. A method for manufacturing a semiconductor device, The steps include forming a first active region by forming a first well of a first conductivity type so as to extend inward from a first region on one surface of a semiconductor substrate, and forming a third active region by forming a third well of the first conductivity type so as to extend inward from a third region separated from the first region on the first surface of the semiconductor substrate, The steps of forming a second active region by forming a second well of a second conductivity type having opposite polarity to the first conductivity type, so as to extend inward from a second region located between the first region and the third region on the first surface of the semiconductor substrate, The steps include forming an isolation layer that extends inward from a region located at the boundary between the second region, the first region and the third region on the first surface of the semiconductor substrate, The steps of forming a first write and erase transistor by forming a first conductor layer that extends on the first surface of the semiconductor substrate, spanning the upper surface of the first region, the upper surface of the second region, and the upper surface of the third region; forming a first read transistor by forming a second conductor layer that traverses the upper surface of the second region in a direction intersecting the extension direction of the second region; and forming a first charge transfer suppression transistor by forming a third conductor layer that is spaced apart from the second conductor layer and traverses the upper surface of the second region in a direction intersecting the extension direction of the second region, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

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