Electronic component embedded circuit board and method for manufacturing the same

Abstract

To provide an electronic component built-in substrate which improves a bond strength of a first substrate and an electronic component, and a manufacturing method thereof.SOLUTION: An electronic component built-in substrate comprises: a first substrate 30; a mount electronic component 50 on the first substrate; a second substrate 10 which is provided at an opposite side of the first substrate while interposing the electronic component therebetween and connected to the first substrate via a substrate connection member 20; and a mold resin 60 filling a gap between the substrates, covering the electronic component and also filling a gap between the electronic component and the first substrate. The first substrate includes a plurality of pads 34q bonded with an electrode 52 of the electronic component via a bonding part 40 and a protective insulation layer 35 including an opening 35x at the side of the electronic component. The plurality of pads includes outermost peripheral pads of an outermost periphery including four corners and an inner pad in a region enclosed by the outermost peripheral pads in a planar view. Among the outermost peripheral pads, outermost peripheral pads disposed in the four corners are exposed into the opening while being isolated from the protective insulation layer. In the inner pad, an outer peripheral part is covered by the protective insulation layer and a portion of a top face is exposed inside of the opening.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a substrate with built-in electronic components and a method for manufacturing the same.

Background Art

[0002] There has been proposed an electronic component built-in substrate including a first substrate, a second substrate facing the first substrate, a substrate connection member interposed between the first substrate and the second substrate for transmitting signals between the first substrate and the second substrate, and a resin filler for sealing the space between the first substrate and the second substrate where the substrate connection member is interposed, and mounting electronic components such as semiconductor chips on the first substrate (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the manufacturing process of the above-described electronic component built-in substrate, after mounting the electronic components on the first substrate, the first substrate and the second substrate are joined via the substrate connection member. When joining the first substrate and the second substrate, since they are heated to a predetermined temperature, thermal stress is applied to the joint between the electronic component and the first substrate, and there is a risk that the joint breaks.

[0005] The present invention has been made in view of the above points, and an object thereof is to provide an electronic component built-in substrate with improved bonding strength between the first substrate and the electronic component.

Means for Solving the Problems

[0006] The electronic component-embedded substrate comprises a first substrate, an electronic component mounted on the first substrate, a second substrate provided on the opposite side of the first substrate from the electronic component and connected to the first substrate via a substrate connecting member, and a sealing resin filled between the first substrate and the second substrate, covering the electronic component and also filled between the electronic component and the first substrate. The first substrate has, on the side of the electronic component, a plurality of pads that are joined to the electrodes of the electronic component via a joint, and a protective insulating layer with openings. The plurality of pads, in a plan view, include outermost pads arranged spaced apart from each other at the outermost periphery including the four corners, and inner pads arranged spaced apart from each other in the region surrounded by the outermost pads. Of the outermost pads, the outermost pads arranged at the four corners are exposed within the openings while separated from the protective insulating layer, and the outer periphery of the inner pads is covered by the protective insulating layer, with a portion of the upper surface exposed within the openings. Furthermore, the area of ​​the upper surface of the outermost pad exposed within the opening while separated from the protective insulating layer is smaller than the area of ​​the upper surface of the inner pad. . [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to provide an electronic component-embedded substrate with improved bonding strength between the first substrate and the electronic component. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view illustrating an electronic component-embedded substrate according to the first embodiment. [Figure 2] Figure 1 is a magnified view of the area near the semiconductor chip. [Figure 3] This is a diagram (part 1) illustrating the manufacturing process of an electronic component-embedded substrate according to the first embodiment. [Figure 4] This is a diagram (part 2) illustrating the manufacturing process of an electronic component-embedded substrate according to the first embodiment. [Figure 5] This is a diagram (part 3) illustrating the manufacturing process of an electronic component-embedded substrate according to the first embodiment. [Figure 6] This is a partially enlarged view of the vicinity of the semiconductor chip in an electronic component-embedded substrate according to Modification 1 of the First Embodiment. [Modes for carrying out the invention]

[0009] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.

[0010] <First Embodiment> [Structure of a circuit board with embedded electronic components] First, the structure of the electronic component-embedded substrate according to the first embodiment will be described. Figure 1 is a cross-sectional view illustrating the electronic component-embedded substrate according to the first embodiment.

[0011] Referring to Figure 1, the electronic component embedded substrate 1 includes a substrate 10, a substrate connecting member 20, a substrate 30, a bonding portion 40, a semiconductor chip 50, and a molding resin 60. In the electronic component embedded substrate 1, the semiconductor chip 50 is mounted on the substrate 30, and the substrate 10 is provided on the opposite side of the substrate 30 from the semiconductor chip 50, with the substrate 10 connected to the substrate 30 via the substrate connecting member 20. The substrate 30 is a typical example of the first substrate according to the present invention, and the substrate 10 is a typical example of the second substrate according to the present invention.

[0012] In this embodiment, for convenience, the solder resist layer 13 side of the electronic component embedded substrate 1 in Figure 1 is referred to as the upper side or one side, and the solder resist layer 37 side as the lower side or the other side. Also, the surface on the solder resist layer 13 side of each part is referred to as one surface or the upper surface, and the surface on the solder resist layer 37 side is referred to as the other surface or the lower surface. However, the electronic component embedded substrate 1 can be used upside down or positioned at any angle. Furthermore, a plan view refers to viewing the object from the direction normal to one surface of the solder resist layer 13, and a planar shape refers to the shape of the object viewed from the direction normal to one surface of the solder resist layer 13. When the electronic component embedded substrate 1 is shown upside down compared to Figure 1, the definitions of the upper and lower surfaces will be reversed to match the display in the drawing.

[0013] The substrate 10 has an insulating layer 11, a wiring layer 12, a solder resist layer 13, a wiring layer 14, and a solder resist layer 15.

[0014] In the substrate 10, the insulating layer 11 can be, for example, a so-called glass epoxy substrate, which is made by impregnating glass cloth with an insulating resin such as epoxy resin. Alternatively, the insulating layer 11 may be a substrate made by impregnating woven or nonwoven fabrics such as glass fibers, carbon fibers, or aramid fibers with an insulating resin such as epoxy resin. The thickness of the insulating layer 11 can be, for example, about 60 to 200 μm. Note that the illustration of glass cloth, etc., is omitted in each figure.

[0015] The wiring layer 12 is formed on one side of the insulating layer 11. The wiring layer 12 is electrically connected to the wiring layer 14 via the insulating layer 11. The wiring layer 12 consists of via wiring filled in via holes 11x that penetrate the insulating layer 11 and expose one side of the wiring layer 14, and a wiring pattern formed on one side of the insulating layer 11.

[0016] The via hole 11x is an inverted frustoconical recess in which the diameter of the opening that opens to the solder resist layer 13 is larger than the diameter of the bottom of the opening formed by the upper surface of the wiring layer 14. The diameter of the via hole 11x can be, for example, about 50 μm. As the material for the wiring layer 12, for example, copper (Cu) can be used. The thickness of the wiring pattern constituting the wiring layer 12 can be, for example, about 10 to 20 μm.

[0017] The solder resist layer 13 is formed on one surface of the insulating layer 11 so as to cover the wiring layer 12. The solder resist layer 13 can be formed of, for example, a photosensitive resin or the like. The thickness of the solder resist layer 13 can be, for example, about 15 to 35 μm. The solder resist layer 13 has an opening 13x, and a part of the wiring layer 12 is exposed in the opening 13x. The wiring layer 12 exposed in the opening 13x constitutes a pad 12p. The pad 12p functions as a pad that is electrically connected to an electronic component (not shown) such as a semiconductor chip or a semiconductor package.

[0018] The solder resist layer 13 may be provided so as to completely expose the pad 12p. In this case, the solder resist layer 13 may be provided such that the side surface of the pad 12p contacts the inner wall surface of the opening 13x, or the solder resist layer 13 may be provided such that a gap is formed between the side surface of the pad 12p and the inner wall surface of the opening 13x.

[0019] If necessary, a metal layer may be formed on one surface of the pad 12p, or an antioxidant treatment such as OSP (Organic Solderability Preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer in which a Ni layer and an Au layer are laminated in this order), a Ni / Pd / Au layer (a metal layer in which a Ni layer, a Pd layer, and an Au layer are laminated in this order), and the like. Further, an external connection terminal such as a solder ball may be formed on one surface of the pad 12p.

[0020] The wiring layer 14 is formed on the other surface of the insulating layer 11. One surface of the wiring layer 14 is in contact with and electrically connected to the lower end portion of the via wiring filled in the via hole 11x of the wiring layer 12. The material and thickness of the wiring layer 14 can be, for example, the same as those of the wiring pattern constituting the wiring layer 12.

[0021] The solder resist layer 15 is formed on the other side of the insulating layer 11 so as to cover the wiring layer 14. The material and thickness of the solder resist layer 15 can be the same as, for example, the solder resist layer 13. The solder resist layer 15 has an opening 15x, and a portion of the wiring layer 14 is exposed within the opening 15x. The wiring layer 14 exposed within the opening 15x constitutes a pad 14p. The pad 14p functions as a pad that is electrically connected to the substrate connection member 20. If necessary, the aforementioned metal layer may be formed on the other side of the pad 14p, or an anti-oxidation treatment such as OSP treatment may be applied.

[0022] The substrate 30 has an insulating layer 31, a wiring layer 32, an insulating layer 33, a wiring layer 34, a solder resist layer 35, a wiring layer 36, and a solder resist layer 37.

[0023] In the substrate 30, the material and thickness of the insulating layer 31 can be the same as, for example, the insulating layer 11. The wiring layer 32 is formed on one side of the insulating layer 31. The material and thickness of the wiring layer 32 can be the same as, for example, the wiring pattern that constitutes the wiring layer 12.

[0024] The insulating layer 33 is formed so as to cover the wiring layer 32 on one side of the insulating layer 31. As the material for the insulating layer 33, for example, an insulating resin such as a thermosetting epoxy resin can be used. The insulating layer 33 may contain fillers such as silica (SiO2). The thickness of the insulating layer 33 can be, for example, about 15 to 35 μm.

[0025] The wiring layer 34 is formed on one side of the insulating layer 33. The wiring layer 34 consists of via wiring filled in via holes 33x that penetrate the insulating layer 33 and expose one side of the wiring layer 32, and a wiring pattern formed on one side of the insulating layer 33.

[0026] The via hole 33x is an inverted truncated cone-shaped recess that opens to the solder resist layer 35 and has its bottom surface formed by one side of the wiring layer 32, with the area of ​​the opening being larger than the area of ​​the bottom surface. The material of the wiring layer 34 and the thickness of the wiring pattern constituting the wiring layer 34 can be the same as, for example, the wiring layer 12.

[0027] The solder resist layer 35 is a protective insulating layer formed on one side of the insulating layer 33 so as to cover the wiring layer 34. The material and thickness of the solder resist layer 35 can be the same as, for example, the solder resist layer 13. The solder resist layer 35 has an opening 35x, in which a portion of the wiring layer 34 is exposed. The wiring layer 34 exposed in the opening 35x constitutes pads 34p and 34q.

[0028] Pad 34p functions as a pad that is joined to the substrate connection member 20. Pad 34q functions as a pad that is joined to the electrode 52 of the semiconductor chip 50 via the joint portion 40. Multiple pads 34q are formed on the semiconductor chip 50 side of the substrate 30. The opening diameters of pad 34p, which is electrically connected to the substrate connection member 20, and pad 34q, which is electrically connected to the semiconductor chip 50, can be set independently. If necessary, the aforementioned metal layer may be formed on one side of pads 34p and 34q, or an anti-oxidation treatment such as OSP treatment may be applied.

[0029] The wiring layer 36 is formed on the other side of the insulating layer 31. The wiring layer 36 comprises via wiring filled in via holes 31x that penetrate the insulating layer 31 and expose the other side of the wiring layer 32, and a wiring pattern formed on the other side of the insulating layer 31.

[0030] The via hole 31x is a frustoconical recess that opens to the solder resist layer 37 and has its bottom surface formed by the other surface of the wiring layer 32, with the area of ​​the opening being larger than the area of ​​the bottom surface. The upper end of the via wiring filled in the via hole 31x of the wiring layer 36 is in contact with the other surface of the wiring layer 32 and is electrically connected. The material of the wiring layer 36 and the thickness of the wiring pattern constituting the wiring layer 36 can be the same as, for example, the wiring layer 12.

[0031] The solder resist layer 37 is formed on the other side of the insulating layer 11 so as to cover the wiring layer 36. The material and thickness of the solder resist layer 37 can be the same as, for example, the solder resist layer 13. The solder resist layer 37 has an opening 37x, and a part of the wiring layer 36 is exposed within the opening 37x. The wiring layer 36 exposed within the opening 37x constitutes a pad 36p. The pad 36p functions as a pad that is electrically connected to a mounting substrate such as a motherboard (not shown). External connection terminals such as solder balls may be formed on the other side of the pad 36p. If necessary, the aforementioned metal layer may be formed on the other side of the pad 36p, or an anti-oxidation treatment such as OSP treatment may be applied.

[0032] A semiconductor chip 50 is flip-chip mounted on one side of the substrate 30 in a face-down state (with the circuit formation surface facing one side of the substrate 30). More specifically, the semiconductor chip 50 has a chip body 51 equipped with a semiconductor integrated circuit and electrodes 52 which are connection terminals, and the electrodes 52 of the semiconductor chip 50 are electrically connected to the pads 34q of the substrate 30 via a junction 40. As the electrodes 52, for example, gold bumps, solder bumps, copper posts with solder at the tip can be used. Similarly, as the junction 40, solder materials such as alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Sb, alloys of Sn and Ag, and alloys of Sn, Ag and Cu can be used. The connection between the substrate 30 and the semiconductor chip 50 will be described in detail separately.

[0033] Furthermore, instead of semiconductor chips, so-called CSPs (chip size packages) with rewiring formed on semiconductor chips may be incorporated or mixed in. In addition, passive elements such as capacitors, inductors, and resistors may also be mixed in.

[0034] The substrate connection member 20 is positioned between the pad 14p of the substrate 10 and the pad 34p of the substrate 30. The substrate connection member 20 electrically connects the substrate 10 and the substrate 30 and also has the function of ensuring a predetermined distance between the substrate 10 and the substrate 30.

[0035] In this embodiment, as an example, a solder ball with a core is used as the substrate connection member 20. The substrate connection member 20 comprises a substantially spherical core 21 and a conductive material 22 covering the outer surface of the core 21, and is arranged so that the core 21 is in contact with the pads 14p and 34p. The diameter of the core 21 before bonding to the substrates 10 and 30 can be, for example, about 100 μm to 300 μm, and is preferably about 200 μm. The overall diameter of the substrate connection member 20, including the conductive material 22 before bonding to the substrates 10 and 30, can be, for example, about 150 μm to 350 μm, and is preferably about 250 μm.

[0036] For the core 21, for example, a metal core made of a metal such as copper or a resin core made of resin can be used. For the conductive material 22, for example, solder materials such as alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Sb, alloys of Sn and Ag, or alloys of Sn, Ag, and Cu can be used. The diameter of the core 21 can be determined considering the height (thickness) of the semiconductor chip 50 and the resin film 55.

[0037] The substrate connection member 20 is not limited to a solder ball with a core, which includes a core 21 and a conductive material 22 covering the outer surface of the core 21. For example, a solder ball without a core may be used. When a solder ball without a core is used, the distance between the substrate 10 and the substrate 30 can be controlled using a predetermined jig during the manufacturing of the electronic component embedded substrate 1. In addition, metal posts such as copper posts or metal bumps such as gold bumps may be used as the substrate connection member 20. If the thickness of the embedded components is thick, metal posts are used for design efficiency. The diameter and height of the metal posts are determined by the thickness of the embedded components. Depending on the mounting method of the metal posts, for example, the ratio of the height (L) to the diameter (D) of the metal posts is preferably around 1.2 to 2.0. For example, when designing the height of the metal posts to be 500 μm, the diameter of the metal posts is preferably around 350 μm.

[0038] In Figure 1, the substrate connection members 20 are shown in a simplified manner; however, in reality, multiple rows of substrate connection members 20 are arranged, for example, in a peripheral configuration. When substrates 10 and 30 are rectangular in plan view, the substrate connection members 20 are provided around the periphery of the substrates, for example, in a peripheral configuration. For example, if the diameter of the substrate connection members 20 is approximately 150 μm, the pitch of the substrate connection members 20 can be approximately 200 μm.

[0039] The molding resin 60 is a sealing resin that is filled between the opposing surfaces of the substrate 10 and the substrate 30, and covers the substrate connecting member 20 and the semiconductor chip 50. The molding resin 60 covers the semiconductor chip 50 and is also filled between the semiconductor chip 50 and the substrate 30, covering the joint 40 and the electrode 52. As the molding resin 60, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used.

[0040] Here, we will explain in detail the connection between the substrate 30 and the semiconductor chip 50. Figure 2 is a magnified view of the area near the semiconductor chip in Figure 1, where Figure 2(a) is a cross-sectional view (cross-section AA in Figure 2(b)) and Figure 2(b) is a plan view. However, only the parts necessary for explanation are shown in Figure 2.

[0041] As shown in Figure 2(b), on the substrate 30, the multiple pads 34q connected to the semiconductor chip 50 are arranged in an area array in a substantially rectangular region. Specifically, the multiple pads 34q include outermost pads arranged spaced apart from each other at the outermost periphery, including the four corners, and inner pads arranged spaced apart from each other in the region surrounded by the outermost pads.

[0042] In the example shown in Figure 2(b), a total of 16 pads 34q are arranged in a 4x4 grid at approximately equal intervals. In this case, the 12 pads 34q on the outermost periphery are the outermost pads, and the 4 inner pads 34q are the inner pads. However, Figure 2(b) is just one example, and the number and arrangement of the pads 34q are determined appropriately according to the specifications of the semiconductor chip to which they are mounted. Furthermore, the arrangement of the pads 34q is not limited to an area array; for example, they may be arranged in a peripheral manner in multiple columns.

[0043] In this embodiment, among the outermost pads included in the multiple pads 34q, the outermost pads located at the four corners have an NSMD (Non Solder Mask Defined) structure. That is, the outermost pads located at the four corners are exposed within the opening 35x while separated from the solder resist layer 35. In other words, a gap is formed between the sides of the outermost pads located at the four corners and the inner wall surface of the opening 35x in the solder resist layer 35, and the two are not in contact.

[0044] In contrast, all inner pads included in the multiple pads 34q are of the SMD (Solder Mask Defined) structure. That is, the outer periphery of the inner pad is covered with a solder resist layer 35, and a portion of the upper surface is exposed within the opening 35x. Of the outermost pads included in the multiple pads 34q, the outermost pads located at locations other than the four corners may be of either an NSMD or SMD structure, but in this embodiment, an SMD structure is used as an example.

[0045] As shown in Figure 2(a), the width of the joint 40 joined to the SMD structured pad 34q is narrower than the width of the joint 40 joined to the NSMD structured pad 34q. Therefore, the SMD structured pad 34q is less prone to short circuits between adjacent joints 40 and is suitable for fine pitch applications. However, because the outer periphery of the SMD structured pad 34q is covered with a solder resist layer 35, the upper surface area of ​​the pad 34q needs to be larger than that of the NSMD structured pad 34q in order to secure the upper surface area of ​​the pad 34q exposed from the opening 35x. In other words, the upper surface area of ​​the NSMD structured pad 34q that is fully exposed from the opening 35x can be smaller than that of the SMD structured pad 34q.

[0046] Furthermore, as shown in Figure 2(a), the NSMD structure pad 34q is joined to the joint 40 on both its top and side surfaces. Therefore, the joint strength between the pad 34q and the joint 40 can be increased compared to the SMD structure where only the top surface of the pad 34q is joined to the joint 40.

[0047] Incidentally, although the details will be described later, thermal stress is applied to the connection between the pad 34q and the joint 40 during the process of joining the substrate 10 and the substrate 30. In particular, significant thermal stress is applied to the connection between the pad 34q and the joint 40 at the four corners, which may cause the joint 40 to fracture. Here, fracture refers to, for example, the occurrence of cracks in the joint 40 or the delamination of the pad 34q and the joint 40.

[0048] Therefore, in this embodiment, the pads 34q at the four corners are made of an NSMD structure, and the other pads 34q are made of an SMD structure, thereby retaining the advantages of the SMD structure pads 34q while increasing the bonding strength between the four NSMD corner pads 34q and the joint 40. As a result, fracture of the joint 40 joined to the four corner pads 34q is suppressed, and the reliability of the connection between the substrate 30 and the semiconductor chip 50 can be improved.

[0049] In this way, by making the pad 34q, which is placed in a position prone to thermal stress, an NSMD structure, it is possible to realize an electronic component embedded substrate 1 with improved bonding strength between the substrate 30 and the semiconductor chip 50.

[0050] [Manufacturing method for circuit boards with embedded electronic components] Next, a method for manufacturing an electronic component-embedded substrate according to the first embodiment will be described. Figures 3 to 5 illustrate the manufacturing process of an electronic component-embedded substrate according to the first embodiment.

[0051] First, in the process shown in Figure 3(a), a substrate 10 is fabricated, and a substrate connection member 20 is mounted on the pads 14p of the substrate 10. Specifically, an insulating layer 11 is prepared using a so-called glass epoxy substrate as described above, and a wiring layer 14 is formed on the other side of the insulating layer 11. Next, via holes 11x are formed in the insulating layer 11 to expose one side of the wiring layer 14, and then a wiring layer 12 is formed on the other side of the insulating layer 11. The wiring layer 12 and the wiring layer 14 are electrically connected via the insulating layer 11.

[0052] After forming the via holes 11x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surface of the wiring layer 14 exposed at the bottom of the via holes 11x. The via holes 11x can be formed by a laser processing method, for example, using a CO2 laser. The wiring layers 12 and 14 can be formed using various wiring formation methods, such as the semi-additive method or the subtractive method. For example, the wiring layers 12 and 14 can be formed by copper plating.

[0053] Next, a solder resist layer 13 is formed on one side of the insulating layer 11 to cover the wiring layer 12, and a solder resist layer 15 is formed on the other side of the insulating layer 11 to cover the wiring layer 14. The solder resist layer 13 can be formed, for example, by applying an insulating resin such as a liquid or paste-like photosensitive epoxy resin to one side of the insulating layer 11 using a screen printing method, roll coating method, or spin coating method so as to cover the wiring layer 12.

[0054] Similarly, the solder resist layer 15 can be formed by applying an insulating resin, such as a liquid or paste-like photosensitive epoxy resin, to the other surface of the insulating layer 11 in a similar manner so as to cover the wiring layer 14. Alternatively, instead of applying a liquid or paste-like resin, an insulating resin, such as a film-like photosensitive epoxy resin, may be laminated.

[0055] Then, by exposing and developing the coated or laminated insulating resin, openings 13x and 15x are formed in the solder resist layers 13 and 15, and pads 12p and 14p are formed (photolithography method). This completes the substrate 10. The openings 13x and 15x may also be formed by laser processing or blasting. The planar shape of each of the openings 13x and 15x can be, for example, circular. The diameter of each of the openings 13x and 15x can be arbitrarily designed to suit the connection target.

[0056] Next, the substrate connection member 20 is placed on the pad 14p exposed within the opening 15x of the solder resist layer 15 of the substrate 10. Then, it is heated to a predetermined temperature to melt the conductive material 22 constituting the substrate connection member 20, and then hardened to bond it with the pad 14p. A portion of the core 21 constituting the substrate connection member 20 is in contact with the pad 14p. The substrate connection member 20 is arranged, for example, in a peripheral configuration.

[0057] Next, in the process shown in Figure 3(b), a substrate 30 is prepared having a pad 34p, a plurality of pads 34q, and a solder resist layer 35 having openings 35x that expose at least a portion of the pads 34p and each pad 34q. Specifically, an insulating layer 31 using a so-called glass epoxy substrate as described above is prepared, and a wiring layer 32 is formed on one side of the insulating layer 31. Next, via holes 31x are formed in the insulating layer 31 that expose the other side of the wiring layer 32, and then a wiring layer 36 is formed on the other side of the insulating layer 31. The wiring layer 32 and the wiring layer 36 are electrically connected via the insulating layer 31.

[0058] After forming the via holes 31x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 31x. The via holes 31x can be formed, for example, by a laser processing method using a CO2 laser. The wiring layers 32 and 36 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.

[0059] Next, an insulating resin film, such as a thermosetting epoxy resin, is laminated to one side of the insulating layer 31 so as to cover the wiring layer 32, thereby forming an insulating layer 33. Alternatively, instead of laminating with an insulating resin film such as a thermosetting epoxy resin, a liquid or paste-like insulating resin, such as a thermosetting epoxy resin, may be applied and then cured to form the insulating layer 33.

[0060] Next, via holes 33x are formed in the insulating layer 33, penetrating the insulating layer 33 and exposing one side of the wiring layer 32. The via holes 33x can be formed, for example, by a laser processing method using a CO2 laser. After forming the via holes 33x, it is preferable to perform a desmear treatment to remove any resin residue adhering to the surface of the wiring layer 32 exposed at the bottom of the via holes 33x.

[0061] Next, a wiring layer 34 is formed on one side of the insulating layer 33. The wiring layer 34 consists of via wiring filled in via holes 33x and a wiring pattern formed on one side of the insulating layer 33. The wiring layer 34 is electrically connected to the wiring layer 32 exposed at the bottom of the via holes 33x. The wiring layer 34 can be formed using various wiring formation methods such as the semi-additive method or the subtractive method.

[0062] Next, a solder resist layer 35 is formed on one side of the insulating layer 33 to cover the wiring layer 34, and a solder resist layer 37 is formed on the other side of the insulating layer 31 to cover the wiring layer 36, similar to the solder resist layer 13 of the substrate 10. Then, openings 35x and 37x are formed in the solder resist layers 35 and 37, similar to the openings 13x of the substrate 10, to form pads 34p and 36p (photolithography). This completes the substrate 30.

[0063] Next, in the process shown in Figure 3(c), the semiconductor chip 50 is mounted on the substrate 30 such that the electrodes 52 of the semiconductor chip 50 are joined to the pads 34q via the joint 40. Specifically, first, the joint 40 is formed on the pads 34q of the substrate 30. For example, the joint 40 is formed by applying a paste-like solder material to the pads 34q. Then, a semiconductor chip 50 is prepared with electrodes 52 formed on the circuit formation side of the chip body 51 equipped with a semiconductor integrated circuit, and for example, the back surface of the semiconductor chip 50 is mounted on the bottom surface of a pickup jig. Then, the pickup jig with the semiconductor chip 50 mounted on its bottom surface is moved to the top of the substrate 30, the electrodes 52 of the semiconductor chip 50 and the joint 40 are aligned, and the semiconductor chip 50 is placed on the substrate 30. After removing the pickup jig from the semiconductor chip 50, the joint 40 is heated and melted by reflow or the like, and then solidified. As a result, the electrodes 52 of the semiconductor chip 50 are electrically connected to the pads 34q of the substrate 30 via the joint 40.

[0064] Next, in the process shown in Figures 4(a) to 5(a), the substrate 10 is stacked on the substrate 30 with the semiconductor chip 50 sandwiched in between so that the substrate connection member 20 is positioned corresponding to the pad 34p, and the substrate 10 and the substrate 30 are electrically connected via the substrate connection member 20. Specifically, first, as shown in Figure 4(a), the substrate 30 with the semiconductor chip 50 mounted on it is placed on the first mold 510 which has a built-in heater. Next, as shown in Figure 4(b), the substrate 10 with the substrate connection member 20 mounted on it is placed on the second mold 520 which has a built-in heater, and then it is inverted upside down and aligned with the substrate 30 placed on the first mold 510.

[0065] Next, as shown in Figure 5(a), the substrate 10 and the substrate 30 are joined by the TCB (Thermal Compression Bonding) method. First, the distance between the first mold 510 and the second mold 520 is adjusted to hold the laminate of substrate 10 and substrate 30 between the first mold 510 and the second mold 520, and the substrate 10 is pressed towards the substrate 30 with a predetermined pressure to pressurize the laminate. Then, with the laminate pressed, the first mold 510 and the second mold 520 are heated with heaters. As a result, heat from the first mold 510 is transferred to the substrate connecting member 20 via the substrate 10, and heat from the second mold 520 is transferred to the substrate connecting member 20 via the substrate 30, causing the conductive material 22 of the substrate connecting member 20 to melt. The heating temperature by the heaters does not need to be higher than the temperature at which the conductive material 22 melts, for example, it can be around 250°C.

[0066] Subsequently, as the conductive material 22 solidifies, the upper side of the core 21 constituting the substrate connecting member 20 is joined to the pad 14p of the substrate 10, and the lower side is joined to the pad 34p of the substrate 30. In other words, the substrate 10 and the substrate 30 are electrically connected via the substrate connecting member 20. Furthermore, the core 21 of the substrate connecting member 20 ensures a predetermined distance between the substrate 10 and the substrate 30. In this process, the first mold 510 and the second mold 520 pressurize the substrate 10 toward the substrate 30, so even if the substrate 10 and the substrate 30 expand due to heating, it is possible to suppress a shift in the distance between the substrate 10 and the substrate 30. As a result, the two can be joined with the distance between the substrate 10 and the substrate 30 set to a desired value determined by the core 21.

[0067] Next, in the step shown in Figure 5(b), molding resin 60 is filled between the substrate 10 and the substrate 30 to seal the substrate connection member 20 and the semiconductor chip 50. The molding resin 60 covers the semiconductor chip 50 and is also filled between the semiconductor chip 50 and the substrate 30, covering the joint 40 and the electrode 52. As the molding resin 60, for example, an insulating resin such as a thermosetting epoxy resin containing a filler can be used. The molding resin 60 can be formed, for example, by a transfer molding method using a sealing mold.

[0068] In this way, by filling the space between the semiconductor chip 50 and the substrate 30 with mold resin 60, it is not necessary to provide a separate process to fill the space between the semiconductor chip 50 and the substrate 30 with underfill resin, thus simplifying the manufacturing process of the electronic component embedded substrate 1.

[0069] The electronic component-embedded circuit board 1 is completed through the above steps. If necessary, external connection terminals such as solder balls may be formed on pad 36p.

[0070] Incidentally, in the process shown in Figure 5(a) (TCB process), the substrates 10 and 30 are heated by the first mold 510 and the second mold 520, causing the substrates 10 and 30 to expand thermally. On the other hand, this heat is not easily transferred to the semiconductor chip 50, so the semiconductor chip 50 at the joint 40 does not expand thermally, and only the substrate 30 side expands thermally. Also, the vicinity of the joint 40 is exposed between the substrate 10 and the substrate 30 and is not protected by a protective material such as resin at this point. Therefore, a large amount of thermal stress is applied to the connection between the pad 34q and the joint 40. A large amount of thermal stress is applied to the connection between the pad 34q located on the outer periphery and the joint 40, and in particular, a large amount of thermal stress is applied to the connection between the pad 34q at the four corners and the joint 40. However, since the pads 34q at the four corners of the substrate 30 are made of an NSMD structure, the bonding strength between the pad 34q and the joint 40 is increased, so the joint 40 does not break, and the substrate 30 and the semiconductor chip 50 can be bonded with high reliability.

[0071] <Variation 1 of the First Embodiment> Modification 1 of the first embodiment shows an example in which the arrangement of the NSMD structured pads differs from that of the first embodiment. In Modification 1 of the first embodiment, descriptions of components that are the same as those described in the previously described embodiment may be omitted.

[0072] Figure 6 is a partially enlarged view of the vicinity of the semiconductor chip in an electronic component embedded substrate according to Modification 1 of the First Embodiment, where Figure 6(a) is a cross-sectional view (BB cross-section in Figure 6(b)) and Figure 6(b) is a plan view. However, only the parts necessary for explanation are shown in Figure 6.

[0073] Referring to Figure 6, in the modified example 1 of the first embodiment of the embedded electronic component substrate, all outermost pads have an NSMD structure. In the process shown in Figure 5(a) (TCB process), significant thermal stress is applied to the connection between the pads 34q at the four corners and the bonding portion 40, but relatively significant thermal stress is also applied to the connection between the pads 34q located on the outermost periphery other than the four corners and the bonding portion 40. Therefore, by making all of the outermost pads 34q have an NSMD structure, the substrate 30 and the semiconductor chip 50 can be bonded with higher reliability.

[0074] Furthermore, it is not necessary to make all of the outermost pads an NSMD structure; at least one of the outermost pads located outside the four corners may be an NSMD structure. In this case as well, the substrate 30 and the semiconductor chip 50 can be bonded with higher reliability.

[0075] Although preferred embodiments and their variations have been described in detail above, the invention is not limited to the embodiments and their variations described above, and various modifications and substitutions can be made to the embodiments and their variations described above without departing from the scope of the claims.

[0076] For example, a build-up substrate with more layers of wiring and insulating layers may be used as the first or second substrate. In this case, a coreless build-up substrate or a build-up substrate with a core may be used. Furthermore, a lead frame may be used as the first substrate. [Explanation of Symbols]

[0077] 1. Circuit board with embedded electronic components 10, 30 circuit boards 11, 31, 33 Insulating layer 11x, 31x, 33x Beer Hall 12, 14, 32, 34, 36 wiring layers 12p, 14p, 34p, 34q, 36p pads 13, 15, 35, 37 Solder resist layers 13x, 15x, 15y, 35x, 37x opening 20. Board connection member 21 cores 22 Conductive materials 40 Joint 50 semiconductor chips 51 Chip body 52 electrodes 60 mold resin

Claims

1. First circuit board and Electronic components mounted on the first substrate, A second substrate is provided on the opposite side of the first substrate, with the aforementioned electronic component in between, and is connected to the first substrate via a substrate connecting member. The device comprises a sealing resin that is filled between the first substrate and the second substrate, covering the electronic component, and also filled between the electronic component and the first substrate, The first substrate has, on the side of the electronic component, a plurality of pads that are joined to the electrodes of the electronic component via a joint, and a protective insulating layer having an opening. Multiple of the aforementioned pads are In a plan view, the outermost pads, which are spaced apart from each other, are located at the outermost perimeter including the four corners, The region surrounded by the outermost pad includes inner pads arranged spaced apart from each other, Of the outermost pads, the four outermost pads positioned at the corners are exposed within the opening while separated from the protective insulating layer. The inner pad has its outer periphery covered by the protective insulating layer, and a portion of its upper surface is exposed into the opening. An electronic component substrate in which the area of ​​the upper surface of the outermost pad exposed within the opening while separated from the protective insulating layer is smaller than the area of ​​the upper surface of the inner pad.

2. The electronic component substrate according to claim 1, wherein at least one of the outermost pads, which are located in a position other than the four corners, is exposed within the opening while being separated from the protective insulating layer.

3. The electronic component substrate according to claim 2, wherein all of the outermost pads are exposed within the opening, separated from the protective insulating layer.

4. The electronic component substrate according to any one of claims 1 to 3, wherein the upper surface and side surface of the outermost pad exposed in the opening while separated from the protective insulating layer are in contact with the joint.

5. A first substrate is prepared having a plurality of first pads, a second pad, and a protective insulating layer having an opening that exposes at least a portion of each of the first pads and the second pads; and an electronic component is mounted on the first substrate such that the electrodes of the electronic component are joined to the first pads via a joint; The process involves arranging the substrate connection member so that it is positioned at a location corresponding to the second pad, stacking the second substrate on the first substrate with the electronic components in between, and electrically connecting the first substrate and the second substrate via the substrate connection member. The process includes a step of filling a sealing resin between the first substrate and the second substrate, In the step of filling with the sealing resin, the sealing resin covers the electronic component and is also filled between the electronic component and the first substrate. In the process of connecting the first substrate and the second substrate, the laminate of the first substrate and the second substrate is held between a first mold containing a heater and a second mold containing a heater, and while the laminate is under pressure, the first mold and the second mold are heated with the heater to join the substrate connecting member and the second pad. Multiple first pads, In a plan view, the outermost pads, which are spaced apart from each other, are located at the outermost perimeter including the four corners, The region surrounded by the outermost pad includes inner pads arranged spaced apart from each other, Of the outermost pads, the four outermost pads positioned at the corners are exposed within the opening while separated from the protective insulating layer. The inner pad has its outer periphery covered by the protective insulating layer, and a portion of its upper surface is exposed into the opening. A method for manufacturing an electronic component substrate, wherein the area of ​​the upper surface of the outermost pad exposed within the opening while separated from the protective insulating layer is smaller than the area of ​​the upper surface of the inner pad.

6. The method for manufacturing an electronic component substrate according to claim 5, wherein at least one of the outermost pads, which are arranged in a manner other than the four corners, is exposed within the opening while being separated from the protective insulating layer.

7. The method for manufacturing an electronic component substrate according to claim 6, wherein all of the outermost pads are exposed within the opening while being separated from the protective insulating layer.

8. The method for manufacturing an electronic component substrate according to any one of claims 5 to 7, wherein the upper surface and side surface of the outermost pad exposed in the opening while separated from the protective insulating layer are in contact with the joint.

Images