Manufacturing method for semiconductor devices

Abstract

To provide a technique of suppressing decomposition of a gallium nitride semiconductor at the time of an annealing treatment while forming a groove for positioning.SOLUTION: A manufacturing method may include: a protection film formation step that is a step of forming a protection film on the front surface of a semiconductor substrate constructed by gallium nitride, and forming the protection film so that the groove is existed on the front surface of the protection film, and a bottom part of the groove is positioned in the protection film; and an ion implantation step of forming an ion implantation region by implanting an ion to the semiconductor substrate. The protection film formation step and the ion implantation step may be executed so that the groove and the ion implantation region are relatively positioned. After the step of forming the protection film and the step of forming the ion implantation region, the manufacturing method may further include: an annealing step of executing an annealing treatment for the semiconductor substrate; and a processing step of forming a processing part in the semiconductor substrate in a state of being positioned to the groove after the annealing step.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a technique for forming a p-type semiconductor region in a gallium nitride (GaN)-based semiconductor substrate by ion implantation. In this technique, after p-type impurities are implanted, a protective film is formed on the surface of the semiconductor substrate. After the protective film is formed, the semiconductor substrate is annealed. During annealing, the decomposition of gallium nitride is suppressed by the protective film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Grooves may be formed on the surface of a semiconductor substrate as alignment marks. When a protective film is formed on the surface of the semiconductor substrate with grooves formed thereon, the thickness of the protective film may become thin at the boundary between the bottom surface and the side surface of the grooves. When such a location occurs, gallium nitride of the semiconductor substrate is likely to decompose during the annealing process at this location. In this specification, a technique is provided for suppressing the decomposition of gallium nitride during the annealing process while forming grooves for alignment.

Means for Solving the Problems

[0005] This specification discloses a method for manufacturing a semiconductor device. The manufacturing method may include a step of forming a protective film (48) on the surface (10c) of a semiconductor substrate (10) made of a gallium nitride-based semiconductor, wherein grooves (42) exist on the surface of the protective film and the bottom of the grooves are located within the protective film; and an ion implantation step of implanting ions into the semiconductor substrate to form an ion implantation region (30). The protective film formation step and the ion implantation step may be performed so that the grooves and the ion implantation region are aligned with each other. The manufacturing method may further include an annealing step of performing an annealing treatment on the semiconductor substrate after the step of forming the protective film and the step of forming the ion implantation region, and a processing step of forming processed parts (50, 52, 54) on the semiconductor substrate in a state aligned with the grooves after the annealing step.

[0006] In the above technology, "gallium nitride semiconductor" refers to semiconductors whose main component is GaN, such as GaN, AlGaN, and InGaN.

[0007] In the above technology, the order in which the protective film formation step and the ion implantation step are performed is not particularly limited. That is, the ion implantation step may be performed after the protective film formation step, or the protective film formation step may be performed after the ion implantation step. Furthermore, the ion implantation step may be performed in the middle of the protective film formation step.

[0008] In the above technology, "alignment" includes both direct alignment and indirect alignment. That is, "the groove and the ion implantation region are aligned with each other" means that the groove and the ion implantation region may be directly aligned with each other, or the groove and the ion implantation region may be indirectly aligned with each other by aligning the groove with other members and the ion implantation region with other members. Furthermore, "forming the processed portion (50, 52, 54) on the semiconductor substrate in a state aligned with the groove" means that the processed portion may be formed in a state directly aligned with the groove, or the processed portion may be formed in a state indirectly aligned with the groove by aligning it with other members that are aligned with the groove.

[0009] A protective film is formed on the surface of the semiconductor substrate, with a groove whose bottom is located within the protective film. By adjusting the depth of the groove, a sufficient thickness of the protective film can be ensured to suppress the decomposition of gallium nitride in the lower part of the groove. This suppresses the decomposition of gallium nitride during the annealing process. Furthermore, the groove and the ion implantation region are aligned with each other before the annealing process. After the annealing process, the processed area is formed on the semiconductor substrate while it is aligned with the groove. Thus, the processed area can be formed while being aligned with the ion implantation region. In this way, the above configuration makes it possible to form a groove for alignment while suppressing the decomposition of gallium nitride during the annealing process. [Brief explanation of the drawing]

[0010] [Figure 1] This is a diagram illustrating the first cap film formation step of Example 1. [Figure 2] This is a diagram illustrating the first groove formation step of Example 1. [Figure 3] This is a diagram illustrating the first cap film removal step in Example 1. [Figure 4] This is a diagram illustrating the ion implantation process in Example 1. [Figure 5] This is a diagram illustrating the second cap film formation step and annealing step of Example 1. [Figure 6] This is a diagram illustrating the second cap film removal step in Example 1. [Figure 7] This is a diagram illustrating the electrode formation process in Example 1. [Figure 8] This is a diagram illustrating the recess formation process in Example 2. [Figure 9] This is a diagram illustrating the second cap film removal step in Example 2. [Figure 10] This is a diagram illustrating the electrode formation process in Example 2. [Figure 11] This is a diagram illustrating the ion implantation process in Example 3. [Figure 12] This is a diagram illustrating the cap film formation process in Example 3. [Figure 13] This is a diagram illustrating the groove formation process and annealing process of Example 3. [Figure 14] This is a diagram illustrating the cap film removal process in Example 3. [Figure 15] This is a diagram illustrating the electrode formation process in Example 3. [Modes for carrying out the invention]

[0011] In one embodiment of the present technology, the protective film forming step includes a first protective film forming step of forming a first protective film (20) and a second protective film forming step of forming a second protective film (40). These steps are carried out in the order of the first protective film forming step, the ion implantation step, and the second protective film forming step. In the first protective film forming step, on the surface of the semiconductor substrate, the first protective film has an opening where a first groove (22) exists on the surface of the first protective film, the bottom of the first groove is located within the first protective film, and the surface of the semiconductor substrate is exposed, and the first protective film is formed. In the ion implantation step, the ion implantation region is formed within the opening in a state aligned with the first groove. In the second protective film forming step, the second protective film is formed so as to cover the opening and the first protective film. In the second protective film forming step, a second groove (42) may be formed along the first groove on the surface of the second protective film, and the second groove may be the groove.

[0012] Even with this configuration, it is possible to suppress the decomposition of gallium nitride during the annealing process while forming grooves for alignment.

[0013] In one embodiment of the present technology, the protective film forming step may be carried out after the ion implantation step, and in the protective film forming step, the groove may be formed in a state aligned with the ion implantation region.

[0014] Even with this configuration, it is possible to suppress the decomposition of gallium nitride during the annealing process while forming grooves for alignment.

[0015] After the annealing step, a step of forming a recess (112) on the surface of the semiconductor substrate by deepening the groove so as to reach the semiconductor substrate, and a step of removing the protective film after forming the recess may be further included. In the processing step, the processed portion may be formed in a state aligned with the recess.

[0016] This configuration also allows for the formation of grooves for alignment while suppressing the decomposition of gallium nitride during the annealing process. In particular, since recesses that reach the semiconductor substrate are formed, the recesses are highly visible when forming the processed part while aligned with the recesses.

[0017] (Example 1) A method for manufacturing a semiconductor device of Example 1 will now be described. The semiconductor device is manufactured from a semiconductor substrate 10 shown in Figure 1. The semiconductor substrate 10 is made of gallium nitride (GaN). In a modified example, the semiconductor substrate 10 may be made of a GaN-based semiconductor, such as AlGaN or InGaN, which has GaN as the main component. The semiconductor substrate 10 has a drain layer 10a and a drift layer 10b. Both the drain layer 10a and the drift layer 10b are n-type semiconductor regions. The n-type impurity concentration of the drain layer 10a is higher than the n-type impurity concentration of the drift layer 10b. The semiconductor substrate 10 has a front surface 10c and a back surface 10d. The front surface 10c is part of the drift layer 10b. The back surface 10d is part of the drain layer 10a.

[0018] The manufacturing method of Example 1 comprises a first cap film formation step, a first groove formation step, a first cap film removal step, an ion implantation step, a second cap film formation step, an annealing step, a second cap film removal step, and an electrode formation step.

[0019] In the first cap film formation step, as shown in Figure 1, a first cap film 20 is formed on the front surface 10c and back surface 10d of the semiconductor substrate 10. The first cap film 20 is composed of AlN, AlGaN, ScN, ScAlN, C, etc. Although Figure 1 shows a single layer of the first cap film 20, the first cap film 20 may have a laminated structure of two or more layers. The first cap film 20 is an example of the "first protective film".

[0020] In the first groove formation step, as shown in Figure 2, a first groove 22 is formed on the surface of the first cap film 20. The first groove 22 is formed, for example, by etching. The first groove 22 is formed such that its bottom is located inside the first cap film 20.

[0021] In the first cap film removal step, a portion of the first cap film 20 is removed, as shown in Figure 3. Specifically, the first cap film 20 is removed in areas other than the vicinity of the first groove 22 by selective etching. In the areas where the first cap film 20 has been removed, the surface 10c of the semiconductor substrate 10 is exposed.

[0022] In the ion implantation process, as shown in Figure 4, p-type and n-type impurities are selectively implanted into the surface 10c within the exposed area. This forms an ion implantation region 30 within the drift layer 10b. During ion implantation, the first groove 22 is used as an alignment mark. That is, the ion implantation region 30 is formed in a state aligned with the first groove 22. Therefore, the first groove 22 and the ion implantation region 30 are aligned with each other.

[0023] The ion implantation region 30 comprises a body layer 32, a source layer 34, and a contact layer 36. The body layer 32 and the contact layer 36 are p-type semiconductor regions. The source layer 34 is an n-type semiconductor region. The p-type impurity concentration in the body layer 32 is lower than that in the contact layer 36. Also, the n-type impurity concentration in the source layer 34 is higher than that in the drift layer 10b.

[0024] In the second cap film formation process, as shown in Figure 5, a second cap film 40 is formed on the upper part of the semiconductor substrate 10. In the area where the surface 10c is exposed, the second cap film 40 is formed to cover the surface 10c. In the area where the first cap film 20 exists, the second cap film 40 is formed on top of the first cap film 20. The second cap film 40 is formed to cover the first cap film 20. On the surface of the second cap film 40, a second groove 42 is formed along the first groove 22 formed in the first cap film 20. Since the second groove 42 is formed along the first groove 22, the second groove 42 and the ion implantation region 30 are aligned with each other. The protective film 48 is completed by the first cap film 20 and the second cap film 40. The protective film 48 covers the entire surface 10c of the semiconductor substrate 10. The surface of the protective film 48 has a second groove 42. The bottom of the second groove 42 is located inside the protective film 48. The second cap film 40 is an example of a "second protective film".

[0025] In the annealing process, the semiconductor substrate 10 is subjected to annealing treatment with the protective film 48 formed (i.e., in the state shown in Figure 5). The annealing treatment activates the ion implantation region 30. Since the entire surface 10c of the semiconductor substrate 10 is covered by the protective film 48, the decomposition of gallium nitride on the surface 10c during annealing is suppressed.

[0026] In the second cap film removal step, as shown in Figure 6, a portion of the second cap film 40 is removed. Specifically, the second cap film 40 is removed in areas other than the vicinity of the second groove 42 by selective etching. In the areas where the second cap film 40 has been removed, the surface 10c of the semiconductor substrate 10 is exposed.

[0027] In the electrode formation process, as shown in Figure 7, the gate insulating film 50, gate electrode 52, and source electrode 54 are formed on the upper part of the ion implantation region 30. Here, the second groove 42 is used as an alignment mark to form the gate insulating film 50, gate electrode 52, and source electrode 54. That is, the gate insulating film 50, gate electrode 52, and source electrode 54 are formed by aligning them with the second groove 42. As described above, the ion implantation region 30 is aligned with the first groove 22, and the second groove 42 is aligned with the first groove 22, so the ion implantation region 30 is aligned with the second groove 42. Therefore, by aligning the gate insulating film 50, gate electrode 52, and source electrode 54 with respect to the second groove 42, the second groove 42 can be aligned with respect to the ion implantation region 30. The gate insulating film 50 is formed in a range that spans from the surface of the source layer 34 to the surface of the drift layer 10b. The gate electrode 52 is formed on the upper part of the gate insulating film 50. The source electrode 54 is formed in an area that spans the surface of the source layer 34 and the contact layer 36. The gate insulating film 50, gate electrode 52, and source electrode 54 are examples of "processed parts".

[0028] Furthermore, in the electrode formation process, a drain electrode 56 that contacts the back surface 10d is formed. Through these processes, a semiconductor device (for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)) is completed.

[0029] Thus, with the above configuration, it is possible to form a second groove 42 for alignment while suppressing the decomposition of gallium nitride during the annealing process.

[0030] (Example 2) Next, the manufacturing method of Example 2 will be described. In the manufacturing method of Example 2, the steps from the first cap film formation step to the annealing step are carried out in the same manner as in Example 1. That is, processing is carried out until the state shown in Figure 5. In the manufacturing method of Example 2, after the annealing step, the recess formation step, the second cap film removal step, and the electrode formation step are carried out.

[0031] In the recess formation process, as shown in Figure 8, a recess 112 reaching the semiconductor substrate 10 (more specifically, the drift layer 10b) is formed by deepening the second groove 42. The recess 112 is formed by deepening the second groove 42, for example, by etching. As described above, the second groove 42 and the ion implantation region 30 are aligned. Since the recess 112 is formed by deepening the second groove 42, the recess 112 and the ion implantation region 30 are aligned with each other.

[0032] In the second cap film removal step, as shown in Figure 9, the entirety of the first cap film 20 and the second cap film 40 are removed by etching. After the second cap film removal step is performed, the surface 10c of the semiconductor substrate 10 is exposed.

[0033] Next, in the electrode formation process, the gate insulating film 50, gate electrode 52, and source electrode 54 are formed as shown in Figure 10. Here, the recess 112 is used as an alignment mark to form the gate insulating film 50, gate electrode 52, and source electrode 54. As described above, the recess 112 is aligned with respect to the ion implantation region 30. Therefore, by forming the gate insulating film 50, gate electrode 52, and source electrode 54 while aligning with the recess 112, the gate insulating film 50, gate electrode 52, and source electrode 54 can be aligned with respect to the ion implantation region 30. In addition, in the electrode formation process, a drain electrode 56 that contacts the back surface 10d is formed. The semiconductor device is completed through the above steps.

[0034] In the configuration of Example 2, it is possible to form recesses 112 for alignment while suppressing the decomposition of gallium nitride during the annealing process. In particular, in the configuration of Example 2, since recesses 112 deeper than the second groove 42 can be formed, the recesses 112 are more easily recognized as alignment marks.

[0035] (Example 3) Next, the manufacturing method for Example 3 will be described. The manufacturing method for Example 3 includes an ion implantation step, a cap film formation step, a groove formation step, an annealing step, a cap film removal step, and an electrode formation step.

[0036] In the ion implantation process, ion implantation regions 30 and 230 are formed as shown in Figure 11. Specifically, first, ions are selectively implanted into the semiconductor substrate 10 to form a source layer 34 and an ion implantation region 230 in the area exposed on the surface 10c. At this stage, the ion implantation region 230 is visible. Next, ion implantation is performed using the ion implantation region 230 as an alignment mark to form a contact layer 36 and a body layer 32. Thus, the ion implantation region 230 and the ion implantation region 30 are aligned with each other.

[0037] In the cap film formation process, as shown in Figure 12, a cap film 20 is formed on the front surface 10c and the back surface 10d of the semiconductor substrate 10. The cap film 20 is transparent.

[0038] In the groove formation process, grooves 22 are formed on the surface of the cap film 20, as shown in Figure 13. The grooves 22 are formed, for example, by etching. Since the cap film 20 is transparent, the ion implantation region 30 can be optically detected from the outside. Here, the ion implantation region 30 is used as an alignment mark to form the grooves 22 in the cap film 20. That is, the grooves 22 are formed in a state aligned with the ion implantation region 30. Here, the grooves 22 are formed above the ion implantation region 230. The grooves 22 are formed so that their bottoms are located inside the cap film 20. Furthermore, the grooves 22 are formed to a depth such that a cap film 20 with a thickness (e.g., 40 nm or more) that does not decompose during the annealing process remains below the grooves 22.

[0039] In the annealing process, the semiconductor substrate 10 is annealed with the cap film 20 formed (i.e., in the state shown in Figure 13). The annealing process activates the ion implantation region 30. Since the entire surface 10c of the semiconductor substrate 10 is covered by the cap film 20, the decomposition of gallium nitride on the surface 10c during annealing is suppressed. After the annealing process is performed, the ion implantation region 230 changes color and becomes invisible. For this reason, the groove 22 is used as an alignment mark after the annealing process is completed.

[0040] After the annealing process is performed, a cap film removal process is carried out. In the cap film removal process, a portion of the cap film 20 is removed, as shown in Figure 14. Specifically, the cap film 20 is removed in areas other than the vicinity of the groove 22 by selective etching. In the areas where the cap film 20 has been removed, the surface 10c of the semiconductor substrate 10 is exposed.

[0041] Subsequently, in the electrode formation process, as shown in Figure 15, the groove 22 is used as an alignment mark to form the gate insulating film 50, the gate electrode 52, and the source electrode 54. Therefore, the gate insulating film 50, the gate electrode 52, and the source electrode 54 can be formed in alignment with the ion implantation region 30. In addition, the drain electrode 56 is formed in the electrode formation process.

[0042] Even with the configuration of Example 3, it is possible to form the alignment groove 22 while suppressing the decomposition of gallium nitride during the annealing process.

[0043] Furthermore, in the configurations of Examples 1 and 2, the process of forming the cap film was performed twice (a first cap film formation step and a second cap film formation step). In contrast, in the configuration of Example 3, the cap film formation step only needs to be performed once. Therefore, the manufacturing of semiconductor devices can be simplified.

[0044] In the modified example of Example 3, instead of performing the cap film removal step and electrode formation step after the annealing step, the steps from the recess formation step onward in Example 2 may be performed.

[0045] The specific examples of the technology disclosed in this specification have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes to the specific examples described above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of symbols]

[0046] 10: Semiconductor substrate, 10a: Drain layer, 10b: Drift layer, 10c: Front surface, 10d: Back surface, 20: First cap film, 22: First groove, 30: Ion implantation region, 32: Body layer, 34: Source layer, 36: Contact layer, 40: Second cap film, 42: Second groove, 48: Protective film, 50: Gate insulating film, 52: Gate electrode, 54: Source electrode, 56: Drain electrode, 112: Recess, 230: Ion implantation region

Claims

1. A method for manufacturing a semiconductor device, A step of forming a protective film (48) on the surface (10c) of a semiconductor substrate (10) made of a gallium nitride-based semiconductor, wherein grooves (42) exist on the surface of the protective film, and the protective film is formed such that the bottom of the grooves is located within the protective film, Ion implantation step of implanting ions into the semiconductor substrate to form an ion implantation region (30), It has, The protective film formation step and the ion implantation step are performed so that the groove and the ion implantation region are aligned with each other. The steps include the step of forming the protective film and the step of forming the ion implantation region, followed by an annealing step in which the semiconductor substrate is subjected to an annealing treatment. A processing step is performed after the annealing step, in which processed portions (50, 52, 54) are formed on the semiconductor substrate in a state aligned with the grooves. A manufacturing method that further includes the following.

2. The protective film formation step comprises a first protective film formation step for forming a first protective film (20) and a second protective film formation step for forming a second protective film (40). The steps are carried out in the order of the first protective film formation step, the ion implantation step, and the second protective film formation step. In the first protective film formation step, the first protective film is formed such that a first groove (22) exists on the surface of the first protective film, the bottom of the first groove is located within the first protective film, and the first protective film has an opening through which the surface of the semiconductor substrate is exposed. In the ion implantation step, the ion implantation region is formed within the opening while being aligned with the first groove. In the second protective film formation step, the second protective film is formed so as to cover the opening and the first protective film. In the second protective film formation step, a second groove (42) is formed on the surface of the second protective film along the first groove. The second groove is the groove, The manufacturing method according to claim 1.

3. The protective film formation step is performed after the ion implantation step, In the protective film formation step, the groove is formed in a state aligned with the ion implantation region. The manufacturing method according to claim 1.

4. A step after the annealing step, in which a recess (112) is formed on the surface of the semiconductor substrate by deepening the groove so that it reaches the semiconductor substrate, After forming the recess, the step of removing the protective film, It further possesses, In the aforementioned machining process, the machined portion is formed in a state aligned with the recess. The manufacturing method according to any one of claims 1 to 3.

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