Capacitor and method for manufacturing the same

Abstract

To Provide a capacitor that ensures the rigidity of the substrate on which the grooves are provided.SOLUTION: In a capacitor having at least a substrate having a groove formed on a first major surface and a projection portion, a portion of which is disposed on the first major surface of the substrate, another portion of the projection portion protrudes from the first major surface to the inside of the groove more than the inner surface of the groove formed on the first major surface. The distance between the inner surfaces of the opposing pair of grooves may be longer than the distance between the tips of the pair of projections, each of which protrudes inwardly of the grooves more than the inner surface of the pair, or the openings of the grooves may be blocked by the projections.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a capacitor and a method for manufacturing the same.

Background Art

[0002] A capacitor is known in which a layer arrangement in which a conductive layer and a dielectric layer are alternately deposited is embedded inside a plurality of stripe-shaped grooves provided in a substrate (see Patent Document 1). In Patent Document 1, the layer arrangement embedded inside the grooves is electrically connected to an aluminum electrode on the upper surface side of the substrate and a back surface electrode on the back surface side of the substrate, respectively.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a substrate provided with a plurality of stripe-shaped grooves, the stress generated on the front and back surfaces becomes unbalanced, the substrate warps, and the substrate itself may crack.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a capacitor and a method for manufacturing the same that ensure the rigidity of a substrate provided with grooves.

Means for Solving the Problems

[0006] In order to solve the above problems, a capacitor according to an aspect of the present invention has a protrusion, a part of which is disposed on a first main surface of a substrate, and another part of which protrudes from the first main surface to the inside of a groove beyond an inner surface of the groove formed in the first main surface.

Effects of the Invention

[0007] According to one aspect of the present invention, a capacitor can be provided in which the rigidity of the substrate having grooves is ensured. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a capacitor according to the first embodiment. [Figure 2A] Figure 2A is a plan view showing the first step in the manufacturing process of the capacitor shown in Figure 1. [Figure 2B] Figure 2B is a cross-sectional view along line AA in Figure 2A. [Figure 2C] Figure 2C is a cross-sectional view showing the second step in the manufacturing process of the capacitor shown in Figure 1. [Figure 2D] Figure 2D is a cross-sectional view showing step (3) of the manufacturing process for the capacitor shown in Figure 1. [Figure 2E] Figure 2E is a cross-sectional view showing step (4) of the manufacturing process for the capacitor shown in Figure 1. [Figure 2F] Figure 2F is a cross-sectional view showing step (5) of the manufacturing process for the capacitor shown in Figure 1. [Figure 2G] Figure 2G is a cross-sectional view showing step (6) of the manufacturing process for the capacitor shown in Figure 1. [Figure 2H] Figure 2H is a cross-sectional view showing step (7) of the manufacturing process for the capacitor shown in Figure 1. [Figure 2I] Figure 2I is a plan view of the capacitor in a modified example of the first embodiment, when the first main surface 1F of the substrate 1 is viewed from the direction of its normal. [Figure 3A] Figure 3A is a schematic diagram showing the configuration used in the calculations. [Figure 3B] Figure 3B is a graph illustrating the relationship between the thickness of all protrusions 4 and the section modulus of the structure. [Figure 4] Figure 4 is a schematic cross-sectional view showing the configuration of a capacitor according to the first embodiment. [Figure 5A] Figure 5A is a plan view showing the first step in the manufacturing process of the capacitor shown in Figure 4. [Figure 5B] Figure 5B is a cross-sectional view taken along line B-B of Figure 5A. [Figure 5C] Figure 5C is a cross-sectional view showing step (part 2) of the method for manufacturing the capacitor shown in Figure 4. [Figure 5D] Figure 5D is a cross-sectional view showing step (part 3) of the method for manufacturing the capacitor shown in Figure 4. [Figure 5E] Figure 5E is a cross-sectional view showing step (part 4) of the method for manufacturing the capacitor shown in Figure 4. [Figure 5F] Figure 5F is a cross-sectional view showing step (part 4) of the method for manufacturing the capacitor shown in Figure 4. [Figure 5G] Figure 5G is a cross-sectional view showing step (part 6) of the method for manufacturing the capacitor shown in Figure 4. [Figure 5H] Figure 5H is a cross-sectional view showing step (part 7) of the method for manufacturing the capacitor shown in Figure 4. [Figure 6A] Figure 6A is a perspective view before joining substrates 1a to 1c that constitute substrate 1A. [Figure 6B] Figure 6B is a perspective view after joining substrates 1a to 1c that constitute substrate 1A. [Figure 6C] Figure 6C is a perspective view before joining substrates 1a, 1b, and 1d that constitute substrate 1B. [Figure 6D] Figure 6D is a perspective view after joining substrates 1a, 1b, and 1d that constitute substrate 1B. [Figure 6E] Figure 6E is a perspective view before joining substrates 1b, 1d, and 1e that constitute substrate 1C. [Figure 6F] Figure 6F is a perspective view after joining substrates 1b, 1d, and 1e that constitute substrate 1C. [Figure 6G] Figure 6G is a perspective view before joining substrates 1b, 1e, and 1f that constitute substrate 1D. [Figure 6H] Figure 6H is a perspective view after joining substrates 1b, 1e, and 1f that constitute substrate 1D.

Embodiments for Carrying Out the Invention

[0009] The embodiments will be described below with reference to the drawings. In the drawings, the same parts are denoted by the same reference numerals and their descriptions are omitted. However, the drawings are schematic and may contain parts that differ from reality, such as the relationship between thickness and planar dimensions and the ratio of the thickness of each layer. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0010] (First Embodiment) The configuration of the capacitor according to the first embodiment will be described with reference to Figures 1 and 2A. Figure 1 is a schematic cross-sectional view of the capacitor 100. The capacitor 100 comprises a substrate 1. The substrate 1 has a first main surface 1F, a second main surface 1R opposite to the first main surface 1F, and a groove 2 formed on the first main surface 1F. The groove 2 has an inner surface 2I. The substrate 1 is a single crystal substrate made of silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), or gallium oxide (Ga2O3). In this embodiment, the substrate 1 is doped with a high concentration of N-type or P-type impurities, and the substrate 1 is conductive, similar to the conductive layer described later. Since the substrate 1 can be used as a conductive layer, the capacitance density of the capacitor 100 is improved.

[0011] As shown in Figure 2A, when viewed from the direction normal to the first main surface 1F, groove 2 has a first width W. a A first region 2a having a first width W a Shorter second width W b The groove 2 has a second region 2b having a second region 2a. In this embodiment, the second region 2b is located between the two first regions 2a. By having this groove shape, the material gas used when forming the dielectric layer 5, which will be described later, enters from one of the first regions 2a of the groove 2, passes through the second region 2b, and exits from the other first region 2a, so that the dielectric layer 5 inside the groove 2 can be formed uniformly.

[0012] The capacitor 100 includes a projection 4, part of which is positioned on the first main surface 1F, and another part of which protrudes from the first main surface 1F further inward into the groove 2 than the inner surface 2I of the groove 2. It also includes another projection 4, part of which is positioned on the second main surface 1R, and another part of which protrudes from the second main surface 1R further inward into the groove 2 than the inner surface 2I of the groove 2. The projections 4 are formed, for example, by an atmospheric pressure CVD method using polysilicon. By forming the projections 4 by an atmospheric pressure CVD method using polysilicon, the shape of the groove 2 can be arbitrarily adjusted in a simple and low-cost manner. In this embodiment, the projections 4 are doped with a high concentration of N-type or P-type impurities and have the same conductivity as the substrate 1, but are not limited to this, and the projections 4 may have semiconductor properties or insulating properties.

[0013] The distance D1 between the pair of opposing inner surfaces 2I in the groove 2 is longer than the distance D2 between the tips of the pair of protrusions 4 that protrude inward from the groove 2. The protrusions 4 increase the overall section modulus of the structure consisting of the substrate 1 and the protrusions 4, thereby increasing the rigidity of the substrate 1 in which the groove 2 is provided when stress from the dielectric layer 5 is applied to the substrate 1.

[0014] Furthermore, the opening of the groove 2 may be closed by the projection 4. In this case as well, the section modulus of the entire structure consisting of the substrate 1 and the projection 4 becomes larger, thereby increasing the rigidity of the substrate 1 in which the groove 2 is provided when stress from the dielectric layer 5 is applied to the substrate 1. In this specification, a structure having a cavity in which the opening of the groove is closed is also included as a type of groove.

[0015] The sum of the thickness of the projection 4 on the first main surface 1F and the thickness of the projection 4 on the second main surface 1R is preferably 1 to 60%, more preferably 10 to 60%, and even more preferably 20 to 55% of the sum of the thickness of the substrate 1 and the thickness of the two projections 4. By adjusting the thickness of the projections 4 to the above range, the rigidity per unit volume of the substrate 1 can be efficiently increased.

[0016] The capacitor 100 comprises at least two dielectric layers 5 and at least two conductive layers 6 alternately stacked on the surface of the protrusion 4 and the inner surface 2I of the groove 2. In this embodiment, four dielectric layers 5 and four conductive layers 6 are alternately stacked on at least the surface of the protrusion 4 and the inner surface 2I of the groove 2. The four conductive layers 6 are electrically insulated from each other by the dielectric layers 5. Each of the four dielectric layers 5 and the four conductive layers 6 is formed continuously on at least the surface of the protrusion 4 and the inner surface 2I of the groove 2. The number of dielectric layers and conductive layers stacked on the inner surface 2I of the groove 2 is determined by the width of the groove and the thickness of the dielectric layers and conductive layers, and may be 3 to 4 layers or 5 or more layers, respectively.

[0017] The dielectric layer 5 may be made of, for example, silicon oxide. The high band gap of silicon oxide can reduce leakage current. Alternatively, the dielectric layer 5 may be made of silicon nitride, which has a high dielectric constant. The high dielectric constant of silicon nitride can improve capacitance density. Alternatively, a laminated film of a film made of silicon oxide and a film made of silicon nitride may be used as each dielectric layer 5. The dielectric layer 5 electrically insulates the conductive layer 6, which is electrically connected to the low-potential surface electrode 16 and the low-potential back electrode 18, from the conductive layer 6, which is electrically connected to the high-potential surface electrode 17 and the high-potential back electrode 19.

[0018] The conductive layer 6 may be made of, for example, polysilicon or a metal. If polysilicon is used for the conductive layer 6, the conductive layer 6 can be uniformly grown along the surface of the protrusions 4 and the inner surface 2I of the grooves 2 by methods such as low-pressure CVD. If a metal is used for the conductive layer 6, the equivalent series resistance (ESR) of the conductive layer 6 can be reduced because metals have low resistivity.

[0019] The groove 2 may penetrate between the first main surface 1F and the second main surface 1R. By extending the groove 2 formed in the substrate 1 from the first main surface 1F to the second main surface 1R, the dielectric layer 5 and conductive layer 6 formed on the first main surface 1F and the second main surface 1R can be made symmetrical with respect to the center in the film thickness direction of the substrate 1, thereby mitigating warping of the substrate 1 caused by stress in the dielectric layer 5.

[0020] The capacitor 100 further comprises a low-potential surface electrode 16 (first electrode) embedded in an opening (opening 12 described later) formed on the first main surface 1F, a high-potential surface electrode 17 (second electrode) embedded in an opening formed on the first main surface 1F, a low-potential back electrode 18 embedded in an opening (opening 12 described later) formed on the second main surface 1R, and a high-potential back electrode 19 embedded in an opening formed on the second main surface 1R. The low-potential surface electrode 16 and the low-potential back electrode 18 are electrically connected to the projection 4 and the conductive layer 6. The high-potential surface electrode 17 and the high-potential back electrode 19 are electrically connected to the conductive layer 6, which is not electrically connected to the low-potential surface electrode 16 and the low-potential back electrode 18. In this embodiment, the low-potential electrode corresponds to the first electrode and the high-potential electrode corresponds to the second electrode, but the reverse may also be true.

[0021] In this embodiment, five openings 12 are formed on the first main surface 1F and the second main surface 1R, respectively. Low-potential surface electrodes 16 are formed in the three openings 12 on the first main surface 1F side, and high-potential surface electrodes 17 are formed in the two openings 12 on the first main surface 1F side. Low-potential back surface electrodes 18 are formed in the three openings 12 on the second main surface 1R side, and high-potential back surface electrodes 19 are formed in the two openings 12 on the second main surface 1R side.

[0022] For example, metallic materials can be used as the low-potential surface electrode 16, high-potential surface electrode 17, low-potential back electrode 18, and high-potential back electrode 19. These can include metallic materials such as titanium (Ti), nickel (Ni), and molybdenum (Mo), as well as multilayer films such as titanium / nickel / silver (Ti / Ni / Ag) and titanium / aluminum (Ti / Al).

[0023] Because electrodes (low-potential surface electrode 16, high-potential surface electrode 17, low-potential back electrode 18, and high-potential back electrode 19) are arranged on both sides of the substrate 1 (first main surface 1F side and second main surface 1R side), the capacitor 100 can be easily mounted on a module or the like.

[0024] Next, the basic operation of the capacitor 100 will be explained. A negative voltage is applied to the low-potential surface electrode 16 and the low-potential back electrode 18, and a positive voltage is applied to the high-potential surface electrode 17 and the high-potential back electrode 19. As a result, negative charges are charged to the conductive layer 6 (and protrusions 4) electrically connected to the low-potential surface electrode 16 and the low-potential back electrode 18, and positive charges are charged to the conductive layer 6 electrically connected to the high-potential surface electrode 17 and the high-potential back electrode 19. At this time, polarization occurs inside the dielectric layer 5, and capacitance is generated. The dielectric layer 5 and the conductive layer 6 are stacked and embedded in the groove 2, and these function as a capacitor.

[0025] The manufacturing method for the capacitor according to this embodiment will be described below with reference to the drawings. Note that the manufacturing method for the capacitor described below is just one example, and it can be realized by various other manufacturing methods.

[0026] First, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared. When using a Si substrate, an N-type semiconductor substrate can be manufactured by adding pentavalent elemental impurities such as phosphorus (P) and arsenic (As), and a P-type semiconductor substrate can be manufactured by adding trivalent elemental impurities such as boron (B) and gallium (Ga).

[0027] Next, a groove 2 having a first region 2a and a second region 2b is formed by etching a portion of the substrate 1 from the first main surface 1F to the second main surface 1R, as shown in Figures 2A and 2B. Specifically, first, a mask material is formed on the first main surface 1F of the substrate 1. A silicon oxide film can be used as the mask material, and thermal CVD or plasma CVD can be used as the deposition method. Next, a resist is patterned on the mask material. A general photolithography method can be used as the patterning method. The mask material is etched using the patterned resist as a mask. The mask material has openings in the area where the groove 2 is formed. As the etching method, wet etching using potassium hydroxide aqueous solution, hydrofluoric acid, or hot phosphoric acid, or dry etching such as reactive ion etching can be used. Next, the resist is removed with oxygen plasma or sulfuric acid, etc. Using the mask material formed in this way, the substrate 1 exposed from the openings in the mask material is etched by dry etching to form the groove 2.

[0028] By forming groove 2 using dry etching, groove 2 with a high aspect ratio can be created.

[0029] Grooves 2 may be formed by wet etching. This allows for the formation of grooves 2 at a low cost.

[0030] Next, as shown in Figure 2C, protrusions 4 are formed on the first main surface 1F and the second main surface 1R of the substrate 1 by atmospheric pressure CVD using polysilicon. At this time, since no material gas enters the inside of the groove 2 when polysilicon is formed by atmospheric pressure CVD, it is possible to form protrusions 4 that partially protrude from the first main surface 1F and the second main surface 1R beyond the inner surface 2I of the groove 2.

[0031] Next, as shown in Figure 2D, a dielectric layer 5 is deposited so as to cover the surface of the protrusion 4 and the inner surface 2I of the groove 2. A silicon oxide film can be used as the dielectric layer 5, and thermal oxidation or thermal CVD can be used as the deposition method. Furthermore, when using the thermal CVD method, by using reduced pressure conditions, a silicon oxide film can be deposited with good coverage even when the groove 2 is deep.

[0032] Next, a conductive layer 6 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the dielectric layer 5. A polysilicon film can be used as the conductive layer 6, and a reduced-pressure CVD method can be used for deposition. After deposition of the polysilicon film, an annealing treatment is performed in POCl3 at 950°C to form an N-type polysilicon film, thereby giving conductivity to the conductive layer 6. Here, an N-type polysilicon film is used as an example of the conductive layer 6, but a P-type polysilicon film, a semiconductor film such as silicon germanium, a conductive polysilicon carbide film, or a metal film such as titanium (Ti) or aluminum (Al) can also be used.

[0033] Next, as shown in Figure 2E, a dielectric layer 5 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the conductive layer 6.

[0034] Next, a conductive layer 6 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the dielectric layer 5. At this time, because the groove 2 has a wide first region 2a, even if the space between the tips of the opposing protrusions 4 is first blocked by the dielectric layer 5 and the conductive layer 6, material gas can be introduced into the groove 2 from the first region 2a, and the dielectric layer 5 and the conductive layer 6 can be uniformly formed inside the groove 2.

[0035] Next, as shown in Figure 2F, an interlayer film 7 is deposited on the first main surface 1F and the second main surface 1R of the substrate 1. A silicon oxide film can be used for the interlayer film 7.

[0036] Next, a mask material 8 made of photoresist is formed on the first main surface 1F and the second main surface 1R of the substrate 1, and the mask material 8 is patterned using lithography and etching techniques. The patterned mask material 8 has openings for forming openings 9. Using the mask material 8, the interlayer film 7, conductive layer 6, and dielectric layer 5 exposed from the openings in the mask material 8 are selectively etched in sequence. For example, an anisotropic etching method may be used for the etching method. This forms the openings 9.

[0037] Next, as shown in Figure 2G, an interlayer film 10 is deposited on the first main surface 1F and the second main surface 1R of the substrate 1 so as to fill the opening 9. The interlayer film 10 can be made of silicon oxide.

[0038] Next, a mask material 11 made of photoresist is formed on the first main surface 1F and the second main surface 1R of the substrate 1, and the mask material 11 is patterned using lithography and etching techniques. The patterned mask material 11 has openings for forming openings 12. The interlayer film 10 exposed from the openings of the mask material 11 is selectively etched using the mask material 11. For example, an anisotropic etching method may be used for the etching method. This forms the openings 12.

[0039] Next, as shown in Figure 2H, surface electrodes are deposited to cover the first main surface 1F, and back surface electrodes are deposited to cover the second main surface 1R.

[0040] Next, a mask material 15 made of photoresist is formed on the first main surface 1F and the second main surface 1R of the substrate 1, and the mask material 15 is patterned using lithography and etching techniques. The patterned mask material 15 is used to selectively etch the surface electrode and the back electrode by dry etching. As a result, the surface electrode is divided into a low-potential surface electrode 16 and a high-potential surface electrode 17, and the back electrode is divided into a low-potential back electrode 18 and a high-potential back electrode 19.

[0041] Next, the capacitor 100 is completed by removing the mask material 15.

[0042] In this embodiment, an example in which the substrate 1 is conductive has been described, but the substrate 1 is not limited to this, and may have semiconductor properties or insulating properties. If the substrate 1 is insulating, element isolation becomes easier.

[0043] Furthermore, as shown in Figure 2I, the first region 2a of the groove 2 may be located between the two second regions 2b. By shaping the groove 2 in this way, the material gas used to form the dielectric layer 5 can enter from the center of the groove 2 and reach the ends of the groove 2 in a short distance, thereby enabling the uniform formation of the dielectric layer 5 inside the groove 2.

[0044] Next, the effect of the protrusions 4 on the capacitor 100 will be explained using the structure shown in Figure 3A. The structure shown in Figure 3A consists of a substrate 1 and two protrusions 4. When the total thickness of the structure is H1, the thickness of the substrate 1 is H2, the thickness of one protrusion 4 is T1, the thickness of the other protrusion 4 is T2, the total thickness of all protrusions 4 (sum of T1 and T2) is T, the width of the substrate 1 is W1, and the width of the protrusion 4 from the side surface of the substrate 1 (inner surface 2I of the groove 2) to the tip is W2, the change in the section modulus, which represents the rigidity of the substrate 1, was calculated when T was varied while H1 was 525 μm, W1 was 20 μm, and W2 was 3 μm. The calculation results are shown in Figure 3B.

[0045] The dotted line in Figure 3B shows the section modulus when W1 is changed from 20 μm to 26 μm in the configuration without the protrusion 4 (substrate 1 only: H1=H2=525 μm), and it can be seen that it is proportional to the volume of substrate 1. On the other hand, the black circles (●) in Figure 3B show that in the configuration with the protrusion 4, the section modulus increases sharply as T becomes thicker, and it can be seen that the section modulus of the structure (substrate 1) increases as the overall volume of the structure increases.

[0046] Furthermore, using T as a baseline of 0, the rate of increase in section modulus when T is increased saturates when T reaches approximately 60% of H1. Therefore, by adjusting T to 1-60% of H1, the rigidity per unit volume of substrate 1 can be efficiently increased.

[0047] According to this embodiment, the projection 4 increases the section modulus of the entire structure consisting of the substrate 1 and the projection 4, thereby increasing the rigidity of the substrate 1 in which the groove 2 is provided when stress from the dielectric layer 5 is applied to the substrate 1.

[0048] Furthermore, if the sum of the thickness of the projection 4 on the first main surface 1F and the thickness of the projection 4 on the second main surface 1R is between 1% and 60% of the sum of the thickness of the substrate 1 and the thickness of the two projections 4, the rigidity per unit volume of the substrate 1 can be efficiently increased.

[0049] (Second Embodiment) Referring to Figures 4 and 5A, the configuration of the capacitor according to the second embodiment will be described. Compared to the capacitor 100 shown in Figure 1, capacitor 100A is provided with a substrate 1 having grooves 2 formed on the first main surface 1F that do not reach the second main surface 1R.

[0050] The capacitor 100A includes a low-potential surface electrode 16 (first electrode) and a high-potential surface electrode 17 (second electrode) formed on the first main surface 1F side. The low-potential surface electrode 16 is electrically connected to the projection 4 and the conductive layer 6. The high-potential surface electrode 17 is electrically connected to the conductive layer 6, which is not electrically connected to the low-potential surface electrode 16 and the low-potential back electrode 18. In this embodiment, the low-potential electrode corresponds to the first electrode and the high-potential electrode corresponds to the second electrode, but the reverse may also be true.

[0051] In this embodiment, five openings 12 are formed on the first main surface 1F. Low-potential surface electrodes 16 are formed in three of the openings 12 on the first main surface 1F side, and high-potential surface electrodes 17 are formed in two of the openings 12 on the first main surface 1F side.

[0052] As shown in Figure 5A, when viewed from the direction normal to the first main surface 1F, groove 2 has a first width W. a A first region 2a having a first width W a Shorter second width W b The groove 2 has a second region 2b having a second region 2a. In this embodiment, the second region 2b is located between the two first regions 2a. By having this groove shape, the material gas used when forming the dielectric layer 5, which will be described later, enters from one of the first regions 2a of the groove 2, passes through the second region 2b, and exits from the other first region 2a, so that the dielectric layer 5 inside the groove 2 can be formed uniformly.

[0053] Furthermore, the opening of the groove 2 may be closed by the projection 4. In this case as well, the section modulus of the entire structure consisting of the substrate 1 and the projection 4 becomes larger, thereby increasing the rigidity of the substrate 1 in which the groove 2 is provided when stress from the dielectric layer 5 is applied to the substrate 1.

[0054] Furthermore, the dielectric layer 5 and the conductive layer 6 are the same as in the first embodiment, so a further explanation is omitted.

[0055] Since the basic operation of capacitor 100A is the same as in the first embodiment, a further explanation will be omitted.

[0056] The manufacturing method for the capacitor according to this embodiment will be described below with reference to the drawings. Note that the manufacturing method for the capacitor described below is just one example, and it can be realized by various other manufacturing methods.

[0057] Similar to the first embodiment, first, a semiconductor substrate (substrate 1) doped with a high concentration of N-type or P-type impurities is prepared. Next, a groove 2 having a first region 2a and a second region 2b is formed by etching a part of the first main surface 1F of substrate 1, as shown in Figures 5A and 5B.

[0058] Next, as shown in Figure 5C, protrusions 4 are formed on the first main surface 1F of the substrate 1 by atmospheric pressure CVD using polysilicon. At this time, since no material gas enters the inside of the groove 2 when polysilicon is formed by atmospheric pressure CVD, it is possible to form protrusions 4 in which a portion protrudes from the first main surface 1F further inward than the inner surface 2I of the groove 2.

[0059] Next, as shown in Figure 5D, a dielectric layer 5 is deposited so as to cover the surface of the protrusion 4 and the inner surface 2I of the groove 2. Then, a conductive layer 6 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the dielectric layer 5.

[0060] Next, as shown in Figure 5E, a dielectric layer 5 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the conductive layer 6. Next, a conductive layer 6 is deposited on the surface of the protrusion 4 and the inner surface 2I of the groove 2 so as to cover the dielectric layer 5. At this time, because the groove 2 has a wide first region 2a, even if the space between the tips of opposing protrusions 4 is first blocked by the dielectric layer 5 and the conductive layer 6, material gas can be introduced into the groove 2 from the first region 2a, and the dielectric layer 5 and the conductive layer 6 can be uniformly formed inside the groove 2.

[0061] Next, as shown in Figure 5F, an interlayer film 7 is deposited on the first main surface 1F of the substrate 1. The interlayer film 7 can be a silicon oxide film. Next, a mask material 8 made of photoresist is formed on the first main surface 1F of the substrate 1, and the mask material 8 is patterned using lithography and etching techniques. The patterned mask material 8 has openings for forming openings 9. Using the mask material 8, the interlayer film 7, conductive layer 6, and dielectric layer 5 exposed from the openings in the mask material 8 are selectively etched in sequence. For example, an anisotropic etching method may be used for the etching method. This forms the openings 9.

[0062] Next, as shown in Figure 5G, an interlayer film 10 is deposited on the first main surface 1F of the substrate 1 so as to fill the opening 9. The interlayer film 10 can be a silicon oxide film. Next, a mask material 11 made of photoresist is formed on the first main surface 1F of the substrate 1, and the mask material 11 is patterned using lithography and etching techniques. The patterned mask material 11 has openings for forming the opening 12. The interlayer film 10 exposed from the openings of the mask material 11 is selectively etched using the mask material 11. For example, an anisotropic etching method may be used for the etching method. This forms the opening 12.

[0063] Next, as shown in Figure 5H, surface electrodes are deposited to cover the first main surface 1F. Then, a mask material 15 made of photoresist is formed on the first main surface 1F of the substrate 1, and the mask material 15 is patterned using lithography and etching techniques. The surface electrodes are selectively etched by dry etching using the patterned mask material 15. As a result, the surface electrodes are divided into low-potential surface electrodes 16 and high-potential surface electrodes 17.

[0064] Through the above steps, the 100A capacitor is completed.

[0065] According to the manufacturing method of the capacitor 100A of the second embodiment, the same effects and advantages as in the first embodiment can be obtained.

[0066] (Third embodiment) This embodiment describes the configuration of a grooved substrate that can be used in the first and second embodiments. In this embodiment, a grooved substrate and protrusions are formed by bonding multiple substrates with different groove shapes at room temperature. The specific configuration and formation method of the substrate are shown below.

[0067] As shown in Figure 6A, by sandwiching a substrate 1b having groove 2B between a substrate 1a having groove 2A and a substrate 1c having groove 2A and bonding them at room temperature, a substrate 1A having a groove 2 that penetrates from the substrate 1a side to the substrate 1c side can be formed, as shown in Figure 6B. A portion of the area around groove 2A on substrate 1a and a portion of the area around groove 2A on substrate 1c form a projection 4.

[0068] Furthermore, as shown in Figure 6C, a substrate 1b having groove 2B can be sandwiched between a substrate 1a having groove 2A and a substrate 1d, and these are bonded at room temperature to form a substrate 1B having groove 2 as shown in Figure 6D. A portion of the area around groove 2A on substrate 1a forms a projection 4.

[0069] Furthermore, as shown in Figure 6E, by sandwiching the substrate 1b having groove 2B between substrate 1e and substrate 1d having groove 2C and bonding them at room temperature, a substrate 1C having a cavity groove 2, as shown in Figure 6F, can be formed.

[0070] Furthermore, as shown in Figure 6G, by sandwiching a substrate 1b having groove 2B between two substrates 1e having groove 2C and another substrate 1e having groove 2C, and bonding them at room temperature, a substrate 1D having a groove 2 that penetrates from the substrate 1e side to the substrate 1f side and has a cavity can be formed, as shown in Figure 6H.

[0071] According to this embodiment, grooves as shown in the first and second embodiments can be formed by bonding multiple substrates with different groove shapes at room temperature. As a result, the section modulus of the entire structure consisting of the substrate and the protrusions becomes larger, and the rigidity of the substrate can be increased when stress on the dielectric layer is applied to the substrate.

[0072] (Other embodiments) The embodiments described above are examples of ways in which the present invention can be implemented. Therefore, the present invention is not limited to the embodiments described above, and it goes without saying that various modifications can be made to other embodiments, as long as they do not depart from the technical spirit of the present invention, depending on the design and other factors. [Explanation of symbols]

[0073] 1, 1A, 1B, 1C, 1D, 1a, 1b, 1c, 1d, 1e substrate 1st Floor, Main Panel Round 1, Main Field 2 2, 2A, 2B, 2C groove 2I Inner Self 2a 1st area 2b 2nd area 4 Protrusion 5 Dielectric layer 6. Conductive layer 7, 10 Interlaminar membrane 8, 11, 15 Masking material 9, 12 Openings 16 Low potential surface electrode 17 High potential surface electrode 18 Low-potential back surface electrode 19 High-potential back surface electrode 100, 100A capacitor

Claims

1. A substrate having a first main surface, a second main surface opposite to the first main surface, and a groove formed on the first main surface, A first projection, part of which is positioned on the first main surface of the substrate, and the other part which protrudes from the first main surface further inward than the inner surface of the groove, At least two or more dielectric layers and two or more conductive layers are alternately laminated on the surface of the first projection and the inner surface of the groove, A first electrode formed on the first main surface, the first electrode being electrically connected to the first projection or at least one of the conductive layers, The invention comprises a second electrode formed on the first main surface, which is not electrically connected to the first electrode, but is electrically connected to the first projection or at least one of the conductive layers, Viewed from the direction normal to the first main surface, the groove has a first region having a first width and a second region having a second width shorter than the first width. Capacitor.

2. The capacitor according to claim 1, wherein the distance between the inner surfaces of the opposing pair of grooves is longer than the distance between the tips of the pair of first protrusions that each protrude inward into the grooves than the pair of inner surfaces.

3. The capacitor according to claim 1, wherein the opening of the second region of the groove is closed by the first projection.

4. The capacitor according to claim 1, wherein the second region is located between the two first regions.

5. The capacitor according to claim 1, wherein the first region is located between the two second regions.

6. The capacitor according to claim 1, wherein the groove penetrates between the first main surface and the second main surface.

7. The capacitor according to claim 1, further comprising a second projection, the latter part of which is positioned on the second main surface of the substrate and the latter part which protrudes from the second main surface further inward than the inner surface of the groove.

8. The capacitor according to claim 7, wherein the sum of the thickness of the first projection and the thickness of the second projection is 1 to 60% of the sum of the thickness of the substrate, the thickness of the first projection, and the thickness of the second projection.

9. The capacitor according to claim 1, wherein the dielectric layer is made of silicon nitride.

10. The capacitor according to claim 1, wherein the dielectric layer is made of silicon oxide.

11. The capacitor according to claim 1, wherein the conductive layer is made of polysilicon.

12. The capacitor according to claim 1, wherein the conductive layer is made of metal.

13. The capacitor according to claim 1, wherein the substrate is conductive.

14. The capacitor according to claim 1, wherein the substrate is insulating.

15. A method for manufacturing a capacitor according to any one of claims 1 to 14, A method for manufacturing a capacitor in which the first protrusion is formed by a normal pressure CVD method using polysilicon.

16. The capacitor according to claim 15, wherein a first substrate having a first groove formed thereon and a second substrate having a second groove having a different shape from the first groove formed thereon are bonded at room temperature to form the substrate and the first projection. A method for manufacturing this product.

17. A method for manufacturing a capacitor according to claim 15, wherein the groove is formed by dry etching.

18. A method for manufacturing a capacitor according to claim 15, wherein the groove is formed by wet etching.

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