Information processing device, information processing method, program, and circuit information

Abstract

To generate a combination optimization problem at high speed.SOLUTION: An information processing device according to an embodiment performs processing for data. The information processing device comprises a solver device and an information processing circuit. The information processing circuit acquires data. The information processing circuit generates a combination optimization problem on the basis of the data, and causes the solver device to solve the combination optimization problem. A first portion weight group, which is a part of a plurality of weighted values, is the same as a second portion weight group, which is a portion of others. The information processing circuit writes the first portion weight group and the second portion weight group into a common region in a first memory, and gives first information indicative of a storage location of each of the plurality of weighted values in the first memory to the solver device. The solver device reads the plurality of weighted values from the first memory and finds the solution, on the basis of the first information.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] This invention relates to an information processing device, an information processing method, a program, and circuit information. [Background technology]

[0002] The optimization of systems in various application fields such as control, finance, communications, logistics, and chemistry can often be mathematically reduced to combinatorial optimization problems. By solving combinatorial optimization problems, information processing systems have been proposed that realize and improve the efficiency of various information processing functions such as recognition, judgment, and planning.

[0003] A combinatorial optimization problem is a problem in which a cost function is defined with multiple decision variables (e.g., discrete variables) representing the state of the system to be optimized as arguments, and the goal is to find the combination of values ​​for these decision variables that minimizes the defined cost function. The state of the system represented by the multiple decision variables is called a solution. In a combinatorial optimization problem, the number of possible solution states increases exponentially as the number of decision variables increases. This increase in the number of possible solution states is called a combinatorial explosion. Combinatorial optimization, which involves selecting the optimal solution from all candidate solutions, is known to be a computationally difficult problem. Performing large-scale combinatorial optimization in a short amount of time remains a challenging task.

[0004] In recent years, a specific-purpose device called an Ising machine, which searches for the ground state of the Ising spin model, has attracted attention. The problem of searching for the ground state of the Ising spin model is called the Ising problem. The Ising problem is a combinatorial optimization problem that minimizes a cost function given by a quadratic function of the Ising spin, which is one of the binary variables. In the Ising problem, the cost function is called the Ising energy. Many practical combinatorial optimization problems can be transformed into Ising problems. Ising machines can solve Ising problems at high speed. Therefore, many practical combinatorial optimization problems can be solved quickly using Ising machines.

[0005] Incidentally, in situations where circumstances change moment by moment, it is sometimes necessary to generate and solve new combinatorial optimization problems in response to the changes in circumstances, and then process the data based on the obtained solutions. For example, when applying combinatorial optimization problems to trading devices that electronically trade stocks in a financial market, new combinatorial optimization problems are generated in response to fluctuations in stock prices, and trades are executed based on the obtained solutions. Similarly, when applying combinatorial optimization problems to a control system that controls a moving object based on images of the surrounding scenery, new combinatorial optimization problems are generated in response to changes in the images, and the moving object is controlled based on the obtained solutions.

[0006] In such a system, a combinatorial optimization problem is generated each time the situation changes, and this generated combinatorial optimization problem is fed to the solver. For example, if the combinatorial optimization problem is an N-size Ising problem, then N × N quadratic coefficients and N linear coefficients must be generated and fed to the solver. Therefore, in such a system, in order to improve the responsiveness from the time the situation changes until processing based on the solution, it is preferable to be able to generate the combinatorial optimization problem quickly and feed it to the solver. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 6629864 [Patent Document 2] Japanese Patent Publication No. 2021-060864 [Patent Document 3] Japanese Patent Publication No. 2019-145010 [Patent Document 4] Japanese Patent Publication No. 2019-159566 [Patent Document 5] Japanese Patent Publication No. 2021-043667 [Patent Document 6] Japanese Patent Publication No. 2021-043589 [Non-patent literature]

[0008] [Non-Patent Document 1] Hayato Goto, Kosuke Tatsumura and Alexander R. Dixon, “Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems,” Science Advances 5, eaav2372, 2019 [Non-Patent Document 2] Hayato Goto, Kotaro Endo, Masaru Suzuki, Yoshisato Sakai, Taro Kanao, Yohei Hamakawa, Ryo Hidaka, Masaya Yamasaki and Kosuke Tatsumura, “High-performance combinatorial optimization based on classical mechanics”, Science Advances 7, eabe7953, 2021 [Overview of the project] [Problems that the invention aims to solve]

[0009] The problem that this invention aims to solve is to generate combinatorial optimization problems at high speed. [Means for solving the problem]

[0010] The information processing device according to the embodiment performs processing on data. The information processing device comprises a solver device for solving a combinatorial optimization problem and an information processing circuit. The information processing circuit acquires the data. The information processing circuit generates the combinatorial optimization problem based on the data and causes the solver device to solve the combinatorial optimization problem. The cost function in the combinatorial optimization problem includes a plurality of decision variables and a plurality of weight values. The terms included in the cost function are expressed by multiplying one or more decision variables from the plurality of decision variables by any one of the plurality of weight values. A first subweight group, which is a part of the plurality of weight values, is the same as a second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values. In generating the combinatorial optimization problem, the information processing circuit generates the plurality of weight values ​​based on the data and writes the plurality of weight values ​​to the first memory. The information processing circuit writes the first sub-weight group and the second sub-weight group to a common area in the first memory when writing the plurality of weight values, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. Based on the first information, the solver device reads the plurality of weight values ​​from the first memory and finds the solution. [Brief explanation of the drawing]

[0011] [Figure 1] A diagram illustrating a model of the Ising problem. [Figure 2] A diagram showing the internal variables used by the simulated branching algorithm. [Figure 3] A flowchart illustrating the processing flow of a simulated branching machine. [Figure 4] A diagram showing the configuration of an information processing system equipped with an Ising machine. [Figure 5] A diagram illustrating the configuration of an information processing system equipped with a simulated branching machine. [Figure 6] A diagram illustrating the structure of the market system. [Figure 7]A diagram illustrating the configuration of the information processing device according to the first embodiment. [Figure 8] A diagram showing the processing timing of an information processing device. [Figure 9] A diagram showing pseudocode for generating the Q matrix. [Figure 10] A diagram showing an example of multiple weight values. [Figure 11] A diagram showing M subregions, K patterns, and pattern information. [Figure 12] A diagram showing the configuration of a solver apparatus according to the second embodiment. [Figure 13] A diagram showing the configuration of a solver apparatus according to the third embodiment. [Figure 14] Diagram of the arithmetic circuit configuration. [Figure 15] Configuration diagram of the action calculation circuit. [Figure 16] A diagram showing matrix (J). [Figure 17] Configuration diagram of the matrix operation circuit according to the third embodiment. [Figure 18] Configuration diagram of the matrix operation circuit according to the fourth embodiment. [Figure 19] A diagram showing an example of the control system configuration. [Figure 20] Hardware configuration diagram of an information processing device. [Modes for carrying out the invention]

[0012] (Premise) First, we will explain the terminology and technology that are prerequisites for describing the embodiments.

[0013] A combinatorial optimization problem is a problem in which a cost function is defined with multiple decision variables (e.g., discrete variables) representing the state of the system to be optimized as arguments, and the problem is solved by finding the combination of values ​​of the multiple decision variables that minimizes the defined cost function. The cost function is a function of order one or higher that includes multiple decision variables representing the state of the system as arguments. For example, the cost function can be expressed as a linear or quadratic function of the multiple decision variables. The cost function may also be a function of order three or higher that includes multiple decision variables. In other words, the cost function is a function that sums up multiple terms. Each of the multiple terms is a function that multiplies one or more predetermined number of decision variables from the multiple decision variables by a coefficient. The coefficient in each of the multiple terms is a real number and is also called a weight value. That is, each of the multiple terms that make up the cost function is expressed by multiplying one or more decision variables from the multiple decision variables by one of the weight values.

[0014] The state of a system, as represented by multiple decision variables, is called a solution. The set of all possible solutions for the state of the system is called the solution space. The solution that gives the minimum value of the cost function is called the exact solution. A solution that gives a value close to the minimum of the cost function is called a good solution.

[0015] An exact solution method is a method for solving a combinatorial optimization problem that finds an exact solution that minimizes the cost function, and it is guaranteed that the solution is an exact solution.

[0016] A heuristic solution is a method for solving combinatorial optimization problems that seeks either an exact solution that minimizes the cost function or a good solution that is close to the minimum. Heuristic solutions are also called heuristic solutions. Heuristic solutions do not guarantee the accuracy of the solution, i.e., how close the solution is to the minimum of the cost function. Heuristic solutions can produce solutions with practically significant accuracy in a shorter time than exact solutions.

[0017] The computational complexity of solving a combinatorial optimization problem is the number of operations required to obtain the solution, such as the number of multiply-accumulate operations. The time required to solve a combinatorial optimization problem depends not only on the computational complexity but also on the configuration of the computer that performs the operations. For example, the solving time decreases as the degree of parallelism and operating frequency of the computer increase.

[0018] The QUBO (Quadratic Unconstrained Binary Optimization) problem is an unconstrained quadratic optimization problem where the decision variable is binary. In a QUBO problem, each of the multiple terms in the cost function is expressed as a linear or quadratic expression of the decision variable. In the strict definition, a QUBO problem is one where the decision variable is a binary variable of 0 or 1. In this embodiment, the QUBO problem represents the strict definition problem where the decision variable is 0 or 1. In the strict definition of a QUBO problem, the decision variable is sometimes called a bit variable.

[0019] The cost function for the QUBO problem is given by H in equation (1). total_QUBO It is represented by [this].

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[0020] FIG. 1 is a diagram showing a model of the Ising problem. The Ising problem is a problem of searching for the ground state of the Ising model. The Ising problem is one of the QUBO problems. The decision variables of the Ising problem represent discrete variables of -1 or +1.

[0021] The cost function of the Ising problem is H in Equation (2) total_Ising which is represented by.

Number

[0022] The QUBO problem where the decision variable is s i corresponds to the problem of searching for the ground state of the Ising model, which is one of the magnetic models in statistical mechanics. Therefore, s i is sometimes called a spin variable. Also, N, which is the number of decision variables, is sometimes called the number of spins. Also, H total_Ising is sometimes called the Ising energy. H total_Ising The vector represented by the N s [[ID=4C]] i for which becomes the minimum value is sometimes called the ground state (ground spin configuration).

[0023] The cost functions of the QUBO problem and the Ising problem differ only in the value of the constant. Therefore, the QUBO problem and the Ising problem are identical as combinatorial optimization problems. In other words, the QUBO problem and the Ising problem can be converted to each other. For example, the Ising problem and the QUBO problem can be converted to each other by equations (3-1), (3-2), (3-3), and (3-4).

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[0024] The QUBO and Ising problems are known to be NP-complete. That is, many NP-hard problems can be transformed into either a QUBO or an Ising problem in polynomial time. Therefore, many practical combinatorial optimization problems can be transformed into either a QUBO or an Ising problem.

[0025] An Ising machine is a device that solves the Ising problem. Many Ising machines solve the Ising problem using heuristic methods. Various Ising machines based on principles from fields such as electronics, optics, quantum mechanics, and statistical mechanics have been proposed. Many Ising machines can produce an exact solution or a good solution in a short amount of time.

[0026] Simulated bifurcation algorithms are algorithms for solving combinatorial optimization problems. Simulated bifurcation algorithms are heuristic solution algorithms.

[0027] Simulated bifurcation algorithms are shown, for example, in Non-Patent Documents 1-2 and Patent Documents 2-6. Because simulated bifurcation algorithms were discovered inspired by quantum mechanical optimization methods based on the quantum adiabatic theorem, they are also called quantum-inspired algorithms. Simulated bifurcation algorithms can solve combinatorial optimization problems where the cost function is a quadratic function of multiple decision variables. Simulated bifurcation algorithms can also solve combinatorial optimization problems where the cost function is a function of order 3 or higher of multiple decision variables, i.e., HUBO (Higher Order Binary Optimization) problems. For example, a simulated bifurcation algorithm for solving the HUBO problem is shown in Patent Document 5. Furthermore, simulated bifurcation algorithms can also solve combinatorial optimization problems where some or all of the multiple decision variables include continuous variables. A simulated bifurcation algorithm for solving combinatorial optimization problems where some or all of the multiple decision variables include continuous variables is shown in Patent Document 6.

[0028] A simulated branching machine is a computing device that performs processing according to a simulated branching algorithm. A simulated branching machine that solves the QUBO problem or the Ising problem is an example of an Ising machine. In this embodiment, the simulated branching machine solves the Ising problem.

[0029] Figure 2 shows the internal variables used by the simulated branching algorithm.

[0030] The simulated branching algorithm has N decision variables (s1~s N When solving a combinatorial optimization problem in which the cost function is expressed using ), the internal variables are N position variables (x1~x N ) and N momentum variables (y1~y N The simulated branching algorithm uses 2 × N internal variables.

[0031] N position variables (x i ) consists of N decision variables (si It corresponds one-to-one with the i-th position variable (x) among the N position variables. i ) is the i-th decision variable (s) among the N decision variables. i ) corresponds to N momentum variables (y i ) consists of N decision variables (s i It corresponds one-to-one with the i-th momentum variable (y) among the N momentum variables. i ) is the i-th decision variable (s) among the N decision variables. i ) corresponds to this.

[0032] Figure 3 is a flowchart showing the processing flow of a simulated branching machine. The simulated branching machine executes processing according to the simulated branching algorithm in the flow shown in Figure 3.

[0033] First, in S11, the simulated branching machine obtains the Ising problem. Specifically, the simulated branching machine obtains J, which is a matrix containing N × N coefficients, and h, which contains N bias coefficients.

[0034] Next, in S12, the simulated branching machine has 2 × N internal variables, i.e., N position variables (x1~x N ) and N momentum variables (y1~y N Initialize the N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y N The initial values ​​of both or either of the following may be obtained from an external source. In addition, the simulated branching machine has N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y N The initial value of ) may be generated by a random number generation circuit or set to a predetermined value. Note that since the simulated branching machine is a heuristic, even for the same problem, the N position variables (x1~x N Initial values ​​of ) and N momentum variables (y1~y NIf at least one of the initial values ​​of ) is different, it may output different good solutions.

[0035] Next, the simulated branching machine repeats the process from S14 to S16 a predetermined number of times (loop processing between S13 and S17). The process from S14 to S16 involves N position variables (x1~x N A matrix operation that performs matrix multiplication of ) and a matrix containing weight values ​​in N rows × N columns, and N position variables (x1~x N ) and N momentum variables (y1~y N This is a time evolution process for evolving ) over time.

[0036] In S14, the simulated bifurcation machine has N momentum variables (y1~y N The simulated branching machine performs a y-update process that updates each of the i-th momentum variable (y) in the y-update process. i In the update process of ), N position variables (x1~x N ) and the i-th position variable (x) of the N×N matrix (J). i ) and other (N-1) position variables (x 1~i-1, x i+1~N N coefficients (J) representing the interaction between ) i,j ) and the i-th bias coefficient (h i ) and the i-th momentum variable (y i ) Update.

[0037] Next, in S15, the simulated branching machine has N position variables (x1~x N The simulated branch machine executes an x ​​update process that updates each of the i-th position variable (x) in the x update process. i In the update process of ), the i-th momentum variable (y i ) determines the i-th position variable (x i ) Update.

[0038] The simulated branching machine may execute the processes of S14 and S15 in a reversed order.

[0039] Next, in S16, the simulated branching machine has N position variables (x1~x N The simulated bifurcation machine performs wall processing on position variables whose absolute value exceeds 1. Furthermore, the simulated bifurcation machine also performs wall processing on momentum variables corresponding to position variables whose absolute value exceeds 1. For example, in wall processing, the simulated bifurcation machine changes the absolute value of position variables whose absolute value exceeds 1 to a value of 1 or less, while keeping the sign the same. Also, for example, in wall processing, the simulated bifurcation machine changes the value of momentum variables corresponding to position variables whose absolute value exceeds 1 to 0.

[0040] Simulated bifurcation algorithms have variations in the x-update, y-update, and wall-update operations. For example, variations of the simulated bifurcation algorithm include the adiabatic simulated bifurcation (aSB) algorithm, the ballistic simulated bifurcation (bSB) algorithm, and the discrete simulated bifurcation (dSB) algorithm.

[0041] When executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine performs the operation shown in equation (4-1) in the y update process (S14) and the operation shown in equation (4-2) in the x update process (S15). Note that when executing processing according to the adiabatic simulated branching algorithm, the simulated branching machine does not perform the wall process (S15).

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[0042] When performing processing according to the ballistic simulated branching algorithm, the simulated branching machine performs the operation shown in equation (5-1) in the y update process (S14), the operation shown in equation (5-2) in the x update process (S15), and the operation shown in equation (5-3) in the wall processing (S16).

number

[0043] When executing a process according to a discrete simulated branching algorithm, the simulated branching machine performs the operation shown in equation (6-1) in the y update process (S14), the operation shown in equation (6-2) in the x update process (S15), and the operation shown in equation (6-3) in the wall process (S16).

number

[0044] Note that in equations (4-1), (4-2), (5-1), (5-2), (5-3), (6-1), (6-2), and (6-3), t k and t k+1 t represents time. k+1 is, t k This is the time obtained by adding a unit of time (Δt) to that value.

[0045] x i (t k ) is time (t k The i-th position variable (x) in ) i The value of x is shown. i (t k+1 ) is time (t k+1 The i-th position variable (x) in ) i The value of ) is shown. i (t k ) is time (t k The i-th momentum variable (y i The value of ) is shown. i (t k+1 ) is time (t k+1 The i-th momentum variable (yi indicates the value of

[0046] K, a0, η, and c0 are predetermined constants. a(t k ) is a function that changes according to time. a(t k ) is, for example, a positive real number that satisfies a(t1) = 0 and increases as time increases, and becomes a0 at the end time (T) (a(T) = a0). Also, sgn(x i (t k )) is a function that outputs the sign of the i-th position variable (x k ) at time (t i ). If x i (t k ) is 0 or greater, it is +1, and if x i (t k ) is less than 0, it is -1.

[0047] When the simulated branch machine executes the processes of S14 to S16 a predetermined number of times, that is, when the operation is executed until the time t reaches the final time T, it exits the loop process between S13 and S17 and advances the process to S18.

[0048] In S18, the simulated branch machine outputs N decision variables (s1 to s N ) calculated based on the N position variables (x1 to x N ) at the final time, or the N position variables (x1 to x N ) at the final time. The simulated branch machine calculates the i-th decision variable (s N ) among the N decision variables (s1 to s i ) based on sgn(x i ).

[0049] When the simulated branch machine finishes the process of S18, it finishes the process according to the simulated branch algorithm.

[0050] The number of iterations of the time evolution process (the loop between S13 and S17) is predetermined according to the application. The computational complexity required for one iteration of the time evolution process (one iteration from S14 to S16) does not vary. Therefore, the simulated branching machine can minimize the variation in solution time. Consequently, even when applied to real-time systems with time constraints that require processing to be completed by a predetermined time, the simulated branching machine can reliably output a solution within that time.

[0051] Furthermore, as shown in Patent Document 2, for example, a simulated branch machine can be configured using a dedicated parallel processing circuit that includes a large number of arithmetic units. This allows the simulated branch machine to extremely reduce the computation time of a single process in the time evolution process. In addition, unlike software processing, a simulated branch machine implemented in a dedicated hardware circuit does not experience any interrupt processing, so the solution time is strictly fixed. For example, a simulated branch machine implemented in a dedicated hardware circuit can fix the time until a solution is obtained in units of clock cycles. Therefore, when a simulated branch machine implemented in a dedicated hardware circuit is applied to a real-time system, it can output a solution while more reliably adhering to time constraints.

[0052] Figure 4 shows the configuration of an information processing system comprising an Ising machine and a host device. An information processing system capable of solving combinatorial optimization problems can be configured, for example, with an Ising machine and a host device. The host device performs processing other than that performed by the Ising machine. In this case, the Ising machine is introduced for the purpose of shortening the time required to solve combinatorial optimization problems and is considered an accelerator or offloader. The host device includes a general-purpose processor and offloaders other than the Ising machine, memory, storage, sensors, actuators, communication interfaces, etc.

[0053] The host device provides at least information for specifying a QUBO problem (matrix (Q)) or information for specifying an Ising problem (matrix (J) and bias coefficient array (h)) to the Ising machine. The Ising machine may acquire information for specifying a QUBO problem (matrix (Q)) and convert it into information for specifying an Ising problem (matrix (J) and bias coefficient array (h)). Then, after the optimization process, the Ising machine returns, as a solution, the arrangement information (s N ) representing N decision variables (s1 to s opt ) to the host device.

[0054] FIG. 5 is a diagram showing the configuration of an information processing system including a simulated branching machine and a host device.

[0055] An information processing system having a function of solving a combinatorial optimization problem may include a simulated branching machine as an Ising machine. In this case, the host device provides information for specifying an Ising problem (matrix (J) and bias coefficient (h)) to the simulated branching machine. Further, the host device may provide initial values of N position variables (x1 to x N ) and initial values of N momentum variables (y1 to y N ) to the simulated branching machine. Also, the host device may provide various constants and functions (e.g., K, a0, c 0、 a(t) and Δt, etc.) used in the simulated branching algorithm to the simulated branching machine. After the optimization process, the simulated branching machine may return, as a solution, the arrangement information (x N ) representing N position variables (x1 to x opt ) instead of the arrangement information (s N ) representing N decision variables (s1 to s opt ) to the host device.

[0056] (First Embodiment) Next, the market system 10 according to the first embodiment will be described.

[0057] Figure 6 shows the configuration of the market system 10. The market system 10 executes electronic transactions of multiple assets by multiple participants. More specifically, for each of the assets, the market system 10 receives buy and sell orders from each of the multiple participants, matches the price and quantity of the received buy orders with the price and quantity of the sell orders, and electronically completes the transactions.

[0058] In this embodiment, the market system 10 executes buy and sell transactions of multiple stocks (stocks of multiple issues) as electronic transactions of multiple assets. The assets are not limited to stocks, but may also include securities such as bonds, equity investment trusts, and real estate investment trusts, and their futures, as well as financial instruments such as foreign exchange, interest rates, and interest rate futures, or commodities such as gold, crude oil, and grains, and their futures.

[0059] The market system 10 comprises a market server device 12 and a plurality of client devices 14.

[0060] The market server device 12 is a computer used by the market administrator. The market server device 12 is connected to multiple client devices 14 via a network.

[0061] Each of the client devices 14 is a device used by market participants. Each of the client devices 14 is implemented, for example, by a computer.

[0062] Each of the multiple client devices 14 decides which of the multiple stocks it will trade. Each of the multiple client devices 14 generates an order packet containing trading information for the stock it decided to trade and sends it to the market server device 12. The order packet includes, as trading information, for example, identification information that identifies the stock to be traded from among the multiple stocks, the direction of the buy or sell order representing a buy or sell order for the stock identified by the identification information, the price (i.e., stock price), and the quantity (i.e., number of shares). Note that the price is not limited to a specific value, but may be, for example, the price at the time a trade is executed after the market opens, or a value with a certain range.

[0063] The market server device 12 executes trades for multiple stocks. The market server device 12 includes a receiving unit 16, a matching unit 17, and a distribution unit 18.

[0064] The receiving unit 16 receives order packets transmitted from each of the multiple client devices 14. The receiving unit 16 provides the information of the received order packets to the matching unit 17.

[0065] The matching unit 17 matches the price and quantity of sell orders with the price and quantity of buy orders for each of the multiple shares, and executes transactions between sell orders and buy orders with matching prices and quantities in the order they are received. The matching unit 17 provides the distribution unit 18 with information about the executed orders and information about the unexecuted orders.

[0066] The distribution unit 18, based on information obtained from the matching unit 17, simultaneously distributes market information packets containing information indicating the status of stock trading to multiple client devices 14. A market information packet is generated, for example, for each of multiple stocks. The market information packet includes identification information that identifies the stock, and the trading price, which is the latest price at which a transaction was completed for the stock identified by the identification information.

[0067] Furthermore, the market information packet may include quote information for each of the multiple stocks. The quote information includes information indicating the price and quantity of unexecuted buy orders and information indicating the price and quantity of unexecuted sell orders for each of the multiple stocks.

[0068] The distribution unit 18 distributes market information packets irregularly. For example, when a transaction is completed, the distribution unit 18 distributes market information packets for the shares that have been traded. For example, each of the multiple client devices 14 acquires the irregularly distributed market information packets and, based on the information contained in the acquired market information packets, decides which of the multiple shares to trade. Then, each of the multiple client devices 14 generates an order packet for the decided shares and sends it to the market server device 12.

[0069] The information processing device 20 according to this embodiment functions as a client device 14 in the market system 10. The information processing device 20 may be implemented by a computer including a processor and memory, or it may be configured to include a dedicated hardware circuit in addition to a processor and memory.

[0070] Here, the information processing device 20 generates a combinatorial optimization problem based on market information packets acquired irregularly, solves the generated combinatorial optimization problem, and decides whether or not to trade each of the multiple stocks based on the solution to the combinatorial optimization problem obtained.

[0071] In this embodiment, the information processing device 20 uses the function shown in equation (7) as the cost function in the combinatorial optimization problem.

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[0072] In equation (7), N is an integer greater than or equal to 2, and represents the number of stock issues traded on the market server device 12. i is an integer greater than or equal to 1 and less than or equal to N, and is an index that identifies each of the stock issues.

[0073] The cost function in equation (7) contains N decision variables. i This is a binary value of 0 or 1, and is a decision variable that indicates whether or not to trade the i-th stock out of multiple stocks. In this embodiment, b i This value represents 1 if a transaction is made and 0 if no transaction is made.

[0074] t represents any time between the start time and the end time of trading within a single day. t is 0 at the start time of trading and increases as time progresses from the start time. In this embodiment, t is an integer and represents the time using an index.

[0075] p i (t) is the trading price of the i-th stock at time t, i.e., the stock price at time t. i (0) is the trading price of the i-th stock at the start of trading, i.e., the stock price at the start of trading. α and β are predetermined constants.

[0076] p i (t) / p i (0)-1 represents the percentage change based on the trading price at the start of trading. i (t) / p i (0)-1 indicates that if it is greater than 0, the price of the i-th stock is rising, and if it is less than 0, the price of the i-th stock is falling.

[0077] Also, sgn(p i (t) / p i (0)-1) is p i (t) / p i (0)-1 is greater than or equal to 0, then +1, p i (t) / p i (0)-1 is the sign function that is -1 when (0)-1 is less than 0.

[0078] The first term on the right-hand side of the cost function in equation (7) evaluates the difference between the rate of change of each of the multiple stocks and a predetermined value α. Therefore, the cost function in equation (7) decreases when trading stocks whose rate of change is greater than α.

[0079] Furthermore, the information processing device 20 determines the buying or selling direction for the i-th stock, that is, whether to place a sell order or a buy order, based on the rate of change. For example, when the information processing device 20 places a buy order in the case of an uptrend, that is, when following the trend, it places a buy order when the rate of change is positive and a sell order when the rate of change is negative. Conversely, for example, when the information processing device 20 places a sell order in the case of an uptrend, that is, when trading against the trend, it places a sell order when the rate of change is positive and a buy order when the rate of change is negative. In this embodiment, the information processing device 20 places a sell order when the rate of change is positive and a buy order when the rate of change is negative.

[0080] The second term on the right-hand side of the cost function in equation (7) evaluates the difference between the number of shares to be sold and the number of shares to be bought. The second term on the right-hand side of the cost function in equation (7) is 0 when the difference between the number of shares to be sold and the number of shares to be bought is 0, and increases as the difference increases. Therefore, the cost function in equation (7) decreases, for example, when trading a pair of shares with opposite buying and selling directions, where the absolute value of the difference in rate of change is large, i.e., the correlation between the rates of change is small. Also, the cost function in equation (7) decreases, for example, when trading a group of shares that includes multiple shares with the same number of shares to be sold and the same number of shares to be bought, and where the absolute value of the difference in rate of change between them is large, i.e., the correlation between the rates of change between them is small.

[0081] From the above, the combinatorial optimization problem that minimizes the cost function in equation (7) yields a solution that diversifies risk by buying and selling stocks with high price fluctuations while minimizing the difference between the number of stocks to sell and the number of stocks to buy.

[0082] The information processing device 20 obtains the solution to the combinatorial optimization problem that minimizes such a cost function, i.e., the values ​​of the N decision variables. The information processing device 20 decides to trade the stocks corresponding to the decision variables among the N decision variables that have a value of 1. The information processing device 20 then generates an order packet containing trading information for the stocks that it decided to trade among the multiple stocks, and sends it to the market server device 12.

[0083] The information processing device 20 may also solve a combinatorial optimization problem that minimizes a cost function other than the cost function shown in equation (7).

[0084] Figure 7 shows the configuration of the information processing device 20 according to the first embodiment.

[0085] The information processing device 20 acquires data that is provided irregularly, generates a combinatorial optimization problem based on the acquired data, and generates output data based on the solution to the generated combinatorial optimization problem. The information processing device 20 then outputs the generated output data to a first device different from the information processing device 20. In this embodiment, the information processing device 20 receives market information packets that are provided irregularly from the market server device 12 as data. The information processing device 20 generates a combinatorial optimization problem based on the received market information packets, and generates order packets as output data based on the solution to the generated combinatorial optimization problem. In this embodiment, the information processing device 20 then transmits the generated order packets to the market server device 12, which is an example of a first device.

[0086] The information processing device 20 includes an input memory 32, an acquisition unit 36, a solver device 40, a problem generation unit 42, and a processing execution unit 46.

[0087] The input memory 32 stores a plurality of input values ​​that form the basis of a plurality of weight values ​​included in the cost function of a combinatorial optimization problem. In this embodiment, the input memory 32 stores a plurality of values ​​corresponding to a plurality of transaction prices as a plurality of input values. The plurality of transaction price-corresponding values ​​stored in the input memory 32 correspond one-to-one with the plurality of stocks. That is, the input memory 32 stores a value corresponding to the transaction price for each of the plurality of stocks. The value corresponding to the transaction price may be the transaction price, or it may be a value obtained by performing a predetermined process or calculation on the transaction price. For example, the value corresponding to the transaction price may be a rate of change representing the ratio of the latest transaction price to the transaction price at the start of trading.

[0088] The acquisition unit 36 ​​acquires data that is given to it repeatedly at irregular intervals. The data acquired by the acquisition unit 36 ​​includes input information relating to at least one of a group of targets. When the acquisition unit 36 ​​acquires data, it rewrites the input value corresponding to the target related to the input information contained in the acquired data, among the group of input values ​​stored in the input memory 32, based on the input information contained in the acquired data.

[0089] In this embodiment, the acquisition unit 36 ​​acquires a market information packet, which is an example of data that is given repeatedly at irregular intervals, from the market server device 12. The market information packet includes the trading price of at least one stock among a plurality of stocks as input information. When the acquisition unit 36 ​​acquires a market information packet, it rewrites the value corresponding to the trading price of the stock shown in the acquired market information packet from the values ​​corresponding to the trading prices of each of the plurality of stocks stored in the input memory 32, based on the trading price contained in the acquired market information packet.

[0090] The solver device 40 receives a combinatorial optimization problem from the problem generation unit 42 and solves the received combinatorial optimization problem. The solver device 40 then outputs the solution to the received combinatorial optimization problem. In this embodiment, the solver device 40 is a simulated branching machine, which is a type of Ising machine, and is implemented in a dedicated hardware circuit. Note that the solver device 40 may solve the combinatorial optimization problem based on an algorithm other than a simulated branching machine.

[0091] Furthermore, in this embodiment, the solver device 40 includes a weight memory 50 (first memory) and a pattern memory 52 (second memory). The weight memory 50 stores a plurality of weight values ​​included in the cost function of the combinatorial optimization problem. For example, the weight memory 50 stores a matrix (J) and a bias coefficient array (h) representing the plurality of weight values ​​included in the cost function shown in equation (7). The pattern memory 52 stores pattern information (first information) indicating the respective storage locations of the plurality of weight values ​​in the weight memory 50.

[0092] The problem generation unit 42 generates a combinatorial optimization problem based on the data acquired by the acquisition unit 36, and has the solver device 40 solve the generated combinatorial optimization problem. More specifically, the problem generation unit 42 generates multiple weight values ​​to be included in the cost function of the combinatorial optimization problem based on multiple input values ​​stored in the input memory 32, and writes the generated weight values ​​to the weight memory 50. In this embodiment, the solver device 40 is an Ising machine, and the combinatorial optimization problem is an Ising problem. Therefore, the problem generation unit 42 generates a matrix (J) and a bias coefficient array (h), and writes the generated matrix (J) and bias coefficient array (h) to the weight memory 50.

[0093] In this embodiment, the problem generation unit 42 generates a combinatorial optimization problem that minimizes the cost function shown in equation (7). More specifically, the problem generation unit 42 generates a plurality of weight values ​​included in the cost function of the combinatorial optimization problem shown in equation (7) based on a plurality of input values ​​stored in the input memory 32, and writes the generated plurality of weight values ​​to the weight memory 50. More specifically, the problem generation unit 42 generates a matrix (J) and a bias coefficient array (h) obtained by equation (7) based on values ​​corresponding to the trading prices of a plurality of stocks stored in the input memory 32, and writes the generated matrix (J) and bias coefficient array (h) to the weight memory 50.

[0094] Furthermore, the problem generation unit 42 generates pattern information to identify the storage location of each of the multiple weight values ​​in the weight memory 50. Then, the problem generation unit 42 writes the generated pattern information to the pattern memory 52.

[0095] Furthermore, the problem generation unit 42 generates a combinatorial optimization problem in response to data acquisition or at a predetermined interval, and causes the solver device 40 to solve the combinatorial optimization problem. In this embodiment, the problem generation unit 42 generates a combinatorial optimization problem in response to the acquisition unit 36 ​​acquiring market information packets or at a predetermined interval, and causes the solver device 40 to solve the combinatorial optimization problem.

[0096] However, during the problem generation process from the start of generating a combinatorial optimization problem until the solution to the generated combinatorial optimization problem is output, the problem generation unit 42 does not generate a new combinatorial optimization problem even if the acquisition unit 36 ​​acquires a new market information packet. Also, the preset period is longer than the time required from the start of generating a combinatorial optimization problem until the solution to the generated combinatorial optimization problem is output. Furthermore, the preset period does not have to be at fixed intervals and may vary over time.

[0097] The processing execution unit 46 obtains the solution to the combinatorial optimization problem from the solver device 40. In this embodiment, the processing execution unit 46 obtains the solution to the combinatorial optimization problem from the multiple decision variables (b1~b) included in equation (7).N The value of (0 or 1) is obtained as the solution. The processing execution unit 46 executes processing based on the obtained solution, depending on whether a solution has been obtained from the solver device 40.

[0098] For example, when the processing execution unit 46 obtains a solution to a combinatorial optimization problem from the solver device 40, it generates output data that includes output information indicating that a predetermined operation should be performed on at least one stock identified by the solution among multiple stocks, based on the obtained solution. The processing execution unit 46 then outputs the output data to the first device.

[0099] In this embodiment, when the processing execution unit 46 obtains a solution to a combinatorial optimization problem from the solver device 40, it generates an order packet, which is an example of output data. The order packet contains multiple decision variables (b1~b) as output information. N The system includes transaction information indicating that a buy order or sell order will be placed for the stocks corresponding to the decision variable whose value (1) indicates that a transaction will be made. The processing execution unit 46 then outputs the generated order packets to the market server device 12, which is an example of the first device.

[0100] In this embodiment, the multiple weight values ​​included in the cost function in the combinatorial optimization problem are identified by an index representing their position in a predetermined first region. For example, the multiple weight values ​​included in the second term on the right-hand side of equation (7) are identified by an index (i,j) representing the row number (i) and column number (j) of a matrix (J) with N rows and N columns.

[0101] Furthermore, in this embodiment, the first partial weight group, which is a part of a plurality of weight values, is identical to the second partial weight group, which is another part. For example, the first partial weight group included in the first partial region, which is a part of a predetermined first region, is identical to the second partial weight group included in the second partial region, which is another part of the predetermined first region. For example, the N weight values ​​included in the first row of a matrix (J) with N rows and N columns are identical to the N weight values ​​included in the second row of matrix (J).

[0102] In this embodiment, the problem generation unit 42 writes the first partial weight group and the second partial weight group to a common area in the weight memory 50. Then, the solver device 40 reads each of the multiple weight values ​​from the weight memory 50 based on the pattern information stored in the pattern memory 52 and finds the solution.

[0103] Figure 8 is a timing chart showing the processing timing of the information processing device 20. The information processing device 20 executes processing in the flow shown in Figure 8, for example.

[0104] When the acquisition unit 36 ​​acquires a market information packet from the market server device 12, it rewrites the value corresponding to the trading price of the stock included in the market information packet, which is one of the values ​​corresponding to the trading price of each of the multiple stocks stored in the input memory 32. As a result, the values ​​corresponding to the trading prices of each of the multiple stocks stored in the input memory 32 are changed (t1, t5 in Figure 8).

[0105] The problem generation unit 42 generates multiple weight values ​​to be included in the cost function of the combinatorial optimization problem based on values ​​corresponding to the respective trading prices of multiple stocks stored in the input memory 32. The problem generation unit 42 then writes the generated weight values ​​to the weight memory 50 of the solver device 40 and causes the solver device 40 to perform the solving process (t2, t6 in Figure 8). For example, the problem generation unit 42 and the solver device 40 perform problem generation each time they acquire market information packets from the market server device 12, or at predetermined intervals.

[0106] The solver device 40 starts the solution-finding process after multiple weight values ​​have been written to the weight memory 50. When the solver device 40 completes the solution-finding process, it provides the solution to the combinatorial optimization problem to the processing execution unit 46 (t3, t7 in Figure 8).

[0107] The processing execution unit 46 generates order packets in response to obtaining the solution to the combinatorial optimization problem from the solver device 40. The processing execution unit 46 then outputs the generated order packets to the market server device 12 (t4, t8 in Figure 8).

[0108] Figure 9 shows the pseudocode 60 used to generate the Q matrix in QUBO from the second term on the right-hand side of equation (7).

[0109] For example, each of the N rows in matrix (J) contained in the second term on the right-hand side of equation (7) can be represented by one of two patterns, as described below.

[0110] First, let's consider generating an N x N Q matrix in QUBO from the second term on the right-hand side of equation (7). When generating an N x N Q matrix in QUBO from the second term on the right-hand side of equation (7), the problem generation unit 42 executes the pseudocode 60 shown in Figure 9.

[0111] Note that p_sgn(i) is sgn(p i (t) / p i (0)-1) represents. Also, p_sgn(j) is sgn(p j (t) / p j (0)-1) represents

[0112] The first row of the Q matrix contains N weight values ​​(Q 1,1 ,Q 1,2 ,…,Q 1,N ,) becomes {β×p_sgn(1)×p_sgn(1),β×p_sgn(1)×p_sgn(2),…,β×p_sgn(1)×p_sgn(N)}.

[0113] p_sgn(i) and p_sgn(j) are either +1 or -1. Therefore, the N weight values ​​(Q) contained in the first row of the Q matrix are... 1,1 ,Q 1,2 ,…,Q 1,NWhen β×p_sgn(1) is +1, the result is {β×p_sgn(1),β×p_sgn(2),…,β×p_sgn(N)}. Also, the N weight values ​​(Q) contained in the first row of the Q matrix. 1,1 ,Q 1,2 ,…,Q 1,N When β×p_sgn(1) is -1, the result is {-β×p_sgn(1),-β×p_sgn(2),…,-β×p_sgn(N)}. The other rows of the Q matrix are the same as the first row.

[0114] In other words, each of the N rows in matrix Q will be one of two patterns: {β×p_sgn(1),β×p_sgn(2),…,β×p_sgn(N)} or {-β×p_sgn(1),-β×p_sgn(2),…,-β×p_sgn(N)}.

[0115] Similarly, when the Q matrix is ​​transformed into matrix (J) in the Ising problem, each of the N rows will fall into one of two patterns.

[0116] That is, each of the N rows in matrix (J) follows either the first pattern {-0.5×β×p_sgn(1),-0.5×β×p_sgn(2),…,-0.5×β×p_sgn(N)} or the second pattern {0.5×β×p_sgn(1),0.5×β×p_sgn(2),…,0.5×β×p_sgn(N)}.

[0117] In this embodiment, when the problem generation unit 42 generates the matrix (J) included in the second term on the right-hand side of equation (7), it generates a first pattern and a second pattern instead of generating all N rows. The problem generation unit 42 then writes these two patterns, the first pattern and the second pattern, i.e., 2 × N weight values, to the weight memory 50.

[0118] For example, the weight memory 50 includes a first memory area and a second memory area. In this case, the problem generation unit 42 writes N weight values ​​for the first pattern to the first memory area and N weight values ​​for the second pattern to the second memory area.

[0119] Furthermore, the problem generation unit 42 generates pattern information indicating whether each of the N rows in the matrix (J) included in the second term on the right-hand side of equation (7) is the first pattern or the second pattern. For example, the problem generation unit 42 calculates β×p_sgn(i) for each of the rows from the 1st to the Nth. Subsequently, the problem generation unit 42 generates pattern information indicating the value of β×p_sgn(i) (+1 or -1) for each of the rows from the 1st to the Nth. Then, the problem generation unit 42 writes the generated pattern information to the pattern memory 52.

[0120] When solving a combinatorial optimization problem, the solver device 40 reads N×N weight values ​​from the weight memory 50, referencing pattern information stored in the pattern memory 52 to determine whether the row of target weight values ​​to be read belongs to the first pattern or the second pattern. If the row of target weight values ​​belongs to the first pattern, the solver device 40 reads the weight value corresponding to the column of the target weight value from the N weight values ​​stored in the first memory area of ​​the weight memory 50. If the row of target weight values ​​belongs to the second pattern, the solver device 40 reads the weight value corresponding to the column of the target weight value from the N weight values ​​stored in the second memory area of ​​the weight memory 50. In this way, the solver device 40 can read each of the N×N weight values ​​based on the N weight values ​​of the first pattern, the N weight values ​​of the second pattern, and the pattern information.

[0121] As described above, the information processing device 20 according to the first embodiment stores a first sub-weight group and a second weight group with the same pattern from among the multiple weight values ​​included in the cost function of the combinatorial optimization problem in a common area of ​​the weight memory 50. As a result, the information processing device 20 only needs to generate a portion of the multiple weight values, rather than generating all of them, so it can generate the combinatorial optimization problem in a shorter time compared to the generation time when all of the multiple weight values ​​are generated. Therefore, the information processing device 20 can generate the combinatorial optimization problem at high speed and allow the solver device 40 to start solving it early.

[0122] Furthermore, since the solver device 40 does not need to store all of the weight values, but only a portion of them, the size of the weight memory 50 can be reduced. As a result, the information processing device 20 according to this embodiment can reduce the size of the solver device 40.

[0123] (Second Embodiment) Next, the market system 10 according to the second embodiment will be described. The market system 10 according to the second embodiment has substantially the same functions and configuration as the first embodiment, so elements having substantially the same functions and configuration will be given the same reference numerals, and detailed descriptions will be omitted except for differences. The same applies to the third embodiment and subsequent embodiments.

[0124] Figure 10 shows an example of multiple weight values ​​included in the cost function in a combinatorial optimization problem according to the second embodiment.

[0125] For example, each of the multiple weight values ​​is identified by an index representing its position in a predetermined first region. For example, if the multiple weight values ​​are represented by a matrix, each of the multiple weight values ​​is identified by an index represented by a pair of row and column numbers in the matrix. In this embodiment, the number of any row in the matrix is ​​represented as i, and the number of any column in the matrix is ​​represented as j.

[0126] In this embodiment, the predetermined first region is a two-dimensional space represented using matrices. However, the predetermined first region may be a one-dimensional space represented by arrays, or a multi-dimensional space such as a three-dimensional or four-dimensional space represented by tensors.

[0127] Figure 11 shows an example of M subregions, K patterns, pattern information, region conversion information, and partial address conversion information.

[0128] In this embodiment, a predetermined first region where multiple weight values ​​are arranged is divided into M regions having the same shape, where M is an integer of 3 or more.

[0129] In the example shown in Figure 11, the predetermined first region is divided into four subregions in the row direction and four subregions in the column direction. That is, in the example shown in Figure 11, the predetermined first region is divided into 16 subregions of the same shape. Note that if the predetermined first region is a multidimensional space such as a four-dimensional space, each of the M subregions may be a multidimensional space.

[0130] Furthermore, each of the M subregions is identified by a block number (B_N). For example, in Figure 11, each of the 16 subregions is identified by a block number (B_N) from 1 to 16.

[0131] Each of the M subregions contains a sub-weight group, which is a subset of multiple weight values. The sub-weight group in each of the M subregions can be represented by one of K patterns (where K is an integer greater than or equal to 2 and less than M). That is, two or more subregions containing the same pattern contain the same sub-weight group.

[0132] Furthermore, the pattern information indicates which of the K patterns' subweight groups each of the M subregions contains. For example, the pattern information includes pattern identification information (Pk) with the block number (B_N) as the index.

[0133] Furthermore, the region conversion information is information for converting an index representing the position of the target weight value in a given first region into a block number (B_N) that identifies the subregion containing the target weight value among M subregions. For example, the region conversion information is a function {f(i,j)} that converts a pair of row number (i) and column number (j) into a block number (B_N).

[0134] Furthermore, partial address conversion information is information for converting an index representing the position of the target weight value in a predetermined first region to a partial address (i',j') representing the position of the target weight value within a subregion. For example, partial address conversion information may be a function {g(i,j)} that converts a pair of row number (i) and column number (j) to a partial address (i',j').

[0135] In this embodiment, the problem generation unit 42 generates K patterns, pattern information, region conversion information, and partial address conversion information in the generation of a combinatorial optimization problem. The problem generation unit 42 then provides the generated K patterns, pattern information, region conversion information, and partial address conversion information to the solver device 40.

[0136] Furthermore, if the division positions of M sub-regions for a predetermined first region are fixed, the problem generation unit 42 does not need to generate region conversion information and partial address conversion information. In this case, the solver device 40 has the region conversion information and partial address conversion information pre-set.

[0137] Figure 12 shows the configuration of the solver apparatus 40 according to the second embodiment.

[0138] The solver device 40 according to the second embodiment includes a search circuit 62, a sub-region identification circuit 64, a sub-address identification circuit 66, a weight memory 50, a pattern memory 52, and a selector 68.

[0139] The search circuit 62 reads each of the multiple weight values ​​stored in the weight memory 50 and searches for a solution that minimizes the cost function. i,j When reading out the target weight value (J i,j Specify an index representing the position of the target weight value (J) in a predetermined first region. For example, the search circuit 62 specifies the index as the target weight value (J i,j Specify the row number (i) and column number (j) of the row(s).

[0140] The sub-region identification circuit 64 receives region conversion information (f(i,j)) from the problem generation unit 42. If the division positions of M sub-regions for a predetermined first region are fixed, the sub-region identification circuit 64 may have the region conversion information (f(i,j)) pre-set.

[0141] The sub-region identification circuit 64 is determined by the search circuit 62 using the target weight value (J i,j When reading the target weight value (J i,j The row number (i) and column number (j) of the row (i,j) are obtained as indices. Then, the sub-region identification circuit 64 obtains region transformation information (f(i,j)) and target weight value (J i,j Based on the index of ), among the M subregions, the target weight value (J i,j Outputs the block number (B_N) that identifies the target subregion containing ).

[0142] The partial address identification circuit 66 receives partial address translation information (g(i,j)) from the problem generation unit 42. If the division positions of M sub-regions for a predetermined first region are fixed, the partial address identification circuit 66 may have the partial address translation information (g(i,j)) pre-set.

[0143] The partial address identification circuit 66 determines the target weight value (J) of the search circuit 62. i,j When reading the target weight value (J i,j The row number (i) and column number (j) of the ) are obtained. Then, the partial address identification circuit 66 obtains the partial address translation information (g(i,j)) and the target weight value (Ji,j Based on the index of the target subregion, the target weight value (J i,j Outputs the target partial address (i',j') representing the position of ).

[0144] The pattern memory 52 receives pattern information from the problem generation unit 42. The pattern memory 52 receives a block number (B_N) from the sub-region identification circuit 64. When the pattern memory 52 receives a block number (B_N), it outputs information (Pk) indicating the pattern identified by the received block number (B_N) in the stored pattern information.

[0145] The weight memory 50 contains K submemories 70-1 to 70-K. The K submemories 70-1 to 70-K correspond one-to-one with the K patterns. That is, the k-th submemories 70-k (where k is an integer between 1 and K) among the K submemories 70-1 to 70-K correspond to the k-th pattern among the K patterns. The problem generation unit 42 writes the subweight group of the corresponding pattern among the K patterns to each of the K submemories 70-1 to 70-K. That is, the k-th submemories 70-k are written with the subweight group of the k-th pattern.

[0146] Each of the K partial memories 70-1 to 70-K receives a target partial address (i',j') from the partial address identification circuit 66. When each of the K partial memories 70-1 to 70-K receives a target partial address (i',j'), it outputs the weight value from the stored partial weight group that is identified by the target partial address (i',j').

[0147] Selector 68 receives information (Pk) indicating a pattern identified by block number (B_N) from pattern memory 52. ​​When selector 68 receives information (Pk) indicating a pattern, it selects one sub-memory 70 from among K sub-memories 70-1 to 70-K that is specified by the received information (Pk). Then, selector 68 takes the weight values ​​output from the selected sub-memory 70 from pattern memory 52 and assigns them to the target weight values ​​(J i,j This is then provided to the search circuit 62.

[0148] In this way, when the solver device 40 reads a target weight value from among multiple weight values, it identifies the target sub-region containing the target weight value from among the M sub-regions. Next, based on the pattern information, the solver device 40 identifies the target pattern in the target sub-region from among the K patterns. Next, the solver device 40 identifies the target sub-address representing the position of the target weight value in the target sub-region. Then, the solver device 40 reads the weight value identified by the target sub-address in the sub-weight group of the target pattern from the weight memory 50 as the target weight value. As a result, the solver device 40 reads the target weight value (J i,j ) can be read.

[0149] As described above, the information processing device 20 according to the second embodiment stores the subweight groups of K patterns in the weight memory 50. As a result, the information processing device 20 only needs to generate the subweight groups of K patterns, rather than generating all of the weight values, so it can generate the combinatorial optimization problem in a shorter time compared to the generation time when all of the weight values ​​are generated. Therefore, the information processing device 20 can generate the combinatorial optimization problem at high speed and allow the solver device 40 to start solving it early.

[0150] Furthermore, since the solver device 40 does not need to store all of the multiple weight values, but only needs to store the sub-weight groups of K patterns, the size of the weight memory 50 can be reduced. As a result, the information processing device 20 according to this embodiment can reduce the configuration of the solver device 40.

[0151] (Third embodiment) Next, the market system 10 according to the third embodiment will be described.

[0152] Figure 13 shows the configuration of the solver device 40 according to the third embodiment. The information processing device 20 according to the third embodiment includes a solver device 40 that executes a simulated branching algorithm.

[0153] The solver device 40 includes an arithmetic circuit 71, an input circuit 72, an output circuit 73, and a setting circuit 74.

[0154] The arithmetic circuit 71 increases the parameter t, which represents time, by a unit time (Δt) from the initial time (e.g., 0) to the end time. The arithmetic circuit 71 then calculates the first variable (x) associated with each of the N virtual points (virtual particles). i ) and the second variable (y i The following is calculated: The N virtual points correspond to the N spins in the Ising model. The i-th virtual point among the N virtual points corresponds to the i-th spin among the N spins in the Ising model.

[0155] First variable (x i ) is a position variable that represents the position of the corresponding virtual point. The second variable (y i ) is a momentum variable that represents the momentum of the corresponding virtual point.

[0156] The arithmetic circuit 71 calculates N first variables (x) at each unit time from the initial time to the end time. i ) and N second variables (y i Each of the following is sequentially processed at each unit time, and the first variable (x i ) and the second variable (y i) and are calculated alternately. More specifically, the arithmetic circuit 71 performs the operations shown in the algorithms of equations (4-1) and (4-2) at each unit time from the initial time to the end time. The arithmetic circuit 71 may also perform the operations shown in the algorithms of equations (5-1), (5-2) and (5-3), or it may also perform the operations shown in the algorithms of equations (6-1), (6-2) and (6-3). Then, the arithmetic circuit 71 calculates the N first variables (x) at the end time. i The solution to the combinatorial optimization problem is calculated by binarizing each value of (i.e., the position of each of the N virtual points).

[0157] The input circuit 72, prior to the calculation processing by the arithmetic circuit 71, processes N first variables (x) at the initial time. i ) and N second variables (y i The initial values ​​of each of the parameters are obtained and provided to the arithmetic circuit 71. The output circuit 73 obtains the solution to the combinatorial optimization problem from the arithmetic circuit 71 after the arithmetic processing by the arithmetic circuit 71 is completed. The output circuit 73 then outputs the obtained solution. The setting circuit 74 sets each parameter to the arithmetic circuit 71 prior to the arithmetic processing by the arithmetic circuit 71.

[0158] Figure 14 shows the block configuration of the arithmetic circuit 71. In the explanation of Figure 14, the target time (second time) is any time obtained by dividing the time from the initial time to the end time into unit time intervals. In the explanation of Figure 14, the immediately preceding time (first time) is represented as t1. The target time (second time) is represented as t2.

[0159] The arithmetic circuit 71 includes an X memory 81, a Y memory 82, an action arithmetic circuit 83, a time evolution circuit 84 (first circuit), and a control circuit 85.

[0160] The X memory 81 contains N first variables (x) at the previous time (t1). i The X memory 81 stores the N first variables (x) at the immediately preceding time (t1) as the time is updated. i(t1)) is overwritten. That is, X memory 81 contains N first variables (x) at the target time (t2). i If (t2)) is calculated, then the N first variables (x) at the calculated target time (t2) i (t2)) is the N first variable (x) at the new immediately preceding time (t1). i It is written as (t1). The setting circuit 74, prior to the calculation, sets the N first variables x at the initial time. i Write this to memory 81 of X.

[0161] The Y memory 82 contains N second variables (y) at the previous time (t1). i The Y memory 82 stores the N second variables (y) at the immediately preceding time (t1) as the time is updated. i (t1)) is rewritten. That is, the Y memory 82 contains the N second variables (y) at the target time (t2). i If (t2)) is calculated, then the N second variables (y) at the calculated target time (t2) i (t2)) is the N second variable (y) at the new immediately preceding time (t1). i It is written as (t1). The setting circuit 74, prior to the calculation, sets N second variables y at the initial time. i Write this to memory Y 82.

[0162] The action calculation circuit 83 calculates the N first variables (x) at the previous time (t1). j The (t1)) is obtained from the X memory 81. Then, the action calculation circuit 83 calculates the updated value (z) at the previous time (t1) for each of the N virtual points. i Calculate (t1).

[0163] The time evolution circuit 84 calculates the updated value (z) at the previous time (t1) for each of the N virtual points. i The (t1)) is obtained from the action calculation circuit 83. Furthermore, the time evolution circuit 84 obtains the first variable (x) at the previous time (t1) for each of the N virtual points. i (t1)) is obtained from X memory 81, and the second variable (y) at the previous time (t1)i The (t1)) is obtained from the Y memory 82. Then, for each of the N virtual points, the time evolution circuit 84 obtains the first variable (x) at the target time (t2). i (t2)) is calculated, and the first variable (x) at the previous time (t1) stored in X memory 81 is calculated. i (t1)) is rewritten. At the same time, the time evolution circuit 84 rewrites the second variable (y) at the target time (t2) for each of the N virtual points. i (t2)) is calculated, and the second variable (y) at the previous time (t1) stored in Y memory 82 is calculated. i Rewrite (t1).

[0164] The control circuit 85 sequentially updates the target time (t2) every unit time (Δt), thereby determining the first variable (x) for each unit time (Δt) for the action calculation circuit 83 and the time evolution circuit 84. i (t) and the second variable (y i (t)) is calculated sequentially.

[0165] Furthermore, the control circuit 85 generates an index (i) that identifies N virtual points by incrementing from 1 to N at each unit time. The control circuit 85 provides the index (i) to the action calculation circuit 83 and the time evolution circuit 84, and the first variable (x) at the target time (t2) corresponding to each of the N virtual points. i (t2)) and the second variable (y) at the target time (t2) i (t2)) is calculated in index order. Note that the action calculation circuit 83 and the time evolution circuit 84 calculate multiple first variables (x) corresponding to multiple indices. i (t2)) and multiple second variables (y i (t2)) may be calculated in parallel.

[0166] Figure 15 shows the configuration of the action arithmetic circuit 83. The action arithmetic circuit 83 includes a weight memory 50, a matrix operation circuit 93, an alpha function circuit 94, and a first adder circuit 95. The weight memory 50 includes a J memory 91 and an H memory 92.

[0167] The J memory 91 stores patterns for generating an N×N matrix (J) containing (N×N) weight values. i , j This represents the weight value of the i-th row and j-th column in the matrix. i , j This corresponds to the coupling coefficient between the i-th spin and the j-th spin in the Ising model. Prior to the calculation, the setting circuit 74 writes a pattern for generating the matrix (J) generated by the problem generation unit 42 into the J memory 91.

[0168] H memory 92 stores an array containing N bias coefficients. i This represents the i-th bias coefficient in the array. i This corresponds to the local magnetic field coefficient acting on the i-th spin in the Ising model. Prior to the calculation, the setting circuit 74 writes an array containing N bias coefficients, generated by the problem generation unit 42, to the H memory 92.

[0169] The matrix operation circuit 93 retrieves N first variables (x) from the X memory 81 at the previous time (t1). j The matrix operation circuit 93 obtains (t1)). For each of the N virtual points, it obtains the N weight values ​​J contained in the target row from the J memory 91. i,j The matrix operation circuit 93 then obtains the N first variables (x) at the previous time (t1) for each of the N virtual points. j (t1)) and the N weight values ​​J included in the target row. i,j Perform a sum-of-products operation with the specified value.

[0170] The α function circuit 94 retrieves the target bias coefficient h from the H memory 92 for each of the N virtual points. i Obtain the α function circuit 94, for each of the N virtual points, {-h i The operation α(t1) is performed. α(t) is a predefined function.

[0171] The first adder circuit 95 adds the sum-of-products operation result from the matrix operation circuit 93 and the operation result from the alpha function circuit 94 for each of the N virtual points. Through this operation, the first adder circuit 95 calculates the updated value (z) at the previous time (t1), expressed by equation (8), for each of the N virtual points. i Output (t1).

number

[0172] Figure 16 shows an example of matrix (J). In the third embodiment, matrix (J) containing N × N weight values ​​is such that the N weight values ​​contained in each of the N rows are in the first pattern {J1(J1 ,1 J1 ,2 ,…,J1 ,N )} or second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N It is one of the following: )}.

[0173] In the third embodiment, the problem generation unit 42 generates a first pattern and a second pattern as a matrix (J) and stores them in the J memory 91. The problem generation unit 42 also generates pattern information indicating whether each of the N rows in the matrix (J) is the first pattern or the second pattern, and provides this information to the matrix operation circuit 93.

[0174] Figure 17 shows the configuration of the matrix operation circuit 93 according to the third embodiment, along with the J memory 91 and the X memory 81.

[0175] The J memory 91 includes a first partial memory 111 and a second partial memory 112.

[0176] The first partial memory 111 contains N weight values ​​{J1(J1 ,1 J1 ,2 ,…,J1 ,N)} is stored. The first partial memory 111 outputs one weight value at a time in order from the first column among the N weight values every time a clock is applied. Then, after outputting the weight value in the Nth column, the first partial memory 111 returns to the first column and outputs the weight value again one by one for each clock from the first column. That is, the first partial memory 111 starts outputting the weight value from the first column every N clocks.

[0177] The second partial memory 112 stores N weight values {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N )} of the second pattern. The second partial memory 112 outputs one weight value at a time in order from the first column among the N weight values every time a clock is applied. Then, after outputting the weight value in the Nth column, the second partial memory 112 returns to the first column and outputs the weight value again one by one for each clock from the first column. That is, the second partial memory 112 starts outputting the weight value from the first column every N clocks.

[0178] The X memory 81 stores N first variables (x j (t1)) (an example of N first intermediate variables at the first time) at the immediately previous time. The X memory 81 outputs the N first variables (x j (t1)) in order from the first first variable (x1(t1)) to the Nth first variable (x N (t1)) for each clock. After outputting the Nth first variable (x j (t1)), the X memory 81 outputs the first first variable (x N (t1)) at the next clock. The X memory 81 outputs the first first variable (x N (t1)) at the clock when the index (i) is updated.

[0179] The matrix operation circuit 93 includes a pattern memory 52, a pattern selector 113 (the first selector), a multiplication circuit 115, and an accumulation addition circuit 116.

[0180] The pattern memory 52 stores the pattern information generated by the problem generation unit 42. The pattern memory 52 acquires an index (i) representing any one of 1 to N generated from the control circuit 85. The index (i) is incremented every N clocks. The timing at which the index (i) is incremented and the timing at which the weight values of the first column are output from the first partial memory 111 and the second partial memory 112 are synchronized. The pattern memory 52 outputs a selection value (0 or 1) indicating whether the row corresponding to the index (i) is the first pattern or the second pattern. In this example, when the selection value is 0, it indicates the first pattern, and when it is 1, it indicates the second pattern.

[0181] The pattern selector 113 receives a selection value representing 0 or 1 from the pattern memory 52. The pattern selector 113 selects and outputs the weight value output from one of the first partial memory 111 or the second partial memory 112 specified by the selection value.

[0182] The multiplication circuit 115 multiplies the weight value output from the pattern selector 113 and the first variable (x j (t1)) output from the X memory 81, and outputs the multiplication result.

[0183] The cumulative addition circuit 116 includes an adder 121, a reset selector 122, and a second latch circuit 123. The adder 121 adds the multiplication result output from the multiplication circuit 115 and the value stored in the second latch circuit 123. The reset selector 122 supplies the value output from the adder 121 to the second latch circuit 123. Further, the reset selector 122 supplies 0 to the second latch circuit 123 instead of the value output from the adder 121 every N clocks, that is, in synchronization with the update of the index (i). The second latch circuit 123 takes in and stores the value output from the reset selector 122 every clock.

[0184] Such an accumulation adder circuit 116 calculates an accumulation sum value by accumulating and summing the multiplication results output from the multiplication circuit 115 at each clock cycle. The accumulation adder circuit 116 resets the accumulation sum value to 0 every N clock cycles, that is, in synchronization with the update of index (i). In addition, in the cycle immediately preceding the reset of the accumulation sum value to 0, the accumulation adder circuit 116 adds the accumulation sum value to the N weight values ​​(J) contained in the row corresponding to index (i) in the matrix (J). i,1 ~J i,N ) and the first variable (x j Output the result of the sum-of-products operation with (t1).

[0185] Such a matrix operation circuit 93 calculates the sum-of-products result (Z') expressed by equation (9). i (t1)) (an example of the i-th second intermediate variable out of N second intermediate variables) can be calculated.

number

[0186] As described above, the information processing device 20 according to the third embodiment has N weight values ​​{J1(J1 ,1 J1 ,2 ,…,J1 ,N )} and the N weight values ​​of the second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N The values ​​are stored in the weight memory 50. This means that the information processing device 20 only needs to generate 2 × N weight values ​​instead of all N × N weight values, so it can generate the combinatorial optimization problem in a shorter time compared to the generation time when all of the multiple weight values ​​are generated. Therefore, the information processing device 20 can generate the combinatorial optimization problem at high speed and allow the solver device 40 to start solving it early.

[0187] Furthermore, since the solver device 40 only needs to store 2 × N weight values ​​instead of all N × N weight values, the size of the weight memory 50 can be reduced. As a result, the information processing device 20 according to this embodiment can reduce the size of the solver device 40.

[0188] In this embodiment, the N weight values ​​contained in row i of matrix (J) were either the first pattern or the second pattern. However, the N weight values ​​contained in row i of matrix (J) may be any of the K patterns. In this case, the weight memory 50 includes K sub-memories 70-1 to 70-K. The k-th sub-memories 70-k (where k is an integer between 1 and K) among the K sub-memories 70-1 to 70-K store the N weight values ​​of the k-th pattern of the K patterns. Each of the K sub-memories 70-1 to 70-K has N weight values ​​read out in the same way as the first sub-memories 111 and the second sub-memories 112. The pattern information indicates which of the K patterns each of the N rows contained in matrix (J) represents.

[0189] Furthermore, if the weight memory 50 contains K sub-memories 70-1 to 70-K, the pattern selector 113 selects and outputs N weight values ​​from the sub-memories 70 corresponding to the pattern of the i-th row shown in the pattern information, out of the K sub-memories 70-1 to 70-K. The cumulative summing circuit 116 adds each of the N weight values ​​output from the pattern selector 113 and x j The results of multiplying by and are then added together. The cumulative addition circuit 116 then uses the cumulative addition result obtained by the cumulative addition as the sum-of-products result (Z') expressed by equation (9). i Output as (t1)).

[0190] (Fourth Embodiment) Next, the market system 10 according to the fourth embodiment will be described. The market system 10 according to the fourth embodiment is identical to that of the third embodiment, except for the matrix operation circuit 93. The matrix operation circuit 93 according to the fourth embodiment will be described below, and detailed explanations of the same configuration as the third embodiment will be omitted.

[0191] Figure 18 shows the configuration of the matrix operation circuit 93 according to the fourth embodiment, along with the J memory 91 and the X memory 81.

[0192] The matrix operation circuit 93 includes a pattern memory 52, a first multiplication circuit 131, a second multiplication circuit 132, a first cumulative addition circuit 133, a second cumulative addition circuit 134, and an output selector 137.

[0193] The first multiplication circuit 131 takes the weight value output from the first partial memory 111 every clock cycle and the first variable (x) output from the X memory 81. i Multiply (t1) by this and output the result of the first multiplication.

[0194] The second multiplication circuit 132 takes the weight value output from the second partial memory 112 every clock cycle and the first variable (x) output from the X memory 81. i Multiply (t1) by this and output the result of the second multiplication.

[0195] The first cumulative adder circuit 133 has the same configuration as the cumulative adder circuit 116 according to the third embodiment. The first cumulative adder circuit 133 calculates a first cumulative sum value by accumulating and summing the first multiplication results output from the first multiplication circuit 131 at each clock cycle. The first cumulative adder circuit 133 resets the first cumulative sum value to 0 every N clock cycles, that is, in synchronization with the update of index (i). The first cumulative adder circuit 133 also outputs the first cumulative sum value in the cycle immediately preceding the reset of the first cumulative sum value to 0.

[0196] The second cumulative adder circuit 134 has the same configuration as the cumulative adder circuit 116 according to the third embodiment. The second cumulative adder circuit 134 calculates a second cumulative sum value by accumulating and summing the second multiplication results output from the second multiplication circuit 132 at each clock cycle. The second cumulative adder circuit 134 resets the second cumulative sum value to 0 every N clock cycles, that is, in synchronization with the update of index (i). The second cumulative adder circuit 134 also outputs the second cumulative sum value in the cycle immediately preceding the reset of the second cumulative sum value to 0.

[0197] The output selector 137 receives a selection value representing 0 or 1 from the pattern memory 52. ​​The output selector 137 selects the cumulative sum output from either the first cumulative sum circuit 133 or the second cumulative sum circuit 134, whichever is specified by the selection value. Then, the output selector 137 assigns the selected cumulative sum to the N weight values ​​(J) contained in the row corresponding to index (i) in the matrix (J). i,1 ~J i,N ) and the first variable (x j Output the result of the sum-of-products operation with (t1).

[0198] As described above, the information processing device 20 according to the fourth embodiment has N weight values ​​{J1(J1 ,1 J1 ,2 ,…,J1 ,N )} and the N weight values ​​of the second pattern {J2(J2 ,1 ,J2 ,2 ,…,J2 ,N The values ​​are stored in the weight memory 50. This means that the information processing device 20 only needs to generate 2 × N weight values ​​instead of all N × N weight values, so it can generate the combinatorial optimization problem in a shorter time compared to the generation time when all of the multiple weight values ​​are generated. Therefore, the information processing device 20 can generate the combinatorial optimization problem at high speed and allow the solver device 40 to start solving it early.

[0199] Furthermore, since the solver device 40 only needs to store 2×N weight values instead of all N×N weight values, the size of the weight memory 50 can be reduced. As a result, the information processing apparatus 20 according to the present embodiment can reduce the configuration of the solver device 40.

[0200] Note that the N weight values included in the i-th row of the matrix (J) may be any one of the K patterns. In this case, the weight memory 50 includes K partial memories 70-1 to 70-K. The k-th partial memory 70-k among the K partial memories 70-1 to 70-K stores the N weight values of the k-th pattern among the K patterns. Each of the K partial memories 70-1 to 70-K reads out N weight values in the same manner as the first partial memory 111 and the second partial memory 112. Also, the pattern information indicates which pattern among the K patterns each of the N rows included in the matrix (J) is.

[0201] Also, in the fourth embodiment, when the weight memory 50 includes K partial memories 70-1 to 70-K, the matrix operation circuit 93 includes K multiplication circuits and K cumulative addition circuits. The k-th multiplication circuit among the K multiplication circuits outputs the result of multiplying each of the N weight values output from the k-th partial memory 70-k among the K partial memories 70-1 to 70-K by x j And. Each of the K cumulative addition circuits has the same configuration as the first cumulative addition circuit 133 and the second cumulative addition circuit 134. The k-th cumulative addition circuit among the K cumulative addition circuits adds the multiplication results output from the k-th multiplication circuit for N cycles. That is, the k-th cumulative addition circuit outputs the cumulative addition result obtained by cumulatively adding the result of multiplying each of the N weight values output from the k-th partial memory 70-k by x j And. The output selector 137 outputs the cumulative addition result output from the cumulative addition circuit corresponding to the pattern of the i-th row indicated by the pattern information among the K cumulative addition circuits as the sum-of-products operation result (Z´ i (t1)) represented by Equation (9).

[0202] (Fifth embodiment) Next, the control system 210 according to the fifth embodiment will be described.

[0203] In the first to fourth embodiments, examples of applying the information processing device 20 to the market system 10 were described. The information processing device 20 is not limited to the market system 10; it can be applied to other systems as well, as long as they are systems that perform processing using combinatorial optimization problems on data that changes over time. For example, the information processing device 20 can also be applied to a control system 210 that controls the movement of a moving object.

[0204] Figure 19 shows an example of the configuration of the control system 210 according to the fifth embodiment. The control system 210 controls an autonomously moving object such as an autonomous vehicle, drone, or robot.

[0205] The control system 210 comprises an object detection device 212, an information processing device 20, and a control device 214.

[0206] The object detection device 212 acquires image data from, for example, a camera that images the area around the controlled moving object. In addition to image data, the object detection device 212 may also acquire sensor data from other sensor devices. Based on the acquired image data and sensor data, the object detection device 212 detects coordinate data representing the three-dimensional coordinates of one or more objects around the moving object. Furthermore, the object detection device 212 may also detect the three-dimensional coordinates of the controlled moving object itself.

[0207] The object detection device 212 repeatedly outputs data to the information processing device 20 at irregular intervals, which includes identification information that identifies one or more objects, and coordinate data (input information) that represents the coordinates of the object identified by the identification information. In addition to the coordinate data, the input information may also include other relevant information such as the movement speed, acceleration, direction of movement, and type of object of the object identified by the identification information.

[0208] The control device 214 acquires output data from the information processing device 20, which includes output information indicating that a predetermined operation should be performed on the mobile object in order to control it. The control device 214 controls the mobile object based on the acquired output data.

[0209] Furthermore, the output information may indicate that a predetermined operation should be performed on one or more objects surrounding the moving body. For example, the output information may include information indicating that movement control, a predetermined instruction, or a warning should be given to one or more objects surrounding the moving body. In this case, the output data includes identification information that identifies one or more of the objects, and the output information. When such output data is received, the control device 214 performs a predetermined operation on the object identified by the identification information included in the output data.

[0210] The information processing device 20 has the same configuration as described in the first to fourth embodiments.

[0211] The information processing device 20 generates a combinatorial optimization problem based on data irregularly provided by the object detection device 212, and has the solver device 40 solve the combinatorial optimization problem. The information processing device 20 then obtains the solution to the combinatorial optimization problem from the solver device 40, generates output data based on the solution obtained, and outputs the generated output data to the control device 214, which is an example of the first device.

[0212] The information processing device 20 according to this embodiment can generate combinatorial optimization problems at high speed, allowing the solver device 40 to start solving them early. Furthermore, the information processing device 20 according to this embodiment can reduce the size of the solver device 40.

[0213] (Hardware configuration) Figure 20 shows an example of the hardware configuration of the information processing device 20. The partial configuration of the information processing device 20, excluding the solver device 40, is realized by a computer with a hardware configuration as shown in Figure 20. The information processing device 20 comprises a CPU (Central Processing Unit) 301, RAM (Random Access Memory) 302, ROM (Read Only Memory) 303, storage device 304, and communication interface device 305. These components are connected by a bus.

[0214] The CPU 301 is one or more processors that perform arithmetic and control processing according to a program. The CPU 301 uses a predetermined area of ​​the RAM 302 as a working area and performs various processes in cooperation with programs stored in the ROM 303 and storage device 304, etc.

[0215] RAM302 is a type of memory such as SDRAM (Synchronous Dynamic Random Access Memory). RAM302 functions as a workspace for the CPU301. ROM303 is a memory that stores programs and various information in a non-rewritable format.

[0216] The storage device 304 is a device that writes and reads data to and from a storage medium made of semiconductors such as flash memory, or a storage medium that can record magnetically or optically. The storage device 304 writes and reads data to and from the storage medium in response to control from the CPU 301. The communication interface device 305 communicates with external devices via a network in response to control from the CPU 301.

[0217] A program executed on a computer causes the computer to function as an information processing unit 20. This program is loaded onto RAM 302 and executed by the CPU 301 (processor).

[0218] Furthermore, programs executed on a computer are provided as files in a format that can be installed on a computer or in an executable format, recorded on computer-readable recording media such as CD-ROMs, flexible disks, CD-Rs, and DVDs (Digital Versatile Disks).

[0219] Furthermore, this program may be configured to be stored on a computer connected to a network such as the Internet and provided by being downloaded via the network. Alternatively, this program may be configured to be provided or distributed via a network such as the Internet. Furthermore, the program executed by the information processing device 20 may be pre-installed in a ROM 303 or the like and provided accordingly.

[0220] The program for making the computer function as an information processing device 20 has a modular configuration, for example, including an acquisition module, a solver module, a problem generation module, and a processing execution module. When this program is executed by the CPU 301, each module is loaded into the RAM 302, causing the CPU 301 to function as an acquisition unit 36, a solver device 40, a problem generation unit 42, and a processing execution unit 46. If the CPU 301 consists of multiple processors, these parts may be divided among the multiple processors. This program also causes the RAM 302 and the storage device 304 to function as input memory 32. Note that some or all of these components may be made up of hardware.

[0221] Furthermore, the solver device 40 may be implemented by one or more reconfigurable semiconductor devices, such as an FPGA (Field-Programmable Gate Array). Alternatively, the solver device 40 may be implemented by one or more CPUs, microprocessors, GPUs (Graphics Processing Units), ASICs (Application Specific Integrated Circuits), or electronic circuits including these circuits.

[0222] The solver device 40 may be incorporated into the information processing device 20. For example, the solver device 40 may be incorporated as an accelerator in part of the information processing device 20. Alternatively, the solver device 40 may include some functions of the information processing device 20, such as the problem generation unit 42.

[0223] Furthermore, if the information processing device 20 is implemented using a reconfigurable semiconductor device such as an FPGA, the circuit information (configuration data) written to the reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device as the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by downloading it via the network. Alternatively, the circuit information (configuration data) written to the reconfigurable semiconductor device in order to operate the reconfigurable semiconductor device as the information processing device 20 may be recorded on a computer-readable recording medium and provided.

[0224] Furthermore, if the information processing device 20 is implemented using a semiconductor device such as an ASIC, the circuit information representing the circuit configuration described in a hardware description language used in the design and manufacture of the information processing device 20 may be stored on a computer connected to a network such as the Internet and provided by downloading it via the network. Alternatively, the circuit information representing the circuit configuration described in a hardware description language used in the design and manufacture of the information processing device 20 may be recorded on a computer-readable recording medium and provided.

[0225] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0226] (Note) Furthermore, the above embodiments can be summarized in the following technical proposal.

[0227] [Technical proposal 1] An information processing device that performs processing on data, A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The aforementioned information processing circuit is In generating the combinatorial optimization problem, the plurality of weight values ​​are generated based on the data, and the plurality of weight values ​​are written to the first memory. In writing the plurality of weight values, the first partial weight group and the second partial weight group are written to a common area in the first memory, and first information indicating the storage location of each of the plurality of weight values ​​in the first memory is provided to the solver device. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. Information processing device.

[0228] [Technical proposal 2] The information processing circuit further obtains the solution to the combinatorial optimization problem from the solver device and performs processing based on the solution. Information processing device as described in Technical Proposal 1.

[0229] [Technical proposal 3] The first weight value among the plurality of weight values ​​is identified by an index representing a position in a predetermined first region. The predetermined first region is divided into M subregions having the same shape (where M is an integer of 3 or more), The first subregion of the M subregions includes a subweight group which is a part of the plurality of weight values, The subweight group placed in each of the M subregions is represented by one of K patterns (where K is an integer greater than or equal to 2 and less than M), The first memory stores the K patterns, The first information indicates which of the K patterns each of the M subregions contains the subweight group of. An information processing device as described in Technical Proposal 1 or 2.

[0230] [Technical proposal 4] The solver device further includes a second memory for storing the first information, The aforementioned information processing circuit, in generating the combinatorial optimization problem, Based on the aforementioned data, the subweight group of the K patterns is generated and written to the first memory. Based on the aforementioned data, the first information is generated and written to the second memory. Information processing device as described in Technical Proposal 3.

[0231] [Technical proposal 5] When reading the first weight value from the plurality of weight values, the solver device, Of the M subregions, identify the subregion that contains the first weight value. Based on the first information, identify the pattern in the subregion containing the first weight value among the K patterns, Identify a first address representing the position of the first weight value in the subregion containing the first weight value, From the first memory, the weight value identified by the first address in the sub-weight group of the identified pattern is read out as the first weight value. Information processing device as described in Technical Proposal 4.

[0232] [Technical proposal 6] The cost function includes, as the plurality of decision variables, N decision variables (where N is an integer greater than or equal to 2), and as the plurality of weight values, a matrix containing weight values ​​with N rows × N columns. The cost function is expressed as a quadratic function of the N decision variables. An information processing device described in any one of Technical Proposals 3 to 5.

[0233] [Technical proposal 7] Each of the aforementioned multiple decision variables is a binary discrete variable. Information processing device as described in Technical Proposal 6.

[0234] [Technical proposal 8] The aforementioned combinatorial optimization problem is a QUBO (Quadratic Unconstrained Binary Optimization) problem. Information processing device as described in Technical Proposal 7.

[0235] [Technical proposal 9] The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes the Ising model. Information processing device as described in Technical Proposal 8.

[0236] [Technical proposal 10] The solver device solves the Ising problem using a simulated branching algorithm. Information processing device as described in Technical Proposal 9.

[0237] [Technical proposal 11] The cost function is a function of order three or higher of the multiple decision variables, The aforementioned combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. Information processing device as described in Technical Proposal 7.

[0238] [Technical proposal 12] The solver apparatus is, A matrix operation circuit that calculates N second intermediate variables at the first time step by performing matrix multiplication with the matrix, wherein the N first intermediate variables at the first time step are multiplied by the matrix, A first circuit that calculates N first variables at a second time after the first time and N second variables at the second time based on the N second intermediate variables at the first time, A control circuit that causes the matrix arithmetic circuit and the first circuit to execute processing from the start time to the end time, An output circuit that generates and outputs the solution based on the N first variables at the aforementioned end time, Equipped with, In the aforementioned Ising model, the i-th spin among the N spins (where i is an integer between 1 and N) corresponds to the i-th point among the N points. The i-th of the N first variables corresponds to the i-th spin. The i-th of the N second variables corresponds to the i-th spin. The i-th first variable represents the position of the point corresponding to the i-th spin, The i-th second variable represents the momentum of the point corresponding to the i-th spin, The i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable, The i-th first intermediate variable is the i-th first variable or the value obtained by multiplying the i-th first variable by a predetermined coefficient. The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. Information processing device as described in Technical Proposal 10.

[0239] [Technical proposal 13] Each of the N x N weight values ​​included in the matrix is ​​J i,j It is represented by, The above i represents the row number of the matrix, The aforementioned j represents the column number of the matrix, and is an integer between 1 and N, The N weight values ​​contained in row i of the matrix are one of the K patterns, The first piece of information indicates which of the K patterns each of the N rows in the matrix corresponds to. The first memory includes K sub-memories, The k-th sub-memory of the K sub-memories (where k is an integer between 1 and K) stores the k-th pattern of the K patterns. Information processing device as described in Technical Proposal 12.

[0240] [Technical proposal 14] The aforementioned matrix operation circuit is A first selector that selects and outputs the N weight values ​​output from the sub-memory corresponding to the pattern of the i-th row shown in the first information, out of the K sub-memories, A cumulative summing circuit outputs the result of cumulatively summing the results obtained by multiplying each of the N weight values ​​output from the first selector by the j-th first intermediate variable among the N first intermediate variables, as the i-th second intermediate variable among the N second intermediate variables. An information processing device as described in Technical Proposal 13, including the following.

[0241] [Technical proposal 15] The aforementioned matrix operation circuit is K cumulative adder circuits, Output selector and Includes, The k-th cumulative adder among the K cumulative adder circuits outputs a cumulative adder result obtained by multiplying each of the N weight values ​​output from the k-th sub-memory among the K sub-memories by the j-th first intermediate variable among the N first intermediate variables, and then cumulatively adding the results. The output selector outputs the cumulative sum result from the cumulative sum circuit corresponding to the i-th pattern shown in the first information, among the K cumulative sum circuits, as the i-th second intermediate variable among the N second intermediate variables. Information processing device as described in Technical Proposal 13.

[0242] [Technical proposal 16] The information processing circuit, in acquiring the data, acquires market packets as the data from a market server device that conducts transactions on N objects (where N is an integer of 2 or more). The market packet includes the transaction price for at least one of the N items, The cost function includes N decision variables as the plurality of decision variables, The nth decision variable among the N decision variables (where n is an integer between 1 and N) represents whether or not to trade the nth item among the N items. An information processing device described in any one of Technical Proposals 1 to 15.

[0243] [Technical proposal 17] The aforementioned data includes coordinate data representing the coordinates of at least one object. An information processing device described in any one of Technical Proposals 1 to 15.

[0244] [Technical proposal 18] An information processing method that performs processing on data using an information processing device, The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, Each of the multiple terms constituting the cost function is represented by the multiplication of one or more decision variables from the multiple decision variables and one of the weight values ​​from the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the multiple weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. Information processing methods.

[0245] [Technical proposal 19] A program for causing a computer to function as the information processing circuit in an information processing device comprising a solver device for solving combinatorial optimization problems and an information processing circuit, The aforementioned information processing device performs processing on the data, The aforementioned computer, Obtain the aforementioned data, Based on the aforementioned data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver. Make it work like this, The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The computer generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The computer, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. program.

[0246] [Technical proposal 20] Circuit information describing the configuration of a circuit, written in a hardware description language, The aforementioned circuit is made to function as an information processing device that performs processing on data. The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. Circuit information.

[0247] [Technical proposal 21] Circuit information written to a reconfigurable semiconductor device in order to operate the said reconfigurable semiconductor device, The reconfigurable semiconductor device is made to function as an information processing device that performs processing on data. The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. Circuit information. [Explanation of symbols]

[0248] 10 Market System 12 Market Server Equipment 14 Client devices 16 Receiving Unit 17 Matching Department 18 Distribution Department 20 Information Processing Devices 32 Input Memory 36 Acquisition Department 40 Solver device 42 Problem generation part 46 Processing Execution Unit 50 weight memory 52 Pattern Memory 60 Pseudocode 62 Search circuit 64 Partial area identification circuit 66 Partial Address Identification Circuit 68 Selector 70 partial memory 71 Arithmetic circuit 72 Input Circuits 73 Output Circuit 74 Setting Circuit 81 X memory 82 Y memory 83 Action calculation circuit 84-hour time evolution circuit 85 Control circuits 91 J Memory 92 H memory 93 Matrix calculation circuit 94 Alpha function circuit 95 First Adder Circuit 111 First Part Memory 112 Second Part Memory 113 Pattern Selector 115 Multiplier Circuit 116 Cumulative Adder Circuit 121 Adder 122 Reset Selector 123 Second latch circuit 131 First Multiplier Circuit 132 Second Multiplier Circuit 133 First cumulative adder circuit 134 Second cumulative adder circuit 137 Output Selector 210 Control System 212 Object detection device 214 Control device

Claims

1. An information processing device that performs processing on data, A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The aforementioned information processing circuit is In generating the combinatorial optimization problem, the plurality of weight values ​​are generated based on the data, and the plurality of weight values ​​are written to the first memory. In writing the plurality of weight values, the first partial weight group and the second partial weight group are written to a common area in the first memory, and first information indicating the storage location of each of the plurality of weight values ​​in the first memory is provided to the solver device. The solver device reads the plurality of weight values ​​from the first memory based on the first information and obtains the solution. Information processing device.

2. The information processing circuit further obtains the solution to the combinatorial optimization problem from the solver device and performs processing based on the solution. The information processing apparatus according to claim 1.

3. The first weight value among the plurality of weight values ​​is identified by an index representing a position in a predetermined first region. The predetermined first region is divided into M subregions having the same shape (where M is an integer of 3 or more), The first subregion among the M subregions includes a subweight group which is a part of the plurality of weight values, The subweight group arranged in each of the M subregions is represented by one of K patterns (where K is an integer between 2 and M), The first memory stores the K patterns, The first information indicates which of the K patterns each of the M subregions contains the subweight group of. The information processing apparatus according to claim 1.

4. The solver device further includes a second memory for storing the first information, The aforementioned information processing circuit, in generating the combinatorial optimization problem, Based on the above data, the subweight group of the K patterns is generated and written to the first memory. Based on the aforementioned data, the first information is generated and written to the second memory. The information processing apparatus according to claim 3.

5. When reading the first weight value from the plurality of weight values, the solver device, Of the M subregions, identify the subregion that contains the first weight value. Based on the first information, identify the pattern in the subregion containing the first weight value among the K patterns, Identify a first address representing the position of the first weight value in the subregion containing the first weight value, From the first memory, the weight value identified by the first address in the sub-weight group of the identified pattern is read out as the first weight value. The information processing apparatus according to claim 4.

6. The cost function includes, as the plurality of decision variables, N decision variables (where N is an integer of 2 or more), and as the plurality of weight values, a matrix containing weight values ​​with N rows × N columns. The cost function is expressed as a quadratic function of the N decision variables. The information processing apparatus according to claim 3.

7. Each of the aforementioned multiple decision variables is a binary discrete variable. The information processing apparatus according to claim 6.

8. The aforementioned combinatorial optimization problem is a QUBO (Quadratic Unconstrained Binary Optimization) problem. The information processing apparatus according to claim 7.

9. The solver device solves the QUBO problem by reducing it to an Ising problem that minimizes the Ising model. The information processing apparatus according to claim 8.

10. The solver device solves the Ising problem using a simulated branching algorithm. The information processing apparatus according to claim 9.

11. The cost function is a function of order three or higher of the multiple decision variables, The aforementioned combinatorial optimization problem is a HUBO (Higher Order Binary Optimization) problem. The information processing apparatus according to claim 7.

12. The solver apparatus is, A matrix operation circuit that calculates N second intermediate variables at the first time step by performing matrix multiplication with the matrix, and A first circuit that calculates N first variables at a second time after the first time and N second variables at the second time based on the N second intermediate variables at the first time, A control circuit that causes the matrix arithmetic circuit and the first circuit to execute processing from the start time to the end time, An output circuit that generates and outputs the solution based on the N first variables at the aforementioned end time, Equipped with, In the Ising model described above, the i-th spin among the N spins (where i is an integer between 1 and N) corresponds to the i-th point among the N points. The i-th of the N first variables corresponds to the i-th spin, The i-th of the N second variables corresponds to the i-th spin, The i-th first variable represents the position of the point corresponding to the i-th spin, The i-th second variable represents the momentum of the point corresponding to the i-th spin, The i-th first intermediate variable among the N first intermediate variables corresponds to the i-th first variable, The i-th first intermediate variable is the i-th first variable or the value obtained by multiplying the i-th first variable by a predetermined coefficient. The i-th second intermediate variable among the N second intermediate variables corresponds to the i-th second variable. The information processing apparatus according to claim 10.

13. Each of the N x N weight values ​​included in the matrix is ​​J ｉ，ｊ It is represented by, The above i represents the row number of the matrix, The aforementioned j represents the column number of the matrix, and is an integer between 1 and N, The N weight values ​​included in row i of the matrix are one of the K patterns, The first information indicates which of the K patterns each of the N rows in the matrix corresponds to. The first memory includes K sub-memories, The k-th sub-memory of the K sub-memories (where k is an integer between 1 and K) stores the k-th pattern of the K patterns. The information processing apparatus according to claim 12.

14. The aforementioned matrix operation circuit is A first selector selects and outputs the N weight values ​​output from the partial memory corresponding to the pattern of the i-th row shown in the first information, out of the K partial memories, A cumulative summing circuit outputs the result of cumulatively summing the product of each of the N weight values ​​output from the first selector with the j-th first intermediate variable among the N first intermediate variables, as the i-th second intermediate variable among the N second intermediate variables. The information processing apparatus according to claim 13, including the following:

15. The aforementioned matrix operation circuit is K cumulative adder circuits, Output selector and Includes, The k-th cumulative adder among the K cumulative adder circuits outputs a cumulative adder result obtained by multiplying each of the N weight values ​​output from the k-th sub-memory among the K sub-memories by the j-th first intermediate variable among the N first intermediate variables, and then cumulatively adding the results. The output selector outputs the cumulative sum result from the cumulative sum circuit corresponding to the i-th pattern shown in the first information, among the K cumulative sum circuits, as the i-th second intermediate variable among the N second intermediate variables. The information processing apparatus according to claim 13.

16. The information processing circuit, in acquiring the data, acquires market packets as the data from a market server device that conducts transactions on N objects (where N is an integer of 2 or more). The market packet includes the transaction price for at least one of the N items, The cost function includes N decision variables as the plurality of decision variables, The nth decision variable among the N decision variables (where n is an integer between 1 and N) represents whether or not to trade the nth item among the N items. The information processing apparatus according to any one of claims 1 to 15.

17. The aforementioned data includes coordinate data representing the coordinates of at least one object. The information processing apparatus according to any one of claims 1 to 15.

18. An information processing method that performs processing on data using an information processing device, The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, Each of the multiple terms constituting the cost function is expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the multiple weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. Information processing methods.

19. A program for causing a computer to function as the information processing circuit in an information processing device comprising a solver device for solving combinatorial optimization problems and an information processing circuit, The aforementioned information processing device performs processing on the data, The aforementioned computer, Obtain the aforementioned data, Based on the aforementioned data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver. Make it work like this, The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The computer generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The computer, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and finds the solution. program.

20. Circuit information describing the configuration of a circuit, written in a hardware description language, The aforementioned circuit is made to function as an information processing device that performs processing on data. The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and obtains the solution. Circuit information.

21. Circuit information written to a reconfigurable semiconductor device in order to operate the said reconfigurable semiconductor device, The reconfigurable semiconductor device is made to function as an information processing device that performs processing on data. The aforementioned information processing device is A solver device for solving combinatorial optimization problems, Information processing circuit and, Equipped with, The aforementioned information processing circuit is Obtain the aforementioned data, Based on the above data, the combinatorial optimization problem is generated, and the combinatorial optimization problem is to be solved by the solver device. The cost function in the aforementioned combinatorial optimization problem includes multiple decision variables and multiple weight values, The terms included in the cost function are expressed by multiplying one or more of the multiple decision variables by any one of the multiple weight values. The first subweight group, which is a part of the aforementioned plurality of weight values, is identical to the second subweight group, which is another part. The solver device includes a first memory for storing the plurality of weight values, The information processing circuit generates the plurality of weight values ​​based on the data in generating the combinatorial optimization problem, and writes the plurality of weight values ​​to the first memory. The information processing circuit, in writing the plurality of weight values, writes the first partial weight group and the second partial weight group to a common area in the first memory, and provides the solver device with first information indicating the storage location of each of the plurality of weight values ​​in the first memory. The solver device reads the plurality of weight values ​​from the first memory based on the first information and obtains the solution. Circuit information.

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