DRAM-less multilevel cell programming using NAND buffers

Abstract

To provide a DRAM-less multi-level cell programming method using a NAND buffer, and a device.SOLUTION: Programming multi-level cell (MLC) non-volatile (NV) media by reusing built-in buffers is performed to reduce the need for external buffering. The built-in buffer resides on the same die as the NV medium to be programmed, along with a volatile memory for storing data to be programmed. The buffer is to read and program data for the NV media. The programming for the NV medium includes: staging a first partial page in the buffer for the program; reading a second partial page from the NV medium into the volatile memory; and storing the second partial page in the buffer and programming the NV medium on the first partial page and the second partial page.SELECTED DRAWING: Figure 6A

Description

Technical Field

[0001] The described matters are generally related to non-volatile memories. More specifically, the described matters are related to the programming of multi-level cell type non-volatile memories.

Background Art

[0002] Non-volatile storage or non-volatile memory is used for large-capacity storage of computing devices and gaming machines. Non-volatile storage refers to storage that maintains a definite state even when power to the memory is cut off. As the demand for devices increases, the storage space continues to increase. The increase in capacity has been achieved by replacing single-level cells (SLCs) with multi-level cells to increase data density. A multi-level cell can include 2 bits, 3 bits, 4 bits, or even 5 bits per cell.

[0003] Multi-level cells are slower to program than SLCs. The programming of multi-level cells is usually assisted by volatile memory. However, adding a volatile memory device for programming non-volatile storage increases the cost of the non-volatile storage device. For example, for the programming of QLC (quad-level cell), it is necessary to program data for 4 pages, and this data can be as large as 4 MG (megabytes) for a 2 TB (terabyte) drive and is cached in a DRAM (dynamic random access memory) device.

[0004] DRAM-less storage devices exist for three-level cell (TLC) architectures, and these devices have an on-die volatile buffer of approximately 256KB to 384KB. However, with QLC devices, programming using the volatile buffer requires a significantly larger volatile buffer, sometimes requiring approximately 1 to 4MB of memory. Including 1 to 4MB of volatile memory is challenging from the standpoint of cost and die area.

[0005] As an alternative to providing buffers on the non-volatile die, this system can utilize the system's main memory space as a programming data cache. Using system memory as a data cache requires accessing the cache via the host memory bus, which can result in a significant performance penalty due to sharing host bandwidth. Furthermore, considering that the communication bus transitions to a low-power state during the time garbage collection occurs, programming garbage collection routines on the host memory bus is not feasible. Neither using high-capacity on-die volatile storage nor using the host memory bus to access main memory are scalable solutions for increased-capacity non-volatile devices. [Brief explanation of the drawing]

[0006] The following description includes a discussion of diagrams with examples given as illustrations of implementations. These diagrams should be understood as illustrations and not as limitations. In this specification, references to one or more examples are understood to describe a particular function, structure, or feature included in at least one implementation of the invention. Expressions such as "in one example" or "in an alternative example" appearing herein provide examples of implementations of the invention and do not necessarily refer to the same implementation. However, these expressions are not necessarily mutually exclusive.

[0007] [Figure 1]This is a block diagram of an example system with a solid-state drive.

[0008] [Figure 2] This is a block diagram of an example of a non-volatile die with a multi-stage program.

[0009] [Figure 3] This is a block diagram of an example of a non-volatile die equipped with SLC and QLC storage.

[0010] [Figure 4] This is a swimlane diagram illustrating an example of multi-stage program operation in a multi-level cell non-volatile memory.

[0011] [Figure 5] This is a flowchart illustrating an example of the process for programming a multilevel cell non-volatile memory.

[0012] [Figure 6A] This is a block diagram of an example system with a hardware diagram of a solid-state drive (SSD) equipped with a non-volatile array having an internal buffer for multi-stage program operation.

[0013] [Figure 6B] This is a block diagram of an example of a logical diagram for a system having a solid-state drive (SSD) with a non-volatile array that has an internal buffer for multi-stage program operation.

[0014] [Figure 7] This is a block diagram of an example of a computing system in which a non-volatile array with an internal buffer for multi-stage program operation may be implemented.

[0015] [Figure 8]This is a block diagram of an example of a mobile device in which a non-volatile array with an internal buffer for multi-stage program operation may be implemented.

[0016] The following is a description of specific details and implementation forms, which includes a non-exclusive description of diagrams that may illustrate some or all examples and other possible implementation forms. [Modes for carrying out the invention]

[0017] As described herein, multilevel cell (MLC) non-volatile (NV) media may be programmed by reusing an internal buffer to reduce the need for external buffering. The internal buffer resides on the same die as the NV media to be programmed, along with volatile memory that stores the data to be programmed. The internal buffer is for reading data for programming the NV media. Programming the NV media involves staging a first partial page into the buffer for programming, reading a second partial page from the NV media into volatile memory, storing the second partial page in the buffer, and programming the NV media with the first and second partial pages.

[0018] The programming method using the built-in buffer described above provides a scalable solution that does not require additional volatile memory space, whether using on-die memory (such as SRAM (Synchronous Random Access Memory)) or off-die memory (such as DRAM (Dynamic Random Access Memory)), and does not negatively impact performance. Because this programming method utilizes already available built-in buffer space, it is scalable and can be repurposed for different programming operations. Programming using the built-in buffer to buffer write data can be applied to DRAM-less SSDs (Solid State Drives).

[0019] In one example, programming using an embedded buffer enables programming of a DRAM-less QLC NAND-based SSD, even though an additional programming stage is required (while QLC has programming A and B, TLC (triple-level cell) has only program A). Garbage collection of TLC NAND-based SSDs may include an ASIC-based SRAM buffer of about 256 KB to 384 KB, which is sufficient for a QLC SSD with a quad-plane NAND die and a four-channel controller when the embedded buffer is utilized appropriately.

[0020] As a specific example, consider a storage device such as an SSD that uses QLC (quad-level cell) NAND. NAND-based non-volatile memory is generally referred to as flash memory. QLC flash includes an embedded latch or register that operates as an embedded buffer for data transfer between the non-volatile QLC memory array. The embedded register is typically used for internal operations of the NAND. In one example, firmware in a media controller can repurpose the embedded register for system purposes to hold the necessary data and program the NAND flash array. In one example, the SSD firmware performs QLC programming and garbage collection using the embedded buffer. Using the embedded buffer for programming QLC NAND flash results in no power penalty during garbage collection suspension.

[0021] This programming enables a DRAM-less solution that reduces the SRAM footprint on an ASIC (application-specific integrated circuit) controller for flash memory. This solution reduces the cost and power of systems that utilize it, such as hybrid SSDs that include a hybrid SSD that utilizes a QLC non-volatile media and a 3DXP (3D cross-point) write buffering media.

[0022] FIG. 1 is a block diagram of an example of a system including a solid state drive. System 100 includes a host 110 coupled to a solid state drive (SSD) 120. Host 110 represents a computing system platform that stores data in SSD 120. SSD 120 represents a storage device of system 100. The computing system platform may be, for example, a laptop, a gaming console, a tablet or other handheld system, or other computing system.

[0023] Host 110 includes a processor 112, which represents a host processor or primary processor for a computing device of system 100. Processor 112 may be any type of processor, such as a central processing unit (CPU) system on a chip (SOC), a graphics processing unit (GPU), or other processor or controller that performs operations to trigger access to storage resources on SSD 120.

[0024] Host 110 includes an interface 114, which represents an interface for accessing SSD 120. Interface 114 may include hardware, such as signal lines, drivers, receivers, or other hardware for communicating with SSD 120. SSD 120 includes a host interface 122 for communicating with host 110. In one example, interface 114 and host interface 122 can communicate according to the Non-Volatile Memory Express (NVMe) specification. The NVMe specification defines a register-level interface of host software that communicates with an SSD via the Peripheral Component Interconnect Express (PCIe), i.e., a high-speed serial computer expansion bus. The NVM Express specification is available at www.nvmexpress.org. The PCIe specification is available at pcisig.com.

[0025] In one example, the host 110 includes a controller 116, which represents a host-side controller for managing the host's access to the SSD 120. The controller 116 can manage an interface 114 that allows the host 110 to communicate with the SSD 120. The controller 116 receives requests from the processor 112 or another component on the host 110 for data stored in the SSD 120. These requests may be read requests to access data at a specific location, or write or program requests to send data to the SSD 120 for storage.

[0026] In one example, the SSD 120 includes a controller 140, which represents a storage-side controller for managing the host interface 122 and generating internal operations to respond to requests from the host 110. The controller 140 represents the controller of the SSD device itself and can control access to the NVM (non-volatile memory) die 150 and the volatile memory 160. In one example, the SSD 120 may include volatile memory 160 as an internal cache for program or write operations to improve program time between the buffer 130 and the NVM die 150. The program operations described herein can be used to eliminate the volatile memory 160 from the SSD 120. If the SSD 120 includes volatile memory 160, the controller 140 may include a volatile memory (vol mem) control unit 142 that manages access to the volatile memory device. The controller 140 includes an NVM control unit 144 that manages access to the NVM die 150.

[0027] In one example, the SSD120 includes a buffer 130 as a write buffer or write cache for caching write data sent to the SSD120. In one example, buffer 130 may represent a fast-accessible read buffer for holding frequently accessed data in the storage medium. Buffer 130 has a smaller storage capacity than the NVM die 150, but has a shorter access time than the NVM die 150.

[0028] In one example, buffer 130 is a region of NV die 150. For example, NVM die 150 may include a large QLC storage array as primary storage and a smaller SLC storage array as a cache. To improve write times to SSD 120, data may first be written to buffering 130 or an SLC region with shorter write times than would be achieved by writing directly to a QLC region or other multilevel cell region. The data may then be transferred to a multilevel cell region via garbage collection operations (referring to background processing that moves data).

[0029] The controller 140 represents an off-die control device with respect to the NVM die 150. The NVM die 150 may include an on-die controller that manages operations within the NVM die, which is independent of the controller 140. The controller 140 can queue and process commands such as read commands, write or program commands, or erase commands for the NVM die 150, as well as read and write commands for the volatile memory 160.

[0030] The SSD120 includes one or more NVM dies 150. Details of a single die are shown in System 100. In one example, the NVM die 150 is a multiplane die with multiple independent storage channels to improve data access bandwidth.

[0031] The NVM die 150 includes an NVM array 152, which represents a storage medium for the SSD 120. In one example, the NVM die 150 includes a buffer 156, which may represent a register or flip-flop within the NVM die 150 as a buffer interfaced with the NVM array 152. The NVM array 152 may be implemented as any memory medium for writing data to multilevel cells (such as TLC, QLC, 5LC, or MLC implementations of 3DXP), provided that the NVM array has an internal buffer for performing the described program operations. Using the internal buffer 156, the write operation is self-contained within the NVM die 150, eliminating the requirement for external cache resources to perform data transfer and programming of the MLC cells.

[0032] In one example, the NVM die 150 includes a static random access memory (SRAM) 154 within the die as a volatile memory buffer for caching programming operations. For programming operations, the SRAM 154 may contain blocks of data to be written to the NVM array 152, and the buffer 156 contains space for a small number of pages to measure the time for reading from or writing to the NVM array 152. Thus, the SRAM 154 and buffering 156 can provide a cache or buffer for programming operations, and the buffer 156 can provide a place to hold data for programming operations, while other data is loaded into the SRAM 154 and all writes are completed.

[0033] Known QLC SSDs have an "SLC-first" architecture, where host data is written to the NAND in SLC mode, and then rewritten to the NAND in QLC mode during background garbage collection. In one example, the QLC NAND has a two-step or two-stage programming sequence, namely a first stage that writes four states and a second stage that writes sixteen states. In one example, the write in the second stage requires the data from the first stage to be read from the NAND beforehand.

[0034] Garbage collection in SSD120 requires moving valid data from source memory (such as buffer 130, which may be another NAND block or other medium), verifying that valid data, and writing it to the destination NAND block of NVM array 152. Buffer 156 may be a read / write buffer. In normal read or write operations, the data registers or contents of the storage medium in buffer 156 may be overwritten during normal operation. In one example, NVM die 150 is configured to store data between read operations until the data is programmed into NVM array 152.

[0035] In one example, valid data matching involves writing the first portion of the data to buffer 156 and leaving that data in buffer 156, while the remaining portion of the data is read to a volatile medium (such as SRAM 154). In one example, reading to SRAM 154 or volatile memory may involve performing ECC (Error Detection and Correction) on the data. Thus, the data may be error-corrected before being written to the NVM array 152. The remaining portion of the data may also be written to buffer 156, and then all the data may be written from buffer 156 to the NVM array 152.

[0036] For garbage collection, buffer 130 may be a source medium or source memory device that provides data to be written to the NVM array 152. In one example, buffer 130 includes SLC flash. In another example, buffer 130 includes 3DXP. In another example, programming using buffer 156 may be performed between other memory medium and the NVM array 152. For example, the source medium for programming may be a volatile buffer of DRAM (e.g., if volatile memory 160 is used in SSD 120), a non-volatile medium (TLC, another QLC array, 5LC (five-level cell), etc.), or another medium.

[0037] Figure 2 is a block diagram of an example of a non-volatile die with a multi-stage program. System 200 represents a non-volatile die following the example of the NVM die 150 in System 100. System 200 includes an array 230, a buffer 210, and a buffer 220.

[0038] In one example, array 230 is a NAND array that can operate in SLC mode or MLC mode. In SLC mode, array 230 can store single bits of data (binary bits) per memory cell. In multilevel cell mode, the array stores multi-bit data by storing the data as one of several levels of voltage stored in the cell. In one example, array 230 is another non-volatile medium that can store data in binary mode or multilevel cell mode. Array 230 is a destination storage device for program or write operations in MLC mode. In one example, array 230 may be a source in SLC mode.

[0039] Buffer 210 represents a volatile memory buffer. In one example, buffer 210 is an SRAM memory on-die with array 230. In another example, buffer 210 is a DRAM array. Buffer 210 may be a buffer interface to a storage medium located off-die from array 230.

[0040] Buffer 220 represents a read / write buffer for array 230. In a read operation, buffer 220 stores data to be read into buffer 210. In a write operation, buffer 220 may be a staging buffer for loading data into program array 230. In one example, buffer 220 stores write data in the following array read operation and SLC / QLC mode switching operation.

[0041] Although not explicitly stated, array 230 stores data as data blocks, and each block contains multiple pages of data. Each page of data contains multiple bits of data and associated metadata. For example, the array may contain 2K (2048) blocks, each block having 64 pages of 2K bytes of data (and 64 bytes of metadata). Access to read and write data is performed page by page and block by block.

[0042] In one example, system 200 implements the QLC write algorithm and page sequence as follows: In the first write or program stage, the controller (not specifically shown) writes two pages of word lines [N]. In the second write or program stage, the controller writes another two pages of data. In one example, the second stage writes data from another word line in a stepwise manner. By alternating the word lines, the read window budget of the QLC device can be improved, enabling faster programming. The time delay required for sequential programming operations on different word lines is shorter than the time delay required for sequential programming operations on the same word line. Therefore, by writing in a stepwise manner, that is, by writing to one word line in the first program stage and to another word line in the second stage, the overall programming operation is made faster.

[0043] In one example, the controller writes two pages of WL[N-2] in the second stage. In another example, the controller may write two pages of WL[N-1]. It has been confirmed that writing to addresses two or more hops apart can lead to improved writing performance and reduced errors. Therefore, programming can be written to, for example, WL[N], WL[N-2], WL[N+1], WL[N-1], etc. In one example, the program in the second stage may include reading two pre-programmed pages in the first stage of programming to the word line to be written. In one example, the system performs ECC on the read data and then retransmits the data pattern along with the two new pages to be programmed.

[0044] Let's consider the garbage collection procedure in one specific example: writing data to array 230. The data is written, for example, from an SLC NAND device to a QLC NAND device. Therefore, array 230 may represent a QLC NAND device to which data from an SLC NAND device (not shown) is written.

[0045] This operation can begin by loading the data indicated by load data 242 from the SLC-type NAND into buffer 210. In one example, buffer 210 represents a static data cache (SDC), which represents a buffer outside of array 230. In one example, buffer 210 stages the first portion of data (stage data 244) into buffer 220. In the SLC to QLC write, in one example, the first portion consists of two pages of data. The first portion of data may be called the first partial page, referring to the fact that this portion is only a small part of all the pages written to array 230. Thus, system 200 shows two lines (each line representing one page of data), namely the line between register[0] of buffer 210 and buffer 220, and the line between register[1] of buffer 210 and buffer 220. In one example, pages are loaded one at a time into buffer 220.

[0046] In one example, buffer 220 represents a programmable data cache (PDC), and N registers (registers[0] to [N-1]) represent buffer hardware associated with array 230 for programming the array. In one example, a media controller controls the flash 246 of the first portion of data from registers[0] and[1] to array 230. Loading data into the first flash 246 may be considered the first stage of programming array 230.

[0047] In one example, additional data, data for a second part (e.g., data for two other pages), or a second partial page may be loaded into buffer 210. The data for the second part may be staged into buffer 220, as indicated by the stage data 260. In the first part of this operation, the data may be loaded into register [2] and another register (e.g., register [3]), but there is no requirement that the data be loaded into sequential registers or address locations in buffer 220.

[0048] In one example, the controller reads the first portion of the data from array 230, as shown in read 248. In read 248, the data is read from array 230 into a register in buffer 220. In one example, system 200 can provide a read of data to a device outside of system 200, as shown in read 250. In read 250, the data is read from buffer 210 to another part of the computer system (of which system 200 is a part).

[0049] In one example, the controller maintains this data in register[2] and other registers while other data is being read. In one example, system 200 performs ECC on the read data and stores this data or corrected data in buffer 210. Buffer 210 may then stage the read data in buffer 220. In one example, the data is shown to be staged in registers[0] and register[1], as shown in stage data 260. It will be understood that other registers or address spaces in buffer 220 may be used to stage the first portion of the updated data.

[0050] In one example, the controller flushes both portions of the data to array 230, as shown in flash 262. Regardless of the specific location within buffer 220 where the data is stored, it is generally understood that the controller manages the reading and storing of data into buffer 220 and that programming can be performed without the use of an external buffer.

[0051] In one example, the controller resets buffer 220 in response to the loading of new data into buffer 210. The loading of new data may be controlled to hold data used to program array 230. In one example, the held data may include data for another word line if system 200 is programmed stepwise. In one example, the controller flushes buffer 210 when a new address is loaded to indicate that an operation is being performed on another part of the data.

[0052] In one example, a higher page triggers a data flush. In one example, the controller may issue a flush in response to the loading of a higher page. Thus, in response to a new address being loaded for programming, system 200 can flush two parts of data to program all the data into array 230. In one example, system 200 supports explicit flush commands or instructions from an off-die medium controller. Thus, in response to a flush command, system 200 can flush two parts of data to program all the data into array 230.

[0053] Figure 3 is a block diagram of an example of a non-volatile die equipped with SLC and QLC storage. The NVM die 300 represents a non-volatile die according to an example of the NVM die 150 in system 100 or an example of system 200.

[0054] The NVM die 300 includes a buffer 302, which represents an internal buffer for the NVM's QLC block 320. The NVM die 300 uses the buffer 302 to program the NVM's QLC block 320, so that data does not need to be buffered or cached and go outside the NVM die to match the QLC write data. The buffer 302 allows the NVM die 300 to write data from the NVM's SLC block 310 to the NVM's QLC block 320, for example, as part of an internal copy from a block configured in SLC mode to a block configured in QLC mode.

[0055] An NVM's SLC block 310 represents a block configured in SLC mode, and an NVM's QLC block 320 represents a block configured in QLC mode. An NVM's SLC page 312 represents one or more pages of SLC data. An NVM's QLC page 322 represents one or more pages of QLC data. Four NVM SLC blocks 310 may be stored in one NVM QLC block 320, and four NVM SLC pages 312 may be stored in one NVM QLC page 322.

[0056] The internal controller 304 represents a controller or media controller located inside the NVM die 300. In one example, the internal controller 304 manages the transfer of data from the NVM's SLC block 310 to the NVM's QLC block 320. In one example, the internal controller 304 runs firmware that controls garbage collection from the NVM's SLC block 310 to the NVM's QLC block 320. The internal controller 304 may control data transfer to and from a buffer 302, which includes holding write data in the buffer and staging that data for writing to the NVM's QLC block 320 or for matching with other write data for its program. In one example, the internal controller 304 manages four selected copies of the NVM's SLC block 310 on the NVM die 300, which includes temporarily storing data in the buffer 302 before writing it to the NVM's QLC block 320.

[0057] Figure 4 is a swimlane diagram of an example of a multistage program operation of a multilevel cell non-volatile memory. Programming 400 shows a multistage operation that may be performed by an example of system 200 or NVM die 300. The shown programming may be an example of programming two bits for two pages or a first pass or first stage of this programming, followed by programming two more bits for two more pages for a second pass or second stage. This programming may be controlled and operated by an internal controller of the NVM die being programmed, the NVM die including a source medium and a destination medium.

[0058] In one example, a QLC SSD has a front-end SLC write buffer, and all host data passes through the SLC buffer before being written back to the QLC. In one example, the movement from SLC to QLC may be designed as a FIFO (First-In, First-Out) method. In one example, the movement from SLC to QLC may be designed as a LIFO (Last-In, First-Out) method. In one example, the movement from SLC to QLC may be designed as an effectiveness method.

[0059] The following explanation assumes a FIFO (First-In, First-Out) architecture. The following explanation assumes that the smallest atomic unit is four pages of host writes to the SLC, and that four background pages move from the SLC to the QLC. Therefore, the controller may include a write pointer pointing to the top of the stack and a read pointer pointing to the end of the stack. Thus, this operation writes up to N and reads data from 0.

[0060] Programming 400 describes operations performed on a source medium and controller (identified as firmware or FW), SRAM as a volatile buffer, and an NVM medium. In one example, the NVM medium has a source mode for the NVM medium. In one example, the source mode is SLC mode, and data is first written to the SLC as a write cache. In one example, a host write to source mode requires other operations, such as storing the host write data on another source NVM medium and transferring it to a QLC mode medium (QLC to QLC, TLC to QLC, two-level cell, etc. (sometimes abbreviated as MLC, more commonly used herein as any cell that stores two or more bits of data)).

[0061] In one example, in 402, the host writes four pages from the source medium to the destination medium. In 404, this program performs a source-mode write (WR) to block (BLK)[N] on the source medium. In 406, this program performs a source-mode read (RD) from block (BLK)[0]. It will be understood that writes may be performed to BLK[N], during which garbage collection writes from source BLK[0] to BLK[N] in QLC mode, writes to the top address of the stack, and reads for transfer are performed from the lowest address of the stack.

[0062] In 408, a read from source mode is specified as a read of page[1] into SRAM. In 410, SRAM stores page[1]. In 412, SRAM stages page[1] for writing, and the NVM medium loads page[1] into its internal buffer. In 414, this programming performs a source-mode read (RD) from block (BLK)[0]. In 416, a read from source mode is specified as a read of page[2] into SRAM. In 418, SRAM stores page[2]. In 420, SRAM stages page[2] for writing, and the NVM medium loads page[2] into its internal buffer.

[0063] In one example, at 422, the firmware (FW) triggers a program from the internal buffer to the QLC mode medium. At 424, this programming performs the first stage QLC mode write to WL[N]. This program becomes the lower pages, LP and UP, of WL[N] on the QLC mode medium.

[0064] At 426, this program performs a source-mode read (RD) from block (BLK)[0]. At 428, the source-mode read is specified as a read of page [3] into SRAM. At 430, SRAM stores page [3]. At 432, SRAM stages page [3] for writing, and the NVM medium loads page [3] into its internal buffer. At 434, this program performs a source-mode read (RD) from block (BLK)[0]. At 436, the source-mode read is specified as a read of page [4] into SRAM. At 438, SRAM stores page [4]. At 440, SRAM stages page [4] for writing, and the NVM medium loads page [4] into its internal buffer.

[0065] In one example, the final programming of the QLC medium is performed using pages [3] and [4] that were loaded into an internal buffer for another word line, as well as data from pages [1] and [2] read back from the QLC medium. These pages may be pages for another word line, and include pages that are staged and maintained in an internal buffer to await a second stage of the program.

[0066] In 442, this programming performs a QLC mode pre-programmed read (PRE-RD) from WL[N-2]. In 444, the read from source mode is specified as a read of the first stage page[1] for WL[N-2] into SRAM. In 446, SRAM stores the first stage page[1], which is identified as page[1a]. In 448, SRAM stages page[1a] for writing, and the NVM medium loads page[1a] into its internal buffer. In 450, this programming performs a QLC mode pre-programmed read (PRE-RD) from WL[N-2]. In 452, the read from source mode is specified as a read of the first stage page[2] for WL[N-2] into SRAM. In 454, SRAM stores the first stage page[2], which is identified as page[2a]. In 456, SRAM stages page[2a] for writing, and the NVM medium loads page[2a] into an internal buffer.

[0067] In one example, at 458, the firmware (FW) triggers a program from the internal buffer to the QLC mode medium. At 460, this programming performs the second stage writing of QLC mode to WL[N-2]. This program becomes the upper and lower pages, LP, UP, XP, and TP of WL[N-2] on the QLC mode medium.

[0068] Figure 5 is a flowchart illustrating an example of the process for programming a multilevel cell non-volatile memory. Process 500 shows an example of the process for programming the multilevel cells of the NVM. In one example, at 502, the NVM die receives multiple pages of data from the host for programming. In another example, at 504, the NVM die reads and stages these pages individually for programming onto the destination NVM medium.

[0069] In 508, the controller of the NVM die may stage a page for writing to an internal buffer of the destination medium to which the NVM die is moved. If the decision branch in 510 indicates that the controller is not ready to program the NV medium, the controller may identify the next page to be read from the source medium in 512 and return to 506 to read the next page into volatile memory. In one example, the controller decides to program the NV medium based on whether a flash trigger or a program trigger has been received. A program trigger may be the loading of a new address for writing. A program trigger may be the reception of a command indicating a program operation.

[0070] If the controller programs the NV medium at the affirmative branch 510, in one example, at 514 the controller determines whether there are still pages to program in this program path. In one example, if there are still pages to program at the affirmative branch 516, at 518 the controller may increment the write stage and return to the programming operation. If there are other stages to program, there may still be pages to program. The controller then identifies the next page to read at 512 and may return to 506 to read the next page into volatile memory.

[0071] In one example, if there are no more pages of data to write to the NV medium at the negation branch 516, the entire page is staged in an internal buffer, and the controller is ready to program the NV medium. The medium controller may then program the NV medium using the data from these pages at 520.

[0072] Figure 6A is a block diagram of an example system with a hardware diagram of a solid-state drive (SSD) equipped with a non-volatile array having an internal buffer for multi-stage program operation. System 602 represents the components of a non-volatile storage system capable of performing multi-stage program operation according to programming 400. System 602 may include an NVM die according to an example of System 200 or an example of NVM die 300.

[0073] System 602 includes an SSD 620 coupled to a host 610. Host 610 represents a host hardware platform connected to the SSD 620. Host 610 includes a CPU (Central Processing Unit) 612 or other processor as a host processor or host processor device. CPU 612 represents any host processor that generates requests to access data stored in the SSD 620, to read data, or to write data to storage. Such processors may include single-core or multi-core processors, primary processors for computing devices, graphics processors, peripheral processors, spare or auxiliary processors, or a combination thereof. CPU 612 may run the host OS and other applications to cause operations of System 602.

[0074] The host 610 includes a chipset 614, which represents hardware components that may be involved in the connection between the CPU 612 and the SSD 620. For example, the chipset 614 may include interconnection circuits and logic that enable access to the SSD 620. Therefore, the host platform 610 may include a hardware platform drive interconnect that connects the SSD 620 to the host 610. The host 610 includes hardware that interconnects to the SSD. Similarly, the SSD 620 includes corresponding hardware that interconnects to the host 610.

[0075] The host 610 includes a controller 616, which represents the host-side storage controller or memory controller and controls access to the SSD 620. In one example, the controller 616 is included in the chipset 614. In another example, the controller 616 is included in the CPU 612. The controller 616 is sometimes called an NV memory controller, which allows the host 610 to schedule and prepare commands to the SSD 620 for reading and writing data.

[0076] SSD620 represents a solid-state drive or other storage system or module that includes a non-volatile (NV) medium 630 for storing data. SSD620 includes a hardware interface 622, which represents a hardware component that interfaces with the host 610. For example, the hardware interface 622 can interface with one or more buses that implement high-speed interface standards such as NVMe (Non-Volatile Memory Express) or PCIe (Peripheral Component Interconnect Express).

[0077] In one example, SSD620 includes an NV (non-volatile) medium 630 as the primary storage of SSD620. In one example, the NV medium 630 is or includes a block-addressable memory technology such as NAND (negative AND) or NOR (negative OR). In one example, the NV medium 630 may include a non-volatile block-addressable medium, a non-volatile byte-addressable medium, or a non-volatile medium that can be both byte-addressable and block-addressable. In one example, the non-volatile medium stores data based on the resistive state of the memory cells or the phase of the memory cells. For example, the NV medium 630 may be or include a three-dimensional crosspoint (3DXP) memory or storage array based on a chalcogenide phase-change material (e.g., chalcogenide glass). In one example, the NV medium may be, or include, a multi-threshold level NAND flash memory, a NOR flash memory, a single-level or multi-level phase-change memory (PCM) or switched phase-change memory (PCMS), a resistive random-access memory, a nanowire memory, a ferroelectric transistor random-access memory (FeTRAM), a magnetoresistive random-access memory (MRAM) incorporating memristor technology, or a spin-transfer-to-reverse (STT) MRAM, or any combination of the above memories or other memories. In one example, the NV medium 630 includes a 3D NAND cell.

[0078] In one example, the NV medium 630 is implemented as multiple dies, represented as N dies (die[0] to [N-1]), where N is any number of devices, but is often a binary number. The SSD 620 includes a controller 640 that controls access to the NV medium 630 via a hardware interface 622. The controller 640 represents the hardware and control logic within the SSD 620 that performs control over the medium. The controller 640 is located inside the non-volatile storage device or module and is independent of the controller 616 of the host 610.

[0079] In one example, dies[0] to [N-1] contain an NV array 632. In one example, the NV array 632 is a 3D memory array. The NV array 632 includes an associated buffer 634, which represents an internal buffer for reading from and writing to the NV array 632. In one example, the control of reading from and writing to buffer 634, and the storage of data from buffer 634 to the NV array 632, may enable applications to program the NV medium with minimal external resources, following any of the programming examples described. Program 636 represents the control logic for programming. In one example, program 636 represents the control logic implemented together with a controller that manages the programming of the NV medium.

[0080] Figure 6B is a block diagram of an example of a logic diagram of a system having a solid-state drive (SSD) with a non-volatile array having an internal buffer for multi-stage program operation. System 604 shows a system with a non-volatile memory array according to the example of system 602 in Figure 6A.

[0081] System 604 represents the logical layers of the host and SSD of a hardware platform according to System 602. System 604 may represent the software and firmware components, as well as the physical components, of an example of System 602. In one example, Host 650 provides an example of Host 610. In one example, SSD 660 provides an example of SSD 620.

[0082] In one example, host 650 includes host OS652, which represents the host's operating system or software platform for the host. Host OS652 may include a platform on which applications, services, agents, and / or other software run, and the host OS is executed by a processor. Filesystem 654 represents control logic for controlling access to the NV medium. Filesystem 654 can manage which addresses or memory locations are used to store which data. Numerous filesystems are known, and filesystem 654 can implement known filesystems or other dedicated systems. In one example, filesystem 654 is part of host OS652.

[0083] The storage driver 656 represents one or more system-level modules that control the hardware of the host 650. In one example, the driver 656 includes a software application that controls the interface to the SSD 660 and therefore controls the hardware of the SSD 660. The storage driver 656 may provide a communication interface between the host and the SSD.

[0084] The SSD660's controller 670 includes firmware 674, which represents the controller's control software / firmware. In one example, the controller 670 includes a host interface 672, which represents the interface to the host 650. In another example, the controller 670 includes a media interface 676, which represents the interface to the NAND die 662. The NAND die 662 represents a specific example of the NV medium and includes an associated NAND array 664. The NAND array 664 includes an array of memory cells.

[0085] The media interface 676 represents control performed on the hardware of the controller 670. The controller 670 includes hardware interfaced with the host 650, which can be understood as being controlled by the host interface software / firmware 674. Similarly, the controller 670 is understood to include hardware interfaced with the NAND die 662. In one example, the code for the host interface 672 could be part of the firmware 674. In another example, the code for the media interface 676 could be part of the firmware 674.

[0086] In one example, the controller 670 includes an error control unit 680 that handles data errors in the accessed data and corner cases in terms of compliance with signal transmission and communication interface connections. The error control unit 680 may include a hardware or firmware implementation, or a combination of hardware and software.

[0087] In one example, the NAND die 662 includes a buffer 666, which represents an internal buffer for reading from and writing to the NAND array 664. In one example, the control of reading from and writing to buffer 666, and the storage of data from buffer 666 to the NAND array 664, may enable applications to program the NV medium with minimal external resources, following any of the programming examples described. Program 668 represents the control logic for programming. In one example, program 668 represents the control logic implemented together with a controller that manages the programming of the NV medium.

[0088] Figure 7 is a block diagram of an example of a computing system in which a non-volatile array having an internal buffer for multi-stage program operation may be implemented. System 700 represents a computing device according to any example herein, which may be a laptop computer, desktop computer, tablet computer, server, control system for games or entertainment, embedded computing device, or other electronic device.

[0089] In one example, the storage subsystem 780 includes storage 784 with an NV array 790 that stores code / data 786. In one example, the NV array 790 includes an associated buffer 792. In one example, storage 784 includes a controller (CTLR) 794, which represents an on-die controller that manages the programming of the NV array 790 to utilize buffer 792 to avoid the use of external buffering of data. In one example, the controller 794 controls reading and writing to buffer 792, as well as storing data from buffer 792 to the NV array 790, and can be programmed with minimal external resources according to any example of the programming described.

[0090] System 700 includes a processor 710, which may include any kind of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware, or a combination thereof, that provides processing or execution of instructions for System 700. Processor 710 may be a host processor device. Processor 710 controls the overall operation of System 700 and may include one or more programmable general-purpose or dedicated microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or a combination thereof.

[0091] System 700 includes boot / configuration 716, which represents storage for boot code (e.g., Basic Input / Output System (BIOS)), configuration settings, security hardware (e.g., Trusted Platform Module (TPM)), or other system-level hardware operating outside the host OS. Boot / configuration 716 may include non-volatile storage devices such as read-only memory (ROM), flash memory, or other memory devices.

[0092] In one example, system 700 includes an interface 712 coupled to processor 710, which may represent a high-speed or high-throughput interface for system components requiring wider bandwidth connectivity (such as a memory subsystem 720 or a graphics interface component 740). Interface 712 represents an interface circuit, which may be a standalone component or integrated into the processor die. Interface 712 may be integrated as a circuit on the processor die or as a component on the system-on-chip. If present, a graphics interface 740 interfaces with a graphics component to provide a visual display to the user of system 700. The graphics interface 740 may be a standalone component or may be integrated into the processor die or the system-on-chip. In one example, the graphics interface 740 can drive a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, this display may include a touchscreen display. In one example, the graphics interface 740 generates a display based on data stored in memory 730, or based on operations performed by the processor 710, or both.

[0093] The memory subsystem 720 represents the main memory of the system 700 and provides storage for code executed by the processor 710 or for data values ​​used when executing routines. The memory subsystem 720 may include one or more types of random access memory (RAM), such as DRAM, 3DXP (3D Crosspoint), or other memory devices, or combinations of such devices. Memory 730 stores and hosts, in particular, the operating system (OS) 732, which provides a software platform for executing instructions in the system 700. Furthermore, applications 734 may run from memory 730 on the software platform of OS 732. Application 734 represents a program that has its own operational logic and is responsible for executing one or more functions. Process 736 represents an agent or routine that provides auxiliary functions to OS 732 or one or more applications 734 or combinations thereof. OS 732, applications 734, and processes 736 provide the software logic that provides functionality to the system 700. In one example, the memory subsystem 720 includes a memory controller 722, which is a memory controller that generates commands and issues those commands to memory 730. It will be understood that the memory controller 722 may be a physical part of the processor 710 or a physical part of the interface 712. For example, the memory controller 722 may be an integrated memory controller that is built into the circuit with the processor 710 (such as being built into the processor die or system-on-chip).

[0094] Although not specifically stated, it will be understood that System 700 may include one or more buses or bus systems between devices, such as memory buses, graphics buses, and interface buses. These buses or other signal lines may connect each component to each other in a communicative or electrical manner, or connect each component to each other in a communicative and electrical manner. A bus may include a physical communication line, a point-to-point connection, a bridge, an adapter, a controller, or other circuitry, or a combination thereof. A bus may include, for example, one or more of the following: a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or other buses, or a combination thereof.

[0095] In one example, system 700 includes interface 714, which may be coupled to interface 712. Interface 714 may be a slower interface than interface 712. In one example, interface 714 represents an interface circuit, which may include standalone components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 714. Network interface 750 provides system 700 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 750 may include an Ethernet® adapter, a wireless interconnect component, a cellular network interconnect component, USB (Universal Serial Bus), or an interface or dedicated interface based on other wired or wireless standards. Network interface 750 can exchange data with remote devices, which may include transmitting data stored in memory or receiving data stored in memory.

[0096] In one example, system 700 includes one or more input / output (I / O) interfaces 760. The I / O interfaces 760 may include one or more interface components through which the user interacts with system 700 (e.g., voice, alphanumeric, tactile / touch, or other interface connections). Peripheral interfaces 770 may include any hardware interfaces not specifically described above. Peripheral devices generally refer to devices that are dependent on system 700. A dependent connection is one on which system 700 provides a software platform, a hardware platform, or both, through which operations are performed and the user interacts with this platform.

[0097] In one example, system 700 includes a storage subsystem 780 that stores data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of storage 780 may have commonalities with components of memory subsystem 720. Storage subsystem 780 includes a storage device 784, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner (such as one or more magnetic disks, solid-state disks, 3DXP disks, or optical disks, or a combination thereof). Storage 784 holds code or instructions and data 786 in a persistent state (i.e., values ​​are retained even if power to system 700 is cut off). While memory 730 is typically execution memory or operating memory that provides instructions to processor 710, storage 784 may generally be considered "memory". While storage 784 is non-volatile, memory 730 may include volatile memory (i.e., the values ​​or state of data become uncertain when power to system 700 is cut off). In one example, the storage subsystem 780 includes a controller 782 that interfaces with the storage 784. In one example, the controller 782 may be a physical part of the interface 714 or the processor 710, or it may include the circuitry or logic of both the processor 710 and the interface 714.

[0098] Power supply 702 supplies power to each component of system 700. More specifically, power supply 702 typically interfaces with one or more power supply units 704 in system 700 to supply power to each component of system 700. In one example, power supply unit 704 includes an AC / DC (alternating current / direct current) adapter that plugs into a wall outlet. Such AC power may be power supply 702 of renewable energy (e.g., solar power). In one example, power supply 702 includes a DC power source such as an external AC / DC converter. In one example, power supply 702 or power supply unit 704 includes wireless charging hardware that charges by proximity to a charging station. In one example, power supply 702 may include an internal battery or fuel cell power source.

[0099] Figure 8 is a block diagram of an example of a mobile device in which a non-volatile array with an internal buffer for multi-stage program operation may be implemented. System 800 represents a mobile computing device or embedded computing device, such as a computing tablet, mobile phone or smartphone, wearable computing device, or other mobile device. It will be understood that not all components of such a device are shown in System 800, but rather only a few components are generally shown.

[0100] In one example, the memory subsystem 860 includes memory 862 with an NV array 890. In one example, the NV array 890 includes an associated buffer 892. In one example, memory 862 includes a controller (CTLR) 894, which represents an on-die controller that manages the programming of the NV array 890 to utilize buffer 892 to avoid the use of external buffering of data. In one example, the controller 894 controls reading and writing to buffer 892, as well as storing data from buffer 892 to the NV array 890, and can be programmed with minimal external resources according to any of the programming examples described.

[0101] System 800 includes a processor 810, which performs the main processing operations of System 800. The processor 810 may be a host processor device. The processor 810 may include one or more physical devices, such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. Processing operations performed by the processor 810 include the execution of an operating platform or operating system on which applications and device functions are executed. Processing operations include operations related to I / O (input / output) with human users or other devices, operations related to power management, operations related to connecting System 800 to another device, or a combination thereof. Processing operations may also include operations related to voice I / O, display I / O, or other interface connections, or a combination thereof. The processor 810 can execute data stored in memory. The processor 810 can write to or edit data stored in memory.

[0102] In one example, system 800 includes one or more sensors 812. Sensor 812 represents an interface with an embedded sensor or an external sensor, or a combination thereof. Sensor 812 enables system 800 to monitor or detect the state of one or more environments or devices in which system 800 is implemented. Sensor 812 may include environmental sensors (such as temperature sensors, motion sensors, photodetectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors that detect physiological attributes), or other sensors, or combinations thereof. Sensor 812 may also include sensors for biometric authentication systems, such as fingerprint recognition systems, face detection systems or facial recognition systems, or other systems that detect or recognize user characteristics. Sensor 812 should be understood broadly and should not be limited to the many different types of sensors that may be implemented in system 800. In one example, one or more sensors 812 are coupled to the processor 810 via a front-end circuit integrated with the processor 810. In another example, one or more sensors 812 are coupled to the processor 810 via another component of the system 800.

[0103] In one example, system 800 includes an audio subsystem 820, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components related to providing audio functionality to a computing device. Audio functionality may include speaker or headphone outputs and microphone inputs. Devices for such functionality may be built into system 800 or connected to system 800. In one example, the user interacts with system 800 by providing audio commands that are received and processed by processor 810.

[0104] The display subsystem 830 represents hardware (e.g., a display device) and software components (e.g., drivers) that provide a visual display for presentation to the user. In one example, the display includes tactile components or touchscreen elements for the user to interact with the computing device. The display subsystem 830 includes a display interface 832, which includes a specific screen or hardware device used to provide a display to the user. In one example, the display interface 832 includes logic that performs at least some display-related processing, independent of the processor 810 (such as a graphics processor). In one example, the display subsystem 830 includes a touchscreen device that provides both output and input to the user. In one example, the display subsystem 830 includes a high-definition (HD) or ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touchscreen display. In one example, the display subsystem 830 generates display information based on data stored in memory, or based on operations performed by the processor 810, or both.

[0105] The I / O controller 840 represents hardware devices and software components related to user interaction. The I / O controller 840 can operate to manage hardware that is part of the audio subsystem 820 or the display subsystem 830, or both. Furthermore, the I / O controller 840 indicates connection points for additional devices that connect to system 800, through which the user may interact with the system. For example, devices that may connect to system 800 may include microphone devices, speakers or stereo systems, video systems or other display devices, keyboards or keypad devices, buttons / switches, or other I / O devices for use in specific applications (such as card readers or other devices).

[0106] As described above, the I / O controller 840 can interact with the audio subsystem 820, the display subsystem 830, or both. For example, inputs or commands for one or more applications or functions of system 800 may be provided via a microphone or other audio device. Furthermore, audio outputs may be provided instead of or in addition to display outputs. In another example, if the display subsystem includes a touchscreen, the display device may also function as an input device, and the input device may be managed at least partially by the I / O controller 840. System 800 may also have additional buttons or switches to provide I / O functions managed by the I / O controller 840.

[0107] In one example, the I / O controller 840 manages devices such as an accelerometer, camera, light sensor or other environmental sensor, gyroscope, Global Positioning System (GPS), or other hardware that may be included in system 800, or sensor 812. Inputs may be part of direct interaction with the user, or they may provide environmental inputs to the system that affect its operation (such as noise reduction, brightness detection to adjust the display, applying a flash to the camera, or other functions).

[0108] In one example, system 800 includes a power manager 850 that manages battery power usage, battery charging, and functions related to power-saving operations. The power manager 850 manages the power from a power supply 852 that supplies power to each component of system 800. In one example, the power supply 852 includes an AC / DC (alternating current / direct current) adapter that plugs into a wall outlet. Such AC power may be renewable energy (e.g., solar power, motion-based power). In one example, the power supply 852 includes only DC power, which may be supplied by an external DC power source such as an AC / DC converter. In one example, the power supply 852 includes wireless charging hardware that charges by proximity to a charging station. In one example, the power supply 852 may include an internal battery or fuel cell power source.

[0109] The memory subsystem 860 includes a memory device 862 for storing information about the system 800. The memory subsystem 860 may include non-volatile (the state of which does not change when power to the memory device is cut off) or volatile (the state of which becomes uncertain when power to the memory device is cut off) memory devices, or a combination thereof. Memory 860 may store not only application data, user data, music, photographs, documents, or other data, but also system data (whether long-term or temporary) related to the execution of applications and functions of the system 800. In one example, the memory subsystem 860 includes a memory controller 864 (which may also be considered part of the control unit of the system 800, and in some cases part of the processor 810). The memory controller 864 includes a scheduler that generates and issues commands that control access to the memory device 862.

[0110] The connection 870 includes hardware devices (e.g., wireless or wired connectors and communication hardware, or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) that enable the system 800 to communicate with an external device. The external device may be an independent device, such as another computing device, a wireless access point or base station, or even peripheral devices such as a headset, printer, or other device. In one example, the system 800 exchanges data with the external device for storage in memory or for display on a display device. The exchanged data may include data to be stored in memory or data already stored in memory for reading, writing, or editing.

[0111] Connection 870 may include several different types of connections. For generalization, system 800 is shown together with cellular connections 872 and wireless connections 874. Cellular connections 872 generally refer to cellular network connections provided by wireless carriers, such as those provided by GSM® (Global System for Mobile Communications) or its variations or derivatives, CDMA (Code Division Multiple Access) or its variations or derivatives, TDM (Time Division Multiplexing) or its variations or derivatives, LTE (Long-Term Evolution, also known as "4G"), 5G, or other cellular service standards. Wireless connections 874 refer to non-cellular wireless connections, which may include personal area networks (such as Bluetooth®), local area networks (such as WiFi®), wide area networks (such as WiMAX®), or other wireless communications, or combinations thereof. Wireless communication refers to the transfer of data using modulated electromagnetic radiation over a non-solid medium. Wired communication is performed over a solid communication medium.

[0112] The peripheral connection 880 includes hardware interfaces and connectors for making peripheral connections, as well as software components (e.g., drivers, protocol stacks). It will be understood that system 800 may be both a peripheral to other computing devices ("output" 882) and a peripheral connected to system 800 ("input" 884). System 800 generally has a "docking" connector for connecting to other computing devices for purposes such as managing the content of system 800 (e.g., downloading, uploading, modifying, synchronizing). Furthermore, the docking connector may allow system 800 to connect to a specific peripheral device, which may allow system 800 to control content output to, for example, an audiovisual system or another system.

[0113] In addition to dedicated docking connectors or other dedicated connection hardware, System 800 can provide peripheral connections to System 880 via common or standard-based connectors. Common types may include Universal Serial Bus (USB) connectors (which may include any of many different hardware interfaces), DisplayPort (including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI®)), or other types.

[0114] In general, with respect to the description herein, in one example the apparatus includes a non-volatile (NV) medium having an array of multilevel cells on a medium die, a volatile memory on the medium die for storing data for programming the NV medium, and a buffer on the medium die for buffering read data and program data for the NV medium, wherein the program for the NV medium stages a first partial page into the buffer for programming, reads a second partial page from the NV medium into the volatile memory, stores the second partial page in the buffer, and programs the NV medium with the first and second partial pages.

[0115] In one example of the device, programming the NV medium includes garbage collection that moves data from the source medium to the NV medium. In any example of the device, in one example the source medium includes single-level cell (SLC) flash memory, or in one example the source medium includes three-level cell (TLC) flash memory, or in one example the source medium includes quad-level cell (QLC) flash memory, or in one example the source medium includes three-dimensional crosspoint (3DXP) memory, or in one example the source medium includes dynamic random access memory (DRAM). In any example of the device, in one example reading the second partial page into the volatile memory includes performing error detection and correction (ECC) on the second partial page. In any example of the device, in one example programming the NV medium includes flushing the first partial page and the second partial page from the buffer to the NV medium in response to loading new addresses to be programmed in the NV medium. In any of the above examples of this device, in one example, programming the NV medium includes flashing the first partial page and the second partial page from the buffer to the NV medium in response to a flash command. In any of the above examples of this device, in one example, the buffer includes read / write registers for the NV medium. In any of the above examples of this device, in one example, the NV medium includes quad-level cell (QLC) flash memory, or in one example, the NV medium includes three-level cell (TLC) flash memory, or in one example, the NV medium includes five-level cell (5LC) flash memory, or in one example, the NV medium includes three-dimensional crosspoint (3DXP) memory. In any of the above examples of this device, in one example, the volatile memory includes static random-access memory (SRAM).

[0116] In general terms with respect to the description herein, in one example a computing device includes a host processor and a solid-state drive (SSD) coupled to the host processor, the SSD including a non-volatile (NV) medium having an array of multilevel cells on a medium die, volatile memory on the medium die for storing data for programming the NV medium, and a buffer on the medium die for buffering read data and program data for the NV medium, the program of the NV medium staging a first partial page for programming in the buffer, reading a second partial page from the NV medium into the volatile memory, storing the second partial page in the buffer, and programming the NV medium with the first and second partial pages.

[0117] In one example of the computing device, the program on the NV medium includes garbage collection that moves data from the source medium to the NV medium. In any example of the computing device, in one example the source medium includes single-level cell (SLC) flash memory, or in one example the source medium includes three-level cell (TLC) flash memory, or in one example the source medium includes quad-level cell (QLC) flash memory, or in one example the source medium includes three-dimensional crosspoint (3DXP) memory, or in one example the source medium includes dynamic random access memory (DRAM). In any example of the computing device, in one example reading the second partial page into the volatile memory includes performing error detection and correction (ECC) on the second partial page. In any example of the computing device, in one example programming the NV medium includes flushing the first partial page and the second partial page from the buffer to the NV medium in response to loading new addresses to be programmed in the NV medium. In any of the above examples of the computing device, in one example, programming the NV medium includes flashing the first partial page and the second partial page from the buffer to the NV medium in response to a flash command. In any of the above examples of the computing device, in one example, the buffer includes read / write registers for the NV medium. In any of the above examples of the computing device, in one example, the NV medium includes quad-level cell (QLC) flash memory, or in one example, the NV medium includes three-level cell (TLC) flash memory, or in one example, the NV medium includes five-level cell (5LC) flash memory, or in one example, the NV medium includes three-dimensional crosspoint (3DXP) memory.In any of the above examples of the computing device, in one example, the volatile memory includes static random-access memory (SRAM). In any of the above examples of the computing device, in one example, the computing device includes a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that supplies power to the computing device.

[0118] In general, with respect to the description herein, one example of a method includes storing data for programming a non-volatile (NV) medium having an array of multilevel cells in a volatile memory on a medium die, buffering read data and program data for the NV medium in a buffer on the medium die, and programming the NV medium, wherein the programming step includes staging a first partial page in the buffer for programming, reading a second partial page from the NV medium into the volatile memory, storing the second partial page in the buffer, and programming the NV medium with the first and second partial pages.

[0119] In one example of this method, the step of programming the NV medium includes a step of performing garbage collection to move data from the source medium to the NV medium. In any example of this method, in one example the source medium includes single-level cell (SLC) flash memory, or in one example the source medium includes three-level cell (TLC) flash memory, or in one example the source medium includes quad-level cell (QLC) flash memory, or in one example the source medium includes three-dimensional crosspoint (3DXP) memory, or in one example the source medium includes dynamic random access memory (DRAM). In any example of this method, in one example the step of reading the second partial page into the volatile memory includes a step of performing error detection and correction (ECC) on the second partial page. In any of the above examples of this method, in one example, the step of programming the NV medium includes the step of flushing the first partial page and the second partial page from the buffer to the NV medium in response to loading a new address to be programmed in the NV medium. In any of the above examples of this method, in one example, the step of programming the NV medium includes the step of flushing the first partial page and the second partial page from the buffer to the NV medium in response to a flash command. In any of the above examples of this method, in one example, the buffer includes read / write registers for the NV medium. In any of the above examples of this method, in one example, the NV medium includes quad-level cell (QLC) flash memory, or in one example, the NV medium includes three-level cell (TLC) flash memory, or in one example, the NV medium includes five-level cell (5LC) flash memory, or in one example, the NV medium includes three-dimensional crosspoint (3DXP) memory. In any of the above examples of this method, in one example, the volatile memory includes static random-access memory (SRAM).

[0120] Each flow diagram presented herein provides an example of a sequence of various process operations. Flow diagrams may illustrate operations performed by software or firmware routines, as well as physical operations. Flow diagrams may illustrate an example of an implementation of a finite state machine (FSM), which can be implemented in hardware and / or software. The order of operations is shown in a specific sequence or order, but may be changed unless otherwise specified. Therefore, the diagrams presented should be understood as examples only, and processes may occur in a different order, and some operations may occur in parallel. Furthermore, one or more operations may be omitted, and therefore, not all implementations perform all operations.

[0121] To the extent that various operations or functions are described herein, these operations or functions may also be described or defined as software code, instructions, configurations, and / or data. Content may be a directly executable file ("object" format or "executable file" format), source code, or differential code ("delta code" or "patch" code). Software content relating to what is described herein may be provided through the product on which the content is stored, or by operating a communication interface to transmit data through the communication interface. Machine-readable storage media include any mechanism that can cause a machine to perform the described functions or operations and stores information in a format accessible to a machine (e.g., a computing device, an electronic system), such as recordable / non-recordable media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). Communication interfaces include any mechanism that interfaces with any hardwired medium, wireless medium, optical medium, etc., for communication with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface may be configured to provide data signals indicating software content, by providing configuration parameters and / or by transmitting signals to prepare the communication interface. The communication interface may be accessed via one or more commands or signals transmitted to the communication interface.

[0122] The various components described herein may be means for performing the described operations or functions. Each component described herein may include software, hardware, or a combination thereof. Each component may be implemented as a software module, a hardware module, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), an embedded controller, a hardwired circuit, etc.

[0123] In addition to what is described herein, various modifications can be made to the disclosed and implemented forms of the invention without departing from their scope. Therefore, the diagrams and examples herein should be construed as illustrative and not as limiting. The scope of the invention should be evaluated solely by reference to the following claims.

Claims

1. A method of storing data, The step of storing data for programming a non-volatile NV medium (NV medium), A buffering step in which read data and program data for the NV medium are buffered using a buffer on the medium die, wherein the buffer has a plurality of registers each storing a partial page of the data; A programming step for the NV medium, comprising: staging a first partial page for programming in the register of the buffer; reading a second partial page from the NV medium to a volatile memory on the medium die, separate from the buffer; staging the second partial page together with the first partial page in the register of the buffer; and programming the NV medium with the first partial page and the second partial page. Equipped with, The first partial page and the second partial page are stored in a separate register. method.

2. The method according to claim 1, wherein the step of programming the NV medium includes a step of performing garbage collection, which involves moving data from a source medium to the NV medium.

3. The method according to claim 1 or 2, wherein the source medium includes single-level cell (SLC) flash memory, or the source medium includes three-level cell (TLC) flash memory, or the source medium includes quad-level cell (QLC) flash memory.

4. The method according to claim 1 or 2, wherein the source medium includes a three-dimensional crosspoint (3DXP) memory.

5. The method according to claim 1 or 2, wherein the source medium includes dynamic random access memory (DRAM).

6. The method according to any one of claims 1 to 5, wherein the step of reading the second partial page into the volatile memory includes the step of performing error detection and correction (ECC) on the second partial page.

7. The method according to any one of claims 1 to 6, wherein the step of programming the NV medium includes the step of flushing the first partial page and the second partial page from the buffer to the NV medium in response to loading a new address to be programmed in the NV medium.

8. The method according to any one of claims 1 to 6, wherein the step of programming the NV medium includes the step of flushing the first partial page and the second partial page from the buffer to the NV medium in response to a flash command.

9. The method according to any one of claims 1 to 5, wherein the register of the buffer includes a read / write register for the NV medium.

10. The method according to any one of claims 1 to 9, wherein the NV medium includes quad-level cell (QLC) flash memory, or the NV medium includes three-level cell (TLC) flash memory, or the NV medium includes five-level cell (5LC) flash memory, or the NV medium includes three-dimensional crosspoint (3DXP) memory.

11. The method according to any one of claims 1 to 10, wherein the volatile memory includes static random access memory (SRAM).

12. An apparatus comprising means for carrying out the method described in any one of claims 1 to 11, A non-volatile (NV) medium having an array of multilevel cells on a medium die, A volatile memory on the medium die for storing data for programming the NV medium, A buffer on the medium die buffers the read data and program data for the NV medium. Equipped with, A device in which the program of the NV medium stages a first partial page for programming in the buffer, reads a second partial page from the NV medium into the volatile memory, stores the second partial page in the buffer, and programs the NV medium with the first partial page and the second partial page.

13. The apparatus according to claim 12, wherein the volatile memory includes static random access memory (SRAM).

14. Host processor and A solid-state drive (SSD) coupled to the host processor and A computing device comprising, wherein the SSD is A non-volatile medium (NV medium) having an array of multilevel cells on a medium die, A volatile memory on the medium die for storing data for programming the NV medium, A buffer on the medium die for buffering read data and program data for the NV medium, the buffer having a plurality of registers each storing a partial page of data, A computing device in which the program on the NV medium stages a first partial page for programming in the registers of the buffer, reads a second partial page from the NV medium into the volatile memory separate from the buffer, stages the second partial page together with the first partial page in the registers of the buffer, programs the NV medium with the first partial page and the second partial page, and stores the first partial page and the second partial page in separate registers.

15. The computing device according to claim 14, wherein the program of the NV medium includes garbage collection that moves data from a single-level cell (SLC) flash buffer memory to the NV medium.

16. The computing device according to claim 14 or 15, wherein reading the second partial page into the volatile memory includes performing error detection and correction (ECC) on the second partial page.

17. The computing device according to any one of claims 14 to 16, wherein programming the NV medium includes flushing the first partial page and the second partial page from the buffer to the NV medium in response to loading a new address to be programmed in the NV medium.

18. The computing device according to any one of claims 14 to 17, wherein the buffer includes a staging buffer for the NV medium.

19. The computing device according to any one of claims 14 to 18, wherein the NV medium includes quad-level cell (QLC) flash memory.

20. The computing device according to any one of claims 14 to 19, wherein the volatile memory includes static random access memory (SRAM).

21. The computing device further, A display, which is communicatively coupled to the host processor, A network interface that is communicatively coupled to the host processor, or Battery that supplies power to the computing device A computing device according to any one of claims 14 to 20, comprising:

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