Apparatus, methods, and techniques for catalytic chemical etching.

Abstract

A method and system for etching a semiconductor substrate using catalytically influenced chemical etching, wherein a group of independently controlled individual actuators is configured to control an etch depth of a material on the substrate, wherein at least two of the group of independently controlled individual actuators have different operating values, and further wherein the etch depth varies by less than 10% of the feature height across the substrate.

Description

[Technical Field]

[0001] Cross-reference of related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 107,354, “Equipment and Process Technologies for Catalyst Influenced Chemical Etching,” filed on 29 October 2020, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to etching in general, and more particularly to apparatus and method techniques for catalyst-dependent chemical etching. [Background technology]

[0003] In semiconductor device manufacturing, etching refers to any technique for selectively removing material from a thin film on a substrate (with or without a prior structure on its surface) to create a pattern of that material on the substrate. The pattern may be defined by a mask resistant to the etching process. Once the mask is in place, etching of material not protected by the mask can be carried out by either a wet chemical or a "dry" physical method.

[0004] One type of etching is catalytically affected chemical etching (CICE), a catalyst-based etching method that can be used to process features in semiconductors such as silicon and germanium, such as features with a high aspect ratio, low sidewall taper, low sidewall roughness, and / or controllable porosity. This method is used to produce higher density and higher performance static random access memory (SRAM), as well as low-loss waveguides.

[0005] Unfortunately, there are currently limitations to fabricating semiconductor features that utilize CICE. [Overview of the Initiative]

[0006] In one embodiment of the present invention, a system for etching a semiconductor substrate using catalyst-affected chemical etching comprises a group of independently controlled individual actuators configured to control the etching depth of material on the substrate, wherein at least two of the groups of independently controlled individual actuators have different operating values, and the variation in etching depth is less than 10% of the feature height across the substrate.

[0007] In another embodiment of the present invention, a system for etching a semiconductor substrate using catalyst-affected chemical etching comprises a group of separate actuators configured to control the etching depth of the material on the substrate, with etching being started and stopped while resulting in an etching depth variation of less than 10% of the feature height across the entire substrate, and the substrate having type A device patterns next to type B device patterns.

[0008] In a further embodiment of the present invention, a method for etching a semiconductor material using catalyst-affected chemical etching (CICE) comprises providing a semiconductor material and one or more layers of other materials on the semiconductor material, wherein the catalyst layer is one of the one or more layers of other materials, and includes exposing one or more of the one or more layers of other materials to a process for modifying the catalytic activity of the catalyst layer, and exposing the semiconductor material and the one or more layers of other materials containing the catalyst layer having modified catalytic activity to a CICE etchant.

[0009] In another embodiment of the present invention, a method for etching a semiconductor material using catalytic chemical etching comprises providing a semiconductor material. The method further comprises providing a catalyst layer on the surface of the semiconductor material. The method further comprises exposing the catalyst layer and the semiconductor material to an etchant, wherein the exposure of the surface region of the catalyst layer to the etchant is optimized to reduce the porosity during the catalytic chemical etching period.

[0010] In a further embodiment of the present invention, a method for preventing substantial collapse of a high aspect ratio semiconductor structure by catalyst-induced chemical etching includes providing a semiconductor material. The method further includes patterning a catalyst layer on the surface of the semiconductor material, wherein the catalyst layer comprises a plurality of features, wherein unetched areas of the pattern adjacent to the plurality of features comprise features to avoid collapse. The method further includes exposing the patterned catalyst layer and the features to avoid collapse to an etchant, wherein the patterned catalyst layer and the etchant cause etching of the semiconductor material to form a fabricated structure corresponding to the plurality of features, wherein the features to avoid collapse prevent substantial collapse of the etched semiconductor material.

[0011] In another embodiment of the present invention, a method for preventing substantial collapse of high aspect ratio nanostructures includes providing a material to be etched to a substrate. The method further includes providing a patterned etching mask on the substrate. The method further includes etching the material to be etched using the patterned etching mask, wherein a portion of the patterned etching mask prevents substantial collapse of the etched material.

[0012] In a further embodiment of the present invention, a method for preventing substantial collapse of a high aspect ratio nanostructure includes providing a high aspect ratio nanostructure having a collapse-prevention cap. The method further includes depositing a stabilizing material around a portion of the high aspect ratio nanostructure to form a stabilizing material region. The method further includes removing the collapse-prevention cap from regions other than the stabilizing material region.

[0013] In another embodiment of the present invention, a method for preventing substantial collapse of a high aspect ratio nanostructure includes providing a high aspect ratio nanostructure having a collapse-prevention cap. The method further includes bonding a material to the collapse-prevention cap to form a ceiling.

[0014] In another embodiment, a method of using catalytically-induced chemical etching (CICE) to form micro- or nanostructures with an adjustable etch depth to create structures of a predetermined etch depth in different regions of a semiconductor wafer includes creating a predetermined pattern in a material resistant to the chemicals of the CICE etchant, where the predetermined pattern is created on top of the patterned catalyst.

[0015] In another embodiment of the present invention, a method of using catalytically-induced chemical etching (CICE) to form nanostructures with an adjustable etch depth to create structures of a predetermined etch depth in different regions of a semiconductor wafer includes creating a predetermined temperature control profile on the surface of the semiconductor wafer, and the predetermined temperature control profile results in a predetermined etch depth in different regions of the semiconductor wafer.

[0016] The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which may form the subject matter of the claims of the invention.

[0017] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings.

Brief Description of the Drawings

[0018] [Figure 1] FIG. 1 is a diagram showing an exemplary configuration for a side-to-side etchant flow according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing an exemplary design for etchant introduction and discharge across a region of a process wafer according to an embodiment of the present invention. [Figure 3] FIGS. 3A-3B are diagrams showing an exemplary spin-spray type etchant flow system with an eccentrically rotating etch spray arm and passive gravity-driven etchant outflow according to an embodiment of the present invention. [Figure 4]Figure 4 is a diagram showing an exemplary design having a sliding etching zone according to an embodiment of the present invention. [Figure 5] Figures 5A - 5B are diagrams showing exemplary designs for etchant agitation according to an embodiment of the present invention. [Figure 6] Figure 6 is a diagram showing an exemplary etchant flow path showing a mixing chamber and precursor storage according to an embodiment of the present invention. [Figure 7] Figure 7 is a diagram showing an exemplary vacuum - based degassing strategy according to an embodiment of the present invention. [Figure 8] Figures 8A - 8D are diagrams showing exemplary etchant - freezing - based reaction quenching according to an embodiment of the present invention. [Figure 9] Figures 9A - 9D are diagrams showing exemplary reaction quenching based on etchant - freezing sublimation according to an embodiment of the present invention. [Figure 10] Figure 10 is a diagram showing an exemplary design for reaction quenching and heat compensation during initiation according to an embodiment of the present invention. [Figure 11] Figures 11A - 11B are diagrams showing an exemplary in - situ measurement system having a full - wafer cover range according to an embodiment of the present invention. [Figure 12] Figure 12 is a diagram showing a representative measurement system equipped with a scanable optical system according to an embodiment of the present invention. [Figure 13] Figure 13 is a diagram showing an exemplary system for digital micro - mirror device (DMD) modulated wafer thermal control according to an embodiment of the present invention. [Figure 14] Figure 14 is a diagram showing an exemplary system for radio - wave control in a CICE tool (only a cross - section of the CICE tool is shown) according to an embodiment of the present invention. <好 [Figure 15] Figure 15 is a diagram showing an exemplary edge contact design showing a front - side seal forming contact on the outer edge of a process wafer according to an embodiment of the present invention. [Figure 16] Figure 16 is a diagram showing an exemplary back - side contact with a back - side fluid according to an embodiment of the present invention.\ [Figure 17] Figure 17 shows an exemplary back surface contact using a vacuum chuck according to an embodiment of the present invention. [Figure 18] Figure 18 is a flowchart of a method for a Ru minimesh patterning process using correction jet and flash imprint lithography with sparse inkjet droplets according to an embodiment of the present invention. [Figure 19] Figures 19A to 19D show cross-sectional views of a Ru minimesh patterning process using correction jet and flash imprint lithography with sparse inkjet droplets, using the steps described in Figure 18. [Figure 20] Figures 20A to 20C show inclined cross-sectional SEM and top-down optical microscope images of a resist pattern after sparse drop-in printing according to an embodiment of the present invention. [Figure 21] Figures 21A-21D show the effect of plasma used in descam etching on Ru minimesh CICE, which causes various results across the entire minimesh, including relatively ineffective edge regions, according to this embodiment. [Figure 22] Figures 22A to 22F show the desired CICE results using a Ru minimesh, obtained by using a long Ar / CFr plasma for descam etching according to this embodiment. [Figure 23] Figure 23A shows a plot of the maximum height in micrometers versus the diameter in nanometers before nanowire decay according to an embodiment of the present invention. Figure 23B is a schematic diagram of a pair of decayed charged nanowires according to an embodiment of the present invention. Figure 23C shows a marked cross-sectional SEM image of an oversized silicon nanowire after the gold resist cap has been removed according to an embodiment of the present invention. [Figure 24] Figure 24 is a flowchart of a method for fabricating an arbitrary self-supporting high aspect ratio nanostructure having a collapse-avoiding cap according to an embodiment of the present invention. [Figure 25]Figures 25A to 25D are top-down diagrams for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap using the process described in Figure 24, according to embodiments of the present invention. [Figure 26] Figures 26A–26D are cross-sectional views showing the fabrication of any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the process described in Figure 24, according to embodiments of the present invention. [Figure 27] Figure 27 is a flowchart of an alternative method for fabricating any self-supporting high-aspect-ratio nanostructure having a collapse-avoiding cap according to an embodiment of the present invention. [Figure 28] Figures 28A–28D are top-down diagrams for fabricating any self-supporting high aspect ratio nanostructure with a collapse-avoiding cap using the process described in Figure 27, according to embodiments of the present invention. [Figure 29] Figures 29A–29D are cross-sectional views for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the process described in Figure 27, according to embodiments of the present invention. [Figure 30] Figure 30 is a flowchart of an alternative method for fabricating any self-supporting high-aspect-ratio nanostructure having a collapse-avoiding cap according to an embodiment of the present invention. [Figure 31] Figures 31A–31D are top-down diagrams for fabricating any self-supporting high aspect ratio nanostructure with a collapse-avoiding cap using the process described in Figure 30, according to embodiments of the present invention. [Figure 32] Figures 32A-32D are cross-sectional views showing the fabrication of any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the process described in Figure 30, according to embodiments of the present invention. [Figure 33] Figure 33 is a flowchart illustrating a method for fabricating a finFET with a collapse prevention cap using CICE according to an embodiment of the present invention. [Figure 34]Figures 34A to 34G show different diagrams for fabricating a finFET with a collapse-avoiding cap using CICE, with the process described in Figure 33, according to embodiments of the present invention. [Figure 35] Figures 35A to 35G show different diagrams for fabricating a finFET with a collapse-avoiding cap using CICE, with the process described in Figure 33, according to embodiments of the present invention. [Figure 36] Figures 36A to 36G show different diagrams for fabricating a finFET with a collapse-avoiding cap using CICE, with the process described in Figure 33, according to embodiments of the present invention. [Figure 37] Figure 37 is a flowchart of the method for joining cover plates according to an embodiment of the present invention. [Figure 38] Figures 38A to 38B show cross-sectional views for joining cover plates using the steps described in Figure 37, according to an embodiment of the present invention. [Figure 39] Figure 39 is a flowchart of an alternative method for joining cover plates according to an embodiment of the present invention. [Figure 40] Figures 40A to 40C are cross-sectional views showing an embodiment of the present invention for joining cover plates using the process described in Figure 39. [Figure 41] Figure 41 is a flowchart of a further alternative method for joining cover plates according to an embodiment of the present invention. [Figure 42] Figures 42A to 42E are cross-sectional views showing an embodiment of the present invention for joining cover plates using the process described in Figure 41. [Figure 43] Figure 43 is a flowchart of a method for creating metallic fracture in gold using photolithography according to an embodiment of the present invention. [Figure 44] Figures 44A to 44C are cross-sectional views showing the generation of metallic fracture in gold using the process described in Figure 43, according to an embodiment of the present invention. [Figure 45]Figure 45 is a flowchart of a method for creating a metallic fracture in gold using photo / e-beam lithography with a metallic fracture layer according to an embodiment of the present invention. [Figure 46] Figures 46A to 46C are cross-sectional views showing the generation of metallic fracture in gold using the process described in Figure 45, according to an embodiment of the present invention. [Figure 47] Figure 47 is a flowchart of a method for creating a metallic fracture in gold using nanoimprint lithography with a metallic fracture layer according to an embodiment of the present invention. [Figure 48] Figures 48A to 48C are cross-sectional views showing the generation of metallic fracture in gold using the process described in Figure 47, according to an embodiment of the present invention. [Figure 49] Figure 49 is a flowchart of an alternative method for creating a metallic fracture in gold using nanoimprint lithography with a metallic fracture layer, according to an embodiment of the present invention. [Figure 50] Figures 50A to 50D are cross-sectional views showing the generation of metallic fracture in gold using the process described in Figure 49, according to an embodiment of the present invention. [Figure 51] Figure 51A shows a resulting structure formed according to an embodiment of the present invention. Figure 51B is an image of the metal fracture layer after etching according to an embodiment of the present invention. [Figure 52] Figure 52A shows a resulting structure formed according to an embodiment of the present invention. Figure 52B is an image of the metal fracture layer after etching according to an embodiment of the present invention. [Figure 53] Figure 53 is a flowchart of a method for pattern formation and MACE using ruthenium according to an embodiment of the present invention. [Figure 54] Figures 54A to 54H are cross-sectional views of ruthenium patterning and MACE using the process described in Figure 53, according to embodiments of the present invention. [Figure 55]Figures 55A to 55C show exemplary devices having a region in which the fin height changes according to an embodiment of the present invention. [Figure 56] Figure 56 shows the effect of the etching taper angle on the maximum achievable fin height for different technical nodes according to embodiments of the present invention. [Figure 57] Figures 57A to 57B show the effect of minimesh spatial density on Ru MACE etching quality for Ar / CF4 descam and 20s MacEtch with 12.5M HF and 1M H2O2 according to this embodiment. [Figure 58] Figures 58A to 58D show ruthenium MACE for the fabrication of silicon rectangular pillar arrays having different geometric shapes according to embodiments of the present invention. [Figure 59] Figure 59 is a graph illustrating the maximum height of a non-tapered fin before lateral collapse along the length of the fin (in this case, 50 nm) as a function of the half-pitch (or fin width) of the fin according to an embodiment of the present invention. [Figure 60] Figures 60A to 60D show the effects of catalyst material and geometry on catalyst wandering behavior, resulting in lower wandering and a larger catalyst size for ruthenium compared to gold catalyst materials according to embodiments of the present invention. [Figure 61] Figures 61A to 61C show a high aspect ratio hole for a DRAM deep trench capacitor using MACE+ALD according to an embodiment of the present invention. [Figure 62] Figures 62A to 62D show a ruthenium MACE for the fabrication of silicon rectangular pillars, with different shaped inclined cross-sectional scanning electron microscopes and top-down scanning electron microscopes at different magnifications, according to embodiments of the present invention. [Figure 63] Figures 63A to 63H show high-resolution TEM and EDS mapping of silicon fins according to embodiments of the present invention. [Figure 64]Figures 64A to 64B show silicon superlattice etching using epitaxial silicon layers with alternating doping concentrations according to an embodiment of the present invention. [Figure 65] Figure 65A is a schematic diagram of a traditional finFET fabrication flow illustrating the essential processes according to an embodiment of the present invention. Figure 65B is a modified finFET process flow in which linked fins are formed to enable collapse-free, ultra-high aspect ratio fins according to an embodiment of the present invention. [Modes for carrying out the invention]

[0019] As described in the background technology section, in semiconductor device fabrication, etching refers to any technique for selectively removing material from a thin film on a substrate (with or without a prior structure on its surface) and generating a pattern of that material on the substrate by this removal. The pattern may be defined by a mask that is resistant to the etching process. Once the mask is in place, etching of material not protected by the mask may be caused by either a wet chemical method or a "dry" physical method.

[0020] One type of etching is catalytically affected chemical etching (CICE), a catalyst-based etching method that can be used to process features in semiconductors such as silicon and germanium, which have a high aspect ratio, low sidewall taper, low sidewall roughness, and / or controllable porosity. This method is used to create static random-access memory (SRAM) with higher density and higher performance, as well as low-loss waveguides.

[0021] Unfortunately, there are currently limitations to fabricating semiconductor features that utilize CICE.

[0022] The principle of the present invention provides means for utilizing the CICE process to effectively fabricate features in semiconductors using the apparatus and method techniques for catalyst-affected chemical etching of the present invention.

[0023] The means for catalyst-affected chemical etching (CICE) have the following objectives: to etch nanoscale features using a CICE process at a target yield (or higher) and target processing volume (or higher). To achieve the target yield, further variation in etching height is required, which is less than a certain percentage of the etching height (e.g., 30% in one embodiment, 20%, 10%, 5%, or less in other embodiments). To achieve this objective, several subsystems and capabilities are required, including, but not limited to, the ability to handle corrosive etchants without leaching contaminants (such as metals). Inert polymers such as PTFE, PFA, and HDPE meet this requirement.

[0024] Furthermore, this objective lens requires the ability to handle wafer sizes of 300 mm or larger. This necessitates automated loading and unloading of 300 mm wafers between the internal chambers of the tool and between the internal chambers of the tool and the input / output ports. Moreover, it also requires a tool chamber sized to handle 300 mm wafers. Automated wafer handling and tool processing solutions are provided to meet these requirements. In one embodiment, the process wafer is processed in a vertical configuration, but once etching is performed, the wafer is rotated to a horizontal configuration, which is handled using, for example, a SCARA-type robotic arm.

[0025] Furthermore, this objective requires front-side etchant flow control. At the front of the process wafer where the CICE process is performed, the reactants for the CICE process must be maintained at a uniform concentration across the entire wafer, while ensuring that the CICE process products are continuously removed from the reaction sites. By utilizing design features that improve etchant uniformity and employing chamber-in-etchant stirring methods that prevent etchant stagnation regions, a uniform reactant concentration can be maintained through continuous or intermittent etchant circulation.

[0026] Etchant circulation can be achieved in several ways. For example, in one embodiment, when peripheral contacts are used within the front chamber for etchant containment, a group of one or more inlet ports (which may be in the form of nozzles) can be used to introduce the etchant into the chamber, and a group of one or more outlet ports can be used to remove the etchant from the chamber. In one embodiment, the bases of the inlet and outlet ports are machined integrally with the front chamber. Computational fluid dynamics (CFD) based on fluid simulations, such as discussed in Wendt, John F., ed. Computational Flid Dynamics: An Introduction. Springer Science & Business Media, 2008, along with design optimization techniques, such as discussed in Rao, R. Venkata, and Vimal J. Savsani. Mechanical Design Optimization Using Advanced Optimization Techniques, is incorporated herein by reference in its entirety. Springer Science & Business Media, 2021, which is incorporated herein by reference in its entirety, may be used to ensure the minimization of flow non-uniformity and stagnation.

[0027] Referring to the figures, Figure 1 shows an exemplary design for side-to-side etchant flow according to an embodiment of the present invention. Figure 2 shows an exemplary design for etchant introduction and exit across a region of a process wafer according to an embodiment of the present invention.

[0028] As shown in Figure 1, such a design includes an inlet manifold 101, a process chamber filled with etchant 102, a process wafer 103, and an outlet manifold 104. As shown in Figure 2, such a design includes a multilayer front-side cover 201, a process wafer 202, an etchant inlet 203, an etchant outlet 204, an etching product 205, and a local etchant flow direction 206.

[0029] Furthermore, as shown in Figure 1, fluid is introduced and exits from the side of the chamber 102. In Figure 2, fluid is introduced and discharged using inlet ports 203 and outlet ports 204 located along the entire length of the chamber wall. These designs can be manufactured using standard computer numerical control (CNC) machines. In one embodiment, a multilayer front cover (shown in Figure 2) can be manufactured by joining multiple two-dimensional machined pieces using polymer welding of machined PTFE pieces, as discussed, for example, in Stokes, Vijay K. “Joining methods for plastics and plastic composites: an overview” and Polymer Engineering & Science, Vol. 29 No. 19, 1989, pp. 1310-1324, which is entirely incorporated herein by reference.

[0030] In one embodiment, a spin-spray type apparatus can be used for the delivery and circulation of front-side etchant. In one embodiment of this apparatus, a rotating arm is used to distribute new etchant onto the process wafer, in which case the process wafer is kept fixed. An active strategy can be used to remove used etchant from the wafer surface, in which a first arm or a second arm otherwise integrated can be used to move the used etchant by centrifugal force. Alternatively, a passive strategy can be used, in which the wafer is kept in a vertical orientation and gravity is used to pull the used etchant down into the collection chamber. The axis of rotation of the arm may be fixed or movable, and may be coaxial with the process wafer or eccentric. In a second embodiment, the etchant distribution arm can be fixed while the process wafer itself is rotated. In all embodiments of the spin-spray type apparatus, a CICE-compatible chamber may be used to surround the entire front of the process wafer and to accommodate the etchant being thrown in various directions by the rotating process wafer and / or etchant distribution arm. Figures 3A to 3B illustrate one of the embodiments described above. Specifically, Figures 3A to 3B show an exemplary spin-spray type etchant flow system 300, comprising an eccentric rotating etching spray arm and a passive gravity-driven etchant outflow, according to an embodiment of the present invention.

[0031] Referring to Figure 3A, which shows a side view (cross-section), the system 300 includes a front cover 301, an etchant inlet 302, a gravity-driven etchant outlet 303, an etchant 304, an eccentrically rotating etchant spray arm 305, and a fixed, vertically positioned process wafer 306. Furthermore, Figure 3B shows a top view in one embodiment showing the rotation direction of the spray arm 305.

[0032] In one embodiment, a system with a sliding etching zone can be used. A group of inlet and outlet nozzles, positioned close together, can be used to create a locally circulating etchant area. The group of nozzles can scan the entire wafer to etch the entire wafer, as shown in Figure 4. Figure 4 illustrates an exemplary design having a sliding etching zone according to an embodiment of the present invention.

[0033] Referring to Figure 4, Figure 4 shows a scannable group of inlets and outlets 401, an etchant outlet 402, an etchant inlet 403, a sliding etching area 404, an etchant 405, a front cover 406, and a fixed, horizontal process wafer 407.

[0034] In one embodiment, geometric elements such as baffles and fins can be arranged within the etchant chamber to ensure the desired flow. In one embodiment, these can be fabricated integrally with the front side chamber. Computational fluid dynamics (CFD)-based fluid simulations may be used to design these geometric elements, along with design optimization techniques.

[0035] With regard to active etchant stirring, a chamber-moving assembly can be used to stir the etchant and prevent stagnation. In one embodiment, these assemblies may take the form of a group of intersecting arms. In another embodiment, these assemblies may be a group of arms having separate centers of rotation. In another embodiment, the movable assembly may have an inlet and outlet for the etchant. In another embodiment, the movable assembly may have geometric elements such as baffles and fins. The actuation mechanism for these assemblies may be indirect (such as the actuation of an assembly having a monolithic magnet using a rotating external magnetic field), direct (such as the use of a direct-drive motor), or use fluid reaction and impulse force (in a manner similar to reaction and impulse turbines, as discussed in Dick, Erik. Fundamentals of turbomachines. Vol. 109. Springer, 2015, which is incorporated herein by reference in whole). Exemplary dual-shaft, dual-arm assemblies with fluid actuation are shown in Figures 5A–5B.

[0036] Figures 5A to 5B show exemplary designs for etchant stirring according to embodiments of the present invention.

[0037] Referring to Figure 5A, which shows a side view (cross-section), such a design includes a reverse-rotating etchant stirring arm 501, a front cover 502, an etchant 503, an etchant outlet 504, and a process wafer 505. Figure 5B shows a top view with the etchant inlet jet 506 drawn.

[0038] The etchant circulated within the etching chamber can be mixed and stored in a mixing chamber. In one embodiment, the mixing chamber is located at a distance from the etching chamber and connected to it using CICE-compatible tubing. The mixing chamber may have various monitors of the etchant condition, such as a concentration monitor, flow rate monitor, temperature monitor, impurity / precipitant / particle monitor, and pressure monitor. The mixing chamber may also have various operating mechanisms for modifying the etchant condition, such as an etchant inlet for an etchant precursor to dynamically correct the etchant concentration, and a heating assembly to correct the etchant temperature. The flow of etchant between the mixing chamber and the process chamber, and between the mixing chamber and the precursor storage, can be handled using a CICE-compatible pump.

[0039] In one embodiment, the etchant precursor can be stored in a container such as a mixing chamber, and the precursor storage may have precursor state monitors such as a concentration monitor, a temperature monitor, an impurity / precipitant monitor, and a pressure monitor, as well as a precursor state operating mechanism such as an inlet for dynamically changing the precursor concentration, and a heating assembly for changing the precursor temperature.

[0040] Figure 6 shows an exemplary etchant flow path illustrating a mixing chamber and precursor storage according to an embodiment of the present invention. In particular, Figure 6 shows the entire etchant flow assembly comprising a process chamber, a mixing chamber, precursor storage, a pump assembly, and etchant and precursor state sensing and operating mechanisms.

[0041] Referring to Figure 6, Figure 6 shows the process wafer 601, etchant inlet 602, etchant outlet 603, front cover 604, CICE compatible etchant pump 605, mixing chamber 606, etchant state sensor 607, thermal operation of mixing chamber etchant 608, and precursor state sensor 609 in the precursor storage units 610A-610N. Here, N is a positive integer (identified in Figure 6 as "storage for precursor 1," "storage for precursor 2," and "storage for precursor N," respectively). The precursor storage units 610A-610N may be referred to collectively or individually as a plurality of precursor storage units 610 or precursor storage units 610.

[0042] Regarding degassing, one of the products of the CICE process is gaseous H2. Actively producing H2 during CICE can lead to the formation of bubbles in the etchant near the reaction site, resulting in non-uniformity of the etchant concentration. This can, for example, reduce visibility through the etchant used for in-situ measurement, clog the etchant flow system, or decrease efficiency. It should be noted that while bubbles do not need to be completely eliminated, they must be controlled to the extent that they do not interfere with in-situ measurement, etchant flow, and reaction uniformity. Several methods may be used to reduce bubble formation in the CICE process.

[0043] For example, certain CICE regimes result in higher bubble formation, as discussed in Li, Yinxiao, and Chuanhua Duan. “Bubble-Regulated Silicon Nanowire Synthesis on Micro-Structured Surfaces by Metal-Assisted Chemical Etchingm” Langmuir 31, No. 44, November 10, 2015, pp. 12291-1299, which is incorporated herein by reference in its entirety. Therefore, operating under a regime that reduces H2 production can mitigate the bubble problem.

[0044] In another example, lowering the etching rate can also reduce the rate of bubble formation. This can be achieved, for example, by lowering the etchant concentration or the concentration of the rate-limiting etchant precursor. This can also be achieved by lowering the temperature of the etchant, as discussed in Backes, Andreas, Markus Leitgeb, Achim Bittner, and Ulrich Schmid, “Temperature Dependent Pore Formation in Metal Assisted Chemical Etching of Silicon,” ECS Journal of Solid State Science and Technology, Vol. 5, No. 12, January 1, 2016, pp. 653-656, which is incorporated herein by reference in its entirety.

[0045] In a further example, increasing the etchant pressure can increase the solubility of gases in the etchant, and therefore reduce the formation of bubbles.

[0046] In another example, lowering the temperature of the etchant can be used to increase the solubility of the gas in the etchant and reduce the formation of bubbles.

[0047] In further examples, with respect to membrane degassing, PTFE-based CICE-compatible gas-liquid separation membranes, process chamber walls, or other locations in the etchant path can be used to selectively extract gas from the etchant and reduce bubble formation.

[0048] In another example, ultrasonic treatment can be used to separate bubbles adhering to the surface of a process wafer and drive them into the bulk etchant. Ultrasonic treatment can be achieved, for example, using piezoelectric elements integrated into the front and / or rear covers.

[0049] In further examples, a vacuum-based degassing chamber can be used, either as part of or separately from the mixing chamber, to reduce the amount of dissolved gas in the etchant solution.

[0050] In another example, the tool can be operated so that the process wafer is vertical during the CICE process, resulting in bubbles moving upward against gravity to the top of the tool instead of to the front of the tool in a horizontal configuration, obstructing the view for potential field measurements.

[0051] In a further example, bubbles attached to the surface of a process wafer can be released using a movable arm with a knife edge that moves across the surface of the process wafer while maintaining a small gap between the wafer and the knife edge (on a sub-millimeter scale).

[0052] Next, referring to Figure 7, Figure 7 shows an exemplary vacuum-based degassing strategy according to an embodiment of the present invention.

[0053] As shown in Figure 7, this strategy includes a degassing chamber 701 where a vacuum or partial vacuum for H2 702, a process wafer 703, H2 bubbles 704, an etchant inlet 705, an etchant outlet 706 (e.g., H2 saturation), and a front cover 707 are located.

[0054] Regarding reaction quenching and reaction initiation, it is crucial to carefully manage spatial variations at the start and stop of the CICE process to ensure uniform etching across the entire wafer. For example, in a wet process, if the reaction quenching fluid (e.g., water) is injected into one end of the process wafer 703 and it takes 5 seconds for the quenching front to cover the entire wafer, at a sampling etching rate of 1 μm / min, this will result in an etching height variation of ~80 nm across the wafer. Similarly, if the etchant at the start of the CICE process is injected into one end of the process wafer 703 and it takes 5 seconds for the etchant front to cover the entire wafer, at a sampling etching rate of 1 μm / min, this will result in an etching height variation of ~80 nm across the wafer. Several methods can be used to reduce etching height variations during reaction quenching and initiation.

[0055] For example, reducing the etching rate before reaction quenching or throughout the etching process can reduce variations in etching height. This reduction in etching rate can be achieved by changing the relative concentration of the etchant precursor (in the mixing chamber) or by lowering the wafer temperature, which results in a corresponding reduction in etching rate, as discussed in Backes, Andreas, Markus Leitgeb, Achim Bittner, and Ulrich Schmid, “Metal Assisted Chemical Etching of Silicon,” ECS Journal of Solid State Science and Technology, Vol. 5, No. 12, January 1, 2016, pp. 653-656, which is incorporated herein by reference in its entirety.

[0056] In another example, with respect to the injection of etchant and quenching fluid from the front of the wafer, the flow path of the etchant can be reduced by introducing the etchant and quenching fluid from the front of the wafer. This reduces the amount of time-stray etchant remaining in the process chamber, and therefore reduces the reaction quenching time and the corresponding etching non-uniformity. Similarly, it shortens the time required for the etchant to be introduced during the start of etching. Many of the methods described in the etching circulation section above may be used for front-side introduction of etchant and quenching fluid. For example, the design shown in Figure 2 may be used in such a case.

[0057] In yet another example, with respect to etchant freezing, a process wafer can be cooled using a Peltier element so that, for example, a thin layer of etchant immediately adjacent to the wafer freezes (which may stop the CICE reaction). Then, while the etchant immediately adjacent to the wafer is still frozen, the unfrozen etchant can be replaced with a reaction quenching fluid such as water. The thin layer of frozen etchant can then be heated so that it melts and rapidly dissipates into the large amount of quenched liquid present immediately adjacent to it. Examples of such quenching are shown in Figures 8A-8D.

[0058] Referring to Figures 8A to 8D, Figures 8A to 8D show an example of etchant-freeze-based quenching according to this embodiment.

[0059] Figure 8A shows a sub-zero thermoelectric cooler 801, wafer chuck 802, process wafer 803, heat sealing device 804, etchant inlet 805, etchant outlet 806, and front cover 807.

[0060] Figure 8B shows a thin layer of frozen etchant 808.

[0061] Furthermore, Figure 8C shows an example where a large amount of etchant liquid was replaced with quenching solution 809.

[0062] Furthermore, Figure 8D shows a thin layer of etchant having TEC801 set to melt and heat 810.

[0063] Alternatively, after the freezing process, a large amount of liquid can be replaced with air, and then the thin frozen layer of etchant can be evacuated to allow it to sublimate. Evacuation can be achieved by placing the entire etch chamber inside a larger CICE-compatible vacuum chamber, or alternatively, by connecting a CICE-compatible vacuum pump, such as a bellows pump, to the reaction chamber itself and drawing out the filled air. Diagrams of such rapid cooling are shown in Figures 9A-9D.

[0064] Figures 9A to 9D show an example of etchant freeze-sublimation based quenching according to this embodiment.

[0065] Figure 9A shows the process wafer 901, the weber chuck 902, the sub-zero thermoelectric cooler 903, the large vacuum chamber 904, the front cover 905, the heat seal section 906, the etchant outlet 907, and the etchant inlet 908.

[0066] Figure 9B shows a thin layer of frozen etchant 909.

[0067] Figure 9C shows an example where a large amount of etchant liquid was replaced with air 910.

[0068] Figure 9D shows a thin layer of etchant formed by sublimation of 911, while 912 is under reduced pressure.

[0069] With regard to thermal compensation, an array of thermal actuators can be used to actively compensate for any changes in etching rate that occur during etching initiation and quenching. To achieve thermal operation, several methods can be used with respect to process variation control, as discussed below. Figure 10 shows an exemplary design for thermal compensation during reaction quenching and initiation according to an embodiment of the present invention.

[0070] As shown in Figure 10, such a design includes a wafer chuck 1001, a process wafer 1002, a grid consisting of an independently controllable thermoelectric cooler 1003, a front cover 1004, an etchant inlet 1005, and an etchant outlet 1006.

[0071] In one embodiment, the entire etchant within the reaction chamber can be rapidly evaporated using reduced pressure, for example, when thin sheets of reactant are used. Evacuation can be achieved by placing the entire etchant chamber inside a larger CICE-compatible vacuum chamber, or alternatively, by connecting a CICE-compatible vacuum pump, such as a Bellows pump, to the reaction chamber itself and drawing out the filled air.

[0072] Regarding process variation control, spatial variations in etchant and etching product concentrations, local etchant flow rate, etchant temperature, pattern concentration variations, and wafer edge influences can lead to variations in etching quality (e.g., degree of porosity, wall roughness, wall angle) and etching rate. In one embodiment, a feedback-based system is used to control process variations. In another embodiment, a purely feedforward approach can be used, in which case likely process variations are known in advance, and a local actuation method (such as thermal actuation) is used in an open-loop manner to compensate for known process variations. In yet another embodiment, a hybrid approach can be used when known process variation trends are combined with real-time process variation measurements to control process actuators.

[0073] Regarding measurement, there are in-situ measurements that can monitor spatial variations in etching rate, or their proxies (such as a unique spectral signature corresponding to a given etching feature height), in situ. This may be achieved using in-situ spectrophotometric methods for wafer processes, as discussed, for example, in Gawlik, Brian, et al., "Hyperspectral imaging for high-throughput, spatially resolved spectroscopic scatterometry of silicon nanopillar arrays", Optics Express, Vol. 28, No. 10, 2020, pp. 14209-14221, which is incorporated herein by reference in its entirety. The measurements may be reflective or transmissive. IR wavelengths would be used when transmissive measurements are required, as discussed in Choi, MS, HM Park, and KN Joo, "Note: Near infrared interferometric silicon wafer metrology", Review of Scientific Instruments 87.4 (2016): 046106, which is incorporated herein by reference in its entirety. Measurements can be performed in real time (synchronously) or asynchronously with the CICE process. Depending on whether the measurement is reflective or transmissive, the front and / or back covers must be fabricated using CICE-compatible transparent materials. Crystalline sapphire is one such material, and it is available in wafer form. The thickness of the etchant sheet may be maintained so that areas of high incident irradiance pass through the etchant (e.g., 90% transmittance, 80%, 70%, 60%, etc.). Figures 11A-11B and 12 show two exemplary systems.

[0074] Figures 11A-11B show exemplary in-situ measurement systems with overall wafer coverage according to embodiments of the present invention. Figure 12 shows a typical measurement system with a scannable optical system according to embodiments of the present invention.

[0075] Referring to Figure 11A, Figure 11A shows a top view indicating the coverage area of ​​the measurement system 1101. Figure 11B shows the finite radius of curvature R. optics Figure 11B shows a side-to-side view in which 1102 and overlapping field of view 1103 enable gapless measurement and operation. Figure 11B further shows the imaging device 1104, sapphire front and back coverings 1105, light source 1106, optical filter 1107, process wafer 1108, back fluid inlet 1109, back fluid outlet 1110, etchant inlet 1111, and etchant outlet 1112.

[0076] Figure 12 shows the process wafer 1201 together with the imaging device assembly 1202 on the XY stage.

[0077] Regarding out-of-situ measurements, spatial variations in CICE etching, or their proxies (such as a unique spectral signature corresponding to a given etching feature height), can be measured outside the field. Measurements may be either reflective or transmissive. IR wavelengths would be used when transmissive measurements are required. The out-of-situ measurement chamber may be located very close to the etching chamber to allow for rapid transfer of the processed wafer. In one embodiment, the measurement system itself is not made of CICE-compatible material but is enclosed within a larger CICE-compatible chamber.

[0078] With respect to thermal operation, a controlled amount of local temperature change may be used to generate a corresponding amount of change in process wafer etching rate, as discussed in Backes, Andreas, Markus Leitgeb, Achim Bittner, and Ulrich Schmid. "Temperature Dependent Pore Formation in Metal Assisted Chemical Etching of Silicon." ECS Journal of Solid State Science and Technology 5, No. 12, January 1, 2016, pp. 653-656, which is incorporated herein by reference in its entirety. This thermal operation of etching rate can be used to actively control spatial variations in etching rate. Thermal operation may be achieved using a contact-based solution, such as thermoelectric cooling, as discussed in DiSalvo, Francis J. "Thermoelectric cooling and power generation" Science 285.5428 (1999): 703-706, which is incorporated herein by reference in whole, or using a non-contact solution, such as heating with visible or IR wavelength DMD-modulated light, as discussed in Hiura, Mitsuru, et al. "Overlay improvements using a novel high-order distortion correction system for NIL high-volume manufacturing", Novel Patterning Technologies, Vol. 10584. International Society for Optics and Photonics, 2018, which is incorporated herein by reference in whole, in whole,

[0079] Figure 13 shows an exemplary system for digital micromirror device (DMD)-modulated wafer thermal control according to an embodiment of the present invention.

[0080] Referring to Figure 13, such an exemplary system includes a sapphire front and back cover 1301, a back fluid 1302 that can be used to set the temperature of the entire wafer, a back fluid inlet 1303, a back fluid outlet 1304, an etchant inlet 1305, an etchant outlet 1306, a process wafer 1307, a focusing optical system 1308, an imaging device 1309, a digital micromirror device (DMD) assembly 1310 with a light source, and an optical filter 1311.

[0081] With regard to electric field control, the electric field can be used to modulate the level of porosity during a CICE process, as discussed in Lianto, Prayudi, Sihang Yu, Jiaxin Wu, CV Thompson, and WK Choi, “Vertical Etching with Isolated Catalyst in Metal-Assisted Chemical Etching of Silicon,” Nanoscale 4, No. 23, December 7, 2012, pp. 7532-7539, which is incorporated herein by reference in whole. In one embodiment, arrays of patterned electrodes on front and back covers are used to generate a local electric field to control local porosity within a process wafer. Figure 14 illustrates an exemplary system for electric field control in a CICE tool (only a cross-section of the CICE tool is shown) according to an embodiment of the present invention.

[0082] As shown in Figure 14, Figure 14 illustrates the process wafer 1401 along with the front of the back transparent electrode 1402, back illumination 1403, and transparent electrode 1404.

[0083] The amount of pattern density change, the amount of pattern density change, and their potential effects on etching rate and quality can be addressed using the various methods described above. In one embodiment, a denser array of process actuators can be used in areas of higher pattern density. In another embodiment, a sliding etching region in which the etchant density can be locally varied can be used to account for variations in pattern density.

[0084] Furthermore, regarding the effects of wafer edges, rapid changes in fluid meniscus, etchant concentration, and electric field near the process wafer edge can lead to significant variations in etching characteristics near the edge. This can be addressed by carefully designing the wafer edge exclusion region so that areas with large etching changes are located outside the exclusion region. In one embodiment, the front cover seal can be made in contact with the outside of the wafer periphery (see Figure 15). In another embodiment, a spin-spray type system can be used on the wafer front without a peripheral seal.

[0085] Referring to Figure 15, Figure 15 illustrates an exemplary edge contact design showing a front side seal that contacts the outer edge of a process wafer according to an embodiment of the present invention.

[0086] As shown in Figure 15, Figure 15 illustrates the process wafer 1501, wafer chuck 1502, front cover 1503, edge exclusion zone 1504, front heat seal shrinkage 1505 on the outer edge of the process wafer 1501, region of high variation in etching 1506, and device region 1507 on the process wafer 1501.

[0087] In one embodiment, backside contact can be established using a chuck made from a CICE-compatible material such as fluoropolymer or sapphire. In one embodiment, the chuck can have pin-type, ring-type, or flat surface contact with the backside of the wafer. In one embodiment, the wafer can be held against the backside chuck using clamps attached to the wafer edge, using vacuum, or using electrostatics. The space between the process wafer and the backside chuck (if any) may be filled with a liquid, such as an etchant or a common electrolyte. The backside fluid can be used to facilitate electric field control during the CICE process. The backside fluid may be stationary or circulating. The frontside etchant flow strategy (described above) can similarly be used for backside fluid flow. Figures 16 and 17 show several exemplary designs for backside contact.

[0088] Figure 16 illustrates an exemplary back surface contact with a back surface fluid according to an embodiment of the present invention. In one embodiment, the back surface fluid can be used to enable electric field control and global temperature control of a process wafer. As shown in Figure 16, such a back surface contact 1600 includes a back surface shrinkage fluid 1601, a chuck pin 1602, a wafer chuck 1603 (pin type), and a process wafer 1604.

[0089] Figure 17 illustrates an exemplary back surface contact using a vacuum chuck according to an embodiment of the present invention. As shown in Figure 17, such back surface shrinkage 1700 includes a vacuum 1701, a chuck pin 1702, a wafer chuck 1703 (pin type), and a process wafer 1704.

[0090] In one embodiment, an electric field may be used to modulate the level of porosity during a CICE process, as discussed in Weisse, Jeffrey M, Chi Hwan Lee, Dong Rip Kim, Lili Cai, Pratap M Rao, and Xiaolin Zheng, "Electroassisted Transfer of Vertical Silicon Wire Arrays Using a Sacrificial Porous Silicon Layer," Nano Lett. 13, No. 9, September 11, 2013, pp. 4362-4368, which is incorporated herein by reference in its entirety. In one embodiment, an electric field is generated using electrodes patterned on front and back covers to control the porosity within the process wafer. It should be noted that patterning of thin, CICE-compatible electrode layers on a flat substrate is available. Furthermore, it should be noted that backlighting can be used to create an ohmic contact for establishing a current through the process wafer, as discussed in Lehmann, Volker. Electrochemistry of Silicon: Instrumentation, Science, Materials and Applications. Wiley, 2002, which is incorporated herein by reference in its entirety. Figure 14 shows an exemplary such system.

[0091] Regarding safety features, in one embodiment, the seals between the front process chamber, process wafer, and rear wafer cover are CICE compatible. The seals may also be CMOS compatible. In one embodiment, the seals can be fabricated integrally within the front and rear process covers. Rotating seals (either fabricated integrally or otherwise) can be used to seal the rotating assembly.

[0092] Regarding tool maintenance and cleaning, intermittent cleaning of the process chamber with a metal contaminant cleaning solution such as nitric acid can be used to remove metal impurities that may accumulate on the process chamber. The tool maintenance schedule could be divided into frequent intermittent metal cleaning and less frequent maintenance involving complete tool disassembly and cleaning.

[0093] It should be noted that the etchant phase may be either gas or liquid. Both gas-phase and liquid-phase CICE have been previously demonstrated. For gas-phase CICE, the generation and control of the electric field may be achieved using an atmospheric pressure plasma, as discussed in Tendero, Claire, et al. “Atmospheric pressure plasmas: A review,” Spectrochimica Acta Part B: Atomic Spectroscopy, Vol. 61, No. 1, 2006, pp. 2-30, which is incorporated herein by reference in its entirety.

[0094] In one embodiment, the CICE apparatus comprises a spin-spray type apparatus for front etchant supply, a back vacuum adsorption apparatus, overall (single setpoint) temperature control of the front etchant, local contact or non-contact temperature control of the back of the wafer, flow or freeze-based reaction quenching, reflection out-of-situ scattering measurement, and optional in-situ IR-based transmission scattering measurement.

[0095] In another embodiment, the CICE tool comprises a thick fluid sheet for the front etchant (defined as the thickness of a fluid sheet having a light transmittance of 50% or less (in the associated measurement spectrum)), a thick fluid sheet on the back, overall (single-setpoint) temperature control of the front etchant, overall (single-setpoint) temperature control on the back of the wafer, fluid-based reaction quenching, out-of-situ reflectance scattering measurement, and diamond-like coating (DLC)-based electric field generation.

[0096] In another embodiment, the CICE tool comprises a thick fluid sheet for the front etchant on the back of the wafer (defined as the thickness of the fluid sheet having a light transmittance of 50% or more (in the relevant measurement spectrum)), a thin fluid sheet, global (single-setpoint) temperature control of the front etchant, global (single-setpoint) or local temperature control on the back of the wafer, flow-based reaction quenching, out-of-situ reflectance scattering measurement, arbitrary in-situ IR-based transmission scattering measurement, and diamond-like coating (DLC)-based electric field generation.

[0097] In another embodiment, the CICE tool comprises a thick fluid sheet for the front etchant, a vacuum chuck for the back, global (single-setpoint) temperature control of the front etchant, global (single-setpoint) or local temperature control of the back of the wafer, flow-based reaction quenching, out-of-situ reflectance scattering measurement, and optional in-situ IR-based transmission scattering measurement.

[0098] In another embodiment, the CICE tool comprises a thin fluid sheet for the front etchant, a thicker fluid sheet on the back, global (single-setpoint) or local temperature control on the front, global (single-setpoint) temperature control on the back of the wafer, flow-based reaction quenching, in-situ reflection scattering measurement, optional out-of-situ reflection scattering measurement, and diamond-like carbon (DLC)-based electric field generation.

[0099] In another embodiment, the CICE tool comprises a thin fluid sheet for the front etchant, a thin fluid sheet on the back, global (single-setpoint) or local temperature control on the front, global (single-setpoint) or local temperature control on the back of the wafer, flow-based reaction quenching, in-situ reflection scattering measurement, optional in-situ IR-based transmission scattering measurement, optional out-of-situ reflection scattering measurement, and DLC-based electric field generation.

[0100] In another embodiment, the CICE tool comprises a thin fluid sheet for the front etchant, a vacuum chuck for the back, global (single-setpoint) or local temperature control for the front, global (single-setpoint) or local temperature control for the back of the wafer, flow or freeze-based reaction quenching, in-situ reflection scattering measurement, optional in-situ IR-based transmission scattering measurement, optional out-of-situ reflection scattering measurement, and DLC-based electric field generation.

[0101] In another embodiment, the CICE tool comprises a front vapor phase etchant, a back thick fluid sheet, front global (single setpoint) or local temperature control, back global (single setpoint) temperature control, in-situ reflection scattering measurement, optional out-of-situ reflection scattering measurement, and optional plasma and DLC-based field generation.

[0102] In another embodiment, the CICE tool comprises a front vapor phase etchant, a back thin fluid sheet, front global (single setpoint) or local temperature control, back global (single setpoint) or local temperature control, in-situ reflection scattering measurement, optional in-situ IR-based transmission scattering measurement, optional out-of-situ reflection scattering measurement, and optional plasma and DLC-based field generation.

[0103] In another embodiment, the CICE tool comprises a front vapor phase etchant, a rear vacuum chuck, a front global (single-setpoint) or local temperature control, a wafer rear global (single-setpoint) or local temperature control, in-situ reflection scattering measurement, optional in-situ IR-based transmission scattering measurement, and optional out-of-situ reflection scattering measurement.

[0104] In another embodiment, the CICE tool consists of a variable-thickness fluid sheet for the front etchant. In yet another embodiment, the CICE tool consists of a variable-thickness fluid sheet on the back surface. The variable-thickness fluid sheet design may be an instrument that uses a deformable polymer front and back cover assembly, for example, a deformable polymer polymer bellows and / or diaphragm.

[0105] The discussion regarding porosity control in CICE is now considered appropriate.

[0106] Details regarding porosity control in CICE are discussed in their entirety in A. Mallavarapu, P. Ajay, C. Barrera, SV Sreenivasan, “Ruthenium Assisted Chemical Etching of Silicon - Enabling CMOS-Compatible 3D Semiconductor Device Nanofabrication,” ACS Applied Materials & Interfaces 2021, Vol. 13, No. 1, pp. 1169-1177, which is incorporated herein by reference.

[0107] Gold is the catalyst of choice in CICE literature due to its ability to robustly create non-porous, high-aspect-ratio, vertical silicon nanostructures. However, Au cannot be used in semiconductor fabs because it is not CMOS compatible and is known to cause undesirable deep-level defects in silicon circuits. While CICE can improve the performance of these devices with its excellent etch anisotropy and sidewall profiles, the use of gold would prohibit process integration in the manufacturing of these devices.

[0108] The CICE mechanism suggests that an open-circuit local redox reaction occurs at the catalytic site, accompanied by the following cathode and anodic reactions (where n depends on the oxidation state of silicon).

[0109]

number

[0110] Catalysts containing one or more elements such as Au, Pt, Pd, Ag, Ru, W, Cu, TiN, Ti, graphene, and carbon catalyze the reduction of H2O2, injecting the resulting electron holes into Si and altering the oxidation state of Si. HF selectively etches this silicon, and the catalyst settles in the etched region, continuing the local redox reaction and thereby generating silicon nanostructures in the catalyst-free regions. The characteristics of the resulting silicon nanostructures depend heavily on the balance of reaction rate, charge transfer, etchant mass transfer, and catalyst motion.

[0111] High aspect ratio, void-free, and tapered silicon nanostructures using CICE have been limited to low-doped Si etching with Au as a catalyst. Other catalysts (such as Ru, Pd, Pt, and TiN) and semiconductors (such as Ge, GaAs, InP, GaN, SiGe, and SiC) in the literature suffer from undesirable external porosity during CICE.

[0112] The following variables are controlled locally and / or globally to control the porosity: Etchant concentration In one embodiment, the porosity is reduced by changing the etchant concentration in order to decrease the concentration of the oxidizing agent in the etchant solution.

[0113] Etchant temperature Lowering the temperature of the etchant during CICE reduces the porosity.

[0114] Electric field during CICE By applying a negative electric field bias to the back surface of the substrate during CICE, the porosity is reduced. In another embodiment, the porosity is reduced by supplying electron holes using an electric current in an etchant solution that does not contain an oxidizing agent.

[0115] Board preparation processThe porosity is reduced by providing an interfacial material between the catalyst and the substrate before CICE. In one embodiment, the interfacial material is one or more of silicon oxide, aluminum oxide, titanium oxide, and titanium. In one embodiment, the thickness of the interfacial material is optimized to reduce the porosity. In another embodiment, the thickness of the interfacial material is optimized to improve the uniformity of etching. Furthermore, the interfacial material is etched off with a CICE etchant during CICE.

[0116] Pattern topology optimization to reduce excess hole generation The catalyst surface region affects the concentration of holes generated during CICE, and thereby affects the porosity. In one embodiment, the catalyst surface region is reduced by optimizing the catalyst geometry to reduce the surface area while maintaining the necessary etching feature constraints.

[0117] Catalyst surface area In one embodiment, a localized region of the catalyst is exposed to a CICE etchant to reduce the concentration of holes generated. In one embodiment, as shown and discussed in relation to Figures 18, 19A–19D and 20A–20C, a patterned catalyst island or "minimesh" is used to reduce the surface region, where the catalyst is patterned using nanoimprint lithography.

[0118] Referring to Figure 18, Figure 18 is a flowchart of Method 1800 for a Ru minimesh patterning process using modified jet and flash imprint lithography with sparse inkjet droplets according to an embodiment of the present invention. Figures 19A–19D show cross-sectional views for a laminimesh patterning process using modified jet and flash imprint lithography with sparse inkjet droplets, using the steps described in Figure 18. Figures 20A–20C show inclined cross-sectional SEM and top-down optical microscope images of the resist pattern after imprinting sparse droplets according to an embodiment of the present invention.

[0119] Referring to Figure 18, and relating to Figures 19A-19D, in step 1801, the sparse resist droplets 1901 are distributed onto the substrate 1902 using an inkjet, as shown in Figure 19A.

[0120] In step 1802, as shown in Figure 19B, the template 1903 is placed on the sparse resist droplet 1901 and the capillary (opening) 1904 of the template 1903 is filled.

[0121] In step 1803, an ultraviolet (UV) flash is applied from a UV lamp 1905 or the like to cure the resist 1901, as shown in Figure 19C.

[0122] In step 1804, the template 1903 is separated from the resist 1901, thereby forming a pattern 1906 as shown in Figure 19D.

[0123] Next, referring to Figures 20A to 20C, Figure 20A shows the center of a cross-sectional scanning electron microscope image of the resist pattern after sparse droplet imprinting. Figure 20B shows a cross-sectional SEM image of the resist pattern after sparse droplet imprinting. Figure 20C shows the edge of a cross-sectional scanning electron microscope image of the resist pattern after sparse droplet imprinting.

[0124] In another embodiment, specific areas of the catalyst are masked during CICE to reduce the total catalyst surface area exposed to the CICE etchant. Here, “masking” means covering the catalyst with a material resistant to the CICE etchant, which can include polymers, photoresists, electron beam resists, carbon, aluminum oxide, chromium, and other materials. The masked catalyst areas are etched in CICE (first CICE), and then a second CICE is performed on the masked catalyst areas after the first CICE process is completed and the first etched structure is masked or the catalyst is removed in those areas. The patterned catalyst in the first CICE and the patterned catalyst in the second CICE process may or may not be connected to each other. In one embodiment, intentional discontinuities between the catalysts in the first and second CICE are patterned, such as streets without catalyst. In another embodiment, the CICE etchant is selectively distributed over local areas of the patterned catalyst, in local areas smaller than the entire patterned catalyst area. In another embodiment, the patterned catalyst is partially covered with a mask material and then subjected to CICE. In yet another embodiment, the minimesh is created as described above, and then the entire substrate is covered with a mask material, followed by a patterning step to open up the minimesh region and leave the mask on the rest of the wafer surface. This patterning step can optionally cover the boundary region of the minimesh, thereby allowing for a small overlap between the minimesh region and the mask region.

[0125] membrane stress At the catalyst / substrate interface, film stress and interfacial stress can affect the CICE reaction rate and porosity. Optimizing film and interfacial stress reduces porosity during CICE. In one embodiment, substrate preparation, substrate surface energy, catalyst deposition method—including deposition process, rate, and temperature, catalyst patterning method, catalyst pattern, and post-patterning surface treatment such as annealing—are used to control film and interfacial stress.

[0126] Plasma treatment of catalysts The catalytic activity can be modified using plasma treatment. The plasma recipe and plasma time are experimentally determined based on the porosity observed after the catalyst has influenced chemical etching. In one embodiment, the plasma recipe is Ar, He, O2, H2, CF4, SF6, Cl2, CH x F y The plasma contains one or more gases, including N2, CO, CO2, BCl3, CH4, SiH4, and C4F8. Plasma treatment can be performed as a separate step after catalyst patterning. In one embodiment, Ru is used as a catalyst for CICE of Si, and the patterned Ru is exposed to an Ar / CF4 plasma. In another embodiment, plasma treatment is performed as part of the etching step during catalyst patterning. In one embodiment, Ru is used as a catalyst for CICE of Si, and the etching mask used on the Ru is etched using an Ar / CF4 plasma, thereby exposing the area beneath the Ru to the mask etching plasma. One embodiment shown in Figures 21A-21D illustrates the effect of plasma treatment of a Ru catalyst for CICE of low-doped silicon.

[0127] Figures 21A-21D show the effects of plasma used in descam etching on Ru minimesh CICE, which yields various results across the entire minimesh with relatively ineffective edge regions, according to embodiments of the present invention. All scale bars are 1 micrometer in length. Figure 21A shows the effects of plasma used in descam etching using argon / O2. Figure 21B shows the effects of plasma used in descam etching using argon. Figure 21C shows the effects of plasma used in descam etching using argon / H2. Figure 21D shows the effects of plasma used in descam etching using argon / CF4.

[0128] In another embodiment, plasma treatment of the catalyst can enable the reduction of defects caused during CICE. In another embodiment, the plasma treatment varies across the catalyst, exposing selected areas of the catalyst to different plasma treatments, thereby resulting in programmable porosity and / or etching depth in selected areas on the substrate. The plasma treatment can be applied by masking areas of the catalyst or by using focused plasma or an ion beam. In one embodiment, the time and sequence of processes between the plasma treatment of the catalyst and CICE are optimized to ensure desired CICE etching characteristics, such as substrate porosity. In one embodiment, the effect of plasma modification of catalytic activity changes with time after plasma modification, and CICE is performed at an optimal time after plasma modification. In one embodiment, the optimal time is less than 15 minutes.

[0129] UV treatment of catalystsThe catalytic activity of a catalyst can be modified using treatments such as ion beam, UV, vacuum UV, IR, and X-ray. In one embodiment, catalytic activity can be modified by UV treatment of the catalyst surface itself, or in the presence of a catalytic activity modifying material such as gas or spin coating chemistry. The catalytic activity modifying material contains one or more of the following: (i) polymers such as acrylates, UV-curable polymers, and fluorinated polymers; (ii) gases such as oxygen, fluorine, helium, argon, hydrogen, CF4, SF6, formic acid, and acetic acid; and (iii) chemical substances such as fluorinated surfactants. In one embodiment, the UV treatment is performed as part of the lithography process during the patterning of the catalyst. In another embodiment, the catalytic activity modifying material is deposited on the catalyst before exposure to UV. In another embodiment, the catalyst is exposed to UV light simultaneously in the presence of the catalytic activity modifying material and UV light, for example, CF4, H2, and Ar. In one embodiment, the UV light process is performed as a separate step before the catalyst is affected by chemical etching, and the material in the lithography step is modified to contain the catalytic activity modifying material. In another embodiment, UV treatment is applied to a selected region of the catalyst in the presence of a catalytic activity modifier, thereby changing the UV treatment across the catalyst and resulting in programmable porosity and / or etching depth in the selected region on the substrate. The UV treatment can be applied by masking a specific region of the catalyst using lithography or by irradiating UV light through the mask.

[0130] Catalyst materials The catalyst material may be an alloy of two or more elements to enable CICE to create nanostructures with the desired porosity. Various alloy materials and compositions can be tested using combinatorial sputtering or cos-sputtering to determine the ideal catalytic behavior. In one embodiment, the catalyst is Ru x Cr y C z It is composed of.

[0131] Substrate materialsThe doping type, doping concentration, and substrate material can be selected to reduce porosity based on the application design and material requirements.

[0132] Etchant phase The CICE etchant may be a liquid phase, vapor phase, gel phase, or plasma phase. In one embodiment, a high aspect ratio nonporous silicon nanostructure is achieved using platinum / platinum silicide with a gas-phase based CICE process, such as that discussed in Romano, Lucia, Matias Kagias, Joan Vila-Comamala, Konstantins Jefimovs, Li-Ting Tseng, Vitaliy A. Guzenko, and Marco Stampanoni, “Metal Assist Chemical Etching of Silicon in the Gas Phase: A Nanofabrication Platform for X-Ray Optics,” Nanoscale Horizons, Vol. 5, No. 5, 200, pp. 869-879, which is incorporated herein by reference in whole. In one embodiment, Ru is used as a catalyst having a gas-phase etchant for CICE. In another embodiment, a vapor-based CICE is used to etch small, closed patterns, such as circular holes, with little to no etch stall (because the transfer rate of the gas phase etchant is faster than that of the liquid phase etchant).

[0133] Substrate / catalyst interface The catalyst / substrate interface can be optimized to allow for reduced porosity. In one embodiment, the catalyst is annealed to produce a silicide for CICE. In another embodiment, the catalyst is deposited on an interface material. In one embodiment, the native oxide layer is the interface material.

[0134] Protective layer during catalyst pattern formationCatalyst patterning may be performed using UV light or other wavelengths of light for lithography and plasma etching for pattern transfer. A protective layer on the catalyst can be used to avoid undesirable changes in catalytic activity during patterning. Examples of protective layers include C, SiN, SiO2, TiN, Cr, etc. In one embodiment, a desired catalytic activity modification process can be integrated into the catalyst patterning process. In another embodiment, the plasma etching of the catalyst may include a desired gas in the etching recipe. Furthermore, a post-processing step after catalyst patterning can be used to modify the final catalytic activity of the catalyst to a desired level before CICE. In another embodiment, Ru plasma etching is modified to include catalytic activity modification chemistry. In one embodiment, Ru is protected using SiN or C during O2 plasma exposure.

[0135] Alternating porous / non-porous layers using plasma and CICE In one cycle, the catalytic activity can be increased using plasma. Then, the catalyst and substrate are exposed to an etchant in gaseous (or liquid) form to form a porous layer of the nanostructure. Next, the catalytic activity is decreased using plasma. Then, the catalyst and substrate are exposed to an etchant in gaseous (or liquid) form to form a non-porous layer of the nanostructure. By repeating these cycles, alternating porous / non-porous layered nanostructures can be achieved.

[0136] Catalytic activity modification for etching depth control In one embodiment, locally varying plasma treatment is used in regions with non-uniform patterns to modify the catalytic activity and, consequently, the etching rate.

[0137] Method for removing the etching mask after catalyst pattern formation.In one embodiment, a three-layer resist pattern is formed on a catalyst film using photolithography. The resist is used as an etching mask to transfer the pattern to the catalyst film using methods such as plasma etching, atomic layer etching, wet etching, and ion milling. In one embodiment, after pattern transfer to the catalyst film, the etching mask is removed using a wet treatment such as a piranha solution, or using an oxygen-free plasma. In one embodiment, a Ru catalyst film is patterned using photolithography, and the photoresist and other films used in the photolithography are removed using an oxygen-free plasma method.

[0138] In one embodiment, these process variables are controlled for low-doped p-type silicon with ruthenium as a catalyst. Ruthenium is already used as a barrier metal for interconnects in semiconductor fabs and is listed in the IRDS roadmap as a next-generation metal for future generations of metal interconnects in logic devices, as well as for metal electrodes in DRAM capacitors. Thus, a semiconductor ecosystem already exists that is in place for ruthenium thin-film deposition with high yield and low defect rates, and for patterning and etching of sub-20nm features in Ru. In one embodiment, a Ru-CICE process is used that can take advantage of recent developments for the integration of Ru in CMOS devices, thereby resulting in a "drop-in" CICE process within a CMOS fab.

[0139] In one embodiment, CICE is used to etch a semiconductor material with one or more material layers on the semiconductor material. The catalyst layer is one of the one or more layers. The catalyst (as described above) may be subjected to a process that modifies the catalytic activity of the catalyst. The following may also be one of the one or more layers: Ru, Au, Pt, Pd, Ag, Cu, Ni, W, TiN, graphene, carbon, Cr, SiO2, and Ti.

[0140] In one embodiment, Ru is patterned using nanoimprint lithography and etched using wet etching. In one embodiment, the undesirable porosity in Ru CICE is reduced by altering the catalytic activity of Ru in the CICE cathode reaction. The resulting optimal Ru CICE process is shown in Figures 22A-22F and features the following characteristics: (i) minimesh: A localized Ru minimesh is used instead of complete coverage of the silicon wafer with patterned Ru to reduce the area of ​​Ru involved in the cathode reaction, and (ii) Ar / CF4 plasma: The plasma chemistry and etching time during the resist decam process play a crucial role in the Ru catalytic activity, enhancing the Ru catalytic activity against oxygen plasma and reducing the activity against oxygen-free Ar / CF4 plasma and other plasma chemistry (resist decam can still be performed with Ar, Ar / H2, etc.). Exposure of Ru to a long (30s) Ar / CF4 plasma during resist etching yielded an improved Ru CICE, thereby producing a non-porous, high-aspect-ratio anisotropic silicon etch with properties comparable to Au CICE.

[0141] Figures 22A–22F show a desired CICE with a Ru minimesh, obtained using a long Ar / CFr plasma for descam etching, according to an embodiment of the present invention. Figure 22A shows a top-down SEM image showing defect-free silicon nanowires at a magnification of 200 micrometers. Figure 22B shows a top-down SEM image showing defect-free silicon nanowires at a magnification of 20 micrometers. Figure 22C shows a top-down SEM image showing defect-free silicon nanowires at a magnification of 200 nanometers. Figures 22D–22F show inclined cross-sectional SEM images at various positions within the minimesh, showing a uniform, defect-free Ru CICE.

[0142] The discussion regarding the avoidance of decay in CICE-etched nanostructures is now considered relevant.

[0143] Details regarding the avoidance of collapse in CICE-etched nanoarrays are discussed in their entirety in A. Mallavarapu, P. Ajay, SV Sreenivasan, "Enabling Ultra-High Aspect Ratio Silicon Nanowires Using Onset of Collapse Onset of Detecting Onseting of Collapse," Nano Letters 2020, 20(11), 7896-7905, which is incorporated herein by reference, and in their entirety in Khorasaninejad, M.; Abedzadeh, N.; Singh Jawanda, A.; O, N.; Anantram, MPP; Singh Saini, S. “Bunching Characteristics of Silicon Nanowire Arrays,” Journal of Applied Physics, Vol. 111, No. 4, 2012, 044328, which is also incorporated herein by reference.

[0144] In one embodiment, the collapse of CICE-etched nanostructures can be delayed or eliminated by using a “collapse prevention cap” or “collapse prevention feature” on the tip of the nanostructure. In one embodiment, the collapse prevention cap prevents collapse due to electrostatic repulsion between nanostructures. In another embodiment, the collapse prevention cap is provided on the tip of a nanostructure fabricated by plasma etching.

[0145] In one embodiment, oversized nanowires are fabricated in CICE using nanoimprint lithography and gold as a catalyst. With respect to nanowires separated by gaps of less than 30 nm, the nanowires remain undecayed for much greater heights than predicted by conventional decay theories, as shown in Figures 23A–23C.

[0146] Figure 23A is a plot of the maximum height (micrometers) versus diameter (nanometers) of a nanowire before decay, according to an embodiment of the present invention. In particular, Figure 23A is a plot with modifications to the lateral decay theory model to include electrostatic repulsion and the effect of removing the gold resist cap on oversized nanowire decay. Figure 23B is a schematic diagram of a pair of decayed charged nanowires according to one embodiment of the present invention. Figure 23C illustrates a marked cross-sectional SEM image of an oversized silicon nanowire after the removal of the gold resist cap, according to an embodiment of the present invention. The scale bar is 1 micrometer.

[0147] The data suggest that additional repulsive forces, not explained by the model, may exist for the small gaps between nanowires that cause the observed abnormally high critical height. In one embodiment, these repulsive forces between nanowires may be due to electrostatic effects arising from charges present within the resist-gold cap of the nanowires or within the silicon nanowires and nanowire surfaces. Removing the decay-avoidance cap reduces the critical decay height to a value close to that predicted by adhesion theory, as shown in Figures 23A-23C. The trend observed in oversized nanowire decay did not match the trend predicted by lateral decay theory (the nanowire decay height increased instead of decreasing with increasing NW diameter). In one embodiment, a theoretical decay type including electrostatic forces was used to predict and design a structure to maximize non-decay. In this model, the lateral decay model (discussed in its entirety in Glassmaker, NJ, A Jagota, CY Hui, and J Kim. "Design of Biomimetic Fibrillar Interfaces: 1. Making Contact." JR Soc. Interface 1, No. 1, November 22, 2004, pp. 23-33, which is incorporated herein) included the charge near the top of the nanowire. Nanowire 2301 decayed, L C Consider the nanowires shown in Figure 23B, which have a contact length of . In one embodiment, each nanowire 2301 is near the top of the nanowire 2301 (in this analysis, LC and the average volume charge density ρ existing therein (inner and maximum) c,avg is assumed to have. In the lateral collapse type, the estimation of the adhesion energy and elastic deformation of the contact region between nanowires requires the calculation of the contact width. Using the Johnson-Kendall-Roberts (JKR) theory of adhesion, the equilibrium contact width for two identical cylinders without external force was predicted. In one embodiment, this model was modified to include the Coulomb repulsion due to static electricity as the external force per unit length P, leading to the updated JKR model in Equation (1):

[0148] [Number]

[0149] Unit length L C External force per unit as P, contact length r c , diameter 2a, E * = E / (1 - ν 2 ), elastic modulus E, Poisson's ratio ν, space 2w, surface energy γ s , and ρ as the charge density c . The equation for P is approximate and is suitable for capturing the trends seen in experiments conducted using embodiments of the present invention.

[0150] Numerically solve Equation (1) for r c and substitute it into the lateral folding theory to derive the folding height. In one embodiment, the probabilistic variations between concentrations within over-sized nanowires with gold resist caps are included using a normal distribution. Based on this new model, a plot with the same trend as that experimentally observed in Figure 23A is achieved.

[0151] In one embodiment, silicon nanowires having a diameter-to-pitch ratio > 0.6 separated by a <30 nm gap are used to avoid collapse, avoiding the caps made of gold and resist with respect to the unexpectedly large height of the nanowires.

[0152] The principles of the present invention provide two important contributions: (1) a process for achieving ultra-high aspect ratio undecayed silicon nanowires that enable an improvement of ~4.5 times in maximum aspect ratio compared to known models, and (2) a modified lateral decay model including an electrostatic repulsion component that fits the observed experimental results.

[0153] In one embodiment, the collapse-avoiding cap contains one or more of insulating materials, semiconductor materials, and conductive materials. The collapse-avoiding cap material and thickness are optimized to maximize repulsion and enable the best possible non-collapse aspect ratio.

[0154] Figures 24, 25A-25D, 26A-26D, 27, 28A-28B, 29A-29B, 30, 30A-30D, and 31A-31D illustrate a process for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap according to embodiments of the present invention.

[0155] Referring to Figure 24, Figure 24 is a flowchart of Method 2400 for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap, according to an embodiment of the present invention. Figures 25A-25D show top-down diagrams for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 24, according to an embodiment of the present invention. Figures 26A-26D show cross-sectional diagrams for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 24, according to an embodiment of the present invention.

[0156] Referring to Figures 25A-25D and 26A-26D in conjunction with Figure 24, in step 2401, the lithography material stack 2601 is patterned on the substrate 2602 as shown in Figures 25A and 26A. In one embodiment, the lithography material stack 2601 includes a disintegration-preventing material.

[0157] In step 2402, the catalyst 2603 is deposited on the material stack 2601, as shown in Figures 25B and 26B.

[0158] In step 2403, the structures shown in Figures 25B and 26B are immersed in a MACE solution and CICE is performed to produce structures as shown in Figures 25C and 26C. In one embodiment, the patterned wafer is immersed in a MAC solution of 12.5 moles of HF and 1 mole of H2O2. In one embodiment, etching can be quenched in the wafer, followed by rinsing with water and drying with an air gun supplying clean, dry air (CDA).

[0159] In step 2404, catalyst 2603 is optionally removed, as shown in Figures 25D and 26D. In one embodiment, catalyst 2603 (e.g., a gold catalyst) is replaced with potassium iodide transene TM The base gold etchant can be optionally removed. The remaining resist can be optionally removed using a short oxygen plasma.

[0160] Referring to Figure 27, Figure 27 is a flowchart of an alternative method 2700 for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap, according to one embodiment of the present invention. Figures 28A-28D show top views for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 27, according to one embodiment of the present invention. Figures 29A-29D depict cross-sectional views for fabricating any self-supporting high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 27, according to an embodiment of the present invention.

[0161] Referring to Figures 28A-28B and 29A-29B in conjunction with Figure 27, in step 2701, as shown in Figures 28A and 29A, a lithography material stack 2901 is patterned on a substrate 2902. In one embodiment, the lithography material stack 2901 includes a disintegration-preventing material.

[0162] In step 2702, plasma etching of nanostructures as shown in Figures 28B and 29B is performed, resulting in the structures shown in Figures 28B and 29B.

[0163] Referring to Figure 30, Figure 30 is a flowchart of an alternative method 3000 for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap, according to an embodiment of the present invention. Figures 31A-31D show a top-down view for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 30, according to one embodiment of the present invention. Figures 32A-32D depict a cross-sectional view for fabricating any independent high aspect ratio nanostructure having a collapse-avoiding cap using the steps described in Figure 30, according to an embodiment of the present invention.

[0164] Referring to Figure 30 in conjunction with Figures 31A-31D and 32A-32D, in step 3001, the catalyst 3201 is patterned on the substrate 3202 as shown in Figures 31A and 32A.

[0165] In step 3002, the decay-avoiding material 3203 is patterned in the non-catalytic region, as shown in Figures 31B and 32B.

[0166] In step 3003, the structures shown in Figures 31B and 32B are immersed in a MACE solution and CICE is performed to produce structures as shown in Figures 31C and 31C. In one embodiment, the patterned wafer is immersed in a MAC solution of 12.5 moles of HF and 1 mole of H2O2. In one embodiment, etching can be quenched in the wafer, followed by rinsing with water and drying with an air gun supplying clean dry air (CDA).

[0167] In step 3004, catalyst 3201 is optionally removed, as shown in Figures 31D and 32D. In one embodiment, catalyst 3201 (e.g., a gold catalyst) is replaced with potassium iodide transene TM The base gold etchant can be optionally removed. The remaining resist can be optionally removed using a short oxygen plasma.

[0168] In Figures 24, 25A-25D, 26A-26D, 27, 28A-28B, 29A-29B, 30, 30A-30D, and 31A-31D, the spacing between high aspect ratio nanostructures in one or more regions of the patterned area is less than 200 nm. In another embodiment, the spacing is less than 50 nm.

[0169] Process integration involving the avoidance of collapse will not be discussed.

[0170] In one embodiment, the decay-avoidance cap can enable ultra-high aspect ratio nanostructures such as silicon fins in transistors, stacked nanopillars for DRAM capacitors, silicon nanowires for nanoDLDs, silicon nanostructures for metalens, and multilayer alternating stacks for 3D flash and memristors. In one embodiment, these nanostructures (of any material) can be etched using plasma etching with the decay-avoidance cap as an etch mask. In another embodiment, the nanostructure is made of a semiconductor material and etched with CICE, and the decay-avoidance cap is placed in an area not occupied by a patterned catalyst.

[0171] Removal of the collapse-avoidance cap may lead to the collapse of the ultra-high aspect ratio nanostructure. In one embodiment, subsequent process steps to stabilize the high aspect ratio nanostructure are integrated before the removal of the collapse-avoidance cap.

[0172] In one embodiment, the material is deposited in the region around the nanostructure before the removal of the collapse-prevention cap.

[0173] Regarding CMOS devices, CMOS scaling is employed in the semiconductor industry to improve chip performance, reduce power consumption, and enhance functionality, typically by increasing transistor density. This scaling is achieved by releasing new technology nodes every 18 months to 2 years. Transistor density is increased by reducing transistor dimensions such as gate length, gate oxide thickness, and spacer thickness. As feature size decreases, new technologies such as high-k dielectrics, metal gates, strain engineering, and low-k spacer dielectrics have been employed along with planar or concave transistors. However, despite reducing the area per transistor, 3D scaling in the form of FinFETs has been introduced to improve electrostatics. The process of manufacturing tall, thin fins with minimal sidewall damage and no collapse has been challenging as dimensions have decreased to less than 20 nm. For the sub-10 nm node, innovative methods have been proposed to improve electrostatics using horizontal nanosheets and nanowires.

[0174] Increasing the number of tailor fins and / or stacked nanosheets and nanowires can, for example, improve chip performance and enable scaling of many nodes. The use of collapse-prevention caps during the fabrication of CMOS devices using plasma etching or CICE can enable the creation of ultra-high aspect ratio nanostructures while preventing substantial collapse. Removal of collapse-prevention caps can lead to the collapse of the ultra-high aspect ratio nanostructures. In one embodiment, subsequent process steps to stabilize the high aspect ratio nanostructures are integrated before the collapse-prevention caps are removed. Exemplary process flows of integration and removal of collapse-prevention caps for fabricating finFETs using CICE are discussed below in relation to Figures 33 and 34A-34G.

[0175] Figure 33 is a flowchart of method 3300 for fabricating a finFET with a collapse-prevention cap using CICE, according to one embodiment of the present invention. Figures 34A-34G, 35A-35G, and 36A-36G show different diagrams for fabricating a finFET with a collapse-prevention cap using CICE, according to an embodiment of the present invention, using the steps described in Figure 33.

[0176] Referring to Figure 33 in conjunction with Figures 34A-34G, 35A-35G, and 36A-36G, in step 3301, the fin 3601 is etched onto a substrate 3603 having a collapse prevention cap 3602, as shown in Figures 34A, 35A, and 36A.

[0177] In step 3302, oxide 3604 is filled into the groove (opposite side of fin 3601), and then etched back as shown in Figures 34B, 35B, and 36B.

[0178] In step 3303, the collapse that avoids the cap 3602 is removed, as shown in Figures 34C, 35C, and 36C.

[0179] In step 3304, as shown in Figures 34D, 35D, and 36D, oxide 3604 is etched back in the patterned region by using dummy gate patterning 3605, etc.

[0180] In step 3305, the dummy gate 3605 is filled with capacitor material 3606 or the like, as shown in Figures 34E, 35E, and 36E.

[0181] In step 3306, shallow trench separation is performed, particularly in the oxide region 3604, in order to deposit the source and drain regions 3607, as shown in Figures 34G, 35G, and 36G.

[0182] In step 3307, metal gate substitution and high-k dielectric deposition of material 3608 are performed, as shown in Figures 34H, 35H, and 36H.

[0183] Further discussion of these and other steps of Method 3300 is provided below.

[0184] In one embodiment, fins are fabricated from alternating layers of material for creating nanosheet FETs. In another embodiment, high aspect ratio nanostructures with collapse-prevention caps are used to prevent the stacked capacitor geometry in a DRAM architecture from collapsing, where capacitor material or dummy material is deposited around the region of the high aspect ratio structure before the collapse-prevention caps are removed.

[0185] In one embodiment, etching of shallow trench-isolated (STI) oxides is performed using vapor-phase HF. Etching of deposited oxides using HF is temperature-dependent, as discussed in Wong, Man, Mehrdad M. Moslehi, and Robert A. Bowling. “Wafer Temperature Dependence of the Vapor-Phase HF Oxide Etch.” Journal of the Electrochemical Society, Vol. 140, No. 1, 1993, page 205, which is incorporated herein by reference in whole. In one embodiment, wafer temperature is used as a knob to control the spatial variation of the STI oxide etching rate. Spatial variation control of etching can be performed using in-situ real-time or offline functional measurement systems, such as those based on spectrophotometric measurements, and thermal actuators, such as thermoelectric coolers or digital micromirror devices.

[0186] Regarding the nanodeterministic lateral displacement (DLD) device, in one embodiment, a polymer is used to deposit material around a high aspect ratio nanostructure with a collapse-prevention cap before the collapse-prevention cap is removed. The cover plate is anodically bonded to the tip of the nanostructure, and then the material is removed from around the high aspect ratio nanostructure. Embodiments showing the bonding of the cover plate are shown in Figures 37, 38A–38B, 39, 40A–40C, 41 and 42A–42E.

[0187] Figure 37 is a flowchart of method 3700 for bonding cover plates according to an embodiment of the present invention. Figures 38A to 38B depict cross-sectional views for bonding cover plates using the steps described in Figure 37 according to an embodiment of the present invention.

[0188] Referring to Figure 37 in conjunction with Figures 38A to 38B, in step 3701, the fin 3801 is etched onto a substrate 3803 having a collapse prevention cap 3802, as shown in Figure 38A.

[0189] In step 3702, as shown in Figure 38B, the cover plate 3804 is bonded to the collapse-prevention cap 3802. In one embodiment, the cover plate 3804 is bonded to the high aspect ratio nanostructure by the collapse-prevention cap 3802. Bonding is performed using anodic bonding.

[0190] Figure 39 is a flowchart of an alternative method 3900 for bonding a cover plate according to one embodiment of the present invention. Figures 40A to 40C show cross-sectional views of bonding a cover plate using the process described in Figure 39 according to one embodiment of the present invention.

[0191] Referring to Figure 39 in conjunction with Figures 40A to 40C, in step 3901, the fin 4001 is etched onto the substrate 4003 having a collapse prevention cap 4002, as shown in Figure 40A.

[0192] In step 3902, as shown in Figure 40B, before the cover plate is bonded, a bonding aid material 4004 (e.g., silicon oxide) is deposited on the collapse prevention cap 4002.

[0193] In step 3903, the cover plate 4005 is bonded to the bonding auxiliary material 4004, as shown in Figure 40C. In one embodiment, the cover plate 4005 is bonded to a high aspect ratio nanostructure via the bonding auxiliary material 4004 and the collapse-prevention cap 4002.

[0194] Figure 41 is a flowchart of a further alternative method 4100 for bonding cover plates according to one embodiment of the present invention. Figures 42A to 42E depict cross-sectional views for bonding cover plates using the steps described in Figure 41 according to embodiments of the present invention.

[0195] Referring to Figure 41 in conjunction with Figures 42A to 42E, in step 4101, the fin 4201 is etched onto a substrate 4203 having a collapse prevention cap 4202, as shown in Figure 42A.

[0196] In step 4102, material 4204 is filled into the trench (opposite the fin 4201) and then etched back as shown in Figure 42B.

[0197] In step 4103, the collapse prevention cap 4202 is etched back, as shown in Figure 42C.

[0198] In step 4104, the cover plate 4205 is bonded to the fin 4201, as shown in Figure 42D. In one embodiment, the cover plate 4205 is bonded to a high aspect ratio nanostructure, provides material 4204 between the nanostructures (see step 4102), and then the collapse that avoids the cap 4202 is removed (see step 4103).

[0199] In step 4105, substance 4204 is removed as shown in Figure 42E. In one embodiment, substance 4204 is polyvinyl alcohol (PVA) and is removed using water. With respect to other devices such as MEMS, metalenses, and optical devices, the use of collapse-prevention caps can enable ultra-high aspect ratio non-collapsible self-supporting nanostructures for metalenses, MEMS devices, vertically aligned nanowire sensors, nanowires for SERS substrates, etc. In applications where features collapse during the feature release step in MEMS devices, a collapse-prevention material can be provided on the sidewall that comes into contact after the feature collapses to prevent collapse during the feature release step.

[0200] Regarding process integration with CICE, in one embodiment, the catalyst is not removed after CICE. In one embodiment, silicon fins are fabricated by CICE using Ru as the catalyst. The Ru is not removed after CICE, but instead is covered with an insulating material, such as silicon oxide used in the shallow trench isolation (STI) layer within the finFET device, and the process for the finFET continues. In another embodiment, the catalyst is not removed after CICE of a DRAM trench capacitor.

[0201] In the nano-DLD apparatus, silicon nanopillar arrays are fabricated using CICE along with gold as a catalyst—the gold is not removed after CICE. The gold at the bottom of the nanopillar array may be covered with a desired material as needed.

[0202] It is deemed appropriate to discuss the adjustable etching depth CICE process.

[0203] In one embodiment of the adjustable etching depth process described herein, the process involves several steps, as outlined below: The catalyst pattern formation process is completed first (step 1), and this pattern formation can be carried out in several ways, including: (a) Use the catalyst destruction treatment shown in Figures 43, 44A-44C, 45, 46A-46C, 47, 48A-48C, 49, 50A-50D, 51A-51B and 52A-52B.

[0204] (b) A catalytic etching process is used as shown in Figures 53 and 54A-54H.

[0205] (c) Use a catalyst lift-off process as described in the following references. Romano, Lucia, Matias Kagias, Joan Vila-Comamala, Konstantins Jefimovs, Li-Ting Tseng, Vitaliy A. Guzenko, and Marco Stampanoni. “Metal Assisted Chemical Etching of Silicon in the Gas Phase: A Nanofabrication Platform for X-Ray Optics.” Nanoscale Horizons 5, No. 5, incorporated herein by reference in its entirety. 2020, pp. 869-879, and Kim, Jeong Dong, Parsian K Mohseni, Karthik Balasundaram, Srikanth Ranganathan, Jayavel Pachamuthu, James J Coleman, and Xiuling Li. "Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by Macetch: Kinetics of Carrier Generation and Mass Transport." Adv. Funct. Mater., February 1, 2017.

[0206] Next (step 2), the CICE process is either not started immediately, or the CICE process is started to generate partial etchings on the target to achieve a predetermined uniform etching depth.

[0207] Next (step 3), openings in a predetermined pattern are generated in a layer of CICE etchant-resistant material, which is deployed on a patterned CICE catalyst that is either not CICE-etched or partially etched using CICE. The predetermined pattern of openings in the layer of CICE etchant-resistant material can be created by one of the following methods: (a) Spin coating involves applying a photoresist such as a g-line resist, i-line resist, KrF resist, ArF resist, ArF immersion resist, or EUV resist, and then patterning this photoresist using the associated photolithography process.

[0208] (b) An electron beam resist such as polymethyl methacrylate (PMMA) is spin-coated and then patterned using an electron beam lithography process.

[0209] (c) A polymer material such as polymethyl methacrylate (PMMA) or spin-on carbon (SOC) material is spin-coated, and the above-mentioned photoresist or electron beam resist material is used as an image forming layer for etching the PMMA or SOC.

[0210] (d) Vacuum-deposited carbon or aluminum oxide (for example, by using chemical deposition, atomic layer deposition or physical deposition), and then patterning the layer using the photoresist or electron beam resist disclosed above to create a predetermined set of openings in the carbon layer.

[0211] (e) The inkjet regions of the polymer or carbon-based material (such as graphene flakes) or plasmajet polymer or carbon-based material create partially covered regions on the wafer, thereby creating a predetermined set of openings in these CICE etchant-resistant materials.

[0212] Next, an optional step (step 4) may include removing the catalytic material region that was exposed after a predetermined pattern was created in step 3, which includes using a wet etchant on a catalyst such as Au, Ru, Pd, or Pt, as described in International Publication No. 2020 / 176425, which is incorporated entirely herein.

[0213] These predetermined patterns are selected to allow a controlled flow of the etchant material onto the pre-patterned catalyst structure discussed in step 1, and optionally, are partially etched structures discussed in step 2.

[0214] Referring to Figure 43, Figure 43 is a flowchart of Method 4300 for generating metallic fracture in gold using photolithography according to an embodiment of the present invention. Figures 44A to 44C show cross-sectional views of generating metallic fracture in gold using the process described in Figure 43 according to an embodiment of the present invention.

[0215] Referring to Figures 44A to 44C in conjunction with Figure 43, in step 4301, material 4402 is deposited on the substrate 4401 as shown in Figure 44A.

[0216] In step 4302, as shown in Figure 44B, material 4402 is patterned to form pillars.

[0217] In step 4303, the catalyst 4403 is deposited on material 4402 and in the trenches (openings between pillars), as shown in Figure 44C.

[0218] Referring to Figure 45, Figure 45 is a flowchart of Method 4500 for generating metallic fracture in gold using photo / e-beam lithography with a metallic fracture layer, according to an embodiment of the present invention. Figures 46A-46C show cross-sectional views of generating metallic fracture in gold using the process described in Figure 45, according to an embodiment of the present invention.

[0219] Referring to Figure 45 in conjunction with Figures 46A to 46C, in step 4501, material 4601 is deposited on the metal fracture layer 4602 present on the substrate 4603, as shown in Figure 46A.

[0220] In step 4502, as shown in Figure 46B, material 4601 and the metal fracture layer 4602 are patterned to form pillars.

[0221] In step 4503, the catalyst 4604 is deposited on material 4601 and in the trenches (openings between pillars), as shown in Figure 46C.

[0222] Referring to Figure 47, Figure 47 is a flowchart of Method 4700 for generating metallic fracture in gold using nanoimprint lithography having a metallic fracture layer, according to an embodiment of the present invention. Figures 48A to 48C depict cross-sectional views of generating metallic fracture in gold using the process described in Figure 47, according to an embodiment of the present invention.

[0223] Referring to Figure 47 in conjunction with Figures 48A to 48C, in step 4701, material 4801 is deposited on the metal fracture layer 4802 present on the substrate 4803, as shown in Figure 48A. As also shown in Figure 48A, material 4801 is etched in a manner that forms pillars, as shown in Figure 48A.

[0224] In step 4702, as shown in Figure 48B, material 4801 and the metal fracture layer 4802 are patterned to form structure 4804.

[0225] In step 4703, the catalyst 4805 is deposited on structure 4804 and in the openings between structures 4804, as shown in Figure 48C.

[0226] Referring to Figure 49, Figure 49 is a flowchart of an alternative method 4900 for generating metallic fracture in gold using nanoimprint lithography with a metallic fracture layer, according to an embodiment of the present invention. Figures 50A to 50D show cross-sectional views of generating metallic fracture in gold using the process described in Figure 49, according to an embodiment of the present invention.

[0227] Referring to Figure 49 in conjunction with Figures 50A to 50D, in step 4901, material 5001 is deposited on the metal fracture layer 5002 present on the substrate 5003, as shown in Figure 50A. As also shown in Figure 50A, material 5001 is etched in a manner that forms pillars, as shown in Figure 50A.

[0228] In step 4902, as shown in Figure 50B, the material 5001 and the metal fracture layer 5002 are patterned to form a cup-shaped structure 5004.

[0229] In step 4903, material 5001 and the metal fracture layer 5002 are etched to form structure 5005, as shown in Figure 50C. In one embodiment, a longer etching of the metal fracture layer 5002 is performed, as shown in Figures 51A-51B. Figure 51A illustrates the resulting structure formed according to an embodiment of the present invention, and Figure 51B illustrates an SEM image of the metal fracture layer 5002 after such etching according to an embodiment of the present invention. In one embodiment, an optimized etching of the metal fracture layer 5002 is performed, as shown in Figures 52A-52B. Figure 52A illustrates the resulting structure formed according to an embodiment of the present invention, and Figure 52B illustrates an SEM image of the metal fracture layer 5002 after such etching according to an embodiment of the present invention.

[0230] Returning to Figure 49, and in conjunction with Figures 50A to 50D, in step 4904, the catalyst 5006 is deposited on the structure 5005 and in the openings between the structures 5005, as shown in Figure 50D.

[0231] Referring to FIG. 53, FIG. 53 is a flowchart of a method 5300 for patterning and MACE using ruthenium according to an embodiment of the present invention. FIGS. 54A-54H show cross-sectional views for patterning and MACE using ruthenium using the steps described in FIG. 53 according to an embodiment of the present invention.

[0232] Referring to FIG. 53 in conjunction with FIGS. 54A-54H, in step 5301, Ru 5401 is deposited on a substrate 5401 (e.g., a silicon substrate) as shown in FIGS. 54A-54B.

[0233] In step 5302, a material 5403 is vapor-deposited on Ru 5401 and patterned by imprint lithography or the like to form a structure as shown in FIG. 54C.

[0234] In step 5303, a residual layer etching (descum) of the material 5403 is performed to form pillars as shown in FIG. 54D.

[0235] In step 5304, Ru 5401 is etched in the manner shown in FIG. 54E, where the Ru 5401 located at the openings between the pillars of the material 5403 is etched.

[0236] In step 5305, the material 5403 (e.g., resist) is removed as shown in FIG. 54F.

[0237] In step 5306, the structure of FIG. 54F is immersed in a MACE solution, resulting in a structure as shown in FIG. 54G.

[0238] In step 5307, Ru 5401 is removed, and a structure as shown in FIG. 54H is obtained.

[0239] Figures 55A to 55C show exemplary apparatus having a region of varying fin height according to embodiments of the present invention. In one embodiment (Figure 55A), the catalyst film 5501 is continuous across the transition zone 5503 of bulk silicon 5502. In another embodiment (Figure 55B), the catalyst film 5501 is not present near the transition zone 5503. This effectively creates a mousse across various height regions. In another embodiment (Figure 55C), the catalyst film 5501 is patterned near the transition zone 5503 in the form of an expandable structure such as a meandering pattern 5504. In such a structure (meandering pattern 5504), deformation is reduced near the transition zone 5503.

[0240] In one embodiment, Figure 55D shows the width (W) and height (H) of various height regions of the fins in Figures 55A-55C according to an embodiment of the present invention. In one embodiment, both the width (W) and height (H) of the varying height regions of the fins are sub-100 μm. In one embodiment, the above process is used to etch region A adjacent to region B, where region B contains all features larger than 1 micrometer in size. In another embodiment, the above process is used to etch region A adjacent to region B, where region B contains all features larger than 0.5 micrometers in size.

[0241] Synchronizable etching depth control is achieved by one or more of the following control parameters, as discussed in International Publication No. 2020 / 176425, which is incorporated herein by reference. 1. The above-mentioned predetermined pattern, 2. The predetermined CICE etchant component affects the etching speed. 3. A predetermined amount of change in the catalyst composition across the entire wafer. 4. Global temperature and local temperature of the substrate. 5. The global and local electric fields applied to the substrate are used to detect the etching level, which is achieved in real time or offline, using local and global optical measurement signals as needed.

[0242] The application of adjustable etching depth structures includes, but is not limited to, variable etching depth nanostructures necessary to achieve cascading micro and nanofluidic devices such as micro and nanoDLD devices; variable etching height fins in transistor structures having different regions of integrated circuits with fins of different heights; and nanosheets, thereby having different regions of integrated circuits with different numbers of individual nanosheets, while also including variable etching height.

[0243] High aspect ratio rectangular silicon fins fabricated by plasma etching are used in transistor fabrication. Due to the properties of plasma etching, the fin sidewalls are tapered to form a trapezoidal prism structure, as opposed to a rectangular parallelepiped. This taper limits the ability to reduce the fin width and fin pitch while maintaining or increasing the fin height. For example, a FinFET with a "14nm" technology node has a taper angle of ~85°, and a physical half-pitch (HP) of 24nm and a pitch of 48nm. Using this ratio of technology node and physical half-pitch, the maximum possible fin heights for different taper angles are plotted in Figure 56. Here, the critical height is calculated by maximum fin height = 0.5 * HP * tan(taper angle). A fin height of 100nm is used for shallow trench isolation (STI) and is not part of the active finFET. Figure 56 is a graph showing the effect of etching taper angle on the maximum fin etching height according to embodiments of the present invention.

[0244] Figure 56 illustrates the effect of the etching taper angle on the maximum achievable fin height for different technical nodes according to embodiments of the present invention. As shown in Figure 56, the etching taper (90° taper angle) does not allow for fins of any arbitrary height.

[0245] Furthermore, Figure 56 shows the scaling potential of vertical non-tapered etching (e.g., MACE) to increase the aspect ratio of the fins. The fabrication of rectangular fins using CMOS-compatible Ru MACE and the method for managing the collapse of ultra-high aspect ratio fins are described below.

[0246] The optimized CMOS-compatible Ru minimesh MACE can be extended to application-specific geometries such as rectangular nanofins for pillars with a rectangular cross-section, in which case results similar to those obtained for circular nanopillars, minimesh, and catalytic plasma modification are required to achieve the desired nonporous silicon etching by Ru MACE. As shown in Figures 57A-57B, the effect of Ru surface coverage is significant. Figures 57A-57B show the effect of minimesh spatial density on Ru MACE etching quality for Ar / CF4 descam and 20S MacEtch with 12.5M HF and 1M H2O2 according to embodiments of the present invention.

[0247] Figure 57A shows a spatial density of 0.192, and Figure 57B shows a spatial density of 0.264. A typical Ru pattern has a spatial density of 1, meaning the entire silicon surface is covered with patterned Ru.

[0248] In Ru MACE on samples treated with Ar / CF4 Descam, increasing the Ru surface coverage (or minimesh spatial density) leads to porosity of etched features. Standard Ru MACE without minimesh has a surface coverage of 1; that is, the entire silicon wafer is covered with patterned Ru—these samples exhibit porous silicon after etching. Minimesh with a spatial density of 0.192 (diameter of 256 μm and pitch of 585 μm) exhibits high aspect ratio nanostructure etching, while one with a spatial density of 0.264 (diameter of 256 μm and pitch of 507 μm) exhibits porous silicon. The pitch is varied by changing the inkjet drop pattern during jet and flash imprint lithography.

[0249] The effect of fin shape on Ru MACE etching rate was determined by etching regular arrays of silicon fins with different rectangular cross-sections. As shown in Figures 58A-58D, a high level of etching uniformity was obtained across the fin shapes.

[0250] Figures 58A–58D show ruthenium MACE for fabricating silicon rectangular pillar arrays with different geometric shapes according to embodiments of the present invention. All samples were etched using optimized Ru MACE (Ar / CF4 descam and 20s MacEtch with 12.5M HF and 1M H2O2). All scale bars are 1 μm long.

[0251] Ru MACE enables ultra-high aspect ratio fins for transistors, but its main limitation to scaling to smaller fin widths is its structural instability. In FinFETs made from bulk silicon, the main portion of its length is used for shallow trench isolation (STI). Assuming a minimum height of 100 nm required for STI, only fins with a width of 10 nm or more can be used. Furthermore, the active site of the fin is much shorter than the initial fin height. Figure 59 shows the maximum achievable fin height for a given half-pitch, along with structural parameters for a rectangular fin, using the lateral collapse type described by Glassmaker et al. This is calculated by equating the bending energy of the fin due to collapse with the surface energy required to isolate the fin.

[0252]

number

[0253] Here, E is the elastic modulus of the fin, I is the moment of inertia about the bending axis, w is the deflection of the fin, i.e., half the distance between the deformed fins, and γ svis the surface energy of the fin material, and a and b are the lengths of the fins perpendicular to the collapsing direction. In the nanosheet layer containing Si and SiGe, the new critical height depends on the modified elastic modulus of the multilayer stacked fins. Considering that the thickness of each nanosheet is 5 nm and the lower region of the fin covered by STI is Si, the new elastic modulus can be calculated by the "slab" model using the inverse rule of the mixture in the composite material patent literature. When the volume fraction of Si is ~75% - 95%, the resulting effective elastic coefficient is ~100 - 150 GPa, and the critical height for the nanosheet fins is the same as that of the finFET fins.

[0254] Referring to FIG. 59, graph 5900 illustrates the maximum height of a fin without a taper before lateral collapse along the length of the fin (in this case 50 nm) as a function of the half-pitch (or fin width) of the fin according to an embodiment of the present invention.

[0255] In one embodiment, a method of improving the structural stability of the fin beyond the height includes (1) the use of repelling the "cap", and (2) the use of a stabilizing structure to avoid the collapse of the fin.

[0256] Another process flow for fin manufacturing to avoid collapse is by using a connecting link between fins to stabilize the fins during etching, as described by Chang and Sakdinawat. After further processing of the device including the adhesion of substances between the fins, the stabilizing structure can be removed. For example, fins connected at both ends create a non-collapsing rectangular hole. However, the MACE of the hole requires isolated catalytic features that tend to sway and cause defects during MACE, as described in the next section.

[0257] Metal catalysts isolated during MACE result in undesirable etching pathways that are not longitudinal. Discrete catalyst features tend to wobble during the MACE process, leading to defects. Hildreth et al. utilized this property to create a 3D spiral microscale structure using gold as a catalyst and calculated the effects of catalyst stiffness and geometric constraints on its motion. MACE of rectangular holes with isolated rectangular catalysts wobbles due to van der Waals forces on the catalyst, as well as stochastic changes in force resulting from changes in local etchant concentration or etch rate. Figures 60A–60D show the effects of catalyst material and geometry on catalyst wandering behavior, with lower wandering and larger catalyst size compared to ruthenium compared to gold catalyst material, according to embodiments of the present invention. As shown below, catalyst wandering with gold is greater than with ruthenium, which is likely due to the lower bending and torsional stiffness of Au.

[0258] [Table 1]

[0259] As shown in Figures 60A–60D, wandering of isolated catalyst structures causes insufficient MACE of holes. Catalyst wandering can be reduced by changing the etchant concentration and optimizing the formulation, but it increases as the size of the etched holes decreases. Kim et al. demonstrate etching of holes with diameters of 200nm–400nm with Au MACE, but observe etching stall and low etching rates for smaller geometric shapes of 100nm.

[0260] Referring to Figures 60A to 60D, Figures 60A to 60D show the effects of catalyst material and geometric shape on hole wandering during MACE. Figures 60A to 60B show the MACE of Au and Ru in rectangular pores. Figures 60C to 60D show the effect of catalyst geometry on wandering for Ru MACE in rectangular pores.

[0261] For CMOS applications such as ultra-high aspect ratio DRAM capacitors, typical cell sizes are <50nm. Here we present another approach to creating deep holes for DRAM. It combines lithography with atomic precision overlays, vertical etching of MACE, and atomic layer deposition. Following the fabrication of fins with a defined DRAM cell-like shape, ALD is performed to fill the desired gap, thereby enabling the deep holes.

[0262] Figures 61A-61C show high aspect ratio holes for DRAM deep trench capacitors using MACE+ALD according to embodiments of the present invention. Figures 61A-61B show scanning electron microscope images illustrating the DRAM cell design and capacitor placement. Figure 61C shows the MACE+ALD process flow illustrating the fin shape fabricated by MACE and the high aspect ratio holes fabricated by filling the designed gaps with ALD.

[0263] The MACE+ALD methodology, which manufactures fins with precise shapes and arrangements, can, when combined with conformal material deposition, enable new design rules for 3D device designs with arbitrary shapes. Furthermore, design specifications do not need to be constrained to the regular periodic shapes shown above. For example, a typical transistor architecture has fins of numerous dimensions and / or spacings determined by the desired circuit design. Arbitrary changing geometric patterns with rectangular fins were etched, and the etch uniformity and independence of etch rate from aspect ratio for Ru MACE were confirmed. Figures 62A-62D confirm the etching uniformity for fin-like geometry beyond regular arrays for Ru MACE, thereby providing a degree of freedom in MACE geometric design for applications in logic, memory, optical, and photonic devices.

[0264] Figures 62A–62D show ruthenium MACE for the fabrication of silicon rectangular pillars with different geometrically inclined cross-sectional scanning electron microscopes and top-down scanning electron microscopes at different magnifications, according to embodiments of the present invention. All scale bars are 1 μm long.

[0265] The porosity of the features after optimized etching was characterized using TEM and EDS mapping, and as shown in Figures 63A–63H, the upper part of the features shows sidewall porosity of ~15 nm thickness, while the lower part of the features shows no porosity. HRTEM and EDS indicate that the porous silicon at the top of the features is oxidized, with the oxidized porous silicon being amorphous, while the remainder of the silicon fins is crystalline. This porosity is likely due to the diffusion of holes from the Ru / Si interface to the top and sidewalls of the nanofins, as well as prolonged exposure of the fin tops in the etching solution.

[0266] Figures 63A-63H show high-resolution TEM and EDS mappings of silicon fins according to embodiments of the present invention. Figure 63A shows the TEM mapping of the silicon fin. Figure 63B shows the EDS mapping of the silicon fin along its length. The upper portion of the fin, shown by (Figure 63C) cross-sectional SEM, (Figure 63D) HRTEM, and (Figure 63E) EDS mapping, shows a sidewall porosity of ~15 nm and oxidation (X), in contrast to the rest of the silicon fin (Y). The bottom portion of the fin, shown by (Figure 63F) cross-sectional SEM, (Figure 63G) HRTEM, and (Figure 63H) EDS mapping, shows the Ru catalyst and etch front. The etch front (P) shows amorphous silicon, and the surrounding silicon (Q) is crystalline.

[0267] The image also shows the MACE front beneath the Ru catalyst at the bottom of the fin—amorphous Si is observed locally at the etch front beneath the silicon. Note that the amorphous silicon is not oxidized, thereby suggesting that the mechanism of the anodic Si dissolution reaction proceeds by direct dissolution of silicon, as opposed to dissolution following silicon oxide formation. Unlike other studies on TEM of MACE porous Si nanowires, no crystalline structure clusters are observed in HR-TEM, so the silicon beneath the etch front is amorphous, in contrast to the porous Si.

[0268] Transistor and memory architectures with ultra-high aspect ratio nanostructures can be fabricated using CMOS-compatible MACE in this way. In one embodiment, silicon fins are used for FinFETs, while fins made of alternating Si / SiGe are used for nanosheet FETs and complementary FETs. Tapered fins for nanosheet FETs and CFETs are created by plasma etching of Si / SiGe layers deposited using epitaxial growth. MACE can create fins without etch taper, and MACE of SiGe and Si / Ge superlattices has been demonstrated in the literature for sub-20 nm nanowires. Alternatively, such superlattices can be fabricated from bulk silicon by utilizing morphological control during MACE. The morphology of silicon nanostructures includes arbitrary changes in pore size diameter, pore orientation, and porosity along the length of the nanostructure. MACE can be used to control the porosity when a catalyst is etched into silicon by utilizing the electrochemical properties of etching. Silicon superlattice etching involves etching silicon with a catalyst while simultaneously creating a superlattice with alternating layers in which one of the layers is porous. Similar to the selective removal of the SiGe layer in Si / SiGe superlattice fins during nanosheet FET fabrication, the porous silicon layer can be selectively removed in non-porous Si / porous Si superlattice fins fabricated by MACE.

[0269] Alternating layers can be formed by electric field parameter modulation, etching through layers with alternating doping characteristics, or by alternating MACE etchant concentrations. High current density, high doping concentration, and high oxidant-to-HF ratio increase silicon porosity, respectively. Weisse et al. and Chiappini et al. demonstrated alternating porous Si superlattice nanostructures using electric field and etchant concentration modulation. However, the electric field does not produce non-porous layers, resulting in superlattices with alternating porosity layers. Alternating etchant concentrations can produce non-porous / porous layers, but it is a time-limited etching process requiring a constant change in etchant, reducing yield and processing capacity.

[0270] The study demonstrated the effect of silicon substrate doping concentration on the resulting porosity after MACE. Highly doped wafers produced highly porous silicon, while low-doped wafers produced non-porous silicon nanostructures. Multilayers with various doping concentrations separated by a Ge barrier layer also exhibited doping level-dependent porosity. While a Ge barrier layer is used to prevent dopant diffusion, gas switching occurs during epitaxial growth of the film, increasing deposition costs and reducing throughput. This section builds upon previous literature and demonstrates a process for fabricating porous silicon superlattices with sharp non-porous / porous silicon interfaces in the nanostructure without using barrier layers between different doped films.

[0271] MACE can etch into silicon while simultaneously changing its morphology, depending on tunable material properties such as doping concentration and dopant type of deposited alternating layers. The method used for depositing alternating layers or "superlattices" depends on commercial availability, cost, throughput, growth rate, thermal budget, number of layers, and layer thickness. Polycrystalline silicon layers can also be used, but they do not have reliable vertical MACE due to grain boundaries and tend to reduce the size of the structures etched. Epitaxial (epi) growth of silicon uses chemical vapor deposition (CVD) to produce crystalline silicon films, which is a process in which a thin solid film is synthesized from a gaseous phase by chemical reactions.

[0272] Temperature, pressure, gas flow rate, substrate preparation, surface treatment, and oxidation prevention are the main parameters that determine the quality and crystallinity of the epitaxial superlattice. The partial pressure of the gas used for doping, such as B2H6 or PH3, determines the doping concentration within the epilayer. Lower total pressure during growth reduces contamination from the gas of the previous layer, resulting in better bonding, but this is not a problem when growing alternating epitaxial silicon films with the same doping type but different doping concentrations.

[0273] When alternating epitaxial layers with high and low doping concentrations are deposited with a thickness of submicrons per layer, the concentration gradient across the interface between the two layers becomes shallow due to the limitation of the deposition process at high deposition rates, as well as the diffusion of dopants across the interface. This results in a non-abrupt change in doping across the stack thickness, such as a shallow gradient across the interface. Epitaxial layers of silicon doped with different concentrations are shown in Figures 64A-64B, generating porous / non-porous layers of silicon nanostructures, where the porous layer is 1E18cm -3 As a result, the non-porous layer is obtained from highly B-doped epitaxial silicon with doping, 1E15cm -3 The results are from B doping. Epitaxial silicon wafers are obtained from Lawrence Semiconductor Research Labs (LSRL).

[0274] Figures 64A-64B show silicon superlattice etching with alternating doping concentrations of epitaxial Si layers according to embodiments of the present invention. Figure 64A illustrates the doping concentration profile of a custom epitaxial wafer from Lawrence Semiconductor Laboratory (LSRL) having a P++ / P-doped alternating epitaxial silicon layer, showing high doping (~1E18cm). -3 ) and low doping (~1E15cm) -3 This shows a shallow (>100 nm thick) transition between ). Figure 64B illustrates a cross-sectional SEM of the porous / non-porous interface fabricated by MACE of differently doped epitaxial silicon layers.

[0275] In multilayer epitaxial layer MACE, etching is tuned to ensure that the morphology changes from porous to nonporous at specific doping concentrations, thereby transforming a shallow doping concentration gradient into a steep step function at the porous / nonporous interface. As MACE proceeds through the epitaxial layer, a catalytic mesh etches the silicon stack to reveal high aspect ratio nanostructures with tuned porosity.

[0276] Therefore, MACE can enable the fabrication of not only nanostructures with porous silicon superlattices but also ultra-high aspect ratio silicon nanostructures. Methods for preventing process excursions such as nanostructure collapse due to isolated catalyst features and catalyst wandering, as well as nanostructure design, were described. These methods can be incorporated into application-specific design algorithms to create MACE-based designs for manufacturing frameworks.

[0277] An example integration scheme for a finFET is shown in Figures 65A-65B, where linked fins are etched with MACE to prevent fin collapse and catalyst wandering, thereby providing a new direction for transistor design with ultra-high aspect ratio fins.

[0278] Figure 65A is a schematic diagram of a conventional finFET fabrication flow showing the essential process according to one embodiment of the present invention. Figure 65B is a modified finFET process flow according to an embodiment of the present invention, in which linked fins are formed to enable collapse-free ultra-high aspect ratio fins. Steps (4-5) are added to the conventional finFET flow to remove the fin links.

[0279] As a result of the foregoing, the principles of the present invention provide means for utilizing the CICE process to effectively produce features in semiconductors using the apparatus and process technology for catalyst-induced chemical etching of the present invention.

[0280] The descriptions of various embodiments of the present invention are presented for illustrative purposes only and are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications or technical improvements to the technology available on the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A system for etching a semiconductor substrate using catalytic chemical etching, The system comprises a group of independently controlled, separate actuators configured to control the etching depth of the material on the substrate, At least two of the groups of the independently controlled individual actuators have different operating values, A real-time measurement system configured to measure local etching parameters across the entire substrate, A feedback-based system configured to control spatial fluctuations of the etching rate by adjusting the operating values ​​of the individual actuators using the local etching parameters measured by the real-time measurement system, Furthermore, The variation in etching depth is less than 10% of the feature height across the entire substrate. system.

2. To reduce variations in etching height, the etching rate is reduced before the reaction is stopped. The system according to claim 1.

3. The spatial changes in etching rate are monitored in real time. The system according to claim 1.

4. The spatial variation of the etching rate is monitored in situ. The system according to claim 3.

5. The spectral signature corresponding to the feature height is used as the surrogate. The system according to claim 4.

6. The aforementioned on-site monitoring is achieved using spectrophotometric measurement of the process wafer. The system according to claim 3.

7. Feedback-based systems are used to control process variations. The system according to claim 1.

8. A feedforward approach is used to suppress process variability. The system according to claim 1.

9. A hybrid approach is used to control process variations. The system according to claim 1.

10. The etchant used to etch the aforementioned material is in vapor form. The system according to claim 1.

11. The individual actuators include thermal actuators. The system according to claim 1.

12. The substrate has a type A device pattern next to a type B device pattern. The system according to claim 1.

13. The aforementioned Type B pattern does not include patterns smaller than 0.5 micrometers in size. The system according to claim 12.

14. A method for etching semiconductor materials using catalyst-affected chemical etching (CICE), The invention provides a semiconductor material and one or more layers of other materials on the semiconductor material, wherein the catalyst layer is one of the one or more layers of other materials. A process for modifying the catalytic activity of the catalyst layer involves exposing one or more of the other materials to one or more of the other materials, wherein the process is varied throughout the catalyst layer and generates programmable porosity and / or etching depth in selected regions of the semiconductor material. Exposing one or more layers of the other material containing the modified catalytic layer having catalytic activity and the semiconductor material to a CICE etchant, A method that includes this.

15. The catalyst layer is one or more alloys of Ru, Au, Pt, Pd, Ag, Cu, Ni, W, TiN, graphene, carbon, and Cr. The method according to claim 14.

16. The catalytic activity of the catalyst layer is modified by exposing the catalyst to plasma. The method according to claim 14.

Images