Source-drain formation in gate-all-around transistors

Abstract

A semiconductor device and a method for its manufacture are described. The method includes forming a bottom dielectric insulation (BDI) layer on a substrate and depositing a template material in source / drain trenches. The template material is etched and then crystallized. Epitaxial growth of source and drain regions then proceeds, advantageously on the bottom and sidewalls of the source and drain regions.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments of the present disclosure are directed to gate-all-around (GAA) devices having a continuous sidewall silicon template.

Background Art

[0002]

[0002] Transistors are an important component of most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, faster transistors generally require a larger gate width. Therefore, there is a trade-off between the size and speed of a transistor, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that significantly increases the transistor size without significantly increasing the installation area of the transistor, and are currently applied to many integrated circuits. However, finFETs also have drawbacks.

[0003]

[0003] As the feature size of transistor devices continues to shrink to achieve improved circuit density and high performance, it is necessary to improve the transistor device structure to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, horizontal gate-all-around (hGAA) structures, and the like. The hGAA device structure includes a plurality of lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure provides good electrostatic control and can be widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0004]

[0004] The presence of a bottom dielectric insulating layer is becoming a key layer for improving the performance of nanosheet devices. However, when a bottom insulating dielectric (BDI) layer is present beneath the source / drain, the epitaxial source / drain can only grow from the sidewalls and not from the bottom, resulting in numerous defects during the growth / formation of the source and drain regions. Therefore, improved methods are needed for forming gate-all-around devices. [Overview of the project]

[0005]

[0005] One or more embodiments of the present disclosure relate to methods for forming semiconductor devices. In one or more embodiments, a method for forming a semiconductor device includes forming a superlattice structure on the upper surface of a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately so as to form a plurality of stacked pairs; patterning the superlattice structure to form a plurality of nanosheets separated by trenches; forming shallow trench isolation (STI) layers in the trenches; forming dummy gates adjacent to the superlattice structure and on the STI layers; depositing spacer layers on the dummy gates; forming source trenches and drain trenches adjacent to the superlattice structure; forming bottom dielectric isolation layers in the source trenches and drain trenches; forming inner spacers on each of the plurality of semiconductor material layers; recessing the inner spacers to form recessed regions; depositing amorphous layers in the recessed regions, on the superlattice structure and on the dummy gates; etching the amorphous layers to expose the plurality of horizontal channel layers; crystallizing the amorphous layers; and forming source and drain regions.

[0006]

[0006] Additional embodiments of the present disclosure relate to methods for forming semiconductor devices. In one or more embodiments, a method for forming a semiconductor device includes forming source trenches and drain trenches adjacent to a superlattice structure of a gate structure, the source trenches and drain trenches comprising a plurality of semiconductor material layers corresponding to a plurality of horizontal channel layers arranged alternately such that the superlattice structure forms a plurality of stacked pairs on the upper surface of a substrate; forming bottom dielectric insulating layers within the source trenches and drain trenches; forming inner spacers on each of the plurality of semiconductor material layers; recessing the inner spacers to form recessed regions; depositing template material within the recessed regions, on the superlattice structure, and on the gate structure; crystallizing the template material; and forming source and drain regions.

[0007]

[0007] To enable a more detailed understanding of the features of the present disclosure described above, a more specific description of the present disclosure, which has been briefly summarized above, can be obtained by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered to limit the scope of the present disclosure, as the present disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] A process flow diagram of a method according to one or more embodiments is shown. [Figure 2A]

[0009] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2B]

[0010] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2C]

[0011] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2D]

[0012] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2E]

[0013] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2F]

[0014] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2G]

[0015] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2H]

[0016] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2I]

[0017] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2J]

[0018] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2K]

[0019] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2L]

[0020] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2M]

[0021] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 2N]

[0022] A cross-sectional view of a device according to one or more embodiments is shown. [Figure 3]

[0023] This document describes a cluster tool in one or more embodiments. [Modes for carrying out the invention]

[0009]

[0024] For ease of understanding, the same reference numerals have been used to indicate identical elements common to the figures where possible. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be incorporated into other embodiments without further description.

[0010]

[0025] Before describing some exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure is capable of other embodiments and can be implemented or executed in various ways.

[0011]

[0026] As used herein and in the appended claims, the term "substrate" refers to a surface or a portion of a surface on which processing acts. It will also be understood by those skilled in the art that a reference to a substrate may, in some cases, refer only to a portion of the substrate, unless the context clearly indicates otherwise. Further, a reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features have been deposited or formed on the surface.

[0012]

[0027] As used herein, the term "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. The substrate includes, but is not limited to, semiconductor wafers. The substrate can be exposed to a pre-treatment process for polishing, etching, reducing, oxidizing, hydroxylating (or otherwise generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps can also be performed in an underlying layer formed on the substrate, as will be disclosed in more detail below. And the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface includes depends on what films are deposited and the specific chemistry used.

[0013]

[0028] Terms such as "precursor", "reactant", "reactive gas", etc. used in this specification and the appended claims are used interchangeably and refer to any gas species that can react with the substrate surface.

[0014]

[0029] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located on the channel region and includes a gate dielectric interposed between the gate electrode in the substrate and the channel region.

[0015]

[0030] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. Conductivity between the drain and source terminals is controlled by an electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G) which regulates the conductivity of the channel. Traditionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and source is denoted as VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0016]

[0031] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the insulated gate determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0017]

[0032] If a MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, and the body is in the p region. If a MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the body is in the n region. The source is the source of charge carriers (electrons in the case of an n-channel, holes in the case of a p-channel) flowing through the channel, and similarly, the drain is named as such because it is where the charge carriers exit the channel.

[0018]

[0033] As used herein, the term "Fin-field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which the gate is located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the general name FinFET because the channel region forms "fins" on the substrate. FinFET devices have fast switching times and high current density.

[0019]

[0034] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0020]

[0035] As used herein, the term "nanowire" means 1 nanometer (10⁻¹⁰ -9 This refers to nanostructures having a diameter of approximately 1000 nanometers. Nanowires can also be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures whose thickness or diameter is limited to tens of nanometers or less, and whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. In this specification, the term “nanosheet” refers to two-dimensional nanostructures having a thickness ranging from about 0.1 nm to about 1000 nm.

[0021]

[0036] Embodiments of the present disclosure are illustrated by diagrams showing devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible applications of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0022]

[0037] One or more embodiments of this disclosure will be described with reference to the figures. In one or more embodiments, a gate-all-around transistor having a bottom isolation (BDI) layer is manufactured using a standard process flow. After the bottom dielectric isolation (BDI) layer is formed, an internal spacer is etched laterally, an amorphous template material is deposited, and the template material is then etched and crystallized to form the source / drain. The crystallized template material allows epitaxial growth not only on the sidewalls but also on the bottom surface of the source / drain trenches. In one or more embodiments, by implementing a continuous sidewall amorphous silicon template, the bottom silicon template is advantageously eliminated. Thus, the BDI can be used to provide isolation between devices and eliminate the need for high subfin doping. In this way, the present method does not reduce channel mobility due to Coulomb scattering, nor does it reduce variability due to random dopant distribution (RDD).

[0023]

[0038] In some embodiments, the amorphous template material is deposited on the bottom surface of the source / drain trench and on one or more of the side walls of the source / drain trench. In some embodiments, the amorphous template material is deposited conformally. Herein, the term “conformal” means that the layer conforms to the contour of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the side wall of a feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate. In one or more embodiments, the amorphous template material is crystallized by rapid heat treatment (RTP) or laser annealing. Forming the source and drain regions involves growing epitaxial layers.

[0024]

[0039] Figure 1 shows a process flow diagram for Method 10 for forming a semiconductor device according to some embodiments of the present disclosure. Figures 2A to 2N show the manufacturing steps of a semiconductor structure according to some embodiments of the present disclosure. With respect to Figures 2A to 2N, Method 10 is described below. Figures 2A to 2N are cross-sectional views of an electronic device (e.g., GAA) according to one or more embodiments. Method 10 may be part of a multi-step manufacturing process for a semiconductor device. Thus, Method 10 may be performed in any suitable process chamber connected to a cluster tool. The cluster tool may include process chambers for manufacturing a semiconductor device, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used for manufacturing a semiconductor device.

[0025]

[0040] Figures 2A to 2N show the manufacturing steps 12 to 36 of Figure 1. Referring to Figure 1, the method 10 for forming device 100 begins in step 12 by providing a substrate 102. In some embodiments, the substrate 102 may be a bulk semiconductor substrate. In this specification, the term “bulk semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 102 includes a semiconductor material, for example, silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 102 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described, the spirit and scope of this disclosure include any material that can function as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices).

[0026]

[0041] In some embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. Herein, the term “n-type” refers to a semiconductor made by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term “n-type” derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. Herein, the term “p-type” refers to the positive charge (or hole) of a well. In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0027]

[0042] Referring to Figures 1 and 2A, in one or more embodiments, in step 14, at least one superlattice structure 101 is formed on the upper surface of the substrate 102. The superlattice structure 101 includes a plurality of semiconductor material layers 106 and a corresponding plurality of horizontal channel layers 104, which are arranged alternately to form a plurality of stacked pairs. In some embodiments, the plurality of stacked groups include silicon (Si) and silicon germanium (SiGe) groups. In some embodiments, the plurality of semiconductor material layers 106 include silicon germanium (SiGe) and the plurality of horizontal channel layers 104 include silicon (Si). In other embodiments, the plurality of horizontal channel layers 104 include silicon germanium (SiGe) and the plurality of semiconductor material layers 106 include silicon (Si).

[0028]

[0043] In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 may include any number of pairs of lattice-matched materials suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 106 and the corresponding plurality of horizontal channel layers 104 include about 2 to about 50 pairs of lattice-matched materials.

[0029]

[0044] In one or more embodiments, the thicknesses of the multiple semiconductor material layers 106 and the multiple horizontal channel layers 104 are in the range of approximately 2 nm to approximately 50 nm, approximately 3 nm to approximately 20 nm, or approximately 2 nm to approximately 15 nm.

[0030]

[0001] Referring to Figures 1 and 2B, in one or more embodiments, in step 16, the superlattice structure 101 is patterned to form openings 108 between adjacent stacks 105. Patterning can be performed by any suitable means known to those skilled in the art. Where used in this regard, the term “opening” means any intentional surface irregularity. Suitable examples of openings include, but are not limited to, trenches having a top, two side walls and a bottom. Openings can have any suitable aspect ratio (ratio of feature width to feature depth). In some embodiments, the aspect ratio is about 5:1, about 10:1, about 15:1, about 20:1, about 25:1, about 30:1, about 35:1 or about 40:1 or more.

[0031]

[0045] Referring to Figures 1 and 2C, in step 18, a shallow trench isolation (STI) 110 is formed. In this specification, the term “shallow trench isolation (STI)” refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, the STI is created by depositing one or more dielectric materials (such as silicon dioxide) to fill a trench or opening 108 and then removing the excess dielectric using a technique such as chemimetric planarization.

[0032]

[0046] Referring to Figures 1 and 2D, in some embodiments, a replacement gate structure 113 (e.g., a dummy gate structure) is formed on and adjacent to the superlattice structure 101. The dummy gate structure 113 defines the channel region of the transistor device. The dummy gate structure 113 can be formed using any suitable conventional deposition and patterning process known in the art.

[0033]

[0047] In one or more embodiments, the dummy gate structure includes one or more of the gate 114 and the polysilicon layer 112. In one or more embodiments, the dummy gate structure includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-doped polysilicon.

[0034]

[0048] Referring to Figures 1 and 2E, in some embodiments, in step 22, a sidewall 116 is formed along the outer sidewall of the dummy gate structure 113 on the superlattice 101. The sidewall spacer 116 may include any suitable insulating material known in the art, such as silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide. In some embodiments, the sidewall spacer is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or isotropic deposition.

[0035]

[0049] Referring to Figure 2F, the spacer 116 is etched away to expose the superlattice structure 101. The channel region 108 separates the superlattice structure 101 from adjacent superlattice structures 101. The spacer 116 can be removed from the superlattice structure 101 by any suitable means known to those skilled in the art.

[0036]

[0050] Referring to Figures 1 and 2G, in step 24, in one or more embodiments, source / drain trenches 118 are formed adjacent to (i.e., on both sides of) the superlattice structure 101.

[0037]

[0051] Referring to Figures 1 and 2H, in step 26, in one or more embodiments, a bottom dielectric insulation (BDI) layer 120 may be formed on the substrate 102. The bottom dielectric insulation (BDI) layer 120 may include any suitable material known to those skilled in the art. In one or more embodiments, the bottom dielectric insulation (BDI) layer 120 includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), or high dielectric constant materials. In some embodiments, the high dielectric constant material is selected from one or more such as aluminum oxide (Al2O3) and hafnium oxide (HfO2). In one or more specific embodiments, the bottom dielectric insulation (BDI) layer 120 includes silicon oxide.

[0038]

[0052] In some embodiments, the bottom dielectric insulating (BDI) layer 120 is deposited on the substrate 102 using conventional chemical vapor deposition. In some embodiments, the bottom dielectric insulating (BDI) layer 120 is recessed below the top surface of the substrate 102 so that the bottom of the superlattice structure 101 is formed from the substrate 102.

[0039]

[0053] Referring to Figures 1 and 2I, in step 28, an inner spacer layer 122 is formed on each of the horizontal channel layers 104. The inner spacer layer 122 may include any suitable material known to those skilled in the art. In one or more embodiments, the inner spacer layer 122 includes a nitride material. In a specific embodiment, the inner spacer layer 122 includes silicon nitride.

[0040]

[0054] As shown in Figure 2J, in step 28, the inner spacer layer 122 is recessed to form a recessed region 124. In one or more embodiments, when the inner spacer layer 122 is recessed, the semiconductor material layer 106 extends beyond the inner spacer layer 122.

[0041]

[0055] Referring to Figures 2K and 1, in step 30, the amorphous template material 126 is deposited within the channel region 108, on the bottom surface of the source / drain trench 118, and above the dummy gate structure 113. The amorphous template material 126 may include any suitable material known to those skilled in the art. In some embodiments, the amorphous template material 126 is amorphous. In one or more embodiments, the amorphous template material 126 is silicon (Si), germanium (Ge), and Silicon germanium (SiGe )of Includes one or more of these. In other embodiments, the amorphous template material includes silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).

[0042]

[0056] The amorphous template material 126 can be deposited using any suitable conventional deposition process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0043]

[0057] In one or more embodiments, the thickness of the amorphous template material 126 is in the range of about 2 nm to about 50 nm, about 3 nm to about 20 nm, or about 2 nm to about 15 nm.

[0044]

[0058] In some embodiments, the amorphous template material 126 may be deposited within the channel region 108, on the bottom surface of the source / drain trench 118 and on the side walls of the superlattice structure 101.

[0045]

[0059] As shown in Figure 2L, in step 32, the amorphous template material 126 is removed, exposing the spacer 116 and the semiconductor material layer 106. The amorphous template material 126 can be removed using any suitable means known to those skilled in the art. In one or more embodiments, the amorphous template material 126 is removed by directional etching. In one or more embodiments, the amorphous template material 126 remains on the inner spacer layer 122.

[0046]

[0060] The etching process in step 32 may include any suitable etching process that is selective for the spacer material 116. In some embodiments, the etching process in step 32 includes one or more wet etching processes or dry etching processes.

[0047]

[0061] In some embodiments, the dry etching process may include conventional plasma etching or remote plasma-assisted dry etching processes such as the SiCoNi® etching process available from Applied Materials, Inc. in Santa Clara, California. In the SiCoNi® etching process, the device is exposed to H2, NF3, and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, the device may undergo simultaneous exposure to H2, NF3, and NH3 plasmas. The SiCoNi® etching process is performed in a SiCoNi® Preclean chamber and can be incorporated into one of various multi-processing platforms, including the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials, Inc. The wet etching process may include a hydrofluoric acid (HF) last process, i.e., a so-called "HF last" process. In this process, HF etching is performed on the surface, leaving the surface hydrogen-terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be used. In some embodiments, the process includes sublimation etching to remove the native oxide film. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conductive-coupled plasma, inductively-coupled plasma, microwave plasma).

[0048]

[0062] Referring to Figures 1 and 2M, in step 34, the amorphous template material 126 is crystallized in order to form the crystalline template material 128.

[0049]

[0063] The amorphous template material 126 can be crystallized by any suitable means known to those skilled in the art. In one or more embodiments, the amorphous template material 126 is crystallized by rapid heat treatment (RTP) or laser annealing.

[0050]

[0064] In some embodiments, rapid heat treatment (RTP) or laser annealing is carried out at temperatures in the range of 500°C to 900°C, 600°C to 900°C, or 600°C to 800°C. In some embodiments, rapid heat treatment (RTP) or laser annealing is carried out at pressures in the range of 5 Torr to 20 Torr. In one or more embodiments, rapid heat treatment or laser annealing is carried out in an atmosphere of atmospheric pressure hydrogen (H2) and oxygen (O2) gases.

[0051]

[0065] Referring to Figures 1 and 2N, in step 36, in some embodiments, the embedded source / drain region 130 is formed within the source / drain trench 118. In some embodiments, the source region 130 is formed adjacent to a first end of the superlattice structure 101, and the drain region 130 is formed adjacent to a second end on the opposite side of the superlattice structure. In some embodiments, the source region and / or drain region 130 are formed from any suitable semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorus (SiP), or silicon arsenic (SiAs). In some embodiments, the source / drain region 130 may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source / drain region 130 is independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0052]

[0066] In some embodiments, an interlayer dielectric (ILD) layer (not shown) is blanket-deposited on a substrate 102 including a source / drain region 130, a dummy gate structure 113, and sidewall spacers 116. The ILD layer may be deposited using conventional chemical vapor deposition methods (e.g., plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition). In one or more embodiments, the ILD layer is formed from, but is not limited to, any suitable dielectric material such as undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. In one or more embodiments, the ILD layer is then polished again using a conventional chemical mechanical planarization method to expose the top surface of the dummy gate structure 113. In some embodiments, the ILD layer is polished to expose the top surface of the dummy gate structure 113 and the top surface of the sidewall spacers 116.

[0053]

[0067] The dummy gate structure 101 may be removed to expose the channel region 108 of the superlattice structure 101. The ILD layer protects the source / drain region 130 while the dummy gate structure 113 is removed. The dummy gate structure 113 may be removed using conventional etching methods such as plasma dry etching or wet etching. In some embodiments, the dummy gate structure 113 contains polysilicon, and the dummy gate structure 113 is removed by a selective etching process. In some embodiments, the dummy gate structure 113 contains polysilicon, and the superlattice structure 101 contains alternating layers of silicon (Si) and silicon germanium (SiGe).

[0054]

[0068] Referring to Figure 1, in steps 38 and 40, the formation of a semiconductor device, e.g., a GAA, continues according to a conventional procedure involving nanosheet emission and substitutional metal gate formation. Specifically, in one or more embodiments not shown, a plurality of semiconductor material layers 106 are selectively etched between a plurality of horizontal channel layers 104 within a superlattice structure 101. For example, if the superlattice structure 101 consists of silicon (Si) layers and silicon germanium (SiGe) layers, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The plurality of semiconductor material layers 106, e.g., silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the plurality of horizontal channel layers 104, such that the etchant etches the plurality of semiconductor material layers 106 at a significantly faster rate than the plurality of horizontal channel layers 104. In some embodiments, selective dry etching or wet etching processes may be used. In some embodiments, when multiple horizontal channel layers 104 are silicon (Si) and multiple semiconductor material layers 106 are silicon germanium (SiGe), the silicon germanium layers can be selectively removed using wet etchants such as (but not limited to) aqueous solutions of carboxylic acid / nitric acid / HF and aqueous solutions of citrate / nitric acid / HF. By removing the multiple semiconductor material layers 106, voids remain between the multiple horizontal channel layers 104. The voids between the multiple horizontal channel layers 104 have a thickness of approximately 3 nm to approximately 20 nm. The remaining horizontal channel layers 104 form a vertical array of channel nanowires connected to the source / drain region 130. The channel nanowires run parallel to the top surface of the substrate 102 and are aligned with each other to form a single row of channel nanowires.

[0055]

[0069] In one or more embodiments, step 40 of method 10 represents one or more post-processing steps. One or more post-processing steps may be any of the processes known to those skilled in the art for completing the device (e.g., formation of a substitution metal gate). For example, in one or more embodiments not shown, a high dielectric constant dielectric is formed. The high dielectric constant dielectric may be any suitable high dielectric constant dielectric material deposited by any suitable deposition technique known to those skilled in the art. The high dielectric constant dielectric in some embodiments includes hafnium oxide. In some embodiments, conductive materials such as titanium nitride (TiN), tungsten (W), cobalt (Co), and aluminum (Al) are deposited on the high dielectric constant dielectric. To ensure the formation of layers with uniform thickness around each of the multiple channel layers, the conductive material may be formed using any suitable deposition process, such as (but not limited to) atomic layer deposition (ALD).

[0056]

[0070] In some embodiments, Method 10 is integrated in such a way that there is no vacuum break. In one or more embodiments, the deposition of the template material (step 30), the directional etching of the template material (step 32), the crystallization of the template material (step 34), and the source / drain epitaxial growth (step 36) may be integrated in such a way that there is no vacuum break between steps.

[0057]

[0071] In some embodiments, the apparatus or process tool is configured to maintain the substrate under vacuum conditions to prevent the formation of an oxide layer after the deposition of the amorphous template material 126. In this type of embodiment, the process tool is configured to move the substrate from a surface treatment chamber (e.g., an annealing chamber) to a rapid processing (RTP) chamber for step 34 (i.e., crystallization) without exposing the substrate to atmospheric conditions.

[0058]

[0072] One or more embodiments of this disclosure relate to methods for forming semiconductor devices. In one or more embodiments, a method for forming a semiconductor device includes forming a superlattice structure on the upper surface of a substrate, the superlattice structure comprising a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged alternately so as to form a plurality of stacked pairs; patterning the superlattice structure to form a plurality of nanosheets separated by trenches; forming shallow trench isolation (STI) layers in the trenches; forming dummy gates adjacent to the superlattice structure and on the STI layers; depositing spacer layers on the dummy gates; forming source trenches and drain trenches adjacent to the superlattice structure; forming bottom dielectric isolation layers in the source trenches and drain trenches; forming inner spacers on each of the plurality of semiconductor material layers; recessing the inner spacers to form recessed regions; depositing amorphous layers in the recessed regions, on the superlattice structure and on the dummy gates; etching the amorphous layers to expose the plurality of horizontal channel layers; crystallizing the amorphous layers; and forming source and drain regions.

[0059]

[0073] Additional embodiments of this disclosure relate to a processing tool 300 for GAA device formation and the method described, as shown in Figure 3. Various multi-processing platforms may be used, including Applied Materials®'s Centura®, Dual ACP, Producer® GT, and Endura® platforms, as well as other processing systems. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and configured to move robot blades and wafers to each of the multiple sides.

[0060]

[0074] The cluster tool 300 comprises several processing chambers 308, 310, and 312, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers include, but are not limited to, pre-cleaning chambers, deposition chambers, annealing chambers (i.e., template crystallization chambers), etching chambers, and any other suitable chambers. The specific arrangement of processing chambers and components can be modified depending on the cluster tool and should not be construed as limiting the scope of this disclosure.

[0061]

[0075] In the embodiment shown in Figure 3, the factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a loading and unloading chamber 302 on its front surface 319.

[0062]

[0076] The size and shape of the loading and unloading chambers 302 may vary, for example, depending on the substrates being processed by the cluster tool 300. In the illustrated embodiment, the loading and unloading chambers 302 are sized to hold a wafer cassette in which multiple wafers are positioned within the cassette.

[0063]

[0077] Robot 304 is located within the factory interface 318 and can move between the loading chamber 302 and the unloading chamber 302. Robot 304 can transfer wafers from the cassette in the loading chamber 302 through the factory interface 318 to the load lock chamber 320. Robot 304 can also transfer wafers from the load lock chamber 320 through the factory interface 318 to the cassette in the unloading chamber 302.

[0064]

[0078] In some embodiments, the robot 316 is a multi-arm robot capable of independently moving multiple wafers at once. The robot 316 is configured to move wafers between chambers around the transfer chamber 314. Each wafer is supported on a wafer transfer blade located at the distal end of the first robotic mechanism.

[0065]

[0079] The system controller 357 communicates with the robot 316 and the multiple processing chambers 308, 310, and 312. The system controller 357 can be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 357 may be a computer including a central processing unit (CPU) 392, memory 394, inputs / outputs 396, suitable circuits 398, and storage.

[0066]

[0080] The process, when executed by a processor, may be stored in the memory of the system controller 357 as a software routine that causes a processing chamber to execute the process of the present disclosure. This software routine may be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may also be executed in hardware. Thus, the process may be implemented in software and executed using a computer system, for example, in hardware as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the chamber operation so that the process can be executed.

[0067]

[0081] In some embodiments, the system controller 357 is configured to control a rapid heat treatment chamber to crystallize the template material.

[0068]

[0082] In one or more embodiments, the processing tool comprises a central transfer station equipped with a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, and including a template deposition chamber and a template crystallization chamber; and controllers connected to the central transfer station and the plurality of process stations, configured to activate the robot to move wafers between process stations and to control the processes performed at each process station.

[0069]

[0083] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar references should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless the context clearly contradicts this. Enumerations of numerical ranges herein are merely intended as abbreviations to refer individually to each distinct value falling within that range, unless otherwise noted herein, and each distinct value is incorporated into the specification as if it were individually listed herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless the context clearly contradicts this. Any and all examples or exemplary language provided herein (e.g., “such as”) are intended merely to better describe the materials and methods and do not limit their scope unless otherwise claimed. Nothing in this specification should be construed as indicating any non-claimed element that is essential to the carrying out of the disclosed materials and methods.

[0070]

[0084] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, expressions such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, particular features, structures, materials, or properties can be combined in any suitable manner in one or more embodiments.

[0071]

[0085] While the disclosures herein have been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, wherein the method is: A superlattice structure is formed on the upper surface of the bottom dielectric insulating layer on a substrate, wherein the superlattice structure includes a plurality of horizontal channel layers and a plurality of corresponding semiconductor material layers, which are arranged alternately to form a plurality of stacked pairs. Forming source trenches and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate, The process involves depositing template material within the source trench and the drain trench, Crystallizing the aforementioned template material, To form a source region and a drain region Includes, A method for crystallizing the template material, comprising one or more of rapid heat treatment (RTP) annealing or laser annealing.

2. A method for forming a semiconductor device, wherein the method is: A superlattice structure is formed on the upper surface of the bottom dielectric insulating layer on a substrate, wherein the superlattice structure includes a plurality of horizontal channel layers and a plurality of corresponding semiconductor material layers, which are arranged alternately to form a plurality of stacked pairs. Forming source trenches and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate, The process involves depositing template material within the source trench and the drain trench, Crystallizing the aforementioned template material, To form a source region and a drain region Includes, A method for forming the source region and the drain region, comprising growing an epitaxial layer thereon.

3. The method according to claim 1 or 2, wherein the template material is amorphous.

4. The method according to claim 3, wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).

5. The method according to claim 3, wherein the template material has a thickness in the range of 2 nm to 50 nm.

6. The method according to claim 1 or 2, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently contain one or more of silicon germanium (SiGe) and silicon (Si).

7. The method according to claim 1 or 2, wherein the source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

8. The method according to claim 1 or 2, wherein the bottom dielectric insulating layer comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high dielectric constant material.

9. The method according to claim 1 or 2, further comprising forming a gate structure on the upper surface of the superlattice structure.

10. The method according to claim 9, further comprising forming a dielectric layer on the gate structure and the superlattice structure.

11. The method according to claim 10, wherein the gate structure comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and N-type doped polysilicon.

12. A method for forming a semiconductor device, wherein the method is: A superlattice structure is formed on the upper surface of the bottom dielectric insulating layer on a substrate, wherein the superlattice structure includes a plurality of horizontal channel layers and a plurality of corresponding semiconductor material layers, which are arranged alternately to form a plurality of stacked pairs. Forming a gate structure on the upper surface of the superlattice structure, Forming dielectric layers on the gate structure and the superlattice structure, Forming source trenches and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate, The process involves depositing template material within the source trench and the drain trench, Annealing the substrate in order to crystallize the template material, To form a source region and a drain region Includes, A method of annealing, comprising one or more of rapid heat treatment (RTP) annealing or laser annealing.

13. A method for forming a semiconductor device, wherein the method is: A superlattice structure is formed on the upper surface of the bottom dielectric insulating layer on a substrate, wherein the superlattice structure includes a plurality of horizontal channel layers and a plurality of corresponding semiconductor material layers, which are arranged alternately to form a plurality of stacked pairs. Forming a gate structure on the upper surface of the superlattice structure, Forming dielectric layers on the gate structure and the superlattice structure, Forming source trenches and drain trenches adjacent to the superlattice structure on the bottom dielectric insulating layer on the substrate, The process involves depositing template material within the source trench and the drain trench, Annealing the substrate in order to crystallize the template material, To form a source region and a drain region Includes, A method for forming the source region and the drain region, comprising growing an epitaxial layer thereon.

14. The method according to claim 12 or 13, wherein the template material is amorphous and has a thickness in the range of 2 nm to 50 nm.

15. The method according to claim 14, wherein the template material comprises silicon (Si), silicon germanium (SiGe), titanium (Ti), zirconium (Zr), and hafnium (Hf).

16. The method according to claim 12 or 13, wherein the plurality of semiconductor material layers and the plurality of horizontal channel layers independently contain one or more of silicon germanium (SiGe) and silicon (Si).

17. The method according to claim 12 or 13, wherein the source region and the drain region are independently doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

18. The method according to claim 12 or 13, wherein the bottom dielectric insulating layer comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high dielectric constant material.

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