Power converter

Abstract

To provide a power conversion device provided with an overvoltage protection circuit, in which a current flowing in the overvoltage protection circuit can be detected.SOLUTION: A capacitor 4 is connected between a first DC bus bar 11 and a second DC bus bar 12. An inverter circuit 6 converts DC power supplied to the first DC bus bar 11 and the second DC bus bar 12 and supplies AC power to a load 100. An overvoltage protection circuit 5 protects the inverter circuit 6 from an overvoltage. Current detection means 7 detects a DC bus bar current flowing in the first DC bus bar 11 or the second DC bus bar 12 between the capacitor 4 and the overvoltage protection circuit 5.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power conversion device that converts DC power into AC power.

Background Art

[0002] As described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2020-124104), when a power conversion device that converts DC power into AC power is connected to a load such as a motor, the DC voltage in the power conversion device may become excessively high due to the influence of a resonance voltage or a surge generated in a circuit including a capacitor. In order to protect the power conversion device from such an overvoltage, an overvoltage protection circuit is provided in the power conversion device of Patent Document 1.

Summary of the Invention

Problems to be Solved by the Invention

[0006] The power converter in the first aspect can detect the current flowing through the overvoltage protection circuit in the first DC bus or the second DC bus using current detection means.

[0007] A power converter in the second aspect is a power converter in the first aspect, wherein the overvoltage protection circuit includes a semiconductor switch and a resistor connected in series between a first DC bus and a second DC bus. A first closed circuit formed by a capacitor, the overvoltage protection circuit, and a portion of the first DC bus and a portion of the second DC bus connecting the capacitor and the overvoltage protection circuit includes a first current path in which a resistor and a semiconductor switch are arranged in series. Current flows through the first current path when the semiconductor switch is turned on.

[0008] In the power conversion device from the second perspective, when the semiconductor switch is turned on, the current flowing through the overvoltage protection circuit flows to the current detection means, making it easier for the current detection means to detect the current value flowing through the overvoltage protection circuit.

[0009] A power converter according to the third aspect is a power converter according to the first or second aspect, wherein the current detection means is arranged to detect the DC bus current flowing through the first DC bus or the second DC bus between the capacitor and the inverter circuit.

[0010] In the third aspect of the power converter, the current detection means is configured to detect the DC bus current flowing through the first or second DC bus between the capacitor and the inverter circuit and between the capacitor and the overvoltage protection circuit. As a result, the number of components in the power converter can be reduced.

[0011] The power converter of the fourth aspect is the power converter of the third aspect, wherein the current detection means detects a first current value flowing through a first closed circuit including a capacitor and an overvoltage protection circuit, a second current value flowing through a second closed circuit including a capacitor and an inverter circuit, or the sum of the first and second current values.

[0012] In the power converter of the fourth perspective, the current detection means detects the first current value, the second current value, and the sum of the first and second current values, so that the current flowing through the overvoltage protection circuit can be detected with high accuracy.

[0013] The power converter of the fifth aspect is the power converter of the fourth aspect, wherein the overvoltage protection circuit turns on or off a semiconductor switch during a period when the voltage vector does not change when the inverter circuit is driven, and the current detection means detects the DC bus current before and after the semiconductor switch is turned on or before and after the semiconductor switch is turned off.

[0014] The power converter in the fifth perspective can easily detect the first current value from the difference in DC bus current detected before and after the semiconductor switch of the overvoltage protection circuit is turned on or off.

[0015] The power converter of the sixth aspect is the power converter of the fourth aspect, wherein the overvoltage protection circuit turns on a semiconductor switch during the zero vector period of the inverter circuit when the inverter circuit is driven, and the current detection means detects the DC bus current when the semiconductor switch is turned on during the zero vector period.

[0016] In the power converter of the sixth perspective, during the zero vector period, the first current value can be easily detected from the DC bus current using the current detection means.

[0017] The power converter according to the seventh perspective is the power converter according to the second perspective, wherein the current detection means detects the DC bus current when the semiconductor switch is on while the load is in a non-driving state.

[0018] In the power conversion device of the seventh perspective, the current detection means can accurately detect the first current value when the second current value in the current detection means becomes zero.

[0019] The power converter of the eighth aspect is the power converter of the second aspect, comprising a capacitor and a DC power supply circuit that supplies power to a first DC bus and a second DC bus. The current detection means detects a first current value flowing through the first closed circuit, a third current value flowing through the third closed circuit including the capacitor and the DC power supply circuit, or the sum of the first current value and the third current value.

[0020] In the power converter of the eighth perspective, the means for detecting the first current value and the means for detecting the third current value are combined into a single current detection means, thus reducing the number of components in the power converter.

[0021] The power converter according to the ninth aspect is the power converter according to the eighth aspect, wherein the current detection means detects the DC bus current before and after the semiconductor switch is turned on, or before and after the semiconductor switch is turned off.

[0022] In the power conversion device of the ninth perspective, the first current value can be easily detected from the difference in DC bus current detected before and after the semiconductor switch is turned on or off.

[0023] The power converter according to the tenth perspective is the power converter according to the eighth perspective, wherein the current detection means detects the DC bus current when the semiconductor switch is on while the load is in a non-driving state.

[0024] In the power conversion device of the tenth perspective, the current detection means can accurately detect the first current value when the third current value is approximately zero.

[0025] The power conversion device according to the 11th aspect is any one of the power conversion devices according to the 4th to 10th aspects, and includes a control unit that determines whether the overvoltage protection circuit is normal or abnormal based on the DC bus current detected by the current detection means.

[0026] In the power conversion device according to the 11th aspect, an abnormality in the overvoltage protection circuit can be detected from the DC bus current.

[0027] The power conversion device according to the 12th aspect is any one of the power conversion devices according to the 5th or 6th aspect, and includes an overcurrent protection unit that does not perform overcurrent protection of the inverter circuit using the current value detected by the current detection means during the period when the semiconductor switch is on, and performs the overcurrent protection using the current value detected by the current detection means during the period when the semiconductor switch is off.

[0028] In the power conversion device according to the 12th aspect, overcurrent protection of the inverter circuit can be performed using the current detection means.

[0029] The power conversion device according to the 13th aspect is any one of the power conversion devices according to the 7th, 10th, or 11th aspect, and the overvoltage protection circuit turns on the semiconductor switch before driving at the start of driving of the load every time the inverter circuit drives.

[0030] In the power conversion device according to the 13th aspect, the reliability for reliable execution of the protection operation required at the time of stopping the driving of the load is improved.

Brief Description of Drawings

[0031] [Figure 1] It is a schematic diagram for explaining the configuration of the power conversion device according to the first embodiment. [Figure 2] It is a circuit diagram showing an example of the configuration of the power conversion device according to the first embodiment. [Figure 3] It is a timing chart for explaining the operation of the inverter circuit. [Figure 4] It is a schematic diagram for explaining the configuration of the power conversion device according to the second embodiment. [Figure 5]This is a circuit diagram showing an example of the configuration of a power converter according to the second embodiment. [Modes for carrying out the invention]

[0032] <First Embodiment> (1) Overall structure The power converter 1 according to the first embodiment shown in Figure 1 is a device that converts DC power to AC power and outputs it to a load 100. The power converter 1 includes a first DC bus 11, a second DC bus 12, a capacitor 4, an inverter circuit 6, an overvoltage protection circuit 5, and a current detection means 7. When the power converter 1 is operating, a DC voltage is applied to the first DC bus 11 and the second DC bus 12. The second DC bus 12 is at a lower potential than the first DC bus 11. The capacitor 4 is connected between the first DC bus 11 and the second DC bus 12. One end of the capacitor 4 is connected to the first DC bus 11, and the other end of the capacitor 4 is connected to the second DC bus 12.

[0033] The inverter circuit 6 is connected to the first DC bus 11 and the second DC bus 12. The inverter circuit 6 receives DC power from the first DC bus 11 and the second DC bus 12. The inverter circuit 6 converts the DC power supplied to the first DC bus 11 and the second DC bus 12 and supplies AC power to the load 100.

[0034] The overvoltage protection circuit 5 is connected between the first DC bus 11 and the second DC bus 12. It is also positioned between the capacitor 4 and the inverter circuit 6. The overvoltage protection circuit 5 protects the inverter circuit 6 from overvoltage. The steady-state voltage is defined as the voltage applied to the first DC bus 11 and the second DC bus 12 when the power converter 1 is operating in a steady state. For example, a resonant voltage or surge generated in a circuit including the capacitor 4 transiently causes an overvoltage higher than the steady-state voltage to occur on the first DC bus 11 and the second DC bus 12. Furthermore, when the inverter circuit 6 stops driving the load 100, the energy from the load 100 flows into the capacitor 4, causing an overvoltage higher than the steady-state voltage to occur on the first DC bus 11 and the second DC bus 12. The overvoltage protection circuit 5 is a circuit that suppresses such voltage increases.

[0035] The current detection means 7 detects the DC bus current flowing through the first DC bus 11 or the second DC bus 12 between the capacitor 4 and the overvoltage protection circuit 5. In the example shown in Figure 1, the current detection means 7 detects the DC bus current flowing through the second DC bus 12. Therefore, the current detection means 7 is located on the second DC bus 12. However, the current detected by the current detection means 7 may also be the DC bus current flowing through the first DC bus 11. In that case, the current detection means 7 is located on the first DC bus 11.

[0036] In the power converter 1 shown in Figure 1, the current I2 flowing between the capacitor 4 and the inverter circuit 6 flows to the current detection means 7. Current I2 is indicated by a dashed arrow in Figure 1. Also, the current I1 flowing between the capacitor 4 and the overvoltage protection circuit 5 flows to the current detection means 7. Current I1 is indicated by a dashed arrow in Figure 1. In the power converter 1 shown in Figure 1, when no current I1 flows through the overvoltage protection circuit 5, the current detection means 7 can detect only the current I2 flowing between the capacitor 4 and the inverter circuit 6. In other words, when no current I1 flows through the overvoltage protection circuit 5, the current detection means 7 can detect the current I2 flowing between the capacitor 4 and the inverter circuit 6 without being affected by the current I1 flowing between the capacitor 4 and the overvoltage protection circuit 5. Also, in the power converter 1 shown in Figure 1, when no current I2 flows through the inverter circuit 6, the current detection means 7 can detect only the current I1 flowing between the capacitor 4 and the overvoltage protection circuit 5. In other words, when no current I2 is flowing through the inverter circuit 6, the current detection means 7 can detect the current I1 flowing between the capacitor 4 and the overvoltage protection circuit 5 without being affected by the current I2 flowing between the capacitor 4 and the inverter circuit 6. In this way, using a single current detection means 7, the current detection means 7 can detect both the current flowing between the capacitor 4 and the inverter circuit 6 and the current flowing between the capacitor 4 and the overvoltage protection circuit 5.

[0037] (2) Detailed configuration Figure 2 shows a specific configuration example of the power converter 1 according to the first embodiment.

[0038] (2-1) Supply of DC power to the first DC bus 11 and the second DC bus 12 DC voltages are applied to the first DC bus 11 and the second DC bus 12 shown in Figure 2 from a DC power supply 2. The DC power supply 2 shown in Figure 2 is supplied with three-phase AC power from the commercial power supply 200. The DC power supply 2 in Figure 2 is a rectifier circuit that rectifies the three-phase AC. The rectifier circuit that makes up the DC power supply 2 is a three-phase bridge rectifier circuit consisting of six diodes D1. Here, a three-phase bridge rectifier circuit is given as an example of the DC power supply 2, but the DC power supply 2 is not limited to a three-phase bridge rectifier circuit. For example, a single-phase bridge rectifier circuit can also be used as the DC power supply 2.

[0039] A reactor 3 is inserted in series with the first DC bus 11. The reactor 3 is provided to reduce harmonics generated in the DC link consisting of the first DC bus 11 and the second DC bus 12. Although Figure 2 shows an example in which the reactor 3 is provided with the first DC bus 11, the configuration is not limited to this example. For example, the reactor 3 may be provided with the second DC bus 12, or between the commercial power supply 200 and the DC power supply 2.

[0040] In the first DC bus 11 of the power converter 1 in Figure 2, the components are arranged in the following order: DC power supply 2, reactor 3, one end of capacitor 4, one end of voltage detection circuit 8, one end of overvoltage protection circuit 5, and the upper arm UA of inverter circuit 6. In the second DC bus 12 of the power converter 1 in Figure 2, the components are arranged in the following order: DC power supply 2, the other end of capacitor 4, current detection means 7, the other end of voltage detection circuit 8, the other end of overvoltage protection circuit 5, and the lower arm DA of inverter circuit 6. Therefore, a DC voltage is applied between one end and the other end of capacitor 4 by the first DC bus 11 and the second DC bus 12. In addition, a DC voltage is applied between one end and the other end of voltage detection circuit 8, between one end and the other end of overvoltage protection circuit 5, and between the upper arm UA and lower arm DA of inverter circuit 6 by the first DC bus 11 and the second DC bus 12.

[0041] (2-2) Inverter circuit 6 The inverter circuit 6 shown in Figure 2 converts the DC power supplied to the first DC bus 11 and the second DC bus 12 to supply three-phase AC power to the load 100. The load 100 shown in Figure 2 is an inductive load. In Figure 2, a three-phase AC motor is shown as an example of an inductive load. The inverter circuit 6 shown in Figure 2 is a circuit that converts the DC power supplied to the first DC bus 11 and the second DC bus 12 into three-phase AC power.

[0042] The upper arm UA is equipped with three semiconductor switches. The upper arm UA is equipped with, for example, three transistors as semiconductor switches. The transistors are, for example, N-channel insulated-gate transistors Qup, Qvp, and Qwp, as shown in Figure 2. The collectors of the insulated-gate transistors Qup, Qvp, and Qwp are connected to the first DC bus 11, the emitters are connected to the load 100, and the gates are connected to the gate driver 21. Freewheeling diodes Dup, Dvp, and Dwp are connected in antiparallel to the insulated-gate transistors Qup, Qvp, and Qwp, respectively. In other words, the cathodes of the freewheeling diodes Dup, Dvp, and Dwp are connected to the collectors of the insulated-gate transistors Qup, Qvp, and Qwp, respectively, and the anodes of the freewheeling diodes Dup, Dvp, and Dwp are connected to the emitters of the insulated-gate transistors Qup, Qvp, and Qwp, respectively.

[0043] The lower arm DA is equipped with three semiconductor switches. The lower arm DA is equipped with, for example, three transistors as semiconductor switches. The transistors are, for example, N-channel insulated-gate transistors Qun, Qvn, and Qwn, as shown in Figure 2. The emitters of the insulated-gate transistors Qun, Qvn, and Qwn are connected to the second DC bus 12, the collectors are connected to the load 100, and the gates are connected to the gate driver 21. Freewheeling diodes Dun, Dvn, and Dwn are connected in antiparallel to the insulated-gate transistors Qun, Qvn, and Qwn, respectively. In other words, the cathodes of the freewheeling diodes Dun, Dvn, and Dwn are connected to the collectors of the insulated-gate transistors Qun, Qvn, and Qwn, respectively, and the anodes of the freewheeling diodes Dun, Dvn, and Dwn are connected to the emitters of the insulated-gate transistors Qun, Qvn, and Qwn, respectively. The U phase of the load 100 is supplied with the outputs from the emitter of insulated-gate transistor Qup and the collector of insulated-gate transistor Qun. The V phase of the load is supplied with the outputs from the emitter of insulated-gate transistor Qvp and the collector of insulated-gate transistor Qvn. The W phase of the load 100 is supplied with the outputs from the emitter of insulated-gate transistor Qwp and the collector of insulated-gate transistor Qwn.

[0044] (2-3) Voltage detection circuit 8 The voltage detection circuit 8 is a circuit for detecting the voltage generated between the first DC bus 11 and the second DC bus 12. The voltage detection circuit 8 detects the voltage generated between the first DC bus 11 and the second DC bus 12 between the capacitor 4 and the inverter circuit 6. The circuit includes resistors 81 and 82 connected in series between the first DC bus 11 and the second DC bus 12. The voltage detection circuit 8 outputs the voltage across resistor 81 to the controller 20. The controller 20 has, for example, an AD conversion function and converts the voltage across resistor 81 into the voltage generated between the first DC bus 11 and the second DC bus 12 based on the resistance ratio of resistors 81 and 82.

[0045] (2-4) Basic configuration of overvoltage protection circuit 5 The overvoltage protection circuit 5 shown in Figure 2 is basically a circuit including a semiconductor switch 52 and a resistor 51 connected in series between the first DC bus 11 and the second DC bus 12. In Figure 2, one end of the resistor 51 is connected to the first DC bus 11. The other end of the resistor 51 is connected to one end of the semiconductor switch 52. The other end of the semiconductor switch 52 is connected to the second DC bus 12. In Figure 2, the resistor 51 is connected to the first DC bus 11 and the semiconductor switch 52 is connected to the second DC bus 12, but the overvoltage protection circuit 5 can also be configured by swapping the positions of the resistor 51 and the semiconductor switch 52.

[0046] The overvoltage protection circuit 5 is a component of the first closed circuit CL1 shown in Figure 1. The first closed circuit CL1 is formed by the capacitor 4, the overvoltage protection circuit 5, and a portion 11a of the first DC bus 11 and a portion 12a of the second DC bus 12 that connect the capacitor 4 and the overvoltage protection circuit 5. The first closed circuit CL1 includes a first current path CP1 in which a resistor 51 and a semiconductor switch 52 are arranged in series. Current flows through the first current path CP1 when the semiconductor switch 52 is on. By allowing current to flow through the first current path CP1, power is consumed by the resistor 51, protecting the inverter circuit 6 from overvoltage.

[0047] The current flowing through the overvoltage protection circuit 5 flows to the current detection means 7 when the semiconductor switch 52 is ON. Therefore, by having the current detection means 7 detect the current at the timing when the semiconductor switch 52 is turned ON, it becomes easier for the current detection means 7 to detect the value of the current flowing through the overvoltage protection circuit 5.

[0048] (2-4-1) Detailed configuration of overvoltage protection circuit 5 The overvoltage protection circuit 5 shown in Figure 2 further includes a diode 53 connected in antiparallel to the resistor 51. The cathode of the diode 53 is connected to the first DC bus 11, and the anode is connected to one end of the semiconductor switch 52. When the semiconductor switch 52 is turned off, the current flowing through the first current path (resistor 51 and semiconductor switch 52) is interrupted. If an inductance component exists in the wiring path including the resistor 51 from the first DC bus 11 to the semiconductor switch 52, an electromotive force is generated that generates a voltage between the first DC bus 11 and the semiconductor switch 52. A voltage is applied to the semiconductor switch 52, which is the DC voltage plus this electromotive force. If this voltage exceeds the breakdown voltage of the semiconductor switch 52, the semiconductor switch 52 will be destroyed. The diode 53 clamps the voltage generated in the wiring path including the resistor 51 from the first DC bus 11 to the semiconductor switch 52 so that a large voltage does not occur when the semiconductor switch 52 is turned off. In Figure 2, a diode 53 is provided in the overvoltage protection circuit 5, but an overvoltage protection circuit 5 without such a diode 53 may also be used in the power converter 1.

[0049] (2-5) Current detection means 7 The current detection means 7 is arranged to detect the DC bus current flowing through the first DC bus 11 or the second DC bus 12 between the capacitor 4 and the inverter circuit 6 and between the capacitor 4 and the overvoltage protection circuit 5. The current detection means 7 shown in Figures 1 and 2 is arranged to detect the DC bus current flowing through the second DC bus 12. In other words, the current detection means 7 is arranged to detect the DC bus current flowing through a portion 11a of the first DC bus 11 or a portion 12a of the second DC bus 12 shown in Figure 1. The current detection means 7 shown in Figures 1 and 2 detects a first current value I1 flowing through the first closed circuit CL1 including the capacitor 4 and the overvoltage protection circuit 5, a second current value I2 flowing through the second closed circuit CL2 including the capacitor 4 and the inverter circuit 6, or the sum of the first and second current values.

[0050] When the current detection means 7 detects the value of the DC bus current when no current is flowing through the second closed circuit CL2, it can detect a first current value, which is the value of the current I1 flowing through the first closed circuit CL1. Furthermore, when the current detection means 7 detects the value of the DC bus current when no current is flowing through the first closed circuit CL1, it can detect a second current value, which is the value of the current I2 flowing through the second closed circuit CL2. In addition, when the current detection means 7 detects the value of the DC bus current when current is flowing through both the first closed circuit CL1 and the second closed circuit CL2, it can detect a total current value, which is the sum of the first and second current values.

[0051] Furthermore, when the value of the current I2 flowing through the second closed circuit CL2 is constant, the current I1 flowing through the first closed circuit CL1 can be changed, and the current detection means 7 can detect the value of the DC bus current before the change and the value of the DC bus current after the change. From the difference between the value of the DC bus current before the change and the value of the DC bus current after the change, the current detection means 7 can detect the value of the current I1 flowing through the first closed circuit CL1 (first current value).

[0052] (2-5-1) Detailed configuration of the current detection means 7 Figure 2 shows an example of the configuration of the current detection means 7. The current detection means 7 in Figure 2 includes a resistor 71, a detector 72, and a controller 20. The resistor 71 is inserted in series with a portion 12a of the second DC bus 12. Therefore, a voltage corresponding to the value of the DC bus current flowing through the portion 12a of the second DC bus 12 is generated across the resistor 71. The detector 72 is a device for detecting the value of the current flowing through the resistor 71 from the voltage generated across the resistor 71. The detector 72 has, for example, a function to amplify the voltage generated across the resistor 71 and a filter function to remove noise. The controller 20 acquires the value of the current detected by the detector 72 according to the operating status of the power converter 1. When the value of the DC bus current is acquired from the detector 72 when no current is flowing through the second closed circuit CL2, the controller 20 can acquire the first current value, which is the value of the current I1 flowing through the first closed circuit CL1. Furthermore, if the controller 20 has the function of directly obtaining the value of the DC bus current from the voltage across the resistor 71, the detector 72 may be omitted.

[0053] When the controller 20 obtains the value of the DC bus current from the detector 72 while no current is flowing through the first closed circuit CL1, it can obtain the second current value, which is the value of the current I2 flowing through the second closed circuit CL2. When the controller 20 obtains the value of the DC bus current from the detector 72 while current is flowing through both the first closed circuit CL1 and the second closed circuit CL2, it can obtain the total current value, which is the sum of the first and second current values.

[0054] Furthermore, when the value of the current I2 flowing through the second closed circuit CL2 is constant, the controller 20 can also change the current I1 flowing through the first closed circuit CL1 and obtain the value of the DC bus current before the change and the value of the DC bus current after the change. From the difference between the value of the DC bus current before the change and the value of the DC bus current after the change, the controller 20 can detect the value of the current I1 flowing through the first closed circuit CL1 (first current value).

[0055] (2-5-2) Detection of DC bus current by current detection means 7 (2-5-2-1) The overvoltage protection circuit 5 turns the semiconductor switch 52 on or off during periods when the inverter circuit 6 is running, while the voltage vector of the inverter circuit 6 does not change. The current detection means 7 detects the DC bus current before and after the semiconductor switch 52 is turned on, or before and after the semiconductor switch 52 is turned off.

[0056] The controller 20 in Figure 2 controls the gate drivers 21 that drive the insulated-gate transistors Qup, Qun, Qvp, Qvn, Qwp, and Qwn of the inverter circuit 6. Therefore, the controller 20 has information about when the inverter circuit 6 is driven and when it is not. In addition, the controller 20, which controls the gate drivers 21, has information about the period when the voltage vector does not change. Based on this information, the controller 20 can control the semiconductor switch 52 to turn on or off during the period when the inverter circuit 6 is driven and the voltage vector does not change.

[0057] Here, the voltage vector of the inverter circuit 6 output is represented by the potentials given to each phase (U phase, V phase, and W phase in the case of three-phase AC). For each phase, the potential when the semiconductor switch of the upper arm UA is ON and the semiconductor switch of the lower arm DA is OFF is represented as "1", and the potential when the semiconductor switch of the upper arm UA is OFF and the semiconductor switch of the lower arm DA is ON is represented as "0". The voltage vectors of the inverter circuit 6 outputting three-phase AC power are V(1,0,0), V(1,1,0), V(0,1,0), V(0,1,1), V(0,0,1), V(1,0,1), V(0,0,0), and V(1,1,1). Of these, V(0,0,0) and V(1,1,1) are called the zero vector. In other words, the zero vector is the voltage vector when all the semiconductor switches on the upper arm UA are ON and all the semiconductor switches on the lower arm DA are OFF, or when all the semiconductor switches on the upper arm UA are OFF and all the semiconductor switches on the lower arm DA are ON. Also, the period during which the output voltage vector of the inverter circuit 6 does not change is, in other words, the period during which the ON / OFF state of each semiconductor switch in the inverter circuit 6 does not change.

[0058] Even when the inverter circuit 6 is driven, the period during which the voltage vector of the output of the inverter circuit 6 does not change is a period during which the value of the current I2 can be considered to be approximately constant compared to the change in the current I2 flowing through the second closed circuit CL2 due to the change in the voltage vector. During such a period, the controller 20 turns the semiconductor switch 52 of the overvoltage protection circuit 5 on or off. The controller 20 can obtain the value of the DC bus current before and after the semiconductor switch 52 is turned on, or before and after the semiconductor switch 52 is turned off, via the resistor 71 and the detector 72. From the difference between the value of the DC bus current before the on / off switching of the semiconductor switch 52 and the value of the DC bus current after the on / off switching, the controller 20 can detect the value of the current I1 flowing through the first closed circuit CL1 (first current value).

[0059] (2-5-2-2) The overvoltage protection circuit 5 turns on the semiconductor switch 52 during the zero vector period of the inverter circuit 6 when the inverter circuit 6 is being driven. The current detection means 7 detects the DC bus current when the semiconductor switch 52 is turned on during the zero vector period. The zero vector period is the period during which the voltage vector of the output of the inverter circuit 6 is the zero vector V(0,0,0) or V(1,1,1). Figure 3 shows an example of the driving of insulated gate transistors Qup, Qun, Qvp, Qvn, Qwp, and Qwn when the inverter circuit 6 is being driven, in the case where the load 100 is a three-phase AC motor.

[0060] During the zero-vector period, even if the load 100 is an inductive load, the output current of the inverter circuit 6 flows only to the load 100 via the freewheeling diodes Dup, Dvp, Dwp, Dun, Dvn, and Dwn. Therefore, at this time, the DC bus current between the capacitor 4 and the inverter circuit 6 becomes zero. In other words, at this time, the current I2 flowing through the second closed circuit CL2 becomes zero. Consequently, even when the inverter circuit 6 is driven, the current detection means 7 can detect the value of the current flowing through the overvoltage protection circuit 5 (first current value) by turning on the semiconductor switch 52 of the overvoltage protection circuit 5 during the zero-vector period and detecting the DC bus current.

[0061] As already explained, the controller 20 controls the driving and non-driving of the inverter circuit 6, and controls the driving of the insulated gate transistors Qup, Qun, Qvp, Qvn, Qwp, and Qwn. Therefore, the controller 20 can turn on the semiconductor switch 52 of the overvoltage protection circuit 5 during the zero vector period. In addition, the controller 20 can obtain the value of the DC bus current via the resistor 71 and the detector 72 at the timing when the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on.

[0062] (2-5-2-3) The current detection means 7 detects the value of the DC bus current that flows when the semiconductor switch 52 of the overvoltage protection circuit 5 is ON while the load 100 is not being driven. When the load 100 is a three-phase AC motor, the state in which all insulated gate transistors Qup, Qun, Qvp, Qvn, Qwp, and Qwn of the inverter circuit 6 are OFF in the timing chart of Figure 3 corresponds to the aforementioned state. In this case, the current I2 flowing through the second closed circuit CL2 becomes zero. Therefore, the current detection means 7 can detect the value of the current I1 flowing through the first closed circuit CL1 by turning on the semiconductor switch 52 of the overvoltage protection circuit 5 and detecting the DC bus current while the load 100 is not being driven. In other words, by detecting the value of the DC bus current in this state, the current detection means 7 can detect the value of the current (first current value) flowing through the overvoltage protection circuit 5.

[0063] As already explained, the controller 20 controls the driving and non-driving of the inverter circuit 6, and controls the driving of the insulated gate transistors Qup, Qun, Qvp, Qvn, Qwp, and Qwn. Therefore, the controller 20 can turn on the semiconductor switch 52 of the overvoltage protection circuit 5 when the load 100 is in a non-driving state. In addition, the controller 20 can obtain the value of the DC bus current via the resistor 71 and the detector 72 at the timing when the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on.

[0064] (2-6) Overvoltage protection by overvoltage protection circuit 5 The power converter 1 includes a control unit that determines whether the overvoltage protection circuit 5 is normal or abnormal based on the DC bus current detected by the current detection means 7. In the power converter 1 shown in Figure 2, the controller 20 functions as a control unit that determines whether the overvoltage protection circuit 5 is normal or abnormal. As already explained, the controller 20 can detect the value of the current (first current value) that flows through the overvoltage protection circuit 5 when the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on. For example, if the controller 20 outputs a signal to turn on the semiconductor switch 52 but no current flows, it determines that there is an abnormality, such as a break in the overvoltage protection circuit 5 or a malfunction in the function of switching the semiconductor switch 52. The controller 20 also determines that there is an abnormality if, for example, the first current value that flows when the semiconductor switch 52 is turned on is less than or exceeds a predetermined range. For example, if the controller 20 determines that the overvoltage protection circuit 5 is normal, it determines that the first current value that flows when the semiconductor switch 52 is turned on is within a predetermined range. If the overvoltage protection circuit 5 is determined to be functioning normally, the power converter 1 performs overvoltage protection using the overvoltage protection circuit 5.

[0065] The power converter 1 turns on the semiconductor switch 52 of the overvoltage protection circuit 5 before the inverter circuit 6 starts driving the load 100. This allows the power converter 1 to pre-check for any abnormalities in the overvoltage protection circuit 5 for the protective operation required when the load 100 is stopped, thereby improving the reliability of its execution.

[0066] The controller 20 shown in Figure 2 controls the gate driver 21 and therefore has information regarding the timing of starting the drive of the three-phase AC motor, which is the load 100. Accordingly, the controller 20 can turn on the semiconductor switch 52 of the overvoltage protection circuit 5 before the start of the drive, each time the motor is started by the inverter circuit 6. As a result, the reliability of the protective operation required when the drive of the load 100 is stopped is improved.

[0067] Furthermore, the controller 20 obtains the voltage between the first DC bus 11 and the second DC bus 12 from the voltage detection circuit 8. The controller 20 stores a threshold voltage for determining whether or not an overvoltage is occurring, and can determine if an overvoltage is occurring by comparing the voltage between the first DC bus 11 and the second DC bus 12 with the threshold voltage. When the controller 20 determines that an overvoltage is occurring, it turns on the semiconductor switch 52 of the overvoltage protection circuit 5 to protect the inverter circuit 6 from the overvoltage.

[0068] Furthermore, if it is necessary to speed up the overvoltage protection response, a circuit may be used in conjunction with the comparator, which compares the output voltage of the voltage detection circuit 8 with a threshold voltage and uses the output of the comparator to turn the semiconductor switch 52 on or off. In this case, the controller 20 turns the semiconductor switch 52 on or off to determine whether the overvoltage protection circuit 5 is functioning normally or abnormally.

[0069] (2-7) Overcurrent protection The power converter 1 can be configured to include an overcurrent protection unit that performs overcurrent protection. The overcurrent protection unit of the power converter 1 performs overcurrent protection of the inverter circuit 6 using the value of the DC bus current detected by the current detection means 7 during the period when the semiconductor switch 52 of the overvoltage protection circuit 5 is off. However, the overcurrent protection unit of the power converter 1 does not perform overcurrent protection of the inverter circuit 6 using the value of the DC bus current detected by the current detection means 7 during the period when the semiconductor switch 52 is on. Therefore, the overcurrent protection unit can determine whether or not an overcurrent has occurred using the value of the current I2 (second current value) flowing through the second closed circuit CL2. In other words, since it does not use a value that is superimposed with the current I1 flowing through the first closed circuit CL1, the overcurrent protection unit will not make an incorrect judgment that an overcurrent has occurred in the inverter circuit 6 when there is no overcurrent.

[0070] In the power converter 1 shown in Figure 2, the controller 20 functions as an overcurrent protection unit. As already explained, the controller 20 can obtain the value of the DC bus current detected by the current detection means 7 during the period when the semiconductor switch 52 of the overvoltage protection circuit 5 is off. Furthermore, since the controller 20 controls the gate driver 21, it can control the inverter circuit 6 based on the detected current value. If the value of the DC bus current (second current value) detected during the period when the semiconductor switch 52 of the overvoltage protection circuit 5 is off exceeds a predetermined threshold, the controller 20 can determine that an overcurrent has occurred in the inverter circuit 6. For example, if the controller 20 determines that an overcurrent has occurred, it can turn off all the semiconductor switches of the lower arm DA of the inverter circuit 6 so that no voltage is applied to the load 100 from the first DC bus 11 and the second DC bus 12. By interrupting the voltage applied to the load 100, the controller 20 can prevent overcurrent from flowing into the inverter circuit 6. In this way, the controller 20 can be given the function of a current protection unit.

[0071] Alternatively, overcurrent detection may be performed by directly comparing the output signal of the detector 72 with the threshold voltage using a comparator and using its output. In this case, a logical AND circuit is added to disable the comparator's output during the period when the semiconductor switch 52 is ON. By inputting the comparator's output and the disable signal from the controller 20 into the logical AND circuit, overcurrent detection during the period when the semiconductor switch 52 is ON can be disabled, enabling accurate overcurrent detection. This configuration allows for faster overcurrent detection.

[0072] (3) Configuration of Controller 20 The controller 20 is implemented, for example, by a computer. The computer-implemented controller 20 comprises a control arithmetic unit and a memory device. The control arithmetic unit can use a processor such as a CPU or a GPU. The control arithmetic unit reads a program stored in the memory device and performs control of predetermined devices and circuits and data calculations according to this program. Furthermore, the control arithmetic unit can write calculation results to the memory device and read information stored in the memory device according to the program.

[0073] <Second Embodiment> (4) Overall structure The power converter 1 according to the second embodiment shown in Figure 4 comprises a first DC bus 11, a second DC bus 12, a capacitor 4, an inverter circuit 6, an overvoltage protection circuit 5, a current detection means 7, and a DC power supply 2. The DC power supply 2 is a DC power supply circuit that supplies power to the capacitor 4, the first DC bus 11, and the second DC bus 12.

[0074] The power converter 1 according to the second embodiment shown in Figure 4 differs from the power converter 1 according to the first embodiment shown in Figure 1 in the arrangement of the capacitor 4, inverter circuit 6, overvoltage protection circuit 5, and current detection means 7. In the power converter 1 of Figure 4, the capacitor 4 is positioned closer to the inverter circuit 6, and the overvoltage protection circuit 5 is positioned further away from the inverter circuit 6 than the capacitor 4. In Figure 4, the current I1 flowing through the first closed circuit CL1 is shown by a dashed line, the current I2 flowing through the second closed circuit CL2 is shown by a broken line, and the current I3 flowing through the third closed circuit CL3 is shown by a double dashed line. The first closed circuit CL1 of the second embodiment is formed by the capacitor 4, the overvoltage protection circuit 5, and a part 11a of the first DC bus 11 and a part 12a of the second DC bus 12 that connect the capacitor 4 and the overvoltage protection circuit 5, similar to the first closed circuit CL1 of the first embodiment. The second closed circuit CL2 of the second embodiment is a closed circuit including a capacitor 4 and an inverter circuit 6, similar to the second closed circuit CL2 of the first embodiment. The third closed circuit CL3 is a closed circuit including a DC power supply 2 and a capacitor 4. In the overall configuration of the second embodiment, the capacitor 4, overvoltage protection circuit 5, and inverter circuit 6 in Figure 4 are the same as the capacitor 4, overvoltage protection circuit 5, and inverter circuit 6 described in (1) Overall Configuration of the First Embodiment using Figure 1, except for differences in their arrangement. Therefore, the individual descriptions of the capacitor 4, overvoltage protection circuit 5, and inverter circuit 6 of the second embodiment in terms of overall configuration are omitted.

[0075] The current detection means 7 detects the DC bus current flowing through the first DC bus 11 or the second DC bus 12 between the capacitor 4 and the overvoltage protection circuit 5. The current detection means 7 detects the value of the current I1 (first current value) flowing through the first closed circuit CL1 and the value of the current I3 (third current value) flowing through the third closed circuit CL3 between the capacitor 4 and the overvoltage protection circuit 5. In the example shown in Figure 4, the current detection means 7 detects the DC bus current flowing through the second DC bus 12. Therefore, the current detection means 7 is located on the second DC bus 12. However, the current detected by the current detection means 7 may also be the DC bus current flowing through the first DC bus 11. In that case, the current detection means 7 is located on the first DC bus 11.

[0076] In the power converter 1 shown in Figure 4, the current detection means 7 detects not only the first current value of the current I1 flowing through the first closed circuit CL1, but also the third current value of the current I3 flowing through the third closed circuit CL3. For example, when the overvoltage protection circuit 5 is turned on while the inverter circuit is running, the current I1 of the overvoltage protection circuit flows in addition to the current I3 supplied to the load from the DC power supply. In the case of Figure 4, since I1 and I3 have opposite polarities, the detected current will be I3 minus I1. Therefore, while the inverter circuit is running, it becomes difficult to accurately detect the value of the current I1 (first current value) flowing through the overvoltage protection circuit 5.

[0077] However, the current detection means 7 can detect whether or not current is flowing through the overvoltage protection circuit 5. In this case, it is possible to determine whether or not there is a break in the overvoltage protection circuit (an abnormality) using the presence or absence of current flowing through the overvoltage protection circuit 5.

[0078] (5) Detailed Configuration Figure 5 shows a specific configuration example of the power converter 1 according to the second embodiment.

[0079] (5-1) Supply of DC power to the first DC bus 11 and the second DC bus 12 DC voltages are applied to the first DC bus 11 and the second DC bus 12 shown in Figure 5 from a DC power supply 2. The DC power supply 2 shown in Figure 5 is supplied with single-phase AC power from the commercial power supply 200. The DC power supply 2 in Figure 5 is a rectifier circuit that rectifies single-phase AC. The rectifier circuit that makes up the DC power supply 2 is a single-phase bridge rectifier circuit consisting of four diodes D2. Here, a single-phase bridge rectifier circuit is given as an example of the DC power supply 2, but the DC power supply 2 is not limited to a single-phase bridge rectifier circuit. For example, a three-phase bridge rectifier circuit can also be used as the DC power supply 2.

[0080] A reactor 3 is inserted in series with the first DC bus 11. The reactor 3 is provided to reduce harmonics generated in the DC link consisting of the first DC bus 11 and the second DC bus 12. Although Figure 5 shows an example in which the reactor 3 is provided with the first DC bus 11, the configuration is not limited to this example. For example, the reactor 3 may be provided with the second DC bus 12, or it may be provided between the commercial power supply 200 and the DC power supply 2.

[0081] In the first DC bus 11 of the power converter 1 in Figure 5, the components are arranged in the following order: DC power supply 2, reactor 3, one end of overvoltage protection circuit 5, one end of capacitor 4, one end of voltage detection circuit 8, and the upper arm UA of inverter circuit 6. In the second DC bus 12 of the power converter 1 in Figure 5, the components are arranged in the following order: DC power supply 2, the other end of overvoltage protection circuit 5, current detection means 7, the other end of capacitor 4, other current detection means 9, the other end of voltage detection circuit 8, and the lower arm DA of inverter circuit 6. Therefore, a DC voltage is applied between one end and the other end of capacitor 4 by the first DC bus 11 and the second DC bus 12. In addition, a DC voltage is applied between one end and the other end of voltage detection circuit 8, between one end and the other end of overvoltage protection circuit 5, and between the upper arm UA and the lower arm DA of inverter circuit 6 by the first DC bus 11 and the second DC bus 12. The other current detection means 9 is composed of, for example, a resistor 91, a detector 92, and a controller 20, and is used to detect the current flowing through the second DC bus 12 between the capacitor 4 and the inverter circuit 6. The other current detection means 9 can have the same configuration as the current detection means 7, except for the placement of the resistor 91, and the detector 92 can have the same configuration as, for example, the detector 72. The other current detection means 9 is used, for example, when the load 100 is a motor. The other current detection means 9 are not important for describing the technical features of the power converter 1 of the second embodiment, so a detailed description of the other current detection means 9 is omitted here.

[0082] (5-2) Inverter circuit 6 The configuration of the inverter circuit 6 in the second embodiment shown in Figure 5 is the same as that of the inverter circuit 6 in the first embodiment shown in Figure 2. Therefore, a detailed explanation of the inverter circuit 6 configuration is omitted here. Note that the elements with the same reference numerals in Figure 5 as those in Figure 2 are the same elements as those with the same reference numerals in Figure 2.

[0083] (5-3) Voltage detection circuit 8 The voltage detection circuit 8 of the second embodiment has the same configuration as the voltage detection circuit 8 of the first embodiment, so its description is omitted here. Note that the elements in Figure 5 that have the same reference numerals as those in Figure 2 are the same elements as those with the same reference numerals in Figure 2.

[0084] (5-4) Basic configuration of overvoltage protection circuit 5 The basic configuration of the overvoltage protection circuit 5 in the second embodiment is the same as that of the overvoltage protection circuit 5 in the first embodiment, so a detailed explanation is omitted here. Note that the elements in Figure 5 that have the same reference numerals as those in Figure 2 are the same elements as those with the same reference numerals in Figure 2.

[0085] (5-4-1) Detailed configuration of overvoltage protection circuit 5 The diode 53 in the overvoltage protection circuit 5 shown in Figure 5 is the same as the diode 53 in Figure 2, so its explanation is omitted here.

[0086] (5-5) Current detection means 7 The current detection means 7 is arranged to detect the DC bus current flowing through the first DC bus 11 or the second DC bus 12 between the DC power supply 2 and the capacitor 4, and between the capacitor 4 and the overvoltage protection circuit 5. The current detection means 7 shown in Figures 4 and 5 is arranged to detect the DC bus current flowing through the second DC bus 12. In other words, the current detection means 7 is arranged to detect the DC bus current flowing through a portion 11a of the first DC bus 11 or a portion 12a of the second DC bus 12, as shown in Figure 4. The current detection means 7 shown in Figures 4 and 5 detects the third current value of the current I3 flowing through the third closed circuit CL3, which includes the DC power supply 2 and the capacitor 4, or the sum of the first current value and the third current value. The first current value is the value of the current I1 flowing through the first closed circuit CL1, which includes the capacitor 4 and the overvoltage protection circuit 5, and is the value of the current flowing through the overvoltage protection circuit 5.

[0087] The current detection means 7 can detect whether the DC bus current detected before and after switching the semiconductor switch 52 of the overvoltage protection circuit 5 has changed. Even if the controller 20 sends a signal to the overvoltage protection circuit 5 to switch the semiconductor switch 52 on or off, if the current detection means 7 does not detect a change in the DC bus current, the controller 20 can determine that an abnormality has occurred in the overvoltage protection circuit 5. In other words, the current detection means 7 is configured to detect the DC bus current before and after the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on, or before and after the semiconductor switch 52 is turned off, in order to detect the current flowing through the overvoltage protection circuit 5.

[0088] Alternatively, the current detection means 7 is configured to detect a first current value from the DC bus current that flows when the semiconductor switch 52 is ON and the load 100 is not being driven.

[0089] Furthermore, when the current detection means 7 detects the value of the DC bus current when no current is flowing through the first closed circuit CL1, it can detect a third current value, which is the value of the current I3 flowing through the third closed circuit CL3.

[0090] (5-5-1) Detailed configuration of the current detection means 7 Figure 5 shows an example of the configuration of the current detection means 7, which is similar to the configuration of the current detection means 7 in Figure 5. The current detection means 7 has a resistor 71 inserted in series with a portion 12a of the second DC bus 12, which is between the DC power supply 2 and the capacitor 4, and between the capacitor 4 and the overvoltage protection circuit 5. Therefore, a voltage corresponding to the value of the DC bus current flowing through the portion 12a of the second DC bus 12 is generated across the resistor 71. The detector 72 is a device for detecting the value of the current flowing through the resistor 71 from the voltage generated across the resistor 71. The controller 20 of the current detection means 7 in Figure 5 transmits a signal to the semiconductor switch 52 of the overvoltage protection circuit 5 to turn it on or off. The controller 20 obtains the value of the DC bus current detected by the detector 72 before and after the signal to turn the semiconductor switch 52 on or off. Alternatively, the controller 20 controls the gate driver 21 to put the load 100 into a non-driven state, and when the output current of the DC power supply 2, which is a DC power supply circuit, becomes zero, it sends an ON signal to the semiconductor switch 52. In this case, the controller 20 acquires the value of the DC bus current detected by the detector 72 at the timing after the semiconductor switch 52 has been turned ON.

[0091] Furthermore, when the controller 20 obtains the value of the DC bus current from the detector 72 while no current is flowing through the first closed circuit CL1, it can obtain the third current value, which is the value of the current I3 flowing through the third closed circuit CL3. When the controller 20 obtains the value of the DC bus current from the detector 72 while current is flowing through both the first closed circuit CL1 and the third closed circuit CL3, it can obtain the total current value, which is the sum of the first and third current values.

[0092] (5-5-2) Overvoltage protection by overvoltage protection circuit 5 In the power converter 1 shown in Figure 5 of the second embodiment, the controller 20 functions as a control unit that determines whether the overvoltage protection circuit 5 is normal or abnormal, similar to the first embodiment. Overvoltage protection in the power converter 1 shown in Figure 5 of the second embodiment can be performed in the same way as the overvoltage protection in the power converter 1 shown in Figure 2 of the first embodiment. For example, when it is determined from the detection result of the voltage detection circuit 8 that an overvoltage has occurred, overvoltage protection is performed by turning on the semiconductor switch 52 of the overvoltage protection circuit 5 to protect the inverter circuit 6 from the overvoltage. In addition, each time the inverter circuit 6 starts driving the load 100, the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on before the start of driving to check for abnormalities in the overvoltage protection circuit 5 in advance. For this reason, a detailed explanation of overvoltage protection is omitted here.

[0093] (6) Variant (6-1) Variation A In the first and second embodiments described above, the case in which the current detection means 7 detects current using a resistor 71 was explained. However, the element used by the current detection means 7 to detect current is not limited to a resistor. In the current detection means 7, instead of the resistor 71, for example, a current transformer (CT) or a Hall element can be used.

[0094] (7) Characteristics (7-1) In the first and second embodiments, the current detection means 7 detects the DC bus current flowing between the capacitor 4 and the overvoltage protection circuit 5 in the first DC bus 11 or the second DC bus 12. Therefore, the value of the current I1 flowing through the overvoltage protection circuit 5 in the first DC bus 11 or the second DC bus 12 can be detected by the current detection means 7.

[0095] (7-2) In the power converter 1 of the first and second embodiments, when the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on, the current flowing through the overvoltage protection circuit 5 flows to the current detection means 7, making it easier for the current detection means 7 to detect the value of the current I1 flowing through the overvoltage protection circuit 5.

[0096] (7-3) In the power converter 1 of the first embodiment, the current detection means 7 is configured to detect the DC bus current flowing through the first DC bus 11 or the second DC bus 12 between the capacitor 4 and the inverter circuit 6 and between the capacitor 4 and the overvoltage protection circuit 5. The means for detecting the values ​​of currents I1 and I2 can be combined into the current detection means 7, which reduces the number of components in the power converter 1.

[0097] (7-4) In the power converter 1 of the first embodiment, the current I1 flowing through the capacitor 4 and the inverter circuit 6, and the current I2 flowing through the capacitor 4 and the overvoltage protection circuit 5, both flow through the current detection means 7. Therefore, the current detection means 7 can be used to detect the values ​​of both currents I1 and I2. As a result, the current detection means 7 can accurately detect the current flowing through the overvoltage protection circuit 5.

[0098] (7-5) In the power converter 1 of the first embodiment, there is a period during which the voltage vector does not change when the inverter circuit 6 is driven. During this period, when the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on or off, the current detection means 7 can detect the DC bus current before and after the semiconductor switch 52 is turned on, or before and after the semiconductor switch 52 is turned off. As a result, the first current value can be easily detected from the difference in the DC bus current detected before and after the semiconductor switch 52 is turned on or off.

[0099] (7-6) In the power converter 1 of the first embodiment, there may be a zero vector period when the inverter circuit 6 is driven. If the overvoltage protection circuit 5 turns on the semiconductor switch 52 during this period, the current detection means 7 can detect the DC bus current when the semiconductor switch 52 is on during the zero vector period. As a result, the current detection means 7 can easily detect a first current value from the DC bus current.

[0100] (7-7) In the power converter 1 of the first embodiment, the load 100 can be kept in a non-driven state. In this case, the current detection means 7 detects the value of the DC bus current that flows when the semiconductor switch 52 is ON. At this time, the second current value becomes zero, so the current detection means 7 can accurately detect the first current value.

[0101] (7-8) The power converter 1 of the second embodiment includes a DC power supply 2, which is a DC power supply circuit that supplies power to the first DC bus 11 and the second DC bus 12. The current detection means 7 detects a first current value flowing through the first closed circuit CL1 and a third current value flowing through the third closed circuit CL3, which includes the DC power supply 2. Since the current detection means 7 also serves as the means for detecting the first current value and the means for detecting the third current value, the number of components in the power converter 1 can be reduced.

[0102] (7-9) In the power converter 1 of the second embodiment, the current detection means 7 can detect the DC bus current before and after the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on, or before and after the semiconductor switch 52 is turned off. The first current value can be easily detected from the difference in DC bus current detected before and after the semiconductor switch 52 of the overvoltage protection circuit 5 is turned on or off.

[0103] (7-10) In the power converter 1 of the second embodiment, when the load 100 is in a non-driven state, the current detection means 7 detects a first current value from the DC bus current that flows when the semiconductor switch 52 is ON. The current detection means 7 can accurately detect the first current value when the third current value becomes zero.

[0104] (7-11) In the power converter 1 of the first and second embodiments, the controller 20 functions as a control unit that determines whether the overvoltage protection circuit is normal or abnormal based on the DC bus current detected by the current detection means. As a result, the power converter 1 can detect abnormalities in the overvoltage protection circuit 5 from the DC bus current.

[0105] (7-12) The power converter according to the first embodiment and the second aspect includes a controller 20 that functions as an overcurrent protection unit. When the controller 20 functions as an overcurrent protection unit, it does not perform overcurrent protection of the inverter circuit 6 using the current value detected by the current detection means 7 during the period when the semiconductor switch 52 is ON. It performs the overcurrent protection using the current value detected by the current detection means 7 during the period when the semiconductor switch 52 is OFF. In this way, the power converter 1 can perform overcurrent protection using the current detection means 7.

[0106] (7-13) In the power converter 1 of the first and second embodiments, the overvoltage protection circuit 5 turns on the semiconductor switch 52 before the inverter circuit 6 starts driving the load 100 each time. As a result, the reliability of the protective operation required when the load is stopped is improved.

[0107] While embodiments of this disclosure have been described above, it should be understood that various modifications to the form and details are possible without departing from the spirit and scope of this disclosure as described in the claims. [Explanation of Symbols]

[0108] 1. Power converter 2. DC power supply (example of a DC power supply circuit) 4 Capacitors 5 Overcurrent protection circuit 6. Inverter Circuit 7 Current detection means 11 1st DC bus 12 2nd DC bus 20. Controller (Example of control unit, example of overcurrent protection unit) 51 Resistors 52 Semiconductor switches 100 load CL1 1st closed circuit CL2 2nd closed circuit CL3 3rd closed circuit CP1 First current path [Prior art documents] [Patent Documents]

[0109] [Patent Document 1] Japanese Patent Publication No. 2020-124104

Claims

1. A first DC bus (11) to which a DC voltage is applied, and a second DC bus (12) which is at a lower potential than the first DC bus, A capacitor (4) connected between the first DC bus and the second DC bus, An inverter circuit (6) connected to the first DC bus and the second DC bus, which converts the DC power supplied to the first DC bus and the second DC bus to supply AC power to the load, An overvoltage protection circuit (5) is connected between the first DC bus and the second DC bus to protect the inverter circuit from overvoltage, A current detection means (7) for detecting the DC bus current flowing through the first DC bus or the second DC bus between the capacitor and the overvoltage protection circuit, Equipped with, The overvoltage protection circuit described above is: The system includes a semiconductor switch (52) and a resistor (51) connected in series between the first DC bus and the second DC bus. When the inverter circuit is driven, the semiconductor switch is turned on or off during the period when the voltage vector of the output of the inverter circuit does not change. The first closed circuit (CL1) formed by the capacitor, the overvoltage protection circuit, and a portion of the first DC bus and a portion of the second DC bus connecting the capacitor and the overvoltage protection circuit includes a first current path (CP1) in which the resistor and the semiconductor switch are arranged in series, and when the semiconductor switch is ON, current flows through the first current path. The current detection means is The capacitor and the inverter circuit are arranged to detect the DC bus current flowing through the first DC bus or the second DC bus. It is possible to detect a first current value flowing through the first closed circuit including the capacitor and the overvoltage protection circuit, to detect a second current value flowing through the second closed circuit including the capacitor and the inverter circuit, and to detect the sum of the first and second current values. Power converter (1).

2. A first DC bus (11) to which a DC voltage is applied, and a second DC bus (12) which is at a lower potential than the first DC bus, A capacitor (4) connected between the first DC bus and the second DC bus, An inverter circuit (6) connected to the first DC bus and the second DC bus, which converts the DC power supplied to the first DC bus and the second DC bus to supply AC power to the load, An overvoltage protection circuit (5) is connected between the first DC bus and the second DC bus to protect the inverter circuit from overvoltage, A current detection means (7) for detecting the DC bus current flowing through the first DC bus or the second DC bus between the capacitor and the overvoltage protection circuit, Equipped with, The overvoltage protection circuit described above is: The system includes a semiconductor switch (52) and a resistor (51) connected in series between the first DC bus and the second DC bus. When the inverter circuit is driven, the semiconductor switch is turned on during the zero vector period of the inverter circuit. The first closed circuit (CL1) formed by the capacitor, the overvoltage protection circuit, and a portion of the first DC bus and a portion of the second DC bus connecting the capacitor and the overvoltage protection circuit includes a first current path (CP1) in which the resistor and the semiconductor switch are arranged in series, and when the semiconductor switch is ON, current flows through the first current path. The current detection means is The capacitor and the inverter circuit are arranged to detect the DC bus current flowing through the first DC bus or the second DC bus. It is possible to detect a first current value flowing through the first closed circuit including the capacitor and the overvoltage protection circuit, to detect a second current value flowing through the second closed circuit including the capacitor and the inverter circuit, and to detect the sum of the first and second current values. Power converter (1).

3. The current detection means detects the DC bus current before and after the semiconductor switch is turned on, or before and after the semiconductor switch is turned off. The power conversion device (1) according to claim 1.

4. The current detection means detects the DC bus current when the semiconductor switch is turned on during the zero vector period. The power conversion device (1) according to claim 2.

5. The current detection means detects the DC bus current when the semiconductor switch is on while the load is not in operation. The power conversion device (1) according to claim 1.

6. The current detection means detects the DC bus current when the semiconductor switch is on while the load is not in operation. The power conversion device (1) according to claim 2.

7. A first DC bus (11) to which a DC voltage is applied, and a second DC bus (12) which is at a lower potential than the first DC bus, A capacitor (4) connected between the first DC bus and the second DC bus, An inverter circuit (6) connected to the first DC bus and the second DC bus, which converts the DC power supplied to the first DC bus and the second DC bus to supply AC power to the load, An overvoltage protection circuit (5) is connected between the first DC bus and the second DC bus to protect the inverter circuit from overvoltage, A current detection means (7) for detecting the DC bus current flowing through the first DC bus or the second DC bus between the capacitor and the overvoltage protection circuit, The capacitor and a DC power supply circuit (2) that supplies power to the first DC bus and the second DC bus, Equipped with, The overvoltage protection circuit includes a semiconductor switch (52) and a resistor (51) connected in series between the first DC bus and the second DC bus. The first closed circuit (CL1) formed by the capacitor, the overvoltage protection circuit, and a portion of the first DC bus and a portion of the second DC bus connecting the capacitor and the overvoltage protection circuit includes a first current path (CP1) in which the resistor and the semiconductor switch are arranged in series, and when the semiconductor switch is ON, current flows through the first current path. The current detection means can detect a first current value flowing through the first closed circuit, a third current value flowing through the third closed circuit (CL3) including the capacitor and the DC power supply circuit, and the sum of the first and third current values. Power converter (1).

8. The current detection means detects the DC bus current before and after the semiconductor switch is turned on, or before and after the semiconductor switch is turned off. The power conversion device (1) according to claim 7.

9. The current detection means detects the DC bus current when the semiconductor switch is on while the load is not in operation. The power conversion device (1) according to claim 7.

10. The system includes a control unit (20) that determines whether the overvoltage protection circuit is normal or abnormal based on the DC bus current detected by the current detection means. A power conversion device (1) according to any one of claims 1 to 9.

11. The inverter circuit does not perform overcurrent protection using the value of the DC bus current detected by the current detection means during the period when the semiconductor switch is ON, and performs said overcurrent protection using the value of the DC bus current detected by the current detection means during the period when the semiconductor switch is OFF, comprising an overcurrent protection unit (20), The power conversion device (1) according to claim 3 or claim 4.

12. The overvoltage protection circuit turns on the semiconductor switch before the start of driving each time the inverter circuit starts driving the load. The power conversion device (1) according to claim 10.

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