Photoelectric converter, photoelectric converter system

Abstract

To provide a photoelectric conversion device having an avalanche diode capable of ensuring reliability.SOLUTION: A first electrode to which a first voltage is supplied from outside of the photoelectric conversion device is provided in a first multilayer wiring layer or a second multilayer wiring layer. The first electrode is not electrically connected to a second semiconductor layer.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to the structure of a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] There is known a photoelectric conversion device that can detect weak light at the single photon level by using avalanche (electron avalanche) multiplication. Patent Document 1 discloses a photoelectric conversion device in which both a sensor chip in which a plurality of pixels are arranged and a circuit chip in which a circuit for signal processing is formed are electrically connected in a stacked structure. It is disclosed that an avalanche diode that causes charge avalanche multiplication is used for the pixels in the sensor chip of this photoelectric conversion device.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, no consideration has been given to the wiring when supplying a high voltage for driving the avalanche diode in the stacked structure, and ensuring the reliability of the photoelectric conversion device has not been sufficient.

Means for Solving the Problems

[0006] The photoelectric conversion device according to the present invention makes it possible to provide a photoelectric conversion device having an avalanche diode that can ensure reliability. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic diagram of a photoelectric converter, pixel chip, and circuit chip according to the first embodiment. [Figure 2] This is a block diagram of pixels according to the first embodiment. [Figure 3] This is a cross-sectional view of a photoelectric converter according to the first embodiment. [Figure 4] This is a plan view of a photoelectric converter according to the first embodiment. [Figure 5] This is a cross-sectional view of a photoelectric converter according to a second embodiment. [Figure 6] This is a cross-sectional view of a photoelectric converter according to a third embodiment. [Figure 7] This is a plan view of a photoelectric converter according to the third embodiment. [Figure 8] This is a cross-sectional view of a photoelectric converter according to the fourth embodiment. [Figure 9] This is a plan view of a photoelectric converter according to the fourth embodiment. [Figure 10] This is a cross-sectional view of a photoelectric converter according to the fifth embodiment. [Figure 11] This is a plan view of a photoelectric converter according to the fifth embodiment. [Figure 12]Cross-sectional view of a photoelectric conversion device according to the sixth embodiment. [Figure 13] Block diagram showing the schematic configuration of the seventh embodiment. [Figure 14] Schematic diagram of a photoelectric conversion system and a moving body according to the eighth embodiment. [Figure 15] Flowchart showing the operation of the photoelectric conversion system according to the eighth embodiment.

Embodiments for Carrying Out the Invention

[0008] A photoelectric conversion device according to an embodiment of the present invention will be described. Since the common reference numerals in each embodiment denote the same member or members having the same function and effect, the description may be omitted. Also, the configurations described in each embodiment can be mutually replaced with the configurations described in other embodiments.

[0009] [First Embodiment] FIG. 1(A) is a diagram showing the configuration of a stacked photoelectric conversion device according to an embodiment of the present invention. The photoelectric conversion device 1010 is composed of two chips, a sensor chip 11 and a circuit chip 21, which are stacked and electrically connected.

[0010] A pixel region 12 is arranged in the sensor chip 11, and a circuit region 22 for processing the signal detected in the pixel region 12 is arranged in the circuit chip 21.

[0011] FIG. 1(B) is an arrangement diagram of the sensor chip 11. Pixels 100 having a photoelectric conversion unit 101 for converting light into an electrical signal are arranged two-dimensionally to form the pixel region 12. The pixel 100 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. That is, the pixel 100 may be a pixel for measuring the time when light arrives and the amount of light.

[0012] FIG. 1(C) is a configuration diagram of the circuit chip 21. It has a signal processing unit 102 that processes the charges photoelectrically converted by the photoelectric conversion unit 101 in FIG. 1(B), a control pulse generation unit 109, a horizontal scanning circuit unit 104, a signal line 107, and a vertical scanning circuit unit 103.

[0013] The photoelectric conversion unit 101 in FIG. 1(B) and the signal processing unit 102 in FIG. 1(C) are electrically connected via connection wirings provided for each pixel.

[0014] The vertical scanning circuit unit 103 receives the control pulses supplied from the control pulse generation unit 109 and supplies the control pulses to each pixel. Logic circuits such as a shift register and an address decoder are used in the vertical scanning circuit unit 103.

[0015] The signals output from the photoelectric conversion unit 101 of each pixel are processed by the signal processing unit 102. The signal processing unit 102 is provided with a counter and a memory, and digital signals are held in the memory.

[0016] The horizontal scanning circuit unit 104 inputs control pulses for sequentially selecting each column to the signal processing unit 102 in order to read signals from the memories of each pixel in which digital signals are held.

[0017] Signals are output from the signal processing unit 102 of the pixels selected by the vertical scanning circuit unit 103 to the signal line 107 and the signal line 105 for the selected columns.

[0018] The signals output to the signal line 105 are output to a recording unit or a signal processing unit outside the photoelectric conversion device 1010 via the output circuit 108.

[0019] In Figure 1(B), the arrangement of pixels 100 in the pixel region 12 may be one-dimensional. Furthermore, the vertical scanning circuit section 103 and the horizontal scanning circuit section 104 may be arranged in separate sections of the circuit region 22, divided into multiple regions. The functions of the signal processing unit 102 do not necessarily need to be provided for every pixel 100; for example, a single signal processing unit 102 may be shared by multiple pixels 100, and signal processing may be performed sequentially.

[0020] Figure 2 is an example of a block diagram including the equivalent circuits of Figures 1(B) and 1(C). In Figure 2, the photoelectric conversion unit 101 having a photodiode 201 is provided on the sensor chip 11, and the other components are provided on the circuit chip 21.

[0021] The photodiode 201 generates charge pairs corresponding to the incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the photodiode 201. In addition, a voltage VH (second voltage), which is higher than the voltage VL supplied to the anode, is supplied to the cathode of the photodiode 201. Although not shown, the voltage VH (second voltage) is also supplied to a circuit provided on the circuit chip 21. A reverse bias voltage is supplied to the anode and cathode of the photodiode 201 so that the photodiode 201 behaves as an avalanche diode. By supplying such a voltage, the charge generated by the incident light undergoes avalanche multiplication, and an avalanche current is generated. When a reverse bias voltage is supplied, if the potential difference between the anode and cathode is greater than the breakdown voltage, the avalanche diode operates in Geiger mode. For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 1.1V.

[0022] The quench element 202 is connected to a power supply that provides voltage VH and to the photodiode 201. The quench element 202 has the function of converting the change in avalanche current generated in the photodiode 201 into a voltage signal. When the signal is amplified by avalanche multiplication, the quench element 202 functions as a load circuit (quench circuit) and suppresses the voltage supplied to the photodiode 201, thereby suppressing avalanche multiplication (quench operation). The photodiode 201 provided on the sensor chip 11 and the quench element 202 provided on the circuit chip 21 are electrically connected via connection wiring provided for each pixel.

[0023] The signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. In this specification, the signal processing unit 102 may include any of the waveform shaping unit 203, the counter circuit 209, or the selection circuit 206. For example, the counter circuit 209 is also part of the signal processing unit 102.

[0024] The waveform shaping unit 203 shapes the potential change at the cathode of the photodiode 201 obtained during photon detection and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 203. In Figure 2, an example using one inverter as the waveform shaping unit 203 is shown, but a circuit with multiple inverters connected in series may be used, or other circuits that have a waveform shaping effect may be used.

[0025] The counter circuit 209 counts the pulse signals output from the waveform shaping unit 203. For example, if the counter circuit 209 is an N-bit counter (N: a positive integer), it can count up to approximately 2 to the power of N pulse signals from single photons. The counted signals are held as detected signals. Furthermore, when a control pulse pRES is supplied via the drive line 207, the signals held in the counter circuit 209 are reset.

[0026] The selection circuit 206 receives a control pulse pSEL from the vertical scanning circuit section 103 in Figure 1(C) via the drive line 208 (not shown in Figure 1(C)) in Figure 2, which switches the electrical connection between the counter circuit 209 and the signal line 107. The selection circuit 206 includes, for example, a buffer circuit for outputting a signal.

[0027] A switch such as a transistor may be placed between the quench element 202 and the photodiode 201, or between the photoelectric conversion unit 101 and the signal processing unit 102, to switch the electrical connection. Similarly, the supply of voltage VH or voltage VL to the photoelectric conversion unit 101 may be electrically switched using a switch such as a transistor.

[0028] In a pixel region 12 where multiple pixels are arranged in a matrix, the captured image may be acquired by a rolling shutter operation in which the count of the counter circuit 209 is sequentially reset row by row and the signals held by the counter circuit 209 are sequentially output row by row. Alternatively, the captured image may be acquired by a global electronic shutter operation in which the count of the counter circuit 209 for all pixel rows is simultaneously reset and the signals held by the counter circuit 209 are sequentially output row by row. When performing a global electronic shutter operation, it is preferable to provide a means to switch between when to perform the count of the counter circuit 209 and when not to perform it. The means for switching is, for example, the switch described above.

[0029] In this embodiment, a configuration using a counter circuit 209 is shown. However, instead of the counter circuit 209, a photoelectric converter 1010 may be used that acquires pulse detection timing using a time-to-digital converter (TDC) and memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. The TDC is supplied with a control pulse pREF (reference signal) via a drive line from the vertical scanning circuit unit 103 in Figure 1(C) to measure the timing of the pulse signal. The TDC acquires the signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 203 is relative to the control pulse pREF.

[0030] (Cross-sectional view of the photoelectric converter according to this embodiment: Figure 3) Figure 3 is a cross-sectional view of the photoelectric converter of this embodiment. In this embodiment, the first chip 301 and the second chip 401 are stacked and electrically connected.

[0031] (Configuration of the first chip 301) The first chip 301 has a pixel area 521. The second chip 401 has a circuit area 531 that processes the signal detected in the pixel area 521. The first chip 301 and the second chip 401 correspond to the sensor chip 11 and circuit chip 21 in Figure 1(A), respectively.

[0032] The first chip 301 consists of a semiconductor layer 311 (first semiconductor layer) and a wiring layer 312 (first wiring layer). The light incident surface of the first chip 301 is referred to as surface 313 (first surface), and the surface opposite to surface 313 is referred to as surface 314 (second surface) in the following explanation.

[0033] The semiconductor layer 311 of the first chip 301 contains a first semiconductor region 321 of the first conductivity type and a second semiconductor region 322 of the second conductivity type. The first semiconductor region 321 and the second semiconductor region 322 form a PN junction, which becomes an avalanche diode 324.

[0034] Here, the semiconductor region in the photoelectric conversion section that has charge pairs used as signal charges as majority carriers is called the first conductivity type semiconductor region. The semiconductor region that has charge pairs not used as signal charges as majority carriers is called the second conductivity type semiconductor region. For example, when electrons are used as signal charges, the first conductivity type semiconductor region is composed of an n-type semiconductor, and the second conductivity type semiconductor region is composed of a p-type semiconductor. The opposite is true when holes are used as signal charges. In this embodiment, we will explain the case where electrons are used as signal charges.

[0035] At both ends of the first semiconductor region 321, a third semiconductor region 323 of either a first or second conductivity type is provided to mitigate electric field concentration. In this case, the impurity concentration of the third semiconductor region 323 is lower than that of the first semiconductor region 321. For example, if the impurity concentration of the first semiconductor region 321 is 6.0 × 10⁻¹⁰ 18 When the concentration is [atms / cm3] or higher, the impurity concentration in the third semiconductor region 323 is 1.0 × 10⁻⁶. 16 [atms / cm3] or more, 1.0×10 18 [atms / cm3] should be as follows:

[0036] A fourth semiconductor region 325 of the second conductivity type is arranged in the region on the surface 313 side that is deeper than the second semiconductor region 322. Furthermore, a fifth semiconductor region 326 of the second conductivity type is arranged between adjacent pixels as an inter-pixel isolation region, and a sixth semiconductor region 327 of the second conductivity type is arranged in the region on the surface 313 side that is deeper than the fourth semiconductor region 325.

[0037] Here, the impurity concentrations in the fifth semiconductor region 326 and the sixth semiconductor region 327 are made higher than the impurity concentration in the fourth semiconductor region 325. As a result, the charge converted photoelectrically in the fourth semiconductor region 325 is collected in the avalanche diode 324 without leaking to adjacent pixels, enabling avalanche amplification.

[0038] A pinning film 341 is provided at the interface on the surface 313 side of the first chip 301 to suppress dark current generated at the chip interface.

[0039] A multilayer wiring layer 331 (first multilayer wiring layer) is arranged on the wiring layer 312 of the first chip 301. This multilayer wiring layer 331 is, for example, a wiring layer that provides the anode potential to the avalanche diode 324 and a wiring layer that provides the cathode potential. The signal detected by the avalanche diode 324 is sent to the second chip 401 via the multilayer wiring layer 331 and the junction 332 (first junction).

[0040] A pad electrode 511 (first electrode) is provided at the bottom of the pad opening 501 (first opening). The pad opening 501 is an opening that exposes the pad electrode 511 in order to conduct electricity between the pad electrode 511 and an external power supply. The bottom of the pad opening 501 is provided between the surface 313 (first surface) and surface 314 (second surface) of the first chip 301. A voltage necessary to cause avalanche multiplication at the junction of the first semiconductor region 321 of the first conductivity type and the second semiconductor region 322 of the second conductivity type is applied to the pad electrode 511 (first electrode) via wire bonding. When the top layer of the multilayer wiring layer 331 is the pad electrode 511, the top layer of the multilayer wiring layer 331 may be made of aluminum wiring, and the other wiring layers may be made of copper wiring.

[0041] A trench oxide film 541 is arranged on the semiconductor layer 311. Semiconductor chips with various circuits and pixels need to be protected from moisture and ions that enter from the surrounding atmosphere. Therefore, to protect against moisture and ions entering from pad openings 501, etc., a trench oxide film 541 is arranged on the semiconductor layer 311 around the pad opening 501. In addition, a trench oxide film 541 is also arranged on the semiconductor layer 311 around the pad openings 502 and 503, which will be described later. To further enhance moisture resistance, metal wiring may be arranged in place of, or in addition to, the trench oxide film. This metal wiring can protect the elements from moisture and ions that enter the wiring layer.

[0042] (Configuration of the second chip 401) The second chip 401 has a semiconductor layer 411 (second semiconductor layer) and a wiring layer 412 (second wiring layer). In the second chip 401, the side facing the first chip 301 is referred to as the surface 414 (third surface), and the side opposite to surface 414 is referred to as the surface 413 (fourth surface) for the following explanation.

[0043] The semiconductor layer 411 of the second chip 401 contains a circuit for processing signals sent from the first chip 301. Specifically, a well region 422, a gate electrode 423, and a source / drain region 424 are provided to form a single MOS transistor 425. An example of a MOS transistor 425 provided on the second chip 401 is a quench element. The quench element corresponds to element 202 in Figure 2 and functions as a load circuit when the photoelectrically converted charge is avalanche multiplied. It suppresses the voltage supplied to the avalanche diode 324, thus acting as a quench to suppress avalanche multiplication.

[0044] An element isolation region 421 is placed between adjacent MOS transistors. Examples of element isolation regions 421 include LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation).

[0045] The junction 432 (second junction) located in the wiring layer 412 of the second chip 401 contacts the junction 332 (first junction) of the first chip 301 and serves to send the output of the avalanche diode 324 of the first chip 301 to the second chip 401. This junction is made of metal wiring such as copper wiring.

[0046] A multilayer wiring layer 431 (second multilayer wiring layer) is provided on the wiring layer 412 of the second chip 401. This multilayer wiring layer 431 is used, for example, to transmit signals sent from the first chip 301 to the processing circuit of the second chip 401, as well as to power supply wiring and ground wiring to drive the signal processing unit 102 mounted on the second chip 401.

[0047] A ground region 441 is provided in the semiconductor layer 411 of the second chip 401. The ground potential voltage (ground voltage; third voltage) is supplied to the ground region 441 through a pad electrode 513 (third electrode) located at the bottom of the pad opening 503 (third opening). The bottom of the pad opening 503 is located between the surface 414 (third surface) and surface 413 (fourth surface) of the second chip 401. The third voltage is, for example, 0V. In Figure 3, the voltage applied from the pad electrode 513 (third electrode) is supplied to the ground region 41, but it is not necessary to provide a ground region 411. In this case, the voltage applied from the pad electrode 513 (third electrode) is supplied directly to other circuit elements.

[0048] Furthermore, a predetermined potential is supplied to the drain electrode of the MOS transistor 425, which is located on the second chip 401, through a pad electrode 512 (second electrode) located at the bottom of the pad opening 502 (second opening). The bottom of the pad opening 502 is located between the surface 414 (third surface) and surface 413 (fourth surface) of the second chip 401. As described above, the MOS transistor 425 is a quench element that functions as a load circuit when a signal is multiplied by avalanche multiplication, for example. In this case, the predetermined potential is such that the voltage VH (second voltage) is, for example, 1.1V. Since the voltage VL (first voltage) is, for example, -30V, the potential difference between the voltage VL (first voltage) and the voltage VH (second voltage) is greater than the potential difference between the voltage VH (second voltage) and the ground potential voltage (third voltage). Furthermore, the potential difference between voltage VL (first voltage) and the ground potential voltage (third voltage) is greater than the potential difference between voltage VH (second voltage) and the ground potential voltage (third voltage).

[0049] Figure 4(A) shows a plan view of the dashed line AA' in Figure 3. A plan view refers to the arrangement of the photoelectric converter 1010 when viewed from a direction perpendicular to the main surface of the semiconductor layer 311 or 411 (the normal direction of the main surface). When viewed from a plan view, overlapping components are assumed to be transparent.

[0050] In Figure 4(A), within the pixel region 521, junctions 332 for sending signals generated by each pixel to the second chip 401 are arranged in a two-dimensional manner. That is, multiple junctions 332 are arranged in both the first direction 550 (row direction) and the second direction 560 (column direction) which is orthogonal to the first direction 550. Outside the pixel region 521, multiple pad electrodes 511, 512, and 513 are arranged.

[0051] In the second direction 560 (column direction), the lengths of the pad electrodes 511, 512, and 513 are greater than the length of the junction 332. That is, one pad electrode is provided corresponding to the junction 332 which is provided in multiple rows (two rows in Figure 4(A)). This is because the potential supplied from each pad electrode can be configured to be supplied commonly to pixels in multiple rows. Furthermore, if one pad electrode were to be placed corresponding to one row, a pad electrode would need to be placed for each pixel pitch, which would be unsuitable for miniaturization.

[0052] Furthermore, in Figure 4(A), even in the first direction 550 (row direction), the lengths of the pad electrodes 511, 512, and 513 are greater than the length of the joint 332. As a result, the area of ​​each pad electrode 511, 512, and 513 is greater than the area of ​​the joint 332.

[0053] Furthermore, in Figure 4(A), instead of providing one pad electrode for all rows of junctions 332, one pad electrode is provided for a predetermined number of junctions 332 that are fewer than the total number of rows. In this embodiment, since the pixel portion includes an avalanche diode, an avalanche current flows through the pad electrode that provides potential to the pixel. If one pad electrode were provided for all rows, it would be possible to exceed the limit on the allowable current that can flow through a single pad electrode. Therefore, one pad electrode is provided for a predetermined number of junctions that are not all rows.

[0054] In Figure 4(A), an example is shown where the length of the pad electrode is greater than the length of the joint in both the first direction 550 and the second direction 560. However, the pitch may be increased by increasing the length in only one of the directions.

[0055] Furthermore, although Figure 4(A) shows one pad electrode for multiple rows, it is also possible to configure it so that one pad electrode is placed for multiple columns.

[0056] Furthermore, in Figure 4(A), the pad electrodes 511 are concentrated on the right side of the pixel region, and the pad electrodes 512 and 513 are concentrated on the left side of the pixel region. On the other hand, as shown in Figure 4(B), units consisting of pad electrodes 511, 512, and 513 may be arranged on the right and left sides of the pixel region, respectively. The avalanche-multiplied charge (electrons and holes) of each pixel is collected, for example, electrons are collected on the pad electrode 512 and holes are collected on the pad electrode 511. For example, in Figure 4(A), if electrons and holes are generated from the upper left pixel of the pixel region, the electrons are immediately collected on the pad electrode 512 located on the left side, but the holes are collected on the pad electrode 511 located on the right side after a predetermined time has elapsed. In this case, especially with respect to holes, the avalanche charge is accumulated for each pixel before it is collected on the pad electrode 511 located on the right side, which causes a voltage drop. On the other hand, in Figure 4(B), since the pad electrodes 511 and 512 are positioned on both the right and left sides, both avalanche-multiplied electrons and holes are collected in a short time, making it less likely for the voltage drop described above to occur. The arrangement shown in Figure 4(B) has the advantage of suppressing the occurrence of shading.

[0057] A voltage VH (second voltage) is supplied from the pad electrode 512 to the first semiconductor region 321 of the first conductivity type of the avalanche diode 324 located on the first chip 301. This voltage supply involves the MOS transistor 425, the multilayer wiring layer 431 of the second chip, the junction 432 of the second chip, the junction 332 of the first chip, and the multilayer wiring layer 331 of the first chip. In addition, a voltage VL (first voltage) is supplied to the second semiconductor region 322 of the second conductivity type via the pad electrode 511, the multilayer wiring layer 331, the fifth semiconductor region 326 of the second conductivity type, and the fourth semiconductor region 325 of the second conductivity type, located on the first chip. The voltage difference between voltage VL (first voltage) and voltage VH (second voltage) is assumed to be sufficient to create an electric field at the junction of the first semiconductor region 321 of the first conductivity type and the second semiconductor region 322 of the second conductivity type to cause avalanche multiplication. The required voltage difference is, for example, 6V or more, and the example above described a value of 31.1V.

[0058] Incidentally, the circuit region 531 of the second chip requires the placement of small transistors with low drive voltages in order to increase the integration density of the processing circuits. On the other hand, the voltage VL (first voltage) applied to the pad electrode 511 is a voltage required only for the first chip 301, which is provided with an avalanche photodiode, and does not need to be supplied to the circuit region 531 of the second chip. Therefore, in this embodiment, the pad electrode 511 is configured not to be electrically connected to the semiconductor layer 411 of the second chip 401. Specifically, the wiring electrically connected to the pad electrode 511 is configured not to cross the boundary of the junction surface between the first chip 301 and the second chip 401. This makes it possible to suppress a decrease in the reliability of the circuit region 531 of the second chip.

[0059] Furthermore, the potential applied to the pad electrode 512 is supplied not only to the MOS transistor 425 but also to various processing circuits located on the second chip 401. As the functions required of the processing circuits increase and the number of elements mounted on the second chip 401 increases, high speed may become an issue. In this case, it is preferable to place the pad electrode 512 on the second chip 401 and supply the potential, as shown in Figure 3, rather than placing the pad electrode 512 on the first chip 301 and supplying the potential via the junction. This configuration reduces propagation delay due to wiring, making it possible to operate the various processing circuits located on the second chip 401 at higher speeds.

[0060] Furthermore, the pad electrode 511 on the first chip 301 is positioned on a wiring layer at the same height as the uppermost wiring of the multilayer wiring layer 331 of the first chip 301. The pad electrodes 512 and 513 on the second chip 401 are positioned on a wiring layer at the same height as the uppermost wiring of the multilayer wiring layer 431 of the second chip. In this specification, the multilayer wiring layers 331 and 431 do not include the joint portions 332 and 432. This reduces the step difference between the pad electrodes on the first chip 301 and the second chip 401, making the etching process at the pad opening easier. In addition, this configuration makes it easier to form wire bonding at the pad opening.

[0061] [Second Embodiment] Figure 5 is a cross-sectional view of a photoelectric converter according to the second embodiment. The difference from the first embodiment is that the pad electrodes 512 and 513 are arranged on the first chip 301, and potential is supplied to the second chip via the junctions 333 and 433. A description of the same components as in the first embodiment is omitted.

[0062] As shown in Figure 3, in the first embodiment, the depths of pad opening 501 and pad openings 502 and 503 are different, so it is necessary to apply etching conditions and wire bonding conditions that are optimal for each pad opening depth. On the other hand, in the second embodiment shown in Figure 5, pad electrodes 511, 512 and 513 are formed on the first chip 301. That is, the bottoms of pad openings 501, 502 and 503 are provided between surface 313 (first surface) and surface 314 (second surface) of the first chip 301. With this configuration, it is possible to make the depths of pad openings 501, 502 and 503 the same compared to the first embodiment. Therefore, it is no longer necessary to optimize the etching conditions and wire bonding conditions for each pad when forming the pad openings.

[0063] It is desirable that the pad electrodes 511, 512, and 513 be provided on the same wiring layer of the multilayer wiring layer 331 of the first chip 301. Specifically, in Figure 5, the pad electrodes 511, 512, and 513 are provided on the uppermost layer of the multilayer wiring layer 331. As a result, the depth of each pad opening is the same, so the etching conditions for forming the pad openings and the conditions for forming the wire bonding can be made the same, and these can be formed in the same process.

[0064] In Figure 5, the pad electrodes 512 and 513 and the junction 333 are connected by multiple via plugs. That is, one pad electrode and one junction are connected by multiple via plugs. Similarly, the wiring on the uppermost layer of the multilayer wiring layer 431 provided on the second chip 401 and the junction 433 are connected by multiple via plugs. This reduces electrical resistance and suppresses signal propagation delay.

[0065] Incidentally, as explained in the first embodiment, of the voltages used to avalanche-multiply the avalanche diode 324, a voltage VL (first voltage) is applied to the pad electrode 511 of the first chip. This voltage is routed through the multilayer wiring layer 331 provided on the first chip 301 and is therefore not supplied to the circuit region 531 of the second chip 401. In other words, a decrease in the reliability of the circuit region 531 located on the second chip 401 can be suppressed.

[0066] Note that the plan view including the dashed line AA' in Figure 5 is equivalent to that in Figure 3, so a detailed explanation will be omitted.

[0067] As described above, in the second embodiment, a decrease in reliability of the circuit region 531 of the second chip 401 can be suppressed. Furthermore, the process of forming pad openings and wire bonding can be simplified.

[0068] [Third Embodiment] Figure 6 is a cross-sectional view of a photoelectric converter according to the third embodiment. The difference from the first embodiment is that the pad electrode 511 is arranged on the second chip 401, and potential is supplied to the first chip 301 via the junctions 434 and 334. A description of the same components as in the first embodiment is omitted.

[0069] In the first embodiment, since the depths of pad opening 501 and pad openings 502 and 503 are different, it is necessary to apply etching conditions and wire bonding conditions that are optimal for each pad opening depth. On the other hand, in the third embodiment shown in Figure 6, pad electrodes 511, 512, and 513 are formed on the second chip 401. That is, the bottoms of pad openings 501, 502, and 503 are provided between the surface 414 (third surface) and surface 413 (fourth surface) of the second chip 401. With this configuration, it is possible to make the depths of pad openings 501, 502, and 503 the same compared to the first embodiment. Therefore, it is no longer necessary to optimize the etching conditions and wire bonding conditions for each pad when forming the pad openings.

[0070] As described in the first embodiment, the pad electrode 512 is located on the second chip 401, and its potential is supplied not only to the MOS transistor 425 but also to various processing circuits mounted on the second chip 401. Furthermore, as the functions required of the processing circuits increase and the number of elements mounted on the second chip 401 increases, high speed becomes an issue. In this case, it is preferable to place the pad electrode 512 on the second chip 401 and supply the potential, as shown in Figure 6, rather than placing the pad electrode 512 on the first chip 301 and supplying the potential via the junction. This configuration reduces propagation delay due to wiring, making it possible to operate the various processing circuits located on the second chip 401 at a higher speed.

[0071] Furthermore, in the third embodiment, the pad electrode 511 is configured not to be electrically connected to the semiconductor layer 411 of the second chip 401. This makes it possible to avoid deterioration of the reliability of the circuit region 531 of the second chip.

[0072] Figure 7 is a plan view of the dashed line AA' in Figure 6. Within the pixel region 521, junctions 332 for sending signals generated at each pixel to the second chip 401 are arranged in two dimensions. Outside the pixel region 521, pad electrodes 511, 512, and 513, which are to be placed on the second chip, are arranged. A junction 334 is provided to supply the voltage applied to the pad electrode 511 on the second chip 401 to the pixel region 521 of the first chip 301. In both the first direction 550 and the second direction 560, the length of the junction 334 is greater than the length of the junction 332. Therefore, the area of ​​the junction 334 is greater than the area of ​​the junction 332. The explanation for Figures 4(A) and 4(B) also applies to Figure 7.

[0073] As described above, in the third embodiment, it is possible to increase the speed of various processing circuits mounted on the second chip 401 while suppressing a decrease in the reliability of the circuit region 531 of the second chip. In addition, it is possible to simplify the process of forming pad openings and wire bonding.

[0074] [Fourth Embodiment] Figure 8 is a cross-sectional view of the photoelectric converter according to the fourth embodiment. The difference from the first embodiment is that through-silicon vias (TSVs) are used instead of wire bonding. The following description of the same components as in the first embodiment will be omitted.

[0075] Specifically, the wire bonding wiring provided at the bottom of the pad opening 501 in the first embodiment corresponds to the through electrode 504 in the fourth embodiment. Similarly, the wire bonding wiring at the bottom of the pad opening 502 corresponds to the through electrode 505, and the wire bonding wiring at the bottom of the pad opening 503 corresponds to the through electrode 506.

[0076] The pad electrode 511 (first electrode) in the first embodiment corresponds to the electrode 514 (first electrode) in the fourth embodiment. Similarly, the pad electrode 513 (second electrode) corresponds to the electrode 516 (second electrode), and the pad electrode 512 (third electrode) corresponds to the electrode 515. In other words, these electrodes are electrodes provided on the multilayer wiring layer 431 (second multilayer wiring layer) and are electrodes to which voltage is supplied from outside the photoelectric converter.

[0077] In the fourth embodiment, the bottom of the opening (first opening) formed to expose the electrode 514 in order to conduct electricity between the electrode 514 and an external power supply is provided between the surface 313 (first surface) and surface 314 (second surface) of the first chip 301. This point is also common to the first embodiment. Similarly, the bottoms of the openings (second and third openings) formed to expose the electrodes 516 and 515 are provided between the surface 414 (third surface) and surface 413 (fourth surface) of the second chip 401. This point is also common to the first embodiment. In this specification, even if electrodes are filled after the opening (trench) has been formed, the area where the opening was formed may be referred to as the "opening".

[0078] As in the first to third embodiments, when the electrode structure is wire-bonded wiring, extra space is required for mounting the wires relative to the chip size, making it difficult to miniaturize the package size. On the other hand, in the case of through-electrodes, the through-electrodes and the package substrate are connected via bumps, etc., making it possible to make the chip size and package size roughly the same. Therefore, similar to the first embodiment, which has an advantage in miniaturizing the package size compared to wire-bonded wiring, the potential applied to the through-electrode 504 is supplied to the pixel area 521 of the first chip 301 via electrode 514. Also, the potential applied to the through-electrodes 505 and 506 is supplied to the semiconductor layer 411 corresponding to the circuit area 531 of the second chip 401 via electrodes 515 and 516, respectively. On the other hand, the potential applied to the through-electrode 504 is not supplied to the circuit area 531 of the second chip 401. Therefore, similar to the first embodiment, it is possible to suppress the degradation of the reliability of the circuit area 531 located on the second chip 401. Furthermore, since the through-electrode 505 is located on the second chip 401, it becomes possible to operate the various processing circuits located on the second chip 401 at a higher speed.

[0079] Furthermore, the electrode 514 on the first chip 301 is placed on a wiring layer at the same height as the top layer wiring of the multilayer wiring layer 331 of the first chip 301, and the electrodes 515 and 516 on the second chip 401 are placed on a wiring layer at the same height as the top layer wiring of the multilayer wiring layer 431 of the second chip 401.

[0080] Through-electrodes are formed by etching to create openings (trenches) that penetrate the semiconductor layer 411, and then filling these openings with metal, which will serve as the electrode material. When etching trenches corresponding to multiple through-electrodes, it is easier to process if the difference in trench depth is small. For this reason, as described above, by placing the electrodes that contact the through-electrodes in a wiring layer at the same height as the top layer wiring of each chip, the process of forming through-electrodes can be simplified.

[0081] Figure 9 is a plan view of the dashed line AA' in Figure 8. Within the pixel region 521, junctions 332 for sending signals generated by each pixel to the second chip 401 are arranged in two dimensions. Outside the pixel region 521, electrodes 514 in the first chip 301 and electrodes 515 and 516 in the second chip 401 are arranged, respectively. The explanation for Figures 4(A) and 4(B) also applies to Figure 9.

[0082] As described above, in the fourth embodiment, it is possible to achieve miniaturization of the package size, suppression of reliability degradation for the circuit area 531 of the second chip 401, and acceleration of various processing circuits mounted on the second chip 401.

[0083] [Fifth Embodiment] Figure 10 is a cross-sectional view of the fifth embodiment. The difference from the fourth embodiment is that electrodes 515 and 516 are arranged on the first tip 301. The same components as in the first embodiment will not be described.

[0084] In the fourth embodiment, since the electrodes 514 of the first chip and the electrodes 515 and 516 of the second chip are located in different places, the etching conditions during trench formation and the film deposition conditions when filling the trench with metal must be optimized according to the location of each electrode. On the other hand, in the fifth embodiment, by placing all through electrodes 514, 515, and 516 on the first chip, it becomes unnecessary to optimize the process conditions according to the location of each electrode, thus simplifying the process.

[0085] Furthermore, it is desirable that electrodes 514, 515, and 516 be provided on the same wiring layer of the multilayer wiring layer 331 of the first chip 301. Specifically, in Figure 10, electrodes 514, 515, and 516 are provided on the uppermost layer of the multilayer wiring layer 331. This ensures that the trench depth of each through electrode is the same, making it possible to use the same etching conditions when forming the trenches and the same film deposition conditions when filling the trenches with the metal electrode material, allowing these to be formed in the same process.

[0086] In Figure 10, electrodes 515 and 516 and the junction 335 are connected by multiple via plugs. That is, one electrode and one junction on the multilayer wiring layer are connected by multiple via plugs. Similarly, the wiring on the top layer of the multilayer wiring layer 431 on the second chip 401 and the junction 433 are connected by multiple via plugs. This reduces electrical resistance and suppresses signal propagation delay.

[0087] As explained in the first embodiment, of the voltages used to avalanche-multiply the avalanche diode 324, a voltage VL (first voltage) is applied to the electrode 514 of the first chip. This voltage is routed through the multilayer wiring layer 331 provided on the first chip 301 and is therefore not supplied to the circuit region 531 of the second chip 401. In other words, a decrease in the reliability of the circuit region 531 located on the second chip 401 can be suppressed.

[0088] Figure 11 is a plan view including the dashed line AA' in Figure 10. Within the pixel region 521, junctions 332 for sending signals generated at each pixel to the second chip 401 are arranged in two dimensions. Outside the pixel region 521, electrodes 514, 515, and 516 within the first chip 301, and junctions 335 for transmitting the applied potential of the electrodes to the second chip are arranged. The explanation for Figures 4(A) and 4(B) also applies to Figure 11.

[0089] As described above, in the fifth embodiment, it is possible to suppress the degradation of reliability of the circuit region 531 of the second chip 401. Furthermore, it is possible to simplify the through-electrode formation process.

[0090] [Sixth Embodiment] Figure 12 is a cross-sectional view of the photoelectric converter according to the sixth embodiment. The difference from the fourth embodiment is that the through electrode 514 is placed on the second chip 401. A description of the same components as in the fourth embodiment is omitted.

[0091] In the sixth embodiment, compared to the fourth embodiment, electrodes 514, 515, and 516 are arranged on the second chip, eliminating the need to optimize the etching conditions during trench formation and the film deposition conditions during metal filling of the trenches according to each electrode depth, thus simplifying the process.

[0092] It is desirable that electrodes 514, 515, and 516 be placed at the same depth within the second chip 401. This ensures that the trench depth for each through electrode is the same, allowing for the same etching conditions during trench formation and the same film deposition conditions when filling the trenches with the electrode material metal.

[0093] Furthermore, in the sixth embodiment, the potential applied to the through electrode 504 is supplied to the first chip 301 via the junctions 436 and 336, and is not supplied to the circuit region 531 of the second chip 401. Therefore, a decrease in the reliability of the circuit region 531 of the second chip can be suppressed.

[0094] The through-electrode 515 is positioned on the second chip 401, and its potential is supplied not only to the MOS transistor 425 but also to various processing circuits mounted on the second chip 401. As the functions required of the processing circuits increase and the number of elements mounted on the second chip 401 increases, high speed becomes an issue. In that case, positioning the through-electrode 515 on the second chip 401 and supplying the potential from there, rather than positioning it on the first chip 301 and supplying the potential via the junction, allows the various processing circuits on the second chip to operate at a higher speed. Note that the plan view including the dashed line AA' in Figure 12 is equivalent to Figure 9, so a detailed explanation is omitted.

[0095] As described above, in the sixth embodiment, it is possible to suppress the degradation of reliability of the circuit region 531 of the second chip 401, increase the speed of various processing circuits mounted on the second chip 401, and simplify the through-electrode formation process.

[0096] [Seventh Embodiment] Figure 13 is a region diagram showing the configuration of the photoelectric conversion system 1200 according to this embodiment. The photoelectric conversion system 1200 of this embodiment includes a photoelectric conversion device 1204. The photoelectric conversion device 1204 can be any of the photoelectric conversion devices described in the above embodiments. The photoelectric conversion system 1200 can be used, for example, as an imaging system. Specific examples of imaging systems include digital still cameras, digital camcorders, and surveillance cameras. In Figure 13, an example of a digital still camera is shown as the photoelectric conversion system 1200.

[0097] The photoelectric conversion system 1200 shown in Figure 13 includes a photoelectric conversion device 1204, a lens 1202 that forms an optical image of the subject onto the photoelectric conversion device 1204, an aperture 1203 that varies the amount of light passing through the lens 1202, and a barrier 1201 that protects the lens 1202. The lens 1202 and the aperture 1203 form an optical system that focuses light onto the photoelectric conversion device 1204.

[0098] The photoelectric conversion system 1200 has a signal processing unit 1205 that processes the output signal output from the photoelectric conversion device 1204. The signal processing unit 1205 performs signal processing operations that perform various corrections and compressions on the input signal as needed before outputting it. The photoelectric conversion system 1200 further has a buffer memory unit 1206 for temporarily storing image data, and an external interface unit (external I / F unit) 1209 for communicating with an external computer or the like. Furthermore, the photoelectric conversion system 1200 has a recording medium 1211 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1210 for recording or reading from the recording medium 1211. The recording medium 1211 may be built into the photoelectric conversion system 1200 or it may be detachable. In addition, communication from the recording medium control I / F unit 1210 to the recording medium 1211 and communication from the external I / F unit 1209 may be performed wirelessly.

[0099] Furthermore, the photoelectric conversion system 1200 includes an overall control and calculation unit 1208 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1207 that outputs various timing signals to the photoelectric conversion device 1204 and the signal processing unit 1205. Here, the timing signals and the like may be input from an external source, and the photoelectric conversion system 1200 only needs to have at least a photoelectric conversion device 1204 and a signal processing unit 1205 that processes the output signals output from the photoelectric conversion device 1204.

[0100] The overall control and calculation unit 1208 and the timing generation unit 1207 may be configured to perform some or all of the control functions of the photoelectric converter 1204.

[0101] The photoelectric converter 1204 outputs an image signal to the signal processing unit 1205. The signal processing unit 1205 performs predetermined signal processing on the image signal output from the photoelectric converter 1204 and outputs image data. The signal processing unit 1205 also generates an image using the image signal. The signal processing unit 1205 may also perform distance measurement calculations on the signal output from the photoelectric converter 1204. The signal processing unit 1205 and the timing generation unit 1207 may be mounted on the photoelectric converter. In other words, the signal processing unit 1205 and the timing generation unit 1207 may be provided on a chip on which pixels are arranged. By configuring an imaging system using the photoelectric converters of each embodiment described above, an imaging system capable of acquiring higher quality images can be realized.

[0102] [Eighth Embodiment] The photoelectric conversion system and mobile unit of this embodiment will be described with reference to Figures 14 and 15. Figure 14 is a schematic diagram showing an example configuration of the photoelectric conversion system and mobile unit according to this embodiment. Figure 15 is a flowchart showing the operation of the photoelectric conversion system according to this embodiment. In this embodiment, an example of an in-vehicle camera is shown as the photoelectric conversion system.

[0103] Figure 14 shows an example of a vehicle system and a photoelectric conversion system mounted thereon for imaging. The photoelectric conversion system 1301 includes a photoelectric converter 1302, an image preprocessing unit 1315, an integrated circuit 1303, and an optical system 1314. The optical system 1314 forms an optical image of the subject on the photoelectric converter 1302. The photoelectric converter 1302 converts the optical image of the subject formed by the optical system 1314 into an electrical signal. The photoelectric converter 1302 is one of the photoelectric converters in each of the embodiments described above. The image preprocessing unit 1315 performs predetermined signal processing on the signal output from the photoelectric converter 1302. The functions of the image preprocessing unit 1315 may be incorporated into the photoelectric converter 1302. The photoelectric conversion system 1301 is provided with at least two sets of optical systems 1314, photoelectric conversion devices 1302, and image preprocessing units 1315, and the output from each set of image preprocessing units 1315 is input to the integrated circuit 1303.

[0104] The integrated circuit 1303 is an integrated circuit for imaging system applications and includes an image processing unit 1304 with memory 1305, an optical distance measuring unit 1306, a distance measurement calculation unit 1307, an object recognition unit 1308, and an anomaly detection unit 1309. The image processing unit 1304 performs image processing such as development and defect correction on the output signal of the image preprocessing unit 1315. The memory 1305 stores the primary storage of the captured image and the location of defects in the captured pixels. The optical distance measuring unit 1306 focuses on the subject and measures the distance. The distance measurement calculation unit 1307 calculates distance measurement information from multiple image data acquired by multiple photoelectric converters 1302. The object recognition unit 1308 recognizes subjects such as cars, roads, signs, and people. When the anomaly detection unit 1309 detects an anomaly in the photoelectric converter 1302, it alerts the main control unit 1313 to the anomaly.

[0105] The integrated circuit 1303 may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination of these.

[0106] The main control unit 1313 coordinates and controls the operation of the photoelectric conversion system 1301, vehicle sensor 1310, control unit 1320, etc. Alternatively, there may be no main control unit 1313, and the photoelectric conversion system 1301, vehicle sensor 1310, and control unit 1320 may each have their own communication interfaces and send and receive control signals via a communication network (e.g., CAN standard).

[0107] The integrated circuit 1303 has the function of receiving control signals from the main control unit 1313 or transmitting control signals and set values ​​to the photoelectric converter 1302 via its own control unit.

[0108] The photoelectric conversion system 1301 is connected to the vehicle sensor 1310 and can detect the vehicle's driving conditions, such as vehicle speed, yaw rate, and steering angle, as well as the external environment and the state of other vehicles and obstacles. The vehicle sensor 1310 also serves as a distance information acquisition means for acquiring distance information to objects. Furthermore, the photoelectric conversion system 1301 is connected to the driver assistance control unit 1311, which performs various driving assistance functions such as automatic steering, automatic cruising, and collision avoidance. In particular, regarding the collision judgment function, it determines whether a collision with another vehicle or obstacle has occurred and estimates a collision based on the detection results of the photoelectric conversion system 1301 and the vehicle sensor 1310. This enables avoidance control when a collision is estimated and activation of safety devices in the event of a collision.

[0109] Furthermore, the photoelectric conversion system 1301 is also connected to a warning device 1312 that issues a warning to the driver based on the judgment result of the collision judgment unit. For example, if the collision judgment unit determines that there is a high probability of collision, the main control unit 1313 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1312 warns the user by sounding an alarm, displaying warning information on a display screen such as the car navigation system or instrument panel, or vibrating the seat belt or steering wheel.

[0110] In this embodiment, the photoelectric conversion system 1301 captures images of the area around the vehicle, for example, the front or rear. Figure 14(b) shows an example of the arrangement of the photoelectric conversion system 1301 when it captures images of the front of the vehicle.

[0111] The two photoelectric converters 1302 are positioned in front of the vehicle 1300. Specifically, it is preferable for the two photoelectric converters 1302 to be positioned symmetrically with respect to the axis of symmetry, considering the center line of the vehicle 1300's direction of movement or external shape (e.g., vehicle width), when acquiring distance information between the vehicle 1300 and the object being photographed and determining the possibility of collision. Furthermore, it is preferable that the photoelectric converters 1302 are positioned so as not to obstruct the driver's field of view when the driver is visually observing the situation outside the vehicle 1300 from the driver's seat. The warning device 1312 is preferably positioned so as to be easily visible to the driver.

[0112] Next, the fault detection operation of the photoelectric converter 1302 in the photoelectric conversion system 1301 will be explained using Figure 15. The fault detection operation of the photoelectric converter 1302 is performed according to steps S1410 to S1480 shown in Figure 15.

[0113] Step S1410 is a step in which the photoelectric converter 1302 is configured for startup. Specifically, settings for the operation of the photoelectric converter 1302 are transmitted from outside the photoelectric conversion system 1301 (e.g., the main control unit 1313) or from inside the photoelectric conversion system 1301, and the imaging operation and fault detection operation of the photoelectric converter 1302 are started.

[0114] Next, in step S1420, a pixel signal is acquired from the active pixels. Also, in step S1430, an output value is acquired from a fault detection pixel provided for fault detection. This fault detection pixel, like the active pixels, is equipped with a photoelectric conversion unit. A predetermined voltage is written to this photoelectric conversion unit. The fault detection pixel outputs a signal corresponding to the voltage written to this photoelectric conversion unit. Note that steps S1420 and S1430 may be reversed.

[0115] Next, in step S1440, a determination is made between the expected output value of the fault-detection pixel and the actual output value from the fault-detection pixel. If the determination in step S1440 shows that the expected output value and the actual output value match, the process proceeds to step S1450, where it is determined that the imaging operation is functioning normally, and the process moves to step S1460. In step S1460, the pixel signals of the scanned row are transmitted to the memory 1305 for temporary storage. After that, the process returns to step S1420 and continues the fault detection operation. On the other hand, if the determination in step S1440 shows that the expected output value and the actual output value do not match, the process proceeds to step S1470. In step S1470, it is determined that there is an abnormality in the imaging operation, and an alarm is issued to the main control unit 1313 or the alarm device 1312. The alarm device 1312 displays that an abnormality has been detected on its display unit. Subsequently, in step S1480, the photoelectric converter 1302 is stopped, and the operation of the photoelectric converter system 1301 is terminated.

[0116] In this embodiment, an example is shown where the flowchart is looped every row, but the flowchart may be looped every multiple rows, or the fault detection operation may be performed every frame. The alarm in step S1470 may be notified to an external party via a wireless network.

[0117] Furthermore, although this embodiment describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically drives without deviating from the lane. In addition, the photoelectric conversion system 1301 can be applied not only to vehicles such as the vehicle itself, but also to mobile objects (mobile devices) such as ships, aircraft, or industrial robots. Moreover, it can be applied not only to mobile objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0118] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0119] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features. [Explanation of Symbols]

[0120] 301 First chip 401 Second chip 324 Avalanche Diode 521 pixel area 531 Circuit area 501, 502, 503 Pad opening 511, 512, 513 Pad electrodes

Claims

1. A first chip having a first semiconductor layer equipped with an avalanche diode and a first multilayer wiring layer, The second chip comprises a second semiconductor layer having a signal processing unit that processes a signal based on the output from the avalanche diode, and a second multilayer wiring layer, The first chip and the second chip are stacked and bonded together. The first chip has a first bonding portion, The second chip has a second joint that contacts the first joint, The avalanche diode is supplied with a first voltage and a second voltage. The signal processing unit is supplied with a third voltage. The potential difference between the first voltage and the third voltage is greater than the potential difference between the second voltage and the third voltage. A first electrode, to which the first voltage is supplied from outside the first chip and the second chip, is provided in the first multilayer wiring layer or the second multilayer wiring layer. The second electrode, to which the second voltage is supplied from outside the first chip and the second chip, is provided in the same wiring layer as the wiring layer on which the first electrode is provided, among the first multilayer wiring layer or the second multilayer wiring layer. A photoelectric conversion device characterized in that the first electrode is not electrically connected to the second semiconductor layer.

2. The photoelectric conversion device according to claim 1, characterized in that the first voltage is a negative voltage.

3. The photoelectric conversion device according to claim 1 or 2, characterized in that the potential difference between the first voltage and the second voltage is greater than the breakdown voltage of the avalanche diode.

4. A first chip having a first semiconductor layer equipped with an avalanche diode, The chip comprises a second semiconductor layer having a second semiconductor layer equipped with a signal processing unit that processes a signal based on the output from the avalanche diode, The first chip and the second chip are stacked and bonded together. The first chip has a first bonding portion, The second chip has a second joint that contacts the first joint, The avalanche diode is supplied with a first voltage, which is a negative voltage, and a second voltage, which is a positive voltage. A first electrode, to which the first voltage is supplied from outside the first chip and the second chip, is provided between the surface of the first semiconductor layer and the surface of the second semiconductor layer facing the junction surface between the first chip and the second chip. The second electrode, to which the second voltage is supplied from outside the first chip and the second chip, is provided at the same height as the first electrode between the surface of the first semiconductor layer and the surface of the second semiconductor layer facing the junction surface. A photoelectric conversion device characterized in that the first electrode is not electrically connected to the second semiconductor layer.

5. The first chip has a first multilayer wiring layer, The photoelectric conversion device according to claim 4, characterized in that the second chip has a second multilayer wiring layer.

6. A third voltage is supplied from outside the first and second chips. The photoelectric conversion device according to claim 5, characterized in that the potential difference between the first voltage and the third voltage is greater than the potential difference between the second voltage and the third voltage.

7. The photoelectric conversion device according to claim 6, characterized in that the potential difference between the first voltage and the second voltage is greater than the breakdown voltage of the avalanche diode.

8. The photoelectric conversion device according to any one of claims 1 to 7, characterized in that the quench element that suppresses avalanche multiplication of the avalanche diode is arranged on the second chip.

9. The photoelectric conversion device according to any one of claims 1 to 3, 6, or 7, characterized in that the third electrode, to which the third voltage is supplied from outside the first chip and the second chip, is provided in the first multilayer wiring layer or the second multilayer wiring layer.

10. The photoelectric converter according to any one of claims 1 to 3, 6, 7, or 9, characterized in that the third voltage is a ground voltage.

11. The bottom of the first opening that exposes the first electrode is provided between the first surface of the first chip and the second surface of the first chip opposite to the first surface. The photoelectric conversion device according to any one of claims 1 to 10, characterized in that the bottom of the second opening that exposes the second electrode is provided between the first surface and the second surface.

12. The first and second openings are formed through the second semiconductor layer, The photoelectric conversion device according to claim 11, characterized in that electrodes are filled in the first and second openings.

13. The photoelectric conversion device according to claim 12, characterized in that the electrode is in contact with the first electrode at the bottom of the first opening and is in contact with the second electrode at the bottom of the second opening.

14. The avalanche diode is electrically connected to the quench element via the first junction and the second junction. The photoelectric conversion device according to claim 8, characterized in that, in a plan view, the length of the first electrode in a predetermined direction is greater than the length of the first junction.

15. The photoelectric conversion device according to any one of claims 1 to 13, characterized in that the first voltage supplied to the first electrode is not applied to the junction surface in which the first junction and the second junction are in contact.

16. A photoelectric conversion device according to any one of claims 1 to 15, A photoelectric conversion system characterized by having a signal processing device that processes the signal output by the aforementioned photoelectric conversion device.

17. The photoelectric conversion system according to claim 16, characterized in that the signal processing device performs distance measurement and imaging based on the signal from the photoelectric conversion device.

18. A photoelectric conversion device according to any one of claims 1 to 15, A mobile body having distance information acquisition means for acquiring distance information to an object from distance measurement information based on a signal from the aforementioned photoelectric converter, A mobile body further comprising control means for controlling the mobile body based on the distance information.

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