Vertical transistor cell structure utilizing upper and lower resources

Abstract

Various structures are disclosed that implement topside metal routing and backside metal routing in combination with vertical transistors. The various structures include cells that form inverter, NAND, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors, including either connected gate logic for inverter and NAND devices, or disconnected gate logic for MUX devices.

Description

Technical Field

[0001] The embodiments described in this specification relate to power routing and signal routing for semiconductor devices. More particularly, the embodiments described in this specification relate to power routing and signal routing for vertical transistors.

Background Art

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logical functions, memory functions, and the like. The current trend in the standard cell methodology is to reduce the size of the standard cell while increasing the complexity within the standard cell (e.g., circuit density and the number of components or transistors). However, as the standard cell design becomes smaller, it becomes more difficult to provide access (e.g., connection) to the components within the standard cell within the design / manufacturing constraints of the standard cell.

[0003] The features and advantages of the methods and apparatuses of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred but exemplary embodiments according to the embodiments described in this disclosure, in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] A perspective view of an intended vertical transistor device according to some embodiments is shown.

[0005] [Figure 2] A perspective view of another intended vertical transistor device according to some embodiments is shown.

[0006] [Figure 3] A perspective view of an inverter cell structure according to some embodiments is shown.

[0007] [Figure 4]The upper plan view of an inverter cell structure according to several embodiments is shown.

[0008] [Figure 5] The rear plan view of the inverter cell structure according to several embodiments is shown.

[0009] [Figure 6] Figure 4 shows a cross-sectional view of an inverter cell structure along line 6-6 according to several embodiments.

[0010] [Figure 7] Figure 4 shows a cross-sectional view of an inverter cell structure along line 7-7 according to several embodiments.

[0011] [Figure 8] Perspective views of NAND cell structures according to several embodiments are shown.

[0012] [Figure 9] The images show upper plan views of NAND cell structures according to several embodiments.

[0013] [Figure 10] The following are rear-side plan views of NAND cell structures according to several embodiments.

[0014] [Figure 11] Figure 9 shows cross-sectional views of NAND cell structures along line 11-11 according to several embodiments.

[0015] [Figure 12] Figure 9 shows cross-sectional views of NAND cell structures along line 12-12 according to several embodiments.

[0016] [Figure 13] Perspective views of MUX cell structures according to several embodiments are shown.

[0017] [Figure 14] The top plan view of a MUX cell structure according to some embodiments is shown.

[0018] [Figure 15] The back plan view of a MUX cell structure according to some embodiments is shown.

[0019] [Figure 16] The cross-sectional view of a MUX cell structure along line 16-16 shown in FIG. 14 according to some embodiments is shown.

[0020] [Figure 17] The cross-sectional view of a MUX cell structure along line 17-17 shown in FIG. 14 according to some embodiments is shown.

[0021] [Figure 18] The perspective view of a device according to some embodiments is shown.

[0022] [Figure 19] The cross-sectional view of a device along line 19-19 shown in FIG. 51 according to some embodiments is shown.

[0023] [Figure 20] The perspective view of an inverter cell structure according to some embodiments is shown.

[0024] [Figure 21] The top plan view of an inverter cell structure according to some embodiments is shown.

[0025] [Figure 22] The back plan view of an inverter cell structure according to some embodiments is shown.

[0026] [Figure 23] The cross-sectional view of an inverter cell structure according to some embodiments is shown.

[0027] [Figure 24]Cross-sectional views of inverter cell structures according to several embodiments are shown.

[0028] [Figure 25] Perspective views of NAND cell structures according to several embodiments are shown.

[0029] [Figure 26] The images show upper plan views of NAND cell structures according to several embodiments.

[0030] [Figure 27] The following are rear-side plan views of NAND cell structures according to several embodiments.

[0031] [Figure 28] Cross-sectional views of NAND cell structures according to several embodiments are shown.

[0032] [Figure 29] Cross-sectional views of NAND cell structures according to several embodiments are shown.

[0033] [Figure 30] Perspective views of MUX cell structures according to several embodiments are shown.

[0034] [Figure 31] The image shows an upper plan view of a MUX cell structure according to several embodiments.

[0035] [Figure 32] The following are rear-side plan views of MUX cell structures according to several embodiments.

[0036] [Figure 33] Cross-sectional views of MUX cell structures according to several embodiments are shown.

[0037] [Figure 34] This is a block diagram of one embodiment of an exemplary system.

[0038] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims. [Modes for carrying out the invention]

[0039] This disclosure relates to implementations of vertical transistors within integrated circuit cells (e.g., standard cells) that utilize connections to both the upper and lower metal layers. The upper and lower metal layers may provide routing (e.g., paths) for control signals and / or power signals. The disclosed embodiments provide connections for vertical transistors within integrated circuit cells to either control signal routing or power signal routing in either the upper or lower metal layer. As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. For example, an individual standard cell may be one cell in a library of multiple cells from which various suitable cells may be selected to implement a particular cell design. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. The embodiments of circuit design cells described herein may be implemented in various implementations of logic integrated circuits or memory integrated circuits.

[0040] Many current cell designs provide connections and routing for power or signals to transistors or other structures in an area above the transistor. For example, connections and routing for power or signals may be provided in the upper layers of the device. As used herein, the term “upper” refers to an area within the device that is vertically above the active layer of the device (e.g., above the transistor region of the device when viewed in a typical cross-sectional view). For example, “upper” may refer to components such as contacts or layers that are vertically above the transistor region, as shown in the drawings and described herein. In some cases, the term “front” may be used interchangeably with the term “upper.”

[0041] Some recent advances in standard cell design involve moving connections and routing for power connections to a metal layer beneath the transistor. For example, connections and routing for power may be located within the back layer of the device. As used herein, the term “back” refers to an area within the device that lies vertically below the active layer of the device (e.g., below the transistor region of the device when viewed in a typical cross-sectional view). For example, the back may refer to components such as contacts or layers that are vertically below the transistor region, as shown in the drawings and described herein. As used herein, it should be noted that back elements located below the active layer may be above, inside, or below the silicon substrate on which the active layer is manufactured. That is, as used herein, “back” refers to the active layer, not the silicon substrate. As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments may be conceived in which the metal in the “routing” is replaced with an alternative conductive material. For example, the metal in the “routing” may be replaced with a superconducting material, a semiconductor material, or a non-metallic conductor.

[0042] A recent development in transistor design is the implementation of vertical transistors, in which the cell has vertical transport through vertically displaced source / drain regions, and the gate is positioned vertically between the source / drain regions. Current vertical transistor designs typically include a wide front (e.g., top) power rail at the cell boundary for power supply. However, these wide power rails result in increased, large standard cell height. Increased standard cell height reduces the area efficiency of the vertical transistor, as well as the available connectivity and performance of the transistor.

[0043] This disclosure envisions various embodiments of utilizing back-side power routing in vertical transistor designs to reduce scaling, provide better connectivity, and offer better transistor performance. Specific embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) an upper metal layer above the transistor region of the vertical transistors having signal routing; 3) a back-side metal layer below the transistor region having power routing; and 4) a metal contact layer between the back-side metal layer and the source / drain region of the transistors. In certain embodiments, the transistors are complementary transistors. In some embodiments, vias couple the power routing in the back-side metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routings may also be envisioned in various embodiments.

[0044] This disclosure further envisions various embodiments of vertical transistor designs to reduce scaling, provide better connectivity, and offer better performance of transistors by utilizing back-side power routing in combination with cell height direction (e.g., vertical cell direction) signal routing in the upper layer. Specific embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors, 2) an upper metal layer above the transistor region of the vertical transistors having parallel signal routing in a first direction, 3) gate vias coupling the signal routing in the upper metal layer to at least one of the transistor gates, and 4) parallel power routing in the back metal layer in a second direction perpendicular to the first direction. In certain embodiments, at least one of the transistors is coupled to the power routing. In some embodiments, a gate bridge connects the gates of the transistors. The gate bridge may be connected to the signal routing by gate vias. The signal routing may include both input signal routing and output signal routing, where the input signal routing is coupled to the gate and the output signal routing is coupled to the source / drain region of the transistor. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routings may also be contemplated in various embodiments.

[0045] In various embodiments, control signal and power signal connections are formed using various contacts or vias to implement logic associated with a particular integrated circuit device having multiple vertical transistors for the cell structure described herein. For example, examples of inverter devices, NAND devices, and MUX devices that can be implemented based on the vertical transistor cell structure are described below. Various expected embodiments of connections for control signal and voltage signals to the vertical transistors within the cell structure are also described. Those skilled in the art will understand that many different desired circuits can be generated by implementing various possible combinations of these connections based on the vertical transistor structure within the cell structure disclosed herein.

[0046] In summary, the inventors have recognized that implementing back-side routing for power connections in combination with vertical transistors provides various opportunities for constructing specific transistor designs with reduced scaling. In addition, various techniques are implemented to provide specific routing for control signals and power routing within cell structures having vertical transistors as described herein. The implementation of various disclosed techniques leads to the creation of vertical transistor cell structures that provide improved performance with a small scale factor.

[0047] Figure 1 shows perspective views of several embodiments of a planned vertical transistor device. Figure 2 shows perspective views of another planned vertical transistor device, also in several embodiments. It should be noted that device 3400 shown in Figure 1 and device 3500 shown in Figure 2 are general representations of vertical transistor-based device structures, and the various connections that can be made to these structures are not shown. Exemplary embodiments of connected structures are further disclosed below herein with respect to Figures 3 to 19.

[0048] In the embodiment illustrated in Figure 1, device 3400 includes two vertical transistors 3410 and 3420. In certain embodiments, transistors 3410 and 3420 are complementary transistors. For example, transistor 3410 is a PMOS transistor, and transistor 3420 is an NMOS transistor. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Similarly, transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, gates 3414 and 3424 are fin-type gates. In various embodiments, gate 3414 includes a gate spacer 3415, and gate 3424 includes a gate spacer 3425. For the sake of simplicity in the drawings, gate spacers 3415 and 3425 are not labeled in the remaining drawings.

[0049] As shown in Figure 1, the lower source / drain region, gate, and upper source / drain region are stacked vertically in the transistor. Furthermore, as shown, transistors 3410 and 3420 are parallel, with a gap (e.g., distance) between them in the horizontal direction (e.g., horizontal direction) of device 3400.

[0050] In certain embodiments, transistor 3410 includes an upper contact 3418 coupled to an upper source / drain region 3416, and transistor 3420 includes an upper contact 3428 coupled to an upper source / drain region 3426. Contacts 3418 and 3428 may be metal contacts for contacting various resources in a first metal layer located above transistors 3410 and 3420. For example, as shown in Figure 1, contact 3418 may be routed to a resource by route 3430 (e.g., a routing shown by a dotted line). Route 3430 may be a metal layer route path in the first metal layer above transistors 3410 and 3420. It should be noted that the dotted line depiction of route 3430 is given as an example of one resource (e.g., a routing) in the metal layer, and the metal layer may contain multiple resources (e.g., multiple routings). Furthermore, only the first metal layer above transistors 3410 and 3420 is shown, and there may be multiple additional metal routings above route 3430.

[0051] In various embodiments, transistor 3410 includes a lower contact 3419 coupled to a lower source / drain region 3412, and transistor 3420 includes a lower contact 3429 coupled to a lower source / drain region 3422. Contacts 3419, 3429 may be, for example, metal contacts. Contacts 3419, 3429 may be used for routing to a back-side power routing layer (for example, back-side power routing 3440A or back-side power routing 3440B as shown in Figure 1 and described herein) or for routing to various other resources within device 3400.

[0052] In certain embodiments, device 3400 includes a back-side power layer. In the embodiment illustrated in Figure 1, the back-side power layer includes back-side power routing 3440A and back-side power routing 3440B. Routing 3440A and routing 3440B may provide routing to and from power (e.g., Vdd) and ground (e.g., Vss) resources for device 3400, for example.

[0053] In various embodiments, gates 3414 and 3424 are interconnected by a gate bridge 3450. The gate bridge 3450 may be formed, for example, by extending the gate material of gates 3414 and 3424 to join the gates together. In some embodiments, the gate bridge 3450 may be formed by a single extension of the gate material extending from either gate 3414 or gate 3424 to the other gate. The gate bridge 3450 may also include an extension of the material for gate spacers. The gate bridge 3450 merges gates 3414 and 3424 for the implementation of transistors 3410 and 3420 in various embodiments of the CMOS device, several examples of which are described herein. Various embodiments in which gates 3414 and / or gate 3424 extend in other directions may also be contemplated. For example, the gate may include an extension that extends toward the outer boundary of the device 3400 (for example, toward the outer boundary of the cell structure, in the opposite direction to the gate bridge 3450).

[0054] In the embodiment illustrated in Figure 2, device 3500 does not have a gate bridge connecting gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Various techniques can be contemplated for connecting transistors 3410 and 3420 without a gate bridge. For example, in one contemplated embodiment, contacts 3418 and 3428 may be connected by a strap 3510. The strap 3510 may be, for example, a metal strap. In some embodiments, contacts 3418, 3428, and strap 3510 may be formed as a single contact (e.g., a single strap connecting upper source / drain regions 3416 and 3426). Various embodiments can also be contemplated in which the strap 3510 extends in a different direction from one of the contacts 3418, 3428. For example, the strap 3510 may extend perpendicular to the illustrated embodiment toward another vertical transistor or resource within device 3500.

[0055] In another intended embodiment, contacts 3419 and 3429 may be connected by a strap 3520. The strap 3520 may also be a metal strap. In some embodiments, the strap 3520 is formed together with contacts 3419 and 3429 as a single contact. For example, the strap 3520, contacts 3419, and contacts 3429 may be portions of a single metal contact plate formed within the contact layer. Various embodiments may also be intended in which contacts 3419 and / or contacts 3429 extend outward from the bottom of transistors 3410, 3420. For example, the contacts may have portions that extend toward the outer boundary of device 3500 (for example, toward the outer boundary of a cell structure).

[0056] While various connection structures are shown separately for device 3400 in Figure 1 and device 3500 in Figure 2, it should be understood that in cell design, embodiments may be conceived in which structures from device 3400 are combined with structures from device 3500. For example, a device may be conceived that includes both a gate bridge 3450 and one or both of straps 3510 and strap 3520. Hereinafter, various exemplary device cell configurations based on device 3400 and / or device 3500 are described as examples. It should be noted that various device cell structures are provided as examples, and various additional device cell structures may be implemented based on the description herein.

[0057] Figures 3 to 7 show diagrams of inverter cell structures according to several embodiments. Figure 3 shows a perspective view of an inverter cell structure according to several embodiments. Figure 4 shows an upper plan view of an inverter cell structure according to several embodiments. Figure 5 shows a rear plan view of an inverter cell structure according to several embodiments. Figure 6 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 6-6 shown in Figure 4 (for example, along the gate bridge). Figure 7 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 7-7 shown in Figure 4 (for example, perpendicular to the gate fin of transistor 3410).

[0058] The inverter cell device 3600 can be obtained from the structure of device 3400 shown in Figure 1. In the illustrated embodiments shown in Figures 3 to 7, device 3600 includes vertical transistors 3410 and 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, an upper source / drain region 3416, an upper contact 3418, and a lower contact 3419. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, an upper source / drain region 3426, an upper contact 3428, and a lower contact 3429. In the illustrated embodiments of device 3600, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0059] In a particular embodiment, device 3600 includes back-side vias 3610A and 3610B. Back-side via 3610A is coupled to the lower source / drain region 3412 via a lower contact 3419. Back-side via 3610A couples the lower source / drain region 3412 to back-side power routing 3440A. In the case of device 3600, back-side power routing 3440A supplies power (e.g., Vdd) to the lower source / drain region 3412 and transistor 3410. Back-side via 3610B is coupled to the lower source / drain region 3422 via a lower contact 3429. Back-side via 3610B couples the lower source / drain region 3422 to back-side power routing 3440B. In the case of device 3600, back-side power routing 3440B supplies ground (e.g., Vss) to the lower source / drain region 3422 and transistor 3420.

[0060] In various embodiments, device 3600 includes upper vias 3620A and 3620B. Upper via 3620A may be coupled to the upper source / drain region 3416 via upper contact 3418, and upper via 3620B may be coupled to the upper source / drain region 3426 via upper contact 3428. Upper vias 3620A and 3620B may provide connections to signal routing resources (e.g., routes 3430A-E) in the first metal layer above transistors 3410 and 3420. For example, in the illustrated embodiment, upper via 3620A is coupled to route 3430B, and upper via 3620B is coupled to route 3430D. Routes 3430B and 3430D may provide routes for output signals from transistors 3410 and 3420, respectively.

[0061] In certain embodiments, a route for input signals to transistors 3410 and 3420 is provided by route 3430C. As shown in Figures 3 and 4, route 3430C is coupled to gate via 3630, which is coupled to gate bridge 3450. Thus, gate via 3630 provides a connection between route 3430C (e.g., the input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Connections to the input signal route, output signal route, and power / ground route connect transistors 3410 and 3420 to form an inverter cell device 3600.

[0062] Figures 3 and 4 show five routes 3430A-E within the first metal layer above transistors 3410 and 3420, but it should be noted that the first metal layer may include additional routes. Furthermore, additional metal layers may be located above the first metal layer and provide various connections to either the first metal layer or device 3600. For example, in one embodiment, the metal layer above the first metal layer may include a strap (or other connector) that connects routes 3430B and 3430D so that the outputs of transistors 3410 and 3420 are merged together into a single output. In addition, two back-side power routings (e.g., routing 3440A and routing 3440B) are shown, but the back-side power layer may include additional routing (e.g., routing for other power and signal resources).

[0063] The top and back plan views of device 3600 shown in Figures 4 and 5 further illustrate the gate fins that may be present on the transistor gate. For example, gate fin 3415 is the gate fin for gate 3414, and gate fin 3425 is the gate fin for gate 3424. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 3600 in Figure 6, and gate fin 3415 is shown in the cross-sectional view of transistor 3410 in Figure 7. Note that the cross-sectional view in Figure 7 is perpendicular to the gate fin of transistor 3410, which is in the direction of route 3430B shown in Figures 3 and 4.

[0064] Figures 8 to 12 show diagrams of NAND cell structures according to several embodiments. Figure 8 shows a perspective view of a NAND cell structure according to several embodiments. Figure 9 shows a top plan view of a NAND cell structure according to several embodiments. Figure 10 shows a back plan view of a NAND cell structure according to several embodiments. Figure 11 shows a cross-sectional view of a NAND cell structure according to several embodiments along line 11-11 shown in Figure 9 (for example, along gate bridge 3450'). Figure 12 shows a cross-sectional view of a NAND cell structure according to several embodiments along line 12-12 shown in Figure 9 (for example, perpendicular to the gate fins of transistors 3410 and 3410').

[0065] The NAND cell device 4100 can be obtained from the structure of device 3400 shown in Figure 1. In the illustrated embodiments shown in Figures 8 to 12, device 4100 includes vertical transistors 3410, 3420, 3410', and 3420'. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410' includes a lower source / drain region 3412', a gate 3414', and an upper source / drain region 3416'. Transistor 3420' includes a lower source / drain region 3422', a gate 3424', and an upper source / drain region 3426'. In the illustrated embodiment of device 4100, transistors 3410 and 3410' are PMOS transistors, and transistors 3420 and 3420' are NMOS transistors.

[0066] In certain embodiments, a route for input signals to transistors 3410, 3410', 3420, and 3420' is provided by route 3430C. As shown in Figures 8 and 9, route 3430C is coupled to gate via 3630A coupled to gate bridge 3450 and gate via 3630B coupled to gate bridge 3450'. Thus, gate via 3630A provides a connection between route 3430C (e.g., the input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Gate via 3630B provides a connection between route 3430C (e.g., the input signal route) and both gate 3414' in transistor 3410' and gate 3424' in transistor 3420'.

[0067] In certain embodiments, the upper source / drain region 3416 of transistor 3410 and the upper source / drain region 3416' of transistor 3410' are connected by contact 3418. Similarly, the upper source / drain region 3426 of transistor 3420 and the upper source / drain region 3426' of transistor 3420' are connected by contact 3428. In various embodiments, device 4100 includes an upper via 3620 connected to contact 3418. The upper via 3620 can provide a connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistors 3410 and 3410'.

[0068] In the illustrated embodiment, only transistors 3410, 3410', and 3420 are connected to the back layer. For example, as shown in Figures 7 and 10, transistor 3410 is connected to the back power routing 3440A by contact 3419 and back via 3610A, transistor 3410' is connected to the back power routing 3440A by contact 3419' and back via 3610A', and transistor 3420 is connected to the back power routing 3440B by contact 3429 and back via 3610B. In various embodiments of device 4100, the back power routing 3440A supplies power (e.g., Vdd) to the lower source / drain region 3412 and transistor 3410, as well as the lower source / drain region 3412' and transistor 3410', while the back power routing 3440B supplies ground (e.g., Vss) to the lower source / drain region 3422 and transistor 3420.

[0069] In certain embodiments, the lower source / drain region 3422' within transistor 3420' is connected to contact 3429', which is not connected to the back-side power routing layer. Contact 3429' extends toward the cell boundary away from the lower source / drain region 3422', as shown in Figures 8, 10, and 11. Contact 3429' is then coupled to route 3430E by contact via 4110. Route 3430E is a route in the first metal layer above the transistor region. Contact via 4110 is a via belonging to the cell structure of device 4100 and is not shared with any adjacent cells along the cell boundary. In certain embodiments, route 3430E is a signal route in the first metal layer for the signal output from transistor 3420'. Therefore, signals within the NMOS transistors (e.g., transistors 3420 and 3420') are routed from the lower source / drain region 3422 (connected to ground by the rear power routing 3440B) through the transistors and contact via 4110 to route 3430E.

[0070] In the illustrated embodiment, route 3430E provides a route for the output signals from transistors 3420 and 3420'. The output signals routed through route 3430E can be combined with the output signals from route 3430B. For example, a metal layer above the first metal layer may include a strap (or other connector) that connects route 3430B and route 3430E so that the outputs of the transistors are merged together to form a single output.

[0071] The various routings and connections within device 4100 form a NAND cell device. Figures 9 and 10 show gate fins 3415, 3415', 3425, and 3425' within gates 3414, 3414', 3424, and 3424', respectively. Gate fins 3415' and 3425' are also shown in the cross-sectional view of device 4100 in Figure 11, and gate fins 3415 and 3415' are shown in the cross-sectional view of device 4100 in Figure 12. Note that the cross-sectional view in Figure 12 is perpendicular to the gate fins of transistors 3410 and 3410', which is in the direction of route 3430B shown in Figure 9.

[0072] Figures 13 to 17 show diagrams of MUX (multiplexer) cell structures according to several embodiments. Figure 13 shows a perspective view of a MUX cell structure according to several embodiments. Figure 14 shows a top plan view of a MUX cell structure according to several embodiments. Figure 15 shows a back plan view of a MUX cell structure according to several embodiments. Figure 16 shows a cross-sectional view of a MUX cell structure according to several embodiments along line 16-16 shown in Figure 14 (e.g., along gate fins 3415' and 3425''). Figure 17 shows a cross-sectional view of a MUX cell structure according to several embodiments along line 17-17 shown in Figure 14 (e.g., perpendicular to the gate fins of transistors 3410 and 3410'').

[0073] The MUX cell device 4600 can be obtained from the structure of device 3500 shown in Figure 2. In the illustrated embodiments shown in Figures 13 to 17, device 4600 includes vertical transistors 3410, 3420, 3410'', and 3420''. Similar to device 3500, there are no gate bridges between the gates of the transistors in device 4600, and consequently, there are no common gates between complementary transistors. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410'' includes a lower source / drain region 3412'', a gate 3414'', and an upper source / drain region 3416''. Transistor 3420'' includes a lower source / drain region 3422'', a gate 3424'', and an upper source / drain region 3426''. In the illustrated embodiment of device 4600, transistors 3410 and 3410'' are PMOS transistors, and transistors 3420 and 3420'' are NMOS transistors.

[0074] Since the MUX cell device 4600 is a transmission device, neither transistor 3410 nor transistor 3410'', nor transistor 3420 nor transistor 3420'' are connected to any power within the MUX cell structure. In various embodiments of the MUX cell device 4600, the lower source / drain regions of the transistors are connected together (e.g., merged together). For example, in the illustrated embodiment, the contact plate 4620 is connected to the lower source / drain region 3412 of transistor 3410, the lower source / drain region 3412'' of transistor 3410'', the lower source / drain region 3422 of transistor 3420, and the lower source / drain region 3422'' of transistor 3420''.

[0075] In certain embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 may be connected to contact plate 4620 at or near the center of the contact plate. Then, contact via 4630 is connected to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output routing for the MUX cell device 4600. Thus, contact via 4630 can be referred to as an output pin of the MUX cell device 4600.

[0076] In various embodiments, gates 3414, 3414'', 3424, and 3424'' extend toward the cell boundary, providing a surface for a direct vertical connection from the root in the upper first metal layer to the gate. For example, as shown in Figures 13 to 17, gate 3414 includes a gate extension 4640A that extends toward the cell boundary (e.g., horizontally toward the cell boundary). Similarly, gate 3414'' includes a gate extension 4640B, gate 3424 includes a gate extension 4640C, and gate 3424'' includes a gate extension 4640D. The gate extensions 4640A to D are then connected, respectively, to the root in the upper first metal layer by gate vias 3630A to D. For example, as shown in Figures 13 and 14, gate via 3630A connects gate extension 4640A to route 3430A, gate via 3630B connects gate extension 4640B to route 3430A, gate via 3630C connects gate extension 4640C to route 3430E, and gate via 3630D connects gate extension 4640D to route 3430E. Either or both of routes 3430A and 3430E are located at the cell boundary and are not shared with adjacent cells. Routes 3430A and 3430E may provide input routes to device 4600.

[0077] In a particular embodiment, the upper source / drain region 3416 in transistor 3410 is connected to the upper source / drain region 3426 in transistor 3420 by contact 4610A. This connection merges the upper source / drain region 3416 into the upper source / drain region 3426. Similarly, the upper source / drain region 3416'' in transistor 3410'' is connected to the upper source / drain region 3426'' in transistor 3420'' by contact 4610B. The merging of these upper source / drain regions, along with the common connection between the lower source / drain regions (and a single output via contact via 4630), allows device 4600 to operate as a MUX (multiplexer) with signals input via gate vias 3630A-D and output via contact via 4630.

[0078] Figures 14 and 15 show gate fins 3415, 3415'', 3425, and 3425'' within gates 3414, 3414'', 3424, and 3424'', respectively. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 4600 in Figure 16, and gate fins 3415 and 3415'' are shown in the cross-sectional view of device 4600 in Figure 17. Note that the cross-sectional view in Figure 17 is perpendicular to the gate fins of transistors 3410 and 3410'', which is in the direction of route 3430B shown in Figure 14.

[0079] Figures 18 and 19 show diagrams of cell devices having dielectric walls according to several embodiments. Figure 18 shows a perspective view of device 5100 according to several embodiments. Figure 19 shows a cross-sectional view of device 5100 along line 19-19 shown in Figure 51 (for example, along gate bridge 3450') according to several embodiments.

[0080] Device 5100 can be obtained from the structure of device 3400 shown in Figure 1. In some embodiments, device 5100 may be similar to the inverter cell device 4100 shown in Figures 8 to 12. In the embodiments illustrated in Figures 18 and 19, device 5100 includes vertical transistors 3410 and 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In certain embodiments, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0081] In various embodiments, as shown in Figures 18 and 19, wall 5100A may be located on the first side of the cell (e.g., the side of transistor 3410), and wall 5100B may be located on the second side of the cell (e.g., the side of transistor 3420 opposite to transistor 3410). In certain embodiments, walls 5100A and 5100B are dielectric walls. By placing dielectric walls on one or both sides of device 5100, the space required between device 5100 and another adjacent cell can be reduced. Therefore, walls 5100A and 5100B can be implemented when it is necessary to reduce the scaling of the device.

[0082] Figures 20–33 show various exemplary device cell structures for integrated circuit cell devices having vertical transistors. In these exemplary device cell structures, the device has a first metal layer in the cell height direction (e.g., along the cell height direction) used for signal input / output connections to the vertical transistors. It should be noted that various device cell structures are provided as examples, and various additional device cell structures can be implemented based on the description herein. For example, the illustrated device cell structures include inverter cell structures, NAND cell structures, and MUX (multiplexer) cell structures. These cell structures can provide basic cell structures that can be implemented in various types of integrated circuit devices.

[0083] Figures 20 to 24 show diagrams of inverter cell structures according to several embodiments. Figure 20 shows a perspective view of an inverter cell structure according to several embodiments. Figure 21 shows an upper plan view of an inverter cell structure according to several embodiments. Figure 22 shows a rear plan view of an inverter cell structure according to several embodiments. Figure 23 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 23-23 shown in Figure 21 (for example, along the gate bridge in the cell height direction). Figure 24 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 24-24 shown in Figure 21 (for example, perpendicular to the gate bridge in the gate pitch direction).

[0084] The inverter cell device 5300 can be obtained from the structures of device 3400 shown in Figure 1 and device 3600 shown in Figure 3. In the embodiments illustrated in Figures 20 to 24, device 5300 includes four vertical transistors 5310, 5320, 5330, and 5340. Transistor 5310 includes a lower source / drain region 5312, a gate 5314, a gate spacer 5315, and an upper source / drain region 5316. Transistor 5320 includes a lower source / drain region 5322, a gate 5324, a gate spacer 5325, an upper source / drain region 5326, an upper contact 5328, and a lower contact 5329. Similarly, transistor 5330 includes a lower source / drain region 5332, a gate 5334, a gate spacer 5335, an upper source / drain region 5336, an upper contact 5338, and a lower contact 5339, and transistor 5340 includes a lower source / drain region 5342, a gate 5344, a gate spacer 5345, an upper source / drain region 5346, an upper contact 5348, and a lower contact 5349. In the illustrated embodiment of device 5300, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some of the figures in Figures 20 to 24.

[0085] Device 5300 may include various contacts to transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing or power routing. For example, device 5300 may include, for transistor 5310, an upper contact 5318 connected to the upper source / drain region 5316 and a lower contact 5319 connected to the lower source / drain region 5312; for transistor 5320, an upper contact 5328 connected to the upper source / drain region 5326 and a lower contact 5329 connected to the lower source / drain region 5322; for transistor 5330, an upper contact 5338 connected to the upper source / drain region 5336 and a lower contact 5339 connected to the lower source / drain region 5332; and for transistor 5340, an upper contact 5348 connected to the upper source / drain region 5346 and a lower contact 5349 connected to the lower source / drain region 5342. In various embodiments, device 5300 includes back-side vias 5350A, 5350B, 5350C, and 5350D to transistors 5310, 5320, 5330, and 5340. Back-side via 5350A is coupled to the lower source / drain region 5312 via a lower contact 5319. Back-side via 5350B is coupled to the lower source / drain region 5322 via a lower contact 5329. Back-side via 5350C is coupled to the lower source / drain region 5332 via a lower contact 5339. Back-side via 5350D is coupled to the lower source / drain region 5342 via a lower contact 5349.

[0086] In the illustrated embodiment, back vias 5350A and 5350C connect the lower source / drain regions 5312 and 5332 of transistors 5310 and 5330, respectively, to back power routing 5360A. Back vias 5350B and 5350D connect the lower source / drain regions 5322 and 5342 of transistors 5320 and 5340, respectively, to back power routing 5360B. For device 5300, back power routing 5360A supplies power (e.g., Vdd) to the lower source / drain regions 5312 and 5332 and transistors 5310 and 5330, while back power routing 5360B supplies ground (e.g., Vss) to the lower source / drain regions 5322 and 5342 and transistors 5320 and 5340. However, power can be supplied by switching the rear power routing 5360A to rear power routing 5360B, and grounding can be provided by switching the rear power routing 5360B to rear power routing 5360A.

[0087] The top and back plan views of device 5300 shown in Figures 21 and 22 further illustrate the gate fins that may be present on the gates of the transistor, respectively. For example, gate fin 5313 is the gate fin for gate 5314, gate fin 5323 is the gate fin for gate 5324, gate fin 5333 is the gate fin for gate 5334, and gate fin 5343 is the gate fin for gate 5345. Gate fins 5313 and 5323 are shown in the cross-sectional view of device 5300 in Figure 23, and gate fins 5323 and 5343 are shown in the cross-sectional view of device 5300 in Figure 24.

[0088] In various embodiments, gate pairs (for example, gate pairs 5314 and 5324, or gate pairs 5334 and 5344) are interconnected by gate bridges. For example, in the illustrated embodiment, gates 5314 and 5324 are interconnected by gate bridge 5380A, and gates 5334 and 5344 are interconnected by gate bridge 5380B. Gate bridges 5380A and 5380B can be formed, for example, by extending gate material across the space between gates, as shown in Figures 20 to 23. To implement transistors 5310, 5320, 5330, and 5340 in an inverter device, gate bridge 5380A merges gates 5314 and 5324, while gate bridge 5380B merges gates 5334 and 5344. In some embodiments, the gate bridges 5380A and 5380B may also include extensions of material for gate spacers between transistors. For example, gate bridge 5380A includes extensions of material for gate spacers 5315 and 5325, and gate bridge 5380B includes extensions of material for gate spacers 5335 and 5345.

[0089] In certain embodiments, gate vias 5390A and 5390B are connected to gate bridges 5380A and 5380B, respectively. Gate vias 5390A and 5390B may be vias used to connect gate bridges 5380A and 5380B to routing within the first metal layer, as described below. Connecting gate via 5390A to gate bridge 5380A makes it possible to implement a single signal input connection for connecting the pair of gates 5314 and 5324 merged by the bridge. Similarly, a gain via 5390B connected to gate bridge 5380B provides a single signal input for gates 5334 and 5344.

[0090] In various embodiments, device 5300 includes upper vias 5392A, 5392B, 5392C, and 5392D. The upper vias 5392A, 5392B, 5392C, and 5392D may be coupled to upper source / drain regions 5316, 5326, 5336, and 5346, respectively, via upper contacts 5318, 5328, 5338, and 5348. As shown in the illustrated embodiments, the upper contacts 5318, 5328, 5338, and 5348 may include portions extending from where the upper contacts connect to the upper source / drain regions 5316, 5326, 5336, and 5346 to where the upper contacts connect to upper vias 5392A, 5392B, 5392C, and 5392D. Therefore, the upper contacts 5318, 5328, 5338, and 5348 redistribute the horizontal positions for connections to the upper source / drain regions 5316, 5326, 5336, and 5346 from the horizontal positions of the upper source / drain regions to the horizontal positions of the upper vias 5392A, 5392B, 5392C, and 5392D. The upper vias 5392A, 5392B, 5392C, and 5392D may provide connections to signal routing resources (e.g., routes 5370B, D) in the first upper metal layer above the transistors in device 5300, as described below.

[0091] In certain embodiments, the device 5300 includes a first upper metal layer having signal routing having routes that extend in the cell height direction (for example, along the vertical direction of the integrated circuit cell, as shown in Figures 21 and 22). In the illustrated embodiments, the signal routing of the first upper metal layer includes four signal routes 5370A, 5370B, 5370C, and 5370D (indicated by dashed lines) that extend in the cell height direction. Since these signal routes 5370A-D extend in the cell height direction, the signal routes may have a pitch (e.g., metal pitch) having a ratio of 1:2 with respect to the gate pitch (e.g., contact polypitch) in the device 5300.

[0092] Since the pitch of signal routes 5370A-D is narrower than the pitch of gates 5314, 5324, 5334, and 5344, the signal routes can be used for both input signal routing and output signal routing to transistors 5310, 5320, 5330, and 5340. For example, in the illustrated embodiment, signal routes 5370A and 5370C are input signal routes connected to gate vias 5390A and 5390B, respectively. Thus, signal route 5370A supplies input signals to merged transistors 5310 and 5320 (for example, transistors having gates 5314 and 5324 merged by gate bridge 5380A and coupled to gate via 5390A). Similarly, signal route 5370C supplies input signals to merged transistors 5330 and 5340 (for example, transistors having gates 5334 and 5344 merged by gate bridge 5380B and coupled to gate via 5390B).

[0093] Furthermore, in the illustrated embodiment, signal routes 5370B and 5370D are output signal routes. Signal route 5370B is connected to the outputs of transistors 5310 and 5320 via upper source / drain regions 5316, 5326, upper contacts 5318, 5328, and upper vias 5392A and 5392B. Signal route 5370D is connected to the outputs of transistors 5330 and 5340 via upper source / drain regions 5336, 5346, upper contacts 5338, 5348, and upper vias 5392C and 5392D. In device 5300, due to the metal pitch being half the gate pitch in the device, both input and output signal routes can reside within the same upper metal layer. This pitch difference allows signal routes 5370A and 5370C to be above the gate (e.g., above the gate fin), while signal routes 5370B and 5370D are between the gate (e.g., between the gate fin). Thus, the aforementioned metal pitch allows device 5300 to have connected gate logic via a single upper metal layer for an inverter device having four vertical transistors.

[0094] Figures 20–22 (and additional figures herein) show four routes 5370A–D within a first upper metal layer above transistors 5310, 5320, 5330, and 5340, but it should be noted that the first upper metal layer may include additional routes. Furthermore, additional metal layers may be located above the first upper metal layer and provide various connections to either the first upper metal layer or device 5300. For example, in one embodiment, another upper metal layer above the first upper metal layer may include a strap (or other connector) that connects routes 5370B and 5370D so that the outputs of the transistors are merged together to form a single output. An example of routing within a second upper metal layer is shown in Figure 21 by routes 5410A–G. It should be noted that the routing within the second upper metal layer is perpendicular to the routing within the first upper metal layer. In addition, two back-end power routings (e.g., routing 5360A and routing 5360B) are shown, but the back-end power layer may include additional routing (e.g., routing for other power resources).

[0095] Figures 25 to 29 show diagrams of NAND cell structures according to several embodiments. Figure 25 shows a perspective view of a NAND cell structure according to several embodiments. Figure 26 shows a top plan view of a NAND cell structure according to several embodiments. Figure 27 shows a back plan view of a NAND cell structure according to several embodiments. Figure 28 shows a cross-sectional view of a NAND cell structure along line 28-28 shown in Figure 26 (e.g., across gate fins 5313 and 5333) according to several embodiments. Figure 29 shows a cross-sectional view of a NAND cell structure along line 29-29 shown in Figure 26 (e.g., across gate fins 5323 and 5343) according to several embodiments.

[0096] The NAND cell device 5800 can be obtained from the structures of device 3400 shown in Figure 1 and device 4100 shown in Figure 8. In the embodiments illustrated in Figures 25 to 29, the NAND cell device 5800 includes vertical transistors 5310, 5320, 5330, and 5340. Transistors 5310, 5320, 5330, and 5340 are similar to the corresponding transistors shown in Figures 20 to 24. For example, transistor 5310 includes a lower source / drain region 5312, a gate 5314, a gate spacer 5315, and an upper source / drain region 5316; transistor 5320 includes a lower source / drain region 5322, a gate 5324, a gate spacer 5325, and an upper source / drain region 5326; transistor 5330 includes a lower source / drain region 5332, a gate 5334, a gate spacer 5335, and an upper source / drain region 5336; and transistor 5340 includes a lower source / drain region 5342, a gate 5344, a gate spacer 5345, and an upper source / drain region 5346. In the illustrated embodiment of device 5800, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some of the figures in Figures 25 to 29.

[0097] Device 5800 may include various contacts to transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing or power routing. For example, device 5800 may include an upper contact 5810 connected to both the upper source / drain region 5316 of transistor 5310 and the upper source / drain region 5336 of transistor 5330. The upper contact 5810 also includes an extension portion 5812 that extends (e.g., horizontally) beyond the upper source / drain region 5336 of transistor 5330 toward the cell boundary. Then, an upper via 5392C provides a connection between the upper contact 5810 and route 5370D. Device 5800 further includes an upper contact 5820 connected to both the upper source / drain region 5326 of transistor 5320 and the upper source / drain region 5346 of transistor 5340. Note that there is no extension portion for the upper contact 5820.

[0098] Device 5800 includes lower contacts to the power supply for transistors 5310, 5320, and 5330, as shown in Figure 25, but does not include a power supply contact for transistor 5340. Thus, device 5800 includes a lower contact 5319 connected to the lower source / drain region 5312 of transistor 5310, a lower contact 5329 connected to the lower source / drain region 5322 of transistor 5320, and a lower contact 5339 connected to the lower source / drain region 5332 of transistor 5330. For power connections, device 5800 includes back-side vias 5350A, 5350B, and 5350C to transistors 5310, 5320, and 5330. The rear via 5350A is connected to the lower source / drain region 5312 via the lower contact 5319, the rear via 5350B is connected to the lower source / drain region 5322 via the lower contact 5329, and the rear via 5350C is connected to the lower source / drain region 5332 via the lower contact 5339. In a particular embodiment of device 5800, the rear power routing 5360A supplies power (e.g., Vdd) to the lower source / drain region 5312 and transistor 5310, as well as to the lower source / drain region 5332 and transistor 5330, while the rear power routing 5360B supplies ground (e.g., Vss) to the lower source / drain region 5322 and transistor 5320.

[0099] For transistor 5340 within device 5800, the lower contact 5830 is coupled to the lower source / drain region 5342. The lower contact 5830 includes an extension portion 5832 that extends toward the cell boundary (e.g., horizontally) away from the lower source / drain region 5342 of transistor 5340, as shown in Figure 25. As illustrated, there is no connection between transistor 5340 and the back-side power routing 5360B. For connected gate logic associated with the NAND device, device 5800 includes an upper back-side via 5840 that connects the extension portion 5832 of the lower contact 5830 to route 5370D.

[0100] In certain embodiments, as shown in Figures 25-27, route 5370A provides signal input routing to gate via 5390A, and route 5370C provides signal input routing to gate via 5390B. Thus, device 5800 can receive two separate input signals, one for transistors 5310 and 5320 merged by gate bridge 5380A, and the other for transistors 5330 and 5340 merged by gate bridge 5380B. Route 5370B is not used for the NAND cell device 5800 (e.g., not connected to any transistor).

[0101] The output signal routing of device 5800 is provided by route 5370D. As shown in the illustrated embodiment, route 5370D is connected to the upper source / drain regions 5316 and 5336 of transistors 5310 and 5330, respectively, by upper contact 5810, extension portion 5812, and upper via 5392C. Route 5370D is also connected to the lower source / drain region 5342 of transistor 5340, by lower contact 5830, extension portion 5832, and upper back via 5840. Thus, the outputs of the transistors are merged together at route 5370D. Due to the 1:2 ratio between the metal pitch and gate pitch described above, connections to route 5370D through extension portions 5812 and 5832, and subsequently through upper via 5392C and upper back via 5840, respectively, are possible in device 5800.

[0102] The connections within device 5800 construct connected gate logic for a NAND cell device, having inputs through gate vias 5390A and 5390B and outputs through upper via 5392C and upper back via 5840. Similar to device 5300, due to the metal pitch being half the gate pitch within the device, both the input and output signal routes of device 5800 can reside within the same upper metal layer. This pitch difference allows signal routes 5370A and 5370C to be above the gates (e.g., above the gate fins), and signal routes 5370B and 5370D to be between the gates (e.g., between the gate fins). Thus, the aforementioned metal pitch allows device 5800 to have connected gate logic for a NAND device having four vertical transistors, via a single upper metal layer.

[0103] Figures 20-24 show a device 5300 with connected gate logic for an inverter device, and Figures 25-29 show a device 5800 with connected gate logic for a NAND device. However, it should be understood that various additional embodiments of connected gate logic for other devices can be contemplated using four vertical transistors and signal routes extending in the cell height direction within the first upper metal layer. For example, various other gate extensions, bridges, vias, etc., can be implemented to provide any of the various connected gate logics independently or in combination with the vertical transistors.

[0104] Figures 30 to 33 show diagrams of MUX (multiplexer) cell structures according to several embodiments. Figure 30 shows a perspective view of a MUX cell structure according to several embodiments. Figure 31 shows an upper plan view of a MUX cell structure according to several embodiments. Figure 32 shows a rear plan view of a MUX cell structure according to several embodiments. Figure 33 shows a cross-sectional view of a MUX cell structure according to several embodiments along line 33-33 shown in Figure 31 (for example, across gate fins 5313 and 5333).

[0105] The MUX cell device 6300 can be derived from the structures of device 3500 shown in Figure 2 and device 4600 shown in Figure 13. In the embodiments illustrated in Figures 30 to 33, device 6300 includes vertical transistors 5310, 5320, 5330, and 5340. Transistors 5310, 5320, 5330, and 5340 are similar to the corresponding transistors shown in Figures 20 to 24. For example, transistor 5310 includes a lower source / drain region 5312, a gate 5314, a gate spacer 5315, and an upper source / drain region 5316; transistor 5320 includes a lower source / drain region 5322, a gate 5324, a gate spacer 5325, and an upper source / drain region 5326; transistor 5330 includes a lower source / drain region 5332, a gate 5334, a gate spacer 5335, and an upper source / drain region 5336; and transistor 5340 includes a lower source / drain region 5342, a gate 5344, a gate spacer 5345, and an upper source / drain region 5346. In the illustrated embodiment of device 5800, transistors 5310 and 5330 are PMOS transistors, and transistors 5320 and 5340 are NMOS transistors. Note that some components may be hidden in some of the figures in Figures 25 to 29.

[0106] Device 6300 may include various contacts to transistors (e.g., transistors 5310, 5320, 5330, 5340) for signal routing. In a particular embodiment, device 6300 includes contact 6310, and the upper source / drain region 5316 in transistor 5310 is connected by upper contact 6310 to the upper source / drain region 5326 in transistor 5320. Thus, upper contact 6310 merges the upper source / drain region 5316 with the upper source / drain region 5326. Similarly, the upper source / drain region 5336 in transistor 5330 is connected by contact 6320 to the upper source / drain region 5346 in transistor 5340. Thus, upper contact 6320 merges the upper source / drain region 5336 with the upper source / drain region 5346.

[0107] In various embodiments, gates 5314, 5324, 5334, and 5344 are extended to provide surfaces for direct vertical connections from routes 5370B and 5370D in the first upper metal layer to the gates. For example, as shown in Figures 30 to 33, gate 5314 includes a gate extension 6330A extending toward gate 5334 (e.g., extending horizontally). Similarly, gate 5324 includes a gate extension 6330B extending toward gate 5344 (e.g., extending horizontally). Connection to route 5370B is then provided by gate via 6332A connected to gate extension 6330A and gate via 6332B connected to gate extension 6330B. Due to the 1:2 ratio between the metal pitch and the gate pitch described above, connections to route 5370B through gate extensions 6330A and 6330B, and subsequently through gate vias 6332A and 6332B, are possible in device 6300. Note that gate extensions 6330A to D may include both gate material and gate spacer material.

[0108] The ratio between the metal pitch and the gate pitch further allows the gate extensions 6330C from gate 5334 and 6330D from gate 5344 to extend toward the cell boundary (e.g., horizontally) without increasing the cell size beyond the standard cell size. The gate extensions 6330C and 6330D are connected to route 5370D by gate vias 6332C and 6332D, respectively. Routes 5370B and 5370D may provide input signal routes to device 6300 via connections to the gates of transistors within the device.

[0109] Since the MUX cell device 6300 is a transmission device, none of the transistors 5310, 5320, 5330, and 5340 are connected to any power routing within the MUX cell configuration (e.g., back-side power routing 5360A or back-side power routing 5360B). In various embodiments of the MUX cell device 6300, the lower source / drain regions of the transistors (e.g., lower source / drain regions 5312, 5322, 5332, and 5342) are connected together to provide a transmission device. For example, in the illustrated embodiment, device 6300 includes a contact plate 6340 connected to the lower source / drain region 5312 of transistor 5310, the lower source / drain region 5322 of transistor 5320, the lower source / drain region 5332 of transistor 5330, and the lower source / drain region 5342 of transistor 5340.

[0110] In certain embodiments, the upper back via 6350 is coupled to the contact plate 6340. In certain embodiments, via 6350 is connected to the contact plate 6340 at or near the center of the contact plate 6340. Via 6350 is then connected to route 5370B in the first metal layer above the transistor. In various embodiments, route 5370B provides output routing for device 6300. Thus, via 6350 can be referred to as an output pin of device 6300. By merging the upper source / drain region pair within device 6300 through the common connection between upper contacts 6310 and 6320, as well as the lower source / drain region (and a single output through contact via 6350), device 6300 can operate as a MUX (multiplexer) where signals are input via gate vias 6332A-D and output via contact via 6350. Therefore, the upper metal layer routing and metal pitch versus gate pitch described herein enable device 6300 to have a disconnected gate logic through a single upper metal layer for a MUX device having four vertical transistors.

[0111] Figures 30-33 show device 6300 with disconnected gate logic for a MUX device, but it should be understood that various additional embodiments for other disconnected gate logic for other devices can be contemplated using four vertical transistors and signal routes extending in the cell height direction within the first upper metal layer. For example, various other gate extensions, bridges, vias, etc., can be implemented to provide any of the various disconnected gate logics independently or in combination with the vertical transistors. Exemplary computer system

[0112] Referring now to Figure 34, a block diagram of one embodiment of system 6700 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 6700 includes at least one instance of system on chip (SoC) 6706, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within SoC 6706 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 6706 is coupled to external memory 6702, peripherals 6704, and a power supply 6708.

[0113] A power supply 6708 is also provided, which supplies a supply voltage to the SoC 6706 and one or more supply voltages to the memory 6702 and / or peripheral devices 6704. In various embodiments, the power supply 6708 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 6706 are included (and two or more external memories 6702 are also included).

[0114] Memory 6702 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), RAMBUS DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0115] The peripheral device 6704 includes any desired circuit configuration depending on the type of system 6700. For example, in one embodiment, the peripheral device 6704 includes devices for various wireless communications such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 6704 also includes additional storage, including RAM storage, solid-state storage, or disk storage. The peripheral device 6704 includes user interface devices such as a display screen including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0116] As illustrated, system 6700 is shown to be applicable to a wide range of areas. For example, system 6700 may be used as part of the chips, circuits, components, etc., of a desktop computer 6710, a laptop computer 6720, a tablet computer 6730, a cellular or mobile phone 6740, or a television 6750 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 6760 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0117] System 6700 may be further used as part of one or more cloud-based services 6770. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 6700 may be used in one or more devices of a home 6780 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 34 also shows the application of System 6700 to various modes of transport 6790. For example, System 6700 may be used in control systems and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rental or owned). In various cases, System 6700 can be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications illustrated in Figure 34 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0118] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0119] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0120] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0121] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0122] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0123] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0124] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0125] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0126] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0127] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0128] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0129] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0130] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0131] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0132] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase indicates that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0133] Within this disclosure, various entities (which may be referred to as "units," "circuits," or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when it is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, systems having a processor unit and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0134] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0135] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0136] For the purposes of a U.S. patent application based on this disclosure, to state in the claims that the structure is “configured” to perform one or more tasks is not intended to expressly invoke Section 112(f) of the U.S. Patent Act with respect to that claim. not present If the applicant wishes to invoke Section 112(f) of the U.S. Patent Application under this Disclosure during the examination process, it would use “means for” to perform the function to describe the elements of the claim.

[0137] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0138] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0139] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0140] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0141] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. A first vertical transistor formed within a transistor region of an integrated circuit cell structure, comprising a first lower source / drain region, a first gate, and a first upper source / drain region stacked vertically, A second vertical transistor formed within the transistor region, having a second lower source / drain region, a second gate, and a second upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a first horizontal direction, and having at least some space between the first and second vertical transistors in the first direction, A first metal layer located vertically above the transistor region, the first metal layer includes parallel signal routing in the first direction, A signal routing within the first metal layer and at least one gate via coupled between the horizontally extended portion of the gate material from at least one of the first gate and the second gate, A second metal layer located vertically below the transistor region, comprising a second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction, A third metal layer positioned above the first and second upper source / drain regions and below the first metal layer, comprising at least one metal portion in contact with at least one of the first and second upper source / drain regions, the third metal layer A first contact coupled to the first upper source / drain region of the first vertical transistor, the first contact having a portion extending in the second direction away from the first upper source / drain region, A second contact coupled to the second upper source / drain region of the second vertical transistor, the second contact having a portion extending in the second direction away from the second upper source / drain region, A third metal layer including, A device equipped with the following features.

2. The apparatus according to claim 1, wherein the first vertical transistor and the second vertical transistor are complementary transistor types.

3. The apparatus according to claim 1, wherein the first vertical transistor is a PMOS transistor and the second vertical transistor is an NMOS transistor.

4. The apparatus according to claim 1, wherein the extended portion of the gate material is a gate bridge extending in the first direction over at least a certain distance between the vertical transistors, and the gate bridge is coupled between the first gate and the second gate.

5. The apparatus according to claim 4, wherein the at least one gate via is coupled between the signal routing in the first metal layer and the portion of the gate bridge within at least a fraction of the distance between the vertical transistors.

6. The apparatus according to claim 5, wherein the at least one gate via is coupled between the gate bridge and the signal input route of the signal routing in the first metal layer.

7. The apparatus according to claim 1, further comprising a fourth metal layer disposed below the first and second lower source / drain regions and above the second metal layer, the fourth metal layer including at least one metal portion in contact with at least one of the first and second lower source / drain regions.

8. The apparatus according to claim 7, further comprising a lower via coupled between the at least one metal portion in the fourth metal layer and the power routing in the second metal layer.

9. A first contact via coupled between the end of the first contact distal to the first upper source / drain region of the first vertical transistor and the signal output route of the signal routing within the first metal layer, A second contact via coupled between the end of the second contact, distal to the second upper source / drain region of the second vertical transistor, and the signal output route, The apparatus according to claim 1, further comprising the following:

10. A third vertical transistor formed within the transistor region, having a third lower source / drain region, a third gate, and a third upper source / drain region stacked in the vertical direction, and parallel to the first vertical transistor along the second direction, A fourth vertical transistor formed within the transistor region, having a fourth lower source / drain region, a fourth gate, and a fourth upper source / drain region stacked in the vertical direction, parallel to the third vertical transistor along the first horizontal direction, and having at least some distance between the third vertical transistor and the fourth vertical transistor in the first direction, A first contact in the third metal layer, coupled between the first upper source / drain region of the first vertical transistor and the third upper source / drain region of the third vertical transistor, and having a portion extending in the second direction beyond the upper source / drain region of the third vertical transistor, A second contact in the third metal layer, coupled between the upper second source / drain region of the second vertical transistor and the fourth upper source / drain region of the fourth vertical transistor, The apparatus according to claim 1, further comprising the following:

11. A first contact via coupled between the portion of the first contact extending in the second direction beyond the third upper source / drain region of the third vertical transistor and the signal output route of the signal routing within the first metal layer, A metal extension portion coupled to the bottom of the fourth lower source / drain region of the fourth vertical transistor, the metal extension portion extending in the second direction from the bottom of the fourth lower source / drain region toward the boundary of the integrated circuit cell, A second contact via coupled between the metal extension portion and the signal output route, The apparatus according to claim 10, further comprising the following:

12. It is a device, A first vertical transistor formed within a transistor region of an integrated circuit cell structure, comprising a first lower source / drain region, a first gate, and a first upper source / drain region stacked vertically, A second vertical transistor formed within the transistor region, having a second lower source / drain region, a second gate, and a second upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a first horizontal direction, and having at least some space between the first vertical transistor and the second vertical transistor in the first direction, A first metal layer located vertically above the transistor region, the first metal layer includes parallel signal routing in the first direction, A first gate bridge extending in the first direction over at least a certain distance between the first vertical transistor and the second vertical transistor, wherein the first gate bridge is coupled between the first gate and the second gate, A first gate via coupled between the first signal input route of the signal routing in the first metal layer and the first gate bridge, A second metal layer located vertically below the transistor region, comprising a second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction, A third metal layer disposed below the first and second lower source / drain regions and above the second metal layer, the third metal layer includes lower metal contacts coupled to the first and second lower source / drain regions, The lower contact via between the lower metal contact and the power routing in the second metal layer, A fourth metal layer positioned above the first and second upper source / drain regions and below the first metal layer, the fourth metal layer includes an upper metal contact coupled to the first and second upper source / drain regions, the upper metal contact having a portion extending in the second direction away from the first and second upper source / drain regions, An apparatus comprising: a first signal output route of the signal routing within the first metal layer; and a first set of upper contact vias coupled between the upper metal contacts coupled to the first vertical transistor and the second vertical transistor.

13. The aforementioned lower contact via is A first set of lower contact vias coupled between the first power route of the power routing in the second metal layer and the lower metal contact coupled to the first vertical transistor, The apparatus according to claim 12, comprising: a second power route of the power routing in the second metal layer and a second set of lower contact vias coupled between the lower metal contacts coupled to the second vertical transistor.

14. It is a device, A first vertical transistor formed within a transistor region of an integrated circuit cell structure, comprising a first lower source / drain region, a first gate, and a first upper source / drain region stacked vertically, A second vertical transistor formed within the transistor region, having a second lower source / drain region, a second gate, and a second upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a first horizontal direction, and having at least some space between the first vertical transistor and the second vertical transistor in the first direction, A third vertical transistor formed within the transistor region, having a third lower source / drain region, a third gate, and a third upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a second direction perpendicular to the first horizontal direction, and having at least some space between the first vertical transistor and the third vertical transistor in the second direction, A fourth vertical transistor formed in the transistor region, having a fourth lower source / drain region, a fourth gate, and a fourth upper source / drain region stacked in the vertical direction, parallel to the third vertical transistor in the first direction, with at least some space between the third vertical transistor and the fourth vertical transistor in the first direction, parallel to the second vertical transistor in the second direction, with at least some space between the second vertical transistor and the fourth vertical transistor in the second direction, A first metal layer located vertically above the transistor region, the first metal layer includes parallel signal routing in the first direction, A first gate bridge extending in the first direction over at least a certain distance between the first vertical transistor and the second vertical transistor, coupled between the first gate and the second gate, A second gate bridge extending in the first direction over at least a certain distance between the third vertical transistor and the fourth vertical transistor, coupled between the third gate and the fourth gate, A first gate via coupled between the first signal input route of the signal routing in the first metal layer and the first gate bridge, A second gate via coupled between the second signal input route of the signal routing in the first metal layer and the second gate bridge, A second metal layer located vertically below the transistor region, comprising a second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction, A third metal layer disposed below the first, second, third, and fourth lower source / drain regions and above the second metal layer, A first lower metal contact coupled to the first lower source / drain region of the first vertical transistor, A second lower metal contact coupled to the second lower source / drain region of the second vertical transistor, A third lower metal contact coupled to the third lower source / drain region of the third vertical transistor, and A third metal layer comprising a fourth lower metal contact coupled to the fourth lower source / drain region of the fourth vertical transistor, the fourth lower metal contact including a metal extension portion extending in the second direction toward the boundary of the integrated circuit cell from the fourth lower source / drain region, A fourth metal layer disposed above the first, second, third, and fourth upper source / drain regions and below the first metal layer, A first upper contact, coupled between the first upper source / drain region of the first vertical transistor and the third upper source / drain region of the third vertical transistor, and having a portion that extends in the second direction beyond the upper source / drain region of the third vertical transistor, and The fourth metal layer includes a second upper contact in the fourth metal layer, which is coupled between the second upper source / drain region of the second vertical transistor and the fourth upper source / drain region of the fourth vertical transistor, A first contact via coupled between the portion of the first upper contact extending in the second direction beyond the third upper source / drain region of the third vertical transistor and the signal output route of the signal routing within the first metal layer, A device comprising: a second contact via coupled between the metal extension portion of the fourth lower metal contact and the signal output route.

15. A first vertical transistor formed within a transistor region of an integrated circuit cell structure, comprising a first lower source / drain region, a first gate, and a first upper source / drain region stacked vertically, A second vertical transistor formed within the transistor region, having a second lower source / drain region, a second gate, and a second upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a first horizontal direction, and having at least some space between the first vertical transistor and the second vertical transistor in the first direction, A third vertical transistor formed within the transistor region, having a third lower source / drain region, a third gate, and a third upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a second direction perpendicular to the first horizontal direction, and having at least some space between the first vertical transistor and the third vertical transistor in the second direction, A fourth vertical transistor formed in the transistor region, having a fourth lower source / drain region, a fourth gate, and a fourth upper source / drain region stacked in the vertical direction, parallel to the third vertical transistor in the first direction, with at least some space between the third vertical transistor and the fourth vertical transistor in the first direction, parallel to the second vertical transistor in the second direction, with at least some space between the second vertical transistor and the fourth vertical transistor in the second direction, A first metal layer located vertically above the transistor region, the first metal layer includes parallel signal routing in the first direction, A second metal layer located vertically below the transistor region, the second metal layer includes parallel power routing in a second direction perpendicular to the first horizontal direction, A third metal layer disposed below the first, second, third, and fourth lower source / drain regions and above the second metal layer, the third metal layer includes lower metal contacts coupled between the first, second, third, and fourth lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor, A fourth metal layer disposed above the first, second, third, and fourth upper source / drain regions and below the first metal layer, A first upper contact coupled between the first upper source / drain region of the first vertical transistor and the second upper source / drain region of the second vertical transistor, and A fourth metal layer including a second upper contact coupled between the third upper source / drain region of the third vertical transistor and the fourth upper source / drain region of the fourth vertical transistor, A first gate extension extending horizontally from the first gate for at least a certain distance in the second direction, A second gate extension extending horizontally from the second gate for at least a certain distance in the second direction, A third gate extension extending horizontally from the third gate for at least a certain distance in the second direction, A fourth gate extension extending horizontally from the fourth gate for at least a certain distance in the second direction, A first gate via coupled between the first gate extension and the first signal input route of the signal routing within the first metal layer, A second gate via coupled between the second gate extension and the first signal input route of the signal routing within the first metal layer, A third gate via coupled between the third gate extension and the second signal input route of the signal routing within the first metal layer, A fourth gate via coupled between the fourth gate extension and the second signal input route of the signal routing within the first metal layer, A device comprising a contact via coupled between the lower metal contact and the first signal input route.

16. A first vertical transistor formed within a transistor region of an integrated circuit cell structure, comprising a first lower source / drain region, a first gate, and a first upper source / drain region stacked vertically, A second vertical transistor formed within the transistor region, having a second lower source / drain region, a second gate, and a second upper source / drain region stacked in the vertical direction, parallel to the first vertical transistor along a first horizontal direction, and having at least some space between the first and second vertical transistors in the first direction, A first metal layer located vertically above the transistor region, the first metal layer includes parallel signal routing in the first direction, A signal routing within the first metal layer and at least one gate via coupled between the horizontally extended portion of the gate material from at least one of the first gate and the second gate, A second metal layer located vertically below the transistor region, comprising a second metal layer including parallel power routing in a second direction perpendicular to the first horizontal direction, A third metal layer positioned above the first and second upper source / drain regions and below the first metal layer, comprising at least one metal portion in contact with at least one of the first and second upper source / drain regions, wherein the third metal layer comprises a first contact coupled between the first upper source / drain region of the first vertical transistor and the second upper source / drain region of the second vertical transistor, A device equipped with the following features.

17. A third vertical transistor formed within the transistor region, having a third lower source / drain region, a third gate, and a third upper source / drain region stacked in the vertical direction, and parallel to the first vertical transistor along the second direction, A fourth vertical transistor formed within the transistor region, having a fourth lower source / drain region, a fourth gate, and a fourth upper source / drain region stacked in the vertical direction, parallel to the third vertical transistor along the first horizontal direction, and having at least some distance between the third vertical transistor and the fourth vertical transistor in the first direction, A second contact in the third metal layer, coupled between the third upper source / drain region of the third vertical transistor and the fourth upper source / drain region of the fourth vertical transistor, The apparatus according to claim 16, further comprising the following:

18. The apparatus further comprises a third contact coupled between the first, second, third, and fourth lower source / drain regions of the first vertical transistor, the second vertical transistor, the third vertical transistor, and the fourth vertical transistor, wherein the first gate, the second gate, the third gate, and the fourth gate each include a first gate extension, a second gate extension, a third gate extension, and a fourth gate extension, each gate extension extending horizontally from its individual gate by at least a certain distance in the second direction, and the apparatus is A first gate via coupled between the first gate extension and the first signal input route of the signal routing in the first metal layer, wherein the first gate via is at least one gate via, A second gate via coupled between the second gate extension and the first signal input route of the signal routing within the first metal layer, A third gate via coupled between the third gate extension and the second signal input route of the signal routing within the first metal layer, A fourth gate via coupled between the fourth gate extension and the second signal input route of the signal routing within the first metal layer, The apparatus according to claim 17, further comprising a contact via coupled between the third contact and the first signal input route.

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