Bias voltage generation circuit and electronic circuit

Abstract

This bias voltage generation circuit comprises: a first constant current source for supplying a first constant current; a second constant current source for supplying a second constant current that is smaller than the first constant current; and a bias voltage generation unit that includes at least one first MOS transistor, and generates a prescribed bias voltage on the basis of the second constant current or the first and second constant currents. The current is supplied by using a current mirror circuit made up of the first MOS transistor and at least one second MOS transistor. The bias voltage generation circuit is such that, on the basis of an operation mode switching control signal, when an electronic circuit is not running, a bias voltage generation unit generates a prescribed bias voltage on the basis of the second constant current, and when the electronic circuit is running, the bias voltage generation unit generates a prescribed bias voltage on the basis of the first and second constant currents or the first constant current.

Description

Technical Field

[0001] The present invention relates to a bias voltage generation circuit and an electronic circuit including the bias voltage generation circuit.

Background Art

[0002] It is already known that there is a demand to reduce the consumption current in order to use a rechargeable battery for a long period of time. For example, in the sleep mode, a method of selectively switching in response to an operation mode switching control signal so as to reduce the consumption current compared to the operation mode is disclosed in, for example, Patent Document 1.

[0003] The low dropout (LDO) regulator disclosed in Patent Document 1 (1) a pass gate that controllably couples a voltage rail to a regulator output in response to a pass gate control signal that is an operation mode switching control signal; (2) a controllable through differential amplifier that is switchable between a through limit state and a full through state, receives feedback from the regulator output, and is configured to generate the pass gate control signal at a full through rate in the full through state and at a reduced through rate in the through limit state based on a reference voltage and the feedback.

[0004] Next, a conventional comparator circuit 100 will be specifically described as an example.

[0005] FIG. 17 is a circuit diagram showing the configuration of a comparator circuit 100 according to a conventional example. Further, FIG. 18 is a timing chart of each signal showing the operation of the comparator circuit 100 of FIG. 17.

[0006] In Figure 17, the comparator circuit 100 comprises a comparator section 101 and a bias voltage generation section 102. The comparator section 101 is configured as a typical comparator using a differential amplifier and an inverter INV1, and the differential amplifier is configured with MOS field-effect transistors (hereinafter referred to as MOS transistors) Q1 to Q7.

[0007] In the comparator section 101, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 100 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. During the operation of the comparator section 101, a tail current Itail flows through MOS transistor Q5. The output voltage of the differential amplifier is output to the comparison result signal output terminal T4 via inverter INV1 from the connection point of the drains of MOS transistors Q6 and Q7.

[0008] In the bias voltage generation unit 102, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator unit 101, and is grounded via a constant current source CI1 that supplies the reference current IREF, and switches SW1 and SW2. The connection point of switches SW1 and SW2 generates a bias voltage VNBIAS, which is applied to the drain and gate of MOS transistor Q8 and the gates of MOS transistors Q5 and Q7. The sources of MOS transistors Q8, Q5, and Q7 are grounded.

[0009] The block enable signal BLKEN, which is an operating mode switching control signal input to the block enable signal input terminal T3, is input to the control terminal of switch SW1 and also to the control terminal of switch SW2 via inverter INV2. Here, when a high-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned on and switch SW2 is turned off. MOS transistors Q5, Q7, and Q8 form a current mirror circuit, and current flows through MOS transistor Q8 according to the bias voltage VNBIAS, and a current proportional to that current flows through MOS transistors Q5 and Q7. On the other hand, when a low-level block enable signal BLKEN is input to the block enable signal input terminal T3, switch SW1 is turned off and switch SW2 is turned on.

[0010] In the comparator circuit 100 configured as described above, as shown in Figure 18, at time t1, the block enable signal BLKEN is switched from L level to H level. El Then, the operating mode switches from sleep mode to startup mode. replacement The bias voltage VNBIAS rises from a pulled-down state to the gate-source voltage Vgs of the MOS transistor Q8, which corresponds to the reference current IREF, during a startup period, and then enters active mode at time t2. In other words, the comparator circuit 100 cannot perform to its full potential without going through the startup period from time t1 to t2. The time required for this depends on the magnitude of the reference current IREF and the parasitic capacitance value in the wiring of the bias voltage VNBIAS. [Prior art documents] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Publication No. 2019-053757 [Overview of the Initiative] [Problems that the invention aims to solve]

[0012] However, the conventional method of switching circuits on and off as needed, while achieving low current consumption, had the side effect of not being able to operate stably immediately after startup. For example patent Reference 1 discloses a configuration in which one of the parallel-connected current sources is switched on / off depending on the operating mode, for the purpose of switching the tail current (Itail). However, this circuit had the problem of not being able to operate stably immediately after startup.

[0013] The object of the present invention is to solve the above problems and to provide a bias voltage generation circuit for an electronic circuit that can start the desired operation immediately after switching the current consumption according to the operation mode switching control signal, and an electronic circuit equipped with the internal power supply voltage generation circuit. [Means for solving the problem]

[0014] A bias voltage generation circuit according to a first aspect of the present invention is: A first constant current source that supplies a first constant current, A second constant current source that supplies a second constant current smaller than the first constant current, A bias voltage generating circuit comprising at least one first MOS transistor and a bias voltage generating unit that generates a predetermined bias voltage based on a second constant current or the first and second constant currents, wherein the bias voltage generating circuit is for an electronic circuit to which current is supplied by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor, The bias voltage generation circuit, based on the operating mode switching control signal, (1) When the electronic circuit is not operating, the bias voltage generating unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is in operation, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents, or the first constant current. It is composed.

[0015] Also, the electronic circuit according to the second aspect of the present invention is a first constant current source that supplies a first constant current, a second constant current source that supplies a second constant current smaller than the first constant current, an electronic circuit having a bias voltage generation circuit including at least one first MOS transistor and a bias voltage generation unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, the bias voltage generation circuit is supplied with current by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor, the bias voltage generation circuit is based on an operation mode switching control signal, (1) When the electronic circuit is not operating, the bias voltage generation unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is operating, the bias voltage generation unit is configured to generate a predetermined bias voltage based on the first and second constant currents or the first constant current. It is configured.

Advantages of the Invention

[0016] Therefore, according to the bias voltage generation circuit or the electronic circuit according to the present invention, according to the operation mode switching control signal, in order to reduce power consumption, even if the amount of current of the current source is reduced, the gate voltage of the bias transistor is kept constant, so that the desired operation can be started immediately after switching the operation mode switching control signal.

Brief Description of the Drawings

[0017] [Figure 1] It is a circuit diagram showing a configuration example of the comparator circuit 1 according to Embodiment 1. [Figure 2] It is a timing chart of each signal showing the operation of the comparator circuit 1 in FIG. 1. [Figure 3]This figure shows a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has risen sufficiently to a predetermined voltage when a signal is detected. [Figure 4] This figure shows a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS is in the process of rising sufficiently to a predetermined voltage at the time of signal detection. [Figure 5] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12A according to Modification 1. [Figure 6] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12B according to Modification 2. [Figure 7] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12C related to Modification 3. [Figure 8] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12D according to Modification 4. [Figure 9] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12E according to Modification 5. [Figure 10] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12F according to modified example 6. [Figure 11] This is a circuit diagram showing an example configuration of the bias voltage generation unit 12G according to modified example 7. [Figure 12] This is a circuit diagram showing an example configuration of the source follower circuit 3 according to Embodiment 2. [Figure 13] This is a circuit diagram showing an example configuration of the voltage generation circuit 4 according to Embodiment 3. [Figure 14] This is a circuit diagram showing an example configuration of the time constant circuit 5 according to Embodiment 4. [Figure 15] This is a circuit diagram showing an example configuration of the comparator circuit 1A according to Embodiment 5. [Figure 16] This is a circuit diagram showing an example configuration of the comparator circuit 1B according to Embodiment 6. [Figure 17] This is a circuit diagram showing the configuration of a conventional comparator circuit 100. [Figure 18] Figure 17 shows the timing chart of each signal illustrating the operation of the comparator circuit 100. [Figure 19] This is a circuit diagram showing the configuration of the comparator circuit 100A related to Comparative Example 1. [Figure 20] Figure 19 shows the timing chart of each signal illustrating the operation of the comparator circuit 100A. [Figure 21] This is a circuit diagram showing the configuration of the comparator circuit 100B according to Comparative Example 2. [Modes for carrying out the invention]

[0018] Comparative examples, embodiments, and modified examples of the present invention will be described below with reference to the drawings. The same or similar components are denoted by the same reference numerals.

[0019] (Inventor's insights) The embodiment of the present invention is characterized by keeping the gate voltage of the bias generation transistor constant even when the current amount of the current source is reduced, in order to reduce current consumption when it is desired to reduce circuit current when it is not needed, while still being able to operate immediately when it is needed.

[0020] (Comparative Example 1) Figure 19 is a circuit diagram showing an example configuration of comparator circuit 100A according to Comparative Example 1. Figure 20 is a timing chart of each signal showing the operation of comparator circuit 100A in Figure 19. Comparator circuit 100A in Figure 19 differs from comparator circuit 100 in Figure 17 in the following respects.

[0021] (1) Instead of comparator unit 101, comparator unit 101A is provided, and comparator unit 101A further includes constant current sources CI11, CI12 that generate a reserve current Itailp (Figure 20).

[0022] As shown in the comparative example above, in order to facilitate operation immediately after startup, a small reserve current Itailp (Figure 20) is supplied from constant current sources CI11 and CI12, allowing the comparator section 101A to operate even with a small circuit current.

[0023] However, with the small reserve current Itailp in Comparative Example 1, even though the comparator section 101A attempts to operate, it takes the same amount of time as the unprotected circuit to achieve the expected circuit operation. In addition, a reserve current is required for each current path, and the reserve current needs to be increased as the number of current paths increases.

[0024] Figure 21 is a circuit diagram showing the configuration of comparator circuit 100B according to Comparative Example 2. Comparator circuit 100B in Figure 21 differs from comparator circuit 100 in Figure 17 in the following respects.

[0025] (1) Comparator section 101B is provided instead of comparator section 101. The connection point between the sources of MOS transistors Q3 and Q4 is grounded via switch SW3 and MOS transistor Q5. Also, the drain of MOS transistor Q6 is grounded via switch SW4 and MOS transistor Q7. When the block enable signal BLKEN is at a high level, switches SW3 and SW4 are turned on, while when the block enable signal BLKEN is at a low level, switches SW3 and SW4 are turned off. (2) The bias voltage generation unit 102B is provided instead of the bias voltage generation unit 102. Here, the power supply voltage VDD is grounded via the constant current source CI11 and the MOS transistor Q8.

[0026] In Comparative Example 2, configured as described above, the bias voltage VNBIAS is constantly applied to the gates of MOS transistors Q5 and Q7 to enable immediate operation from startup, thereby reducing power consumption by disconnecting the current path. However, while this allows for both reduction of circuit current and improvement of startup time, it does not allow for a reduction in the reference current IREF.

[0027] Embodiments of the present invention will be described below, including a bias voltage generation circuit that can solve these problems and an electronic circuit equipped with the bias voltage generation circuit.

[0028] (Embodiment 1) Figure 1 is a circuit diagram showing an example configuration of the comparator circuit 1 according to Embodiment 1. Figure 2 is a timing chart of each signal showing the operation of the comparator circuit 1 in Figure 1.

[0029] In Figure 1, the comparator circuit 1 comprises a comparator section 11 and a bias voltage generation section 12. The comparator section 11 is composed of a differential amplifier and an inverter INV1, and further includes switches SW3 and SW4 compared to the comparator section 101 in Figure 17. Here, the differential amplifier is composed of MOS transistors Q1 to Q7. The connection points between the sources of MOS transistors Q3 and Q4 are grounded via switch SW3 and MOS transistor Q5. In addition, the drain of MOS transistor Q6 is grounded via switch SW4 and MOS transistor Q7.

[0030] In the comparator section 11, MOS transistors Q1, Q2, and Q6 are P-channel MOS transistors, and MOS transistors Q3, Q4, Q5, and Q7 are N-channel MOS transistors. The comparator circuit 1 has a non-inverting input terminal T1, an inverting input terminal T2, a block enable signal input terminal T3, and a comparison result signal output terminal T4. During the operation of the comparator section 11, a tail current Itail flows through MOS transistor Q5. The output voltage of the differential amplifier is output to the comparison result signal output terminal T4 via inverter INV1 from the connection point of the drains of MOS transistors Q6 and Q7.

[0031] In the bias voltage generation unit 12, the power supply voltage VDD is connected to the sources of the MOS transistors Q1, Q2, and Q6 of the comparator unit 11, and is grounded through a constant current source CI21 that supplies a first reference current IREFL, switches SW1 and SW2, and a MOS transistor Q9. Also, the power supply voltage VDD is grounded through a constant current source CI22 that supplies a second reference current IREFS (<IREFL), and MOS transistors Q8 and Q9. The connection point of the switches SW1 and SW2 generates a bias voltage VNBIAS, which is applied to the drain and gate of the MOS transistor Q8, the gate of the MOS transistor Q9, and the gates of the MOS transistors Q5 and Q7. The sources of the MOS transistors Q9, Q5, and Q7 are grounded.

[0032] A block enable signal BLKEN, which is an operation mode switching control signal input to the block enable signal input terminal T3, is input to the control terminals of the switch SW1 and the switch SW2. Here, when a high-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned on. The MOS transistors Q5, Q7, and Q9 form a current mirror circuit. According to the bias voltage VNBIAS, a current flows through the MOS transistor Q9, and currents proportional to this current flow through the MOS transistors Q5 and Q7. On the other hand, when a low-level block enable signal BLKEN is input to the block enable signal input terminal T3, the switches SW1 and SW2 are turned off. Note that the gates of the MOS transistors Q1 to Q9 are control terminals.

[0033] In the comparator circuit 1 configured as described above, as shown in FIG. 2, at time t11, the block enable signal BLKEN is switched from the low level to the high level, and the operation mode is switched from the sleep mode to the active mode. Here, (1) In sleep mode (when comparator circuit 1 is not operating), both switches SW1 and SW2 are off, and only the constant current source CI22 supplies the constant current IREFS to the series circuit of MOS transistors Q8 and Q9. This causes the bias voltage corresponding to the constant current IREFS to VNBIAS Generates (Itailpe=0). (2) In active mode (when comparator circuit 1 is operating), both switches SW1 and SW2 are on, and constant current sources CI21 and CI22 supply constant currents IREFL and IREFS, respectively, to MOS transistor Q9. This causes the bias voltage corresponding to the constant current (IREFL + IREFS) to be supplied. VNBIAS This generates a constant current (IREFL + IREFS), and a tail current Itail corresponding to this constant current flows through the MOS transistor Q5.

[0034] In other words, the size of the MOS transistors on the diode connection side (connecting the gate and drain) of the current mirror circuit composed of MOS transistors Q8, Q9, Q5, and Q7 is switched, and the bias voltage generated in the constant current IREFS with reduced current during sleep mode is changed. VNBIAS And, the bias voltage generated by IREFL+IREFS, which is the constant current that we want to flow in active mode. VNBIAS By combining these, the tail current Itail, which corresponds to the sum of the two constant currents IREFL and IREFS, can be immediately supplied at time t11.

[0035] Figure 3 is a diagram showing a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS has risen sufficiently to a predetermined voltage at the time of signal detection. Figure 4 is a diagram showing a comparison of the operation of the comparator circuit 100 according to Comparative Example 1 and the comparator circuit 1 according to the embodiment, and is a timing chart of each signal when the bias voltage VNBIAS is in the process of rising sufficiently to a predetermined voltage at the time of signal detection.

[0036] As is clear from Figures 3 and 4, in Comparative Example 1, when attempting to detect the bias voltage, VNBIAS A difference in detection delay time occurs between when the signal is fully raised (Figure 3) and when it is still rising (Figure 4). That is, Ta1 ≠ Tb1. In contrast, in Embodiment 1, a predetermined tail current Itail can be supplied immediately after the block enable signal BLKEN rises from L level to H level (time t11). That is, there is no difference in detection delay time between these two cases, and Ta2 = Tb2. Furthermore, the current consumption ICe of Embodiment 1 in sleep mode is less than the current consumption ICc of Comparative Example 1. As described above, Embodiment 1 has the aforementioned unique effects compared to the comparative examples.

[0037] As described above, according to Embodiment 1, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is an operating mode switching control signal.

[0038] (Variation 1) Figure 5 is a circuit diagram showing an example configuration of the bias voltage generation unit 12A according to Modification 1. The bias voltage generation unit 12A in Figure 5 differs from the bias voltage generation unit 12 in Figure 1 in the following respects. (1) The gates and drains of both MOS transistors Q8 and Q9 were connected by diodes. The comparator unit 11 shown in Figure 1 is used.

[0039] The comparator circuit having the bias voltage generating unit 12A configured as described above operates in the same manner as the comparator circuit 1 of Embodiment 1, except for the differences in operation in the above configuration.

[0040] (Modification 2) Figure 6 is a circuit diagram showing an example configuration of the bias voltage generation unit 12B according to Modification 2. The bias voltage generation unit 12B in Figure 6 differs from the bias voltage generation unit 12 in Figure 1 in the following respects. (1) The power supply voltage VDD is grounded through a constant current source CI21 that supplies a constant current IREFL, a switch SW1, a switch SW2, and a MOS transistor Q9a having a threshold value VthS. (2) The power supply voltage VDD is grounded through a constant current source CI22 that supplies a constant current IREFS (<IREFL), the connection point of SW1 and SW2, a switch SW5, and a MOS transistor Q9b having a threshold value VthL (>VthS). Note that the connection point of SW1 and SW2 is connected to the gates of MOS transistor Q9a and MOS transistor Q9b. (3) The block enable signal BLKEN is applied to the control terminals of switches SW1 and SW2 and, via an inverter INV3, to the control terminal of switch SW5. Note that the comparator section 11 in FIG. 1 is used.

[0041] In the bias voltage generation section 12B configured as described above, when an L-level block enable signal BLKEN is input, switch SW5 is turned on while switches SW1 and SW2 are turned off. Also, when an H-level block enable signal BLKEN is input, switch SW5 is turned off while switches SW1 and SW2 are turned on.

[0042] The comparator circuit having the bias voltage generation section 12B configured as described above operates in the same manner as the comparator circuit 1 of Embodiment 1, except for the operational differences in the said configuration.

[0043] (Modification 3) FIG. 7 is a circuit diagram showing a configuration example of a bias voltage generation section 12C according to Modification 3. The bias voltage generation section 12C in FIG. 7 is different from the bias voltage generation section 12 in FIG. 1 in the following points. (1) A resistor R1 is provided instead of the MOS transistor Q8. Note that the comparator section 11 in FIG. 1 is used.

[0044] The comparator circuit having the bias voltage generating unit 12C configured as described above operates in the same manner as the comparator circuit 1 of Embodiment 1, except for the differences in operation in the above configuration.

[0045] (Modification 4) Figure 8 is a circuit diagram showing an example configuration of the bias voltage generation unit 12D according to Modification 4. The bias voltage generation unit 12D in Figure 8 differs from the bias voltage generation unit 12A in Figure 5 in the following respects. (1) Replace the MOS transistor Q8 with a resistor R1. The comparator unit 11 shown in Figure 1 is used.

[0046] The comparator circuit having the bias voltage generation unit 12D configured as described above operates in the same way as the comparator circuit of Modification 1, except for the differences in operation in the above configuration.

[0047] (Variation 5) Figure 9 is a circuit diagram showing an example configuration of the bias voltage generation unit 12E according to Modification 5. The bias voltage generation unit 12E in Figure 9 differs from the bias voltage generation unit 12C in Figure 7 in the following respects. (1) A diode D1 is provided in place of resistor R1. Here, the anode of diode D1 is connected to the constant current source CI22, and its cathode is connected to the drain and gate of MOS transistor Q9. The comparator unit 11 shown in Figure 1 is used.

[0048] The comparator circuit having the bias voltage generating unit 12E configured as described above operates in the same way as the comparator circuit of Modification 3, except for the differences in operation in the above configuration.

[0049] (Experimental variation 6) Figure 10 is a circuit diagram showing an example configuration of the bias voltage generation unit 12F according to Modification 6. The bias voltage generation unit 12F in Figure 10 differs from the bias voltage generation unit 12D in Figure 8 in the following respects. (1) A diode D1 is provided in place of resistor R1. Here, the anode of diode D1 is connected to the constant current source CI22, and its cathode is connected to the drain and gate of MOS transistor Q9. The comparator unit 11 shown in Figure 1 is used.

[0050] The comparator circuit having the bias voltage generating unit 12F configured as described above operates in the same way as the comparator circuit of Modification 4, except for the differences in operation in the above configuration.

[0051] (Example 7) Figure 11 is a circuit diagram showing an example configuration of the bias voltage generation unit 12G according to Modification 7. The bias voltage generation unit 12G in Figure 11 differs from the bias voltage generation unit 12A in Figure 5 in the following respects. (1) Diode D2 is provided in place of MOS transistor Q9. Here, the anode of diode D2 is connected to the source of MOS transistor Q8, and its cathode is grounded. (2) Switch SW2 is connected across diode D2, and based on the block enable signal BLKEN, the terminals of diode D2 are short-circuited or open-circuited. The comparator unit 11 shown in Figure 1 is used.

[0052] The comparator circuit having the bias voltage generation unit 12G configured as described above operates in the same way as the comparator circuit of Modification 1, except for the differences in operation in the above configuration.

[0053] Furthermore, the MOS transistors, resistors, and diodes used in Embodiment 1 and Modifications 1 to 7 described above can also be placed on the ground side of the MOS transistor that serves as the reference for the current mirror circuit.

[0054] (Embodiment 2) Figure 12 is a circuit diagram showing an example of the configuration of a source follower circuit 3 according to Embodiment 2.

[0055] In Figure 12, the source follower circuit 3 has an input terminal T11, an output terminal T12, and a block enable signal input terminal T3, and is configured with the bias voltage generation unit 12 shown in Figure 1, a MOS transistor Q4, a switch SW5, and a MOS transistor Q10. Here, MOS transistors Q4 and Q10 are N-channel MOS transistors.

[0056] The power supply voltage VDD is grounded via MOS transistor Q4, switch SW5, and MOS transistor Q10. Bias voltage VNBIAS This is applied to the gate of MOS transistor Q10. The input voltage VIN is input to input terminal T11, and when source follower circuit 3 is operating, from output terminal T12 、 The output voltage Vout is output.

[0057] In the source follower circuit 3 configured as described above, when a low-level block enable signal BLKEN is applied, switches SW1 and SW2 are turned off, and the constant current source CI22 of the bias voltage generation unit 12 operates. Furthermore, when a high-level block enable signal BLKEN is applied, constant current sources CI21 and CI22 operate, increasing the constant current from IREFS to (IREFS + IREFL), and the increased bias voltage corresponding to that current is generated. VNBIAS This is applied to the gate of the MOS transistor Q10.

[0058] In the source follower circuit 3 configured as described above, the block enable signal BLKEN is switched from L level to H level, and the operating mode is switched from sleep mode to active mode. At this time, as described above, the constant current sources CI21 and CI22 operate, and the constant current increases from IREFS to (IREFS + IREFL), and the increased bias voltage corresponding to this current increases VNBIAS This is applied to the gate of the MOS transistor Q10, allowing the source follower circuit 3 to be immediately put into operation.

[0059] As described above, according to Embodiment 2, in accordance with the block enable signal BLKEN, which is the operating mode switching control signal, the desired current consumption is obtained immediately after switching to the increased current consumption. of It can start working.

[0060] Note that the bias voltage generation unit in Figure 12 may be replaced with the bias voltage generation units 12A to 12G shown in modified examples 1 to 7 of Figures 5 to 11.

[0061] (Embodiment 3) Figure 13 is a circuit diagram showing an example configuration of the voltage generation circuit 4 according to Embodiment 3. The voltage generation circuit 4 in Figure 13 differs from the source follower circuit 3 in Figure 12 in the following respects. (1) Replace the MOS transistor Q4 with a resistor R2.

[0062] The voltage generation circuit 4 configured as described above operates when a high-level block enable signal BLKEN is input, and can generate and output a predetermined voltage determined by the resistor R2 and the MOS transistor Q10 from the output terminal T12.

[0063] As described above, according to Embodiment 3, the desired voltage generation operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is an operating mode switching control signal.

[0064] Note that the voltage generation circuit 4 in Figure 13 may be configured using the bias voltage generation units 12A to 12G shown in modified examples 1 to 7 of Figures 5 to 11, instead of the bias voltage generation unit in Figure 13.

[0065] (Embodiment 4) Figure 14 is a circuit diagram showing an example configuration of the time constant circuit 5 according to Embodiment 4. The time constant circuit 5 in Figure 14 differs from the voltage generation circuit 4 in Figure 13 in the following respects. (1) Replace the resistor R2 with a capacitor C1.

[0066] The time constant circuit 5 configured as described above operates when a high-level block enable signal BLKEN is input, and can generate and output a voltage from the output terminal T12 that decreases with a predetermined time constant determined by the current values ​​of capacitor C1 and MOS transistor Q10.

[0067] As described above, according to Embodiment 4, a voltage generation operation with a desired time constant can be started immediately after switching to an increased current consumption in accordance with the block enable signal BLKEN, which is an operating mode switching control signal.

[0068] Note that the time constant circuit 5 in Figure 14 may be configured using the bias voltage generation units 12A to 12G shown in modified examples 1 to 7 of Figures 5 to 11, instead of the bias voltage generation unit in Figure 14.

[0069] (Embodiment 5) Figure 15 is a circuit diagram showing an example configuration of comparator circuit 1A according to Embodiment 5. Comparator circuit 1A in Figure 15 differs from comparator circuit 1 in Figure 1 in the following ways. (1) Instead of MOS transistors Q1 to Q7, MOS transistors Q11 to Q17 are provided. Here, MOS transistors Q13 to Q15 and Q17 are P-channel MOS transistors, and MOS transistors Q11 to Q12 and Q16 are N-channel MOS transistors. (2) Switches SW11 to SW14 are provided instead of switches SW1 to SW4.

[0070] As described above, by replacing some of the N-channel MOS transistors with P-channel MOS transistors, the device can be used not only as a ground-side current source but also as a power-side current source. This is also true for embodiments 2 to 4.

[0071] The comparator circuit 1A, configured as described above, operates when a high-level block enable signal BLKEN is input, allowing currents corresponding to IREFL+IREFS to flow through MOS transistors Q15 and Q17.

[0072] As described above, according to Embodiment 5, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is an operating mode switching control signal.

[0073] Note that the bias voltage generation section in Figure 15 may be configured using the modified circuits 1 to 7 in Figures 5 to 11 instead of the circuit in Figure 15.

[0074] (Embodiment 6) Figure 16 is a circuit diagram showing an example configuration of comparator circuit 1B according to Embodiment 6. Comparator circuit 1B in Figure 16 differs from comparator circuit 1 in Figure 1 in the following ways. (1) A bias voltage generation unit 12H is provided, in which a switch SW11 is inserted between the constant current source CI22 and the drain of the MOS transistor Q8. (2) The block enable signal BLKEN is further input to the control terminal of the switch SW11 via the inverter INV11. That is, the bias voltage generation unit 12H generates a predetermined bias voltage based on a second constant current when the electronic circuit is not operating, and generates another predetermined bias voltage based on a first constant current when it is operating.

[0075] In the comparator circuit 1B configured as described above, when the block enable signal BLKEN is at a low level, switch SW11 is turned on, allowing current corresponding to IREFS to flow through MOS transistors Q8 and Q9.

[0076] As described above, according to Embodiment 6, the desired comparison operation can be started immediately after switching to the increased current consumption in accordance with the block enable signal BLKEN, which is an operating mode switching control signal.

[0077] (Other variations) In the embodiments and modifications described above, a comparator circuit, a source follower circuit, a voltage generation circuit, and a time constant circuit are configured, but the present invention is not limited to these, and various other electronic circuits such as differential amplifier circuits may be configured. [Industrial applicability]

[0078] As described in detail above, according to the bias voltage generation circuit or electronic circuit of the present invention, the gate voltage of the bias transistor is kept constant even when the current amount of the current source is reduced in order to reduce current consumption in accordance with the operating mode switching control signal, so that the desired operation can be started immediately after the operating mode switching control signal is switched. [Explanation of Symbols]

[0079] 1,1A,1B Comparator Circuit 3. Source Follower Circuit 4. Voltage generation circuit 5. Time Constant Circuits 11 Comparator section 12, 12A~12H Bias voltage generation section 100, 100A, 100B comparator circuit 101, 101A, 101B Comparator section 102,102B Bias voltage generation section C1 Capacitor CI1~CI32 Constant current source D1, D2 diodes INV1~INV11 Inverter Q1-Q17, Q9a, Q9b MOS transistors R1~R2 resistance SW1~SW14 Switches T1~T12 terminals

Claims

1. A first constant current source that supplies a first constant current, A second constant current source that supplies a second constant current smaller than the first constant current, A bias voltage generation circuit comprising at least one first MOS transistor and a bias voltage generation unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, wherein the bias voltage generation circuit is for an electronic circuit to which current is supplied by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor, The bias voltage generation circuit, based on the operating mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generation unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is in operation, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents, or the first constant current. The bias voltage generation circuit is configured.

2. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected to each other. The bias voltage generation circuit according to claim 1.

3. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected. The bias voltage generation circuit according to claim 1.

4. The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different thresholds. The bias voltage generation circuit according to claim 1.

5. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The control terminal of the third MOS transistor is connected to the connection point between the second constant current source and the resistor. The bias voltage generation circuit according to claim 1.

6. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.

7. The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.

8. The at least one first MOS transistor is configured by connecting a third MOS transistor connected to the second constant current source and a second diode in series. The third MOS transistor is diode-connected. The bias voltage generation circuit according to claim 1.

9. A first constant current source that supplies a first constant current, A second constant current source that supplies a second constant current smaller than the first constant current, An electronic circuit having a bias voltage generating circuit comprising at least one first MOS transistor and a bias voltage generating unit that generates a predetermined bias voltage based on the second constant current or the first and second constant currents, The bias voltage generation circuit is supplied with current by a current mirror circuit composed of the first MOS transistor and at least one second MOS transistor. The bias voltage generation circuit, based on the operating mode switching control signal, (1) When the electronic circuit is not in operation, the bias voltage generation unit generates a predetermined bias voltage based on the second constant current, (2) When the electronic circuit is in operation, the bias voltage generating unit generates a predetermined bias voltage based on the first and second constant currents, or the first constant current. The electronic circuit that makes up the circuit.

10. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the control terminals of the two MOS transistors are connected to each other. The electronic circuit according to claim 9.

11. The at least one first MOS transistor includes two MOS transistors connected in series with each other, and the two MOS transistors are each diode-connected. The electronic circuit according to claim 9.

12. The at least one first MOS transistor includes two MOS transistors connected in parallel to each other and having different thresholds. The electronic circuit according to claim 9.

13. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The control terminal of the third MOS transistor is connected to the connection point between the second constant current source and the resistor. The electronic circuit according to claim 9.

14. The at least one first MOS transistor includes a third MOS transistor connected in series with a first resistor connected to the second constant current source. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.

15. The at least one first MOS transistor includes a third MOS transistor connected in series with a first diode connected to the second constant current source. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.

16. The at least one first MOS transistor is configured by connecting a third MOS transistor connected to the second constant current source and a second diode in series. The third MOS transistor is diode-connected. The electronic circuit according to claim 9.

17. The aforementioned electronic circuit is a comparator circuit, a source follower circuit, a voltage generation circuit, a time constant circuit, or a differential amplifier circuit. The electronic circuit according to any one of claims 9 to 16.

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