Semiconductor integrated circuit, semiconductor memory device, and memory system

Abstract

Embodiments provide a semiconductor integrated circuit, a semiconductor memory device, and a storage system capable of improving the measurement resolution of a pulse signal while suppressing the area and the consumed current. A semiconductor integrated circuit of one embodiment has an array circuit (52) of delay elements in which a plurality of delay elements each having a delay amount (Tw) are connected in series, a delay line group (530) having flip-flops (53β) of outputs of the delay elements corresponding to a plurality of inputs, a delay element group (540) that generates a plurality of output clock signals having a delay difference of a second delay amount smaller than the delay amount (Tw) from an input clock signal, and a delay section (55) capable of setting a third delay amount smaller than the second delay amount, the delay element group (540) and the delay section (55) being connected in series between an output terminal of an input signal (CLK_DET) and an input terminal of the delay line group (530).

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-147559 (filed on September 10, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] The implementation methods involve semiconductor integrated circuits, semiconductor memory devices, and memory systems. Background Technology

[0003] A semiconductor integrated circuit that measures the period of a pulse signal such as a clock, a semiconductor memory device equipped with the semiconductor integrated circuit, and a memory system are known. Summary of the Invention

[0004] The embodiments provide semiconductor integrated circuits, semiconductor memory devices, and memory systems that can improve the measurement resolution of pulse signals while suppressing area and current consumption.

[0005] The semiconductor integrated circuit of this embodiment includes: a delay element group having a plurality of first delay elements having a first delay amount connected in series; a trigger group having a plurality of triggers, the triggers being input to the output of the corresponding first delay element among the plurality of first delay elements of the delay element group; a second delay circuit generating a plurality of second clock signals having a delay difference of a second delay amount smaller than the first delay amount from a first clock signal; and a variable delay circuit capable of setting a third delay amount smaller than the second delay amount. The second delay circuit and the variable delay circuit are connected in series between the output terminal of the third clock and the input terminal of the trigger group. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example configuration of a storage system according to an embodiment of the present invention.

[0007] Figure 2 This is a block diagram illustrating an example configuration of the semiconductor memory device according to this embodiment.

[0008] Figure 3 This is a block diagram illustrating an example of a DCC circuit configuration.

[0009] Figure 4 This is a block diagram illustrating an example of the configuration of a DCD circuit.

[0010] Figure 5 This is a circuit diagram representing an example of a delay element array circuit.

[0011] Figure 6 This is a circuit diagram illustrating an example of the edge detection circuit of the first embodiment.

[0012] Figure 7 This is a block diagram illustrating an example of the configuration of a DCA circuit.

[0013] Figure 8 This is a circuit diagram illustrating an example of a delay block circuit.

[0014] Figure 9 This is a circuit diagram illustrating an example of the configuration of a FINE delay circuit.

[0015] Figure 10 This is a circuit diagram illustrating an example of the configuration of a waveform generation circuit.

[0016] Figure 11 This is a timing diagram illustrating the operation of a DCC circuit.

[0017] Figure 12 This is a timing diagram illustrating the operation of a DCD circuit.

[0018] Figure 13A This is a timing diagram illustrating the operation of a DCD circuit.

[0019] Figure 13B This is a timing diagram illustrating the operation of a DCD circuit.

[0020] Figure 14 This is a flowchart explaining the operation of the operational circuit.

[0021] Figure 15 This is a waveform diagram representing an example of the input and output clocks of a DCC circuit.

[0022] Figure 16 This is an example of the value of the code signal DN_F.

[0023] Figure 17 This is an example of the value of the code signal DN_C.

[0024] Figure 18 This is an example of the value of the code signal DN_FD.

[0025] Figure 19 This is an example of the value of the code signal DN_CD.

[0026] Figure 20 This is a timing diagram that illustrates the operation of the FINE delay circuit.

[0027] Figure 21 A graph showing the relationship between the delay times of the code signals DN_FD and DN_FDB and the clock signals FOUTB_EVN and FOUTB_ODD.

[0028] Figure 22This is a diagram illustrating an example of a state during the operation of a COURSE delay circuit.

[0029] Figure 23 Yes Figure 22 The timing diagram illustrates the operation of the COURSE delay circuit under the given conditions.

[0030] Figure 24 This is a diagram illustrating an example of a state during the operation of a COURSE delay circuit.

[0031] Figure 25 Yes Figure 24 The timing diagram illustrates the operation of the COURSE delay circuit under the given conditions.

[0032] Figure 26 This is a timing diagram illustrating an example of the operation in a waveform generation circuit.

[0033] Figure 27 This is a circuit diagram illustrating an example of an edge detection circuit for comparison.

[0034] Figure 28 This is a circuit diagram illustrating an example of the edge detection circuit of the second embodiment.

[0035] Figure 29 This is a circuit diagram representing an example of a PI circuit.

[0036] Figure 30A This is a circuit diagram illustrating an example of the operation of a PI circuit.

[0037] Figure 30B This is a circuit diagram illustrating an example of the operation of a PI circuit.

[0038] Figure 31 This is a timing diagram illustrating an example of the operation of a PI circuit.

[0039] Figure 32 This is a block diagram illustrating an example of the configuration of the DLL circuit in the third embodiment.

[0040] Figure 33 This is a timing diagram illustrating an example of the operation of the DCD circuit in the third embodiment.

[0041] Figure 34 This is a timing diagram illustrating the phase adjustment of the clock signal in DDR communication.

[0042] Label Explanation

[0043] 1. Memory controller; 2. Semiconductor memory device; 2A. Interface chip; 2B. Non-volatile memory; 11. RAM; 12. Processor; 13. Host interface; 14. ECC circuit; 15. Memory interface circuit; 16. Internal bus; 20. DCC circuit; 21. Memory cell array; 22. Input / output circuit; 24. Logic control circuit; 26. Register; 27. Sequencer; 28. Voltage generation circuit; 30. Line decoder; 31. Sensing amplifier unit; 32. Input / output pad group; 34. Logic control pad group; 35. Power input terminal group; 41. DCD circuit; 42. Operation circuit. Path; 43 DCA circuit; 44 Waveform generation circuit; 51 Signal generation circuit; 52 Delay element array circuit; 53 Edge detection circuit; 55, 57 Delay section; 551, 552 Delay element; 56 Selector; 58a, 58b Inverter circuit group; 61, 62 Delay block circuit; 530 Delay line group; 531-534 Delay line; 540 Delay element group; 571-574 PI circuit; 611e, 611oFINE delay circuit; 612 COURSE delay circuit; 613 Code control circuit; 615 Delay element; 616 Code conversion circuit Detailed Implementation

[0044] The embodiments will now be described with reference to the accompanying drawings.

[0045] (First Embodiment)

[0046] (1. Composition)

[0047] (1-1. The composition of the storage system)

[0048] Figure 1 This is a block diagram illustrating an example configuration of a storage system according to an embodiment of the present invention. The storage system of this embodiment includes a storage controller 1 and a semiconductor storage device 2. The storage system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a portable terminal.

[0049] Semiconductor memory device 2 includes a memory that stores data in a non-volatile manner (hereinafter referred to as non-volatile memory). Non-volatile memory is, for example, a NAND flash memory (NAND flash memory) having memory cells capable of storing 3 bits per cell, i.e., a 3-bit / Cell (TLC: Triple Level Cell) NAND memory. Furthermore, non-volatile memory 2 can also be a 1-bit / Cell, 2-bit / Cell, or 4-bit / Cell NAND memory.

[0050] The storage controller 1 controls the writing of data to the semiconductor storage device 2 according to write requests from the host. Additionally, the storage controller 1 controls the reading of data from the semiconductor storage device 2 according to read requests from the host. The storage controller 1 and semiconductor storage device 2 transmit and receive the following signals: chip enable signal / CE, ready busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, write protect signal / WP, data signals DQ<7:0>, data strobe signal DQS, and / DQS. Furthermore, in this specification, the symbol " / " before the signal name indicates the inversion logic of the signal name not accompanied by the symbol " / ".

[0051] For example, the semiconductor memory device 2 and the memory controller 1 are formed as semiconductor chips (hereinafter also referred to as "chips").

[0052] The chip enable signal / CE is used to enable the semiconductor memory device 2. The ready busy signal / RB is used to indicate whether the semiconductor memory device 2 is in a ready state (accepting commands from external sources) or a busy state (not accepting commands from external sources). The command latch enable signal CLE indicates that the signal DQ<7:0> represents a command. The address latch enable signal ALE indicates that the signal DQ<7:0> represents an address. The write enable signal / WE is used to fetch the received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 whenever a command, address, or data is received. During the period when the write enable signal / WE is at a "L" level, the semiconductor memory device 2 is indicated to fetch the signal DQ<7:0>.

[0053] The read enable signals RE and / RE are used by the memory controller 1 to read data from the semiconductor memory device 2. For example, they are used to control the timing of the operation of the semiconductor memory device 2 when the output signal DQ<7:0> is displayed. The write protect signal / WP is used to instruct the semiconductor memory device 2 to prohibit data writing and erasing. The signal DQ<7:0> represents the data transmitted and received between the semiconductor memory device 2 and the memory controller 1, including commands, addresses, and data. The data strobe signals DQS and / DQS are used to control the timing of the input and output of the signal DQ<7:0>.

[0054] The storage controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface circuit 13, an ECC (Error Check and Correct) circuit 14, and a memory interface circuit 15. The RAM 11, processor 12, host interface circuit 13, ECC circuit 14, and memory interface circuit 15 are interconnected via an internal bus 16.

[0055] The host interface circuit 13 outputs requests received from the host, user data (write data), etc., to the internal bus 16. Additionally, the host interface circuit 13 sends user data read from the semiconductor storage device 2, responses from the processor 12, etc., to the host.

[0056] The memory interface circuit 15 controls the processes of writing user data to the semiconductor storage device 2 and reading user data from the semiconductor storage device 2 based on the instructions of the processor 12.

[0057] The processor 12 provides overall control over the memory controller 1. The processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When the processor 12 receives a request from the host via the host interface circuit 13, it instructs the memory interface circuit 15 to write user data and parity checks to the semiconductor memory device 2 according to the request. Additionally, the processor 12 instructs the memory interface circuit 15 to read user data and parity checks from the semiconductor memory device 2 according to a request from the host.

[0058] The processor 12 determines the storage area (memory area) on the semiconductor storage device 2 for user data stored in RAM 11. User data is stored in RAM 11 via the internal bus 16. The processor 12 determines the memory area for page-unit data (page data) written as a unit. In this specification, one page of user data stored in the semiconductor storage device 2 is defined as unit data. Generally, unit data is encoded by the ECC circuit 14 and stored as codewords in the semiconductor storage device 2. In this embodiment, encoding is not necessary. The storage controller 1 may also store unit data in the semiconductor storage device 2 without encoding, but... Figure 1 The following example illustrates the encoding configuration. When storage controller 1 does not perform encoding, page data is identical to unit data. Alternatively, a codeword can be generated based on a single unit of data, or based on segmented data obtained by dividing the unit of data. Furthermore, a codeword can also be generated using multiple units of data.

[0059] Processor 12 determines the memory region of semiconductor storage device 2 as the destination for writing data per unit. Physical addresses are allocated to the memory regions of semiconductor storage device 2. Processor 12 manages the memory regions as the destination for writing data per unit using these physical addresses. Processor 12 executes the determined memory region (physical address) and instructs memory interface circuit 15 to write user data to semiconductor storage device 2. Processor 12 manages the correspondence between the logical address (host-managed logical address) of user data and its physical address. Upon receiving a read request including a logical address from the host, processor 12 determines the physical address corresponding to the logical address, specifies the physical address, and instructs memory interface circuit 15 to read the user data.

[0060] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Additionally, ECC circuit 14 decodes the codewords read from semiconductor memory device 2.

[0061] RAM 11 temporarily stores the user data received from the host until it is stored in the semiconductor storage device 2, and temporarily stores the data until it is sent to the host after being read from the semiconductor storage device 2. RAM 11 is a general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0062] exist Figure 1 The diagram shows an example where the memory controller 1 includes both an ECC circuit 14 and a memory interface circuit 15, but it could also be configured such that the ECC circuit 14 is integrated into the memory interface circuit 15. Alternatively, the ECC circuit 14 could be integrated into the semiconductor memory device 2.

[0063] Upon receiving a write request from the host, the storage system operates as follows: Processor 12 temporarily stores the data to be written in RAM 11. Processor 12 reads the data stored in RAM 11 and inputs it to ECC circuit 14. ECC circuit 14 encodes the input data and inputs the codeword to memory interface circuit 15. Memory interface circuit 15 writes the input codeword to semiconductor storage device 2.

[0064] Upon receiving a read request from the host, the storage system operates as follows: The memory interface circuit 15 inputs the codeword read from the semiconductor storage device 2 into the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 sends the data stored in the RAM 11 to the host via the host interface circuit 13.

[0065] (1-2. Structure of a semiconductor memory device)

[0066] Figure 2 This is a block diagram illustrating an example configuration of the semiconductor memory device according to this embodiment. The semiconductor memory device 2 of this embodiment includes an interface chip 2A and a non-volatile memory 2B.

[0067] Interface chip 2A has the function of interfacing between storage controller 1 and non-volatile memory 2B with the chip enable signal / CE, ready busy signal / RB, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals RE and / RE, write protect signal / WP, data signals DQ<7:0>, data strobe signals DQS and / DQS. For example, interface chip 2A transmits the command CMD and address ADD from signals DQ<7:0> together with the data strobe signals DQS and / DQS to non-volatile memory 2B. Furthermore, for example, it transmits and receives write data and read data from signals DQ<7:0> together with the data strobe signals DQS and / DQS between the storage controller 1 and non-volatile memory 2B.

[0068] Furthermore, interface chip 2A has a frequency boosting function to increase the I / O speed of non-volatile memory 2B. For example, interface chip 2A has the function of transmitting signals input from memory controller 1 to non-volatile memory 2B in DDR (Double Data Rate) mode. When using such a high-speed transmission mode, it is necessary to adjust the duty cycle of the signals (specifically the read enable signals RE, / RE and the data strobe signals DQS, / DQS) that indicate the timing of the transmit / receive signals DQ<7:0> between memory controller 1 and non-volatile memory 2B with high precision. In order to adjust the duty cycle of read enable signals RE, / RE and data strobe signals DQS, / DQS, interface chip 2A has a DCC (Duty Cycle Correction) circuit 20.

[0069] More specifically, the interface chip 2A includes: a DCC circuit 20a, which adjusts the duty cycle of the read enable signals RE and / RE output from the memory controller 1 and input to the non-volatile memory 2B; and a DCC circuit 20b, which adjusts the duty cycle of the data strobe signals DQS and / DQS output from the memory controller 1 and input to the non-volatile memory 2B. Furthermore, the DCC circuit 20b can also adjust the duty cycle of the data strobe signals DQS and / DQS output from the non-volatile memory 2 and input to the memory controller 1. The detailed structure of the DCC circuit 20 will be described in detail later.

[0070] The non-volatile memory 2B includes a memory cell array 21, an input / output circuit 22, a logic control circuit 24, a register 26, a sequencer 27, a voltage generation circuit 28, a row decoder 30, a sense amplifier unit 31, an input / output pad group 32, a logic control pad group 34, and a power input terminal group 35.

[0071] The memory cell array 21 includes a plurality of non-volatile memory cell transistors (not shown) associated with word lines and bit lines.

[0072] The input / output circuit 22 transmits and receives signals DQ<7:0> and data strobe signals DQS and / DQS with the memory controller 1 via the interface chip 2A. The input / output circuit 22 transmits the commands and addresses contained in the signals DQ<7:0> to the register 26. Additionally, the input / output circuit 22 transmits and receives write and read data with the sense amplifier unit 31.

[0073] The logic control circuit 24 receives the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE, / RE, and write protect signal / WP from the memory controller 1 via the interface chip 2A. Additionally, the logic control circuit 24 transmits the ready busy signal / RB to the memory controller 1 via the interface chip 2A, notifying the external system of the status of the non-volatile memory 2B.

[0074] The voltage generation circuit 28 generates the voltage required for actions such as writing, reading, and erasing data based on the instructions from the sequencer 27.

[0075] The line decoder 30 receives the block address and line address from the address in the register 26, selects the corresponding block based on the block address, and selects the corresponding word line based on the line address.

[0076] During data readout, the sensing amplifier unit 31 senses the readout data read from the memory cell transistor to the bit line and transmits the sensed readout data to the input / output circuit 22. During data writeout, the sensing amplifier unit 31 transmits the write data written via the bit line to the memory cell transistor. The sensing amplifier unit 31 has multiple sensing amplifiers SA.

[0077] The input / output pad group 32 transmits and receives various signals, including data, with the interface chip 2A. Therefore, it has multiple terminals (pads) corresponding to the signals DQ<7:0> and the data strobe signals DQS and / DQS.

[0078] The logic control pad group 34 transmits and receives various signals with the interface chip 2A. Therefore, it has multiple terminals (pads) corresponding to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE / RE, and write protection signal / WP.

[0079] The power input terminal group 35 supplies various operating power supplies to the non-volatile memory 2B from the outside, and therefore has multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc is a circuit power supply voltage that is generally supplied externally as an operating power supply, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used as a power supply for driving an input / output system used to transmit and receive signals between the memory controller 1 and the non-volatile memory 2B.

[0080] The power supply voltage Vpp is a power supply voltage that is higher than the power supply voltage Vcc, such as a 12V input voltage. For example, if the non-volatile memory 2B is used in an environment where a high voltage cannot be supplied, it is possible not to supply voltage Vpp. Even without supplying power supply voltage Vpp, the non-volatile memory 2B can still perform various operations as long as it is supplied with power supply voltage Vcc. That is, power supply voltage Vcc is the power supply that is normally supplied to the non-volatile memory 2B, while power supply voltage Vpp is, for example, an additional or arbitrary power supply supplied depending on the usage environment.

[0081] The sensing unit 24 detects the data read from the NAND memory cell array 23 during data reading. In addition, the sensing unit 24 temporarily saves the write data input from the memory controller 1 via the interface chip 2 during data writing and transmits it to the NAND memory cell array 23.

[0082] (1-3. Structure of DCC circuit)

[0083] Figure 3 This is a block diagram illustrating an example of the configuration of a DCC circuit. The DCC circuit 20 in this embodiment includes a DCD (Duty Cycle Detector) circuit 41, an arithmetic circuit 42, a DCA (Duty Cycle Adjuster) circuit 43, and a waveform generation circuit 44.

[0084] DCD circuit 41 is a circuit that observes the duty factor error of the clock signal to be corrected and converts it into the number of stages of delay elements. DCD circuit 41 detects (measures) the pulse width (high-level period) of the input clock DCD_IN and the pulse width of the input clock / DCD_IN, and outputs a signal DCD_CODE representing the pulse width of the input clock DCD_IN and the pulse width of the input clock / DCD_IN. The signal DCD_CODE has multiple bits (e.g., 32 bits).

[0085] The arithmetic circuit 42 is a circuit that calculates the delay setting value of the clock signal that is the object of duty factor correction based on the output signal from the DCD circuit 41. The arithmetic circuit 42 receives the signal DCD_CODE output from the DCD circuit 41, compares the pulse width of the input clock DCD_IN with the pulse width of the input clock / DCD_IN, and generates the signal DCA_CODE based on the comparison result.

[0086] DCA circuit 43 generates, based on signal DCA_CODE, the delayed clock CDLY_T of input clock IN and the delayed clock CDLY_B of input clock / IN, which are the objects of duty factor correction.

[0087] The waveform generation circuit 44 receives the delayed clocks CDLY_T and CDLY_B output from the DCA circuit 43 and generates output clocks OUT and / OUT. That is, the output clocks OUT and / OUT are output signals after adjusting the working cycles of the input clocks IN and / IN. In addition, the output clocks OUT and / OUT generated in the waveform generation circuit 44 are output from the DCC circuit 20 and input to the DCD circuit 41.

[0088] (1-3-1. Structure of DCD Circuit)

[0089] Figure 4 This is a block diagram illustrating an example of the configuration of a DCD circuit. The DCD circuit 41 in this embodiment is configured including a signal generation circuit 51, a delay element array circuit 52, and an edge detection circuit 53. Furthermore, the semiconductor integrated circuit in this embodiment is configured including at least the delay element array circuit 52 and the edge detection circuit 53.

[0090] The input clocks DCD_IN and / DCD_IN are input to the signal generation circuit 51. The signal generation circuit 51 generates signals CLK_DLY and CLK_DET based on the input clocks DCD_IN and / DCD_IN.

[0091] The duration of the high level of signal CLK_DLY and the duration of the high level of signal CLK_DET are set to the same length as one cycle of the input clock DCD_IN (= the same length as one cycle of the input clock / DCD_IN).

[0092] The rising edge of the even-numbered cycle of the signal CLK_DLY is set to the same timing as the rising edge of the input clock DCD_IN. Conversely, the rising edge of the odd-numbered cycle of the signal CLK_DLY is set to the same timing as the rising edge of the input clock DCD_IN.

[0093] The rising phase of the even-numbered cycle of the CLK_DET signal is set to the same timing as the falling phase of the input clock DCD_IN. Conversely, the rising phase of the odd-numbered cycle of the CLK_DET signal is set to the same timing as the falling phase of the input clock DCD_IN.

[0094] That is, the signals CLK_DLY and CLK_DET are generated in such a way that the period from the rise of the even-numbered cycle of CLK_DLY to the rise of CLK_DET is the same length as the high level period of the input clock DCD_IN, and the period from the rise of the odd-numbered cycle of CLK_DLY to the rise of CLK_DET is the same length as the high level period of the input clock / DCD_IN. Therefore, by continuously measuring the period from the rise of the input clock DCD_IN to the rise of CLK_DET, the high level period of the input clock DCD_IN and the high level period of the input clock / DCD_IN can be observed alternately.

[0095] Furthermore, in signals CLK_DLY and CLK_DET, the period from the rise of the nth cycle to the rise of the (n+1)th cycle is set to be a sufficient period from the high level of the measurement input clock DCD_IN or / DCD_IN to the generation of DCD_CODE.

[0096] The delay element array circuit 52, which serves as a group of delay elements, uses the signal CLK_DLY input from the signal generation circuit 51 to generate an n-bit signal Dn (D1 to Dn) (n is a natural number greater than 2). The group of signals Dn is latched by the edge detection circuit 53, which will be described later, and represents the pulse width or period of the input clock.

[0097] Figure 5This is a circuit diagram illustrating an example of a delay element array circuit. The delay element array circuit 52, which is a group of delay elements, includes n delay elements 521_1 to 521_n (first delay elements). In each case where α (α is a natural number greater than or equal to 1 and less than n) is greater than or equal to n, the delay element 521_α receives the signal D(α-1) and outputs the signal Dα. Furthermore, the signal D0 is set to be equal to the signal CLK_DLY. Hereinafter, the inclusion of "α" indicates all cases where α is greater than or equal to 1 and less than n. That is, the inclusion of "α" indicates the cases where α is 1, α is 2, ..., and α is n. The signal Dα is the signal after the signal D(α-1) has been delayed by a certain time. The delay element 521_α receives the signal CLK_DLY, maintains the logic level of signal Dα when the signal CLK_DLY transitions to a high level, and continuously outputs the signal Dα with the same logic level as the maintained signal Dα.

[0098] The delay amount in each element of delay elements 521_1 to 521_n may be uneven due to unintentional non-uniformity in the performance of delay elements 521_1 to 521_n, but is desirable to be time Tw. In the following description, the delay amounts of delay elements 521_1 to 521_n are assumed to be equal in time Tw. Delay element 521_α includes, for example, three NAND gates. The first NAND gate receives the signal D(α-1) at one input. Additionally, the first NAND gate is grounded at the other input, i.e., connected to a node at ground potential Vss. The second NAND gate is grounded at both inputs, i.e., connected to a node at ground potential Vss. The second NAND gate receives the outputs of the first NAND gate and the second NAND gate, outputting the signal Dα. Delay element 521_α causes a delay of time Tw.

[0099] The edge detection circuit 53 receives signals D1 to Dn from the delay element array circuit 52 and signal CLK_DET from the signal generation circuit 51, and outputs signal DCD_CODE. Figure 6This is a circuit diagram illustrating an example of the edge detection circuit of the first embodiment. The edge detection circuit 53 has a delay line group 530 as a group of flip-flops. The delay line group 530 includes m (m is a natural number of 2 or more) delay lines 531 to 53m. Each delay line 53β (β is a natural number of 1 or more and less than m) includes n D-type flip-flops (hereinafter referred to as flip-flops only) 53β_1 to 53β_n. Hereinafter, the description including "β" is set to represent all cases where β is 1 or more and less than m. That is, the description including "β" is set to represent the case where β is 1, the case where β is 2, ..., the case where β is m. The edge detection circuit 53 also has a delay element group 540 as a second delay circuit. The delay element group 540 also includes m delay elements 54β (third delay elements). The delay of each delay element 54β is set to be time {1.0+(β-1) / m}×Tw.

[0100] Furthermore, the edge detection circuit 53 has a delay section 55 that generates an input signal CLK_DETa to be input to the delay element 54β. The delay section 55, as a variable delay circuit, includes s delay elements 55δ (δ being a natural number greater than or equal to 1 and less than s) and a selector 56. Hereinafter, the inclusion of "δ" indicates the case where δ is 1, δ is 2, ..., δ is s. The delay amount of each delay element 55δ is set to time {1.0 + (δ - 1) / (m × s)} × Tw.

[0101] Each delay element 55δ (the second delay element) receives the signal CLK_DET output from the signal generation circuit 51, delays it by a set time, and outputs it to the selector 56. The delay element 55δ includes, for example, three NAND gates. The first NAND gate receives the signal CLK_DET at one input. Additionally, the first NAND gate is grounded at the other input, i.e., connected to the node at ground potential Vss. The second NAND gate is grounded at both inputs, i.e., connected to the node at ground potential Vss. The third NAND gate receives the outputs of the first and second NAND gates and outputs the signal CLK_DETaδ. The delay element 55δ generates a delay of {1.0 + (δ - 1) / (m × s)} × Tw. The selector 56 selects one of the signals CLK_DETaδ input from the s delay elements 55δ for output.

[0102] Each delay element 54β receives the signal CLK_DETa output from the selector 56, delays it by a set time, and outputs it to the delay line 53β. The delay element 54β includes, for example, three NAND gates. The first NAND gate receives the signal CLK_DETa at one input. Additionally, the first NAND gate is grounded at another input, i.e., connected to a node at ground potential Vss. The second NAND gate is grounded at both inputs, i.e., connected to a node at ground potential Vss. The third NAND gate receives the outputs of the first NAND gate and the second NAND gate, and outputs the signal CLK_DETm. The delay element 54β thus generates a time delay of {1.0 + (β - 1) / m} × Tw.

[0103] Figure 6 Taking the edge detection circuit 53 with s=2 and m=4 as an example, the delay element 551 has a delay of time {1.0 + (1 - 1) / (4 × 2)}Tw = 1.0Tw. Delay element 551 receives the signal CLK_DET, delays it by 1.0Tw, and outputs the signal CLK_DETa1. The delay element 552 has a delay of time {1.0 + (2 - 1) / (4 × 2)}Tw = 1.125Tw. Delay element 552 receives the signal CLK_DET, delays it by 1.125Tw, and outputs the signal CLK_DETa2. The selector receives both signals CLK_DETa1 and CLK_DETa2, and outputs one of them (signal CLK_DETa).

[0104] The delay element 541 has a delay of time {1.0 + (1 - 1) / 4}Tw = 1.0Tw. Delay element 541 receives the signal CLK_DETa, delays it by 1.0Tw, and outputs the signal CLK_DET1. The delay element 542 has a delay of time {1.0 + (2 - 1) / 4}Tw = 1.25Tw. Delay element 542 receives the signal CLK_DETa, delays it by 1.25Tw, and outputs the signal CLK_DET2. The delay element 543 has a delay of time {1.0 + (3 - 1) / 4}Tw = 1.5Tw. Delay element 543 receives the signal CLK_DETa, delays it by 1.5Tw, and outputs the signal CLK_DET3. The delay element 544 has a delay of time {1.0 + (4 - 1) / 4}Tw = 1.75Tw. The delay element 544 receives the signal CLK_DETa, delays it by 1.75Tw, and outputs the signal CLK_DET4.

[0105] When selector 56 selects signal CLK_DETa1, signal CLK_DETa is a signal that delays signal CLK_DET by 1.0Tw. In this case, signal CLK_DET1 becomes a signal that delays signal CLK_DET by (1.0 + 1.0)Tw = 2.0Tw. Furthermore, signal CLK_DET2 becomes a signal that delays signal CLK_DET by (1.0 + 1.25)Tw = 2.25Tw. Further, signal CLK_DET3 becomes a signal that delays signal CLK_DET by (1.0 + 1.5)Tw = 2.5Tw. Additionally, signal CLK_DET4 becomes a signal that delays signal CLK_DET by (1.0 + 1.75)Tw = 2.75Tw.

[0106] When selector 56 selects signal CLK_DETa2, signal CLK_DETa is a signal that delays signal CLK_DET by 1.125Tw. In this case, signal CLK_DET1 becomes a signal that delays signal CLK_DET by (1.125 + 1.0)Tw = 2.125Tw. Furthermore, signal CLK_DET2 becomes a signal that delays signal CLK_DET by (1.125 + 1.25)Tw = 2.375Tw. Further, signal CLK_DET3 becomes a signal that delays signal CLK_DET by (1.125 + 1.5)Tw = 2.625Tw. Additionally, signal CLK_DET4 becomes a signal that delays signal CLK_DET by (1.125 + 1.75)Tw = 2.875Tw.

[0107] The flip-flop 53β_α of delay line 53β receives the signal Dα output from delay element 521_α of delay element array circuit 52 in the data input, receives the signal CLK_DETβ in the clock input, and outputs the signal Fβα. For example, the flip-flop 531_1 of delay line 531 receives the signal D1 in the data input, receives the signal CLK_DET1 in the clock input, and outputs the signal F11. The flip-flop 534_n of delay line 534 receives the signal Dn in the data input, receives the signal CLK_DET4 in the clock input, and outputs the signal F4n. That is, the edge detection circuit 53 generates an m×n bit signal Fmn, which is output as the signal DCD_CODE.

[0108] (1-3-2. Structure of an operational circuit)

[0109] The arithmetic circuit 42 is a circuit that calculates the delay setting value of the clock signal that is the object of duty factor correction based on the output signal from the DCD circuit 41. The arithmetic circuit 42 receives the signal DCD_CODE output from the DCD circuit 41 and compares the pulse width (high level period) of the input clock DCD_IN with the pulse width (high level period) of the input clock / DCD_IN. Based on the comparison result, it generates the signal DCA_CODE. The code signal DCA_CODE is composed of code signals DN_F and DN_C for correcting the rising timing of the input clock IN, and code signals UP_F and UP_C for correcting the rising timing of the input clock / IN. For example, the code signal DCA_CODE is output in this order: (m×s+1) bit code signal DN_F, 1 bit code signal DN_C, (m×s+1) bit code signal UP_F, and 1 bit code signal UP_C. Furthermore, the generation of the signal DCA_CODE in the arithmetic circuit 42 will be described in detail later.

[0110] (1-3-3. Structure of DCA Circuit)

[0111] Figure 7 This is a block diagram illustrating an example of the configuration of a DCA circuit. The DCA circuit 43 in this embodiment is composed of two delay block circuits 61 and 62. Delay block circuit 61 is a delay circuit that corrects the timing of the rise of the input clock IN. Delay block circuit 61 receives the input clock IN and the code signals DN_F and DN_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_T. Delay block circuit 62 is a delay circuit that corrects the timing of the rise of the input clock IN. Delay block circuit 62 receives the input clock IN and the code signals UP_F and UP_C that constitute the signal DCA_CODE, and generates a delayed clock CDLY_B.

[0112] First, the delay block circuit 61 will be explained. Figure 8 This is a circuit diagram illustrating an example of the configuration of a delay block circuit. The delay block circuit 61 includes two sets of FINE delay circuits 611e and 611o, a COARSE delay circuit 612, and a code control circuit 613.

[0113] FINE delay circuits 611e and 611o are delay circuits that correct the timing of the rise of the input clock IN with a resolution of less than 1.0Tw time (specifically, (1.0 / (m×s))Tw time units). FINE delay circuits 611e and 611o are delay circuits with four input terminals CKIN_A, CKIN_B, FI_T, and FI_B, and one output terminal CKOUT.

[0114] Figure 9 This is a circuit diagram illustrating an example of the configuration of a FINE delay circuit. The FINE delay circuit 611e includes two sets of inverter circuits 614a and 614b. Inverter circuit 614a consists of (m×s) P-side switches 71_1, 71_2, ..., 71_(m×s) and one N-side switch 72. Figure 9 This represents the case where s = 2 and m = 4. The P-side switch 71_ε is configured by connecting two PMOS transistors in series. Hereinafter, the inclusion of "ε" indicates all cases where ε is 1 or more and (m × s) or less. That is, the inclusion of "ε" indicates cases where ε is 1, ε is 2, ..., and ε is (m × s). (m × s) P-side switches 71_ε are connected in parallel between the output terminal CKOUT_T of the inverter circuit 614a and the power supply potential Vcc. The N-side switch 72 is configured by connecting two NMOS transistors in series. The N-side switch 72 is connected between the output terminal CKOUT_T of the inverter circuit 614a and the ground potential Vss.

[0115] The gate of the PMOS transistor (hereinafter referred to as the first PMOS transistor) of the two PMOS transistors constituting the P-side switch 71_ε, whose drain is connected to the output terminal CKOUT_T of the inverter circuit 614a, is connected to the input terminal CKIN_A. The gate of the other PMOS transistor (hereinafter referred to as the second PMOS transistor) constituting the P-side switch 71_ε is input with one bit of data set from the (m×s) bit code signal input from the input terminal FI_T. That is, starting from the P-side switch 71 closest to the output terminal CKOUT_T, the first bit of data, the second bit of data, ..., the (m×s)th bit of data from the code signal input from the input terminal FI_T are sequentially input.

[0116] exist Figure 9In the configuration shown, the first bit of the code signal input from the input terminal FI_T is input to P-side switch 71_8, the second bit of the signal is input to P-side switch 71_7, the third bit of the signal is input to P-side switch 71_6, and the fourth bit of the signal is input to P-side switch 71_5. Furthermore, the fifth bit of the signal is input to P-side switch 71_4, the sixth bit of the signal is input to P-side switch 71_3, the seventh bit of the signal is input to P-side switch 71_2, and the eighth bit of the signal is input to P-side switch 71_1. Specifically, when the 8-bit code signal input from the input terminal FI_T is "11100000", "1 (=H)" is input to the gates of P-side switches 71_1, 71_2, and 71_3, and "0 (=L)" is input to the gates of the second PMOS transistors of P-side switches 71_4, 71_5, 71_6, 71_7, and 71_8.

[0117] The gate of the NMOS transistor (hereinafter referred to as the first NMOS transistor), which forms the N-side switch 72 and whose drain is connected to the output terminal CKOUT_T of the inverter circuit 614a, is connected to the input terminal CKIN_A. The gate of the other NMOS transistor (hereinafter referred to as the second NMOS transistor), which forms the N-side switch 72, is connected to the input terminal CKIN_B.

[0118] The inverter circuit 614b consists of (m×s) P-side switches 73_1, 73_2, ..., 73_(m×s) and one N-side switch 74. The P-side switches 73_ε are configured by connecting two PMOS transistors in series. The (m×s) P-side switches 73_ε are connected in parallel between the output terminal CKOUT_B of the inverter circuit 614a and the power supply potential Vcc. Furthermore, similar to the P-side switches 71_ε, the PMOS transistor whose drain is connected to the output terminal CKOUT_B of the inverter circuit 614b is designated as the first PMOS transistor, and the other PMOS transistor is designated as the second PMOS transistor. The N-side switch 74 is configured by connecting two NMOS transistors in series. The N-side switch 74 is connected between the output terminal CKOUT_B of the inverter circuit 614b and the ground potential Vss. Furthermore, similar to the N-side switch 72, the NMOS transistor on the side whose drain is connected to the output terminal CKOUT_B of the inverter circuit 614b among the two NMOS transistors constituting the N-side switch 74 is referred to as the first NMOS transistor, and the other NMOS transistor is referred to as the second NMOS transistor.

[0119] The gate of the first PMOS transistor, one of the two PMOS transistors constituting the P-side switch 73_ε, is connected to the input terminal CKIN_B. The set 1-bit data from the (m×s) bit code signal input from the input terminal FI_B is input to the gate of the second PMOS transistor in the P-side switch 73_ε. That is, starting from the P-side switch 73 closest to the output terminal CKOUT_B, the 1st bit, the 2nd bit, ..., the (m×s)th bit of the code signal input from the input terminal FI_B are sequentially input.

[0120] exist Figure 9 In the configuration shown, the first bit of the code signal input from input terminal FI_B is input to P-side switch 73_8, the second bit of the signal is input to P-side switch 73_7, the third bit of the signal is input to P-side switch 73_6, and the fourth bit of the signal is input to P-side switch 73_5. Further, the fifth bit of the signal is input to P-side switch 73_4, the sixth bit of the signal is input to P-side switch 73_3, the seventh bit of the signal is input to P-side switch 73_2, and the eighth bit of the signal is input to P-side switch 73_1. Specifically, when the 8-bit code signal input from the input terminal FI_B is "00011111", "1 (=H)" is input to the gate of the P-side switches 73_4, 73_5, 73_6, 73_7, and 73_8, and "0 (=L)" is input to the gate of the second PMOS transistor of the P-side switches 73_1, 73_2, and 73_3.

[0121] The gate of the first NMOS transistor, which constitutes the N-side switch 74, is connected to the input terminal CKIN_B. The gate of the second NMOS transistor, which constitutes the N-side switch 72, is connected to the input terminal CKIN_A.

[0122] The output terminals CKOUT_T and CKOUT_B of inverter circuit 614a and inverter circuit 614b are electrically connected. That is, the output terminals CKOUT_T and CKOUT_B are short-circuited. The signal PI_CLKB, obtained by combining the output signals from inverter circuit 614a and inverter circuit 614b, is logically inverted by the inverter and output from the output terminal CKOUT.

[0123] The FINE delay circuit 611e receives the signal (clock INB) obtained by logically inverting the input clock IN at input terminal CKIN_A, and the signal (clock INB1) obtained by delaying the input clock INB by 1.0Tw at input terminal CKIN_B. Additionally, the FINE delay circuit 611e receives the code signal DN_FD at input terminal FI_T. Further, the code signal DN_FDB is input to input terminal FI_B; this code signal DN_FDB is the logically inverted version of the code signal DN_FD.

[0124] The FINE delay circuit 611e receives clock INB, clock INB1, code signal DN_FD, and code signal DN_FDB, and generates clock FOUTB_EVN. Clock FOUTB_EVN is a signal obtained by delaying the rise of the input clock IN within the range of 0 to 1.0TW and then logically inverting it based on the code signals DN_FD and DN_FDB.

[0125] The FINE delay circuit 611o receives the logically inverted signal (clock INB) of the input clock IN at input terminal CKIN_B, and the signal (clock INB1) of the input clock INB delayed by 1.0Tw at input terminal CKIN_A. Additionally, the FINE delay circuit 611e receives the code signal DN_FD at input terminal FI_T. Further, it receives the code signal DN_FDB at input terminal FI_B, which is the logically inverted signal of code signal DN_FD.

[0126] The FINE delay circuit 611o receives clock INB, clock INB1, code signal DN_FD, and code signal DN_FDB, and generates clock FOUTB_ODD. Clock FOUTB_ODD is a signal obtained by delaying the rise of the input clock IN within the range of 0 to 1.0TW and then logically inverting it based on the code signals DN_FD and DN_FDB. Furthermore, the generation of clocks FOUTB_EVN and FOUTB_ODD in the FINE delay circuits 611e and 611o will be described in detail later.

[0127] The code control circuit 613 receives code signals DN_C and DN_F, and generates a code signal DN_FD that is input to the input terminals FI_T of the FINE delay circuit 611e and FI_T of the FINE delay circuit 611o. The code signal DN_FD is a (m×s) bit thermometer code. The generation of the code signal DN_FD in the code control circuit 613 will be described in detail later.

[0128] The COARSE delay circuit 612 is a delay circuit that corrects the timing of the rise of the input clock IN in 1.0Tw time units. The COARSE delay circuit 612 accepts the signals FOUTE_EVN, FOUTE_ODD, and code signal DN_C. Based on the code signal DN_C, for either the clock FOUTE_EVN or the clock FOUTE_ODD, the selected signal is delayed by an amount based on the code signal DN_C, and the delayed signal is output as the output clock CDLYOUT.

[0129] The COARSE delay circuit 612 includes 1+1 delay elements 615_0 to 615_l. The delay elements 615_0 to 615_l are arranged in the order of delay elements 615_0, 615_1, 615_2, ..., 615_l, starting from the side closest to the output terminal. In each case where γ (γ is a natural number greater than or equal to 1 and less than 1) is 0 to 1, the delay element 615_γ includes, for example, 3 NAND gates. Hereinafter, the inclusion of "γ" indicates all cases where γ is greater than or equal to 0 and less than 1. That is, the inclusion of "γ" indicates cases where γ is 0, γ is 1, ..., and γ is 1. The delay element 615_γ generates a delay of 1.0 Tw.

[0130] Additionally, the COARSE delay circuit 612 includes a code conversion circuit 616. The code conversion circuit 616 receives the code signal DN_C contained in the signal DCA_CODE output from the arithmetic circuit 42 and decodes it, converting the binary code into thermometer code to generate the code signal DN_CD. The code signal DN_CD is a 1-bit code signal. For example, when the binary code "100" representing the decimal number "4" is received as the code signal DN_C, the code conversion circuit 616 generates "0...01111" as the code signal DN_CD. That is, the code conversion circuit 616 generates the code signal DN_CD by setting the first bit to the bits represented by the code signal DN_C to "1" and setting the other bits to "0". The code conversion circuit 616 outputs the generated code signal DN_CD to the delay element 615.

[0131] The first NAND gate of delay element 615_γ accepts either clock FOUTB_EVN or clock FOUTB_ODD at one input. Specifically, it accepts clock FOUTB_EVN when γ is even and clock FOUTB_ODD when γ is odd. Additionally, the first NAND gate accepts the code signal DN_CDγ (the value of the γth bit of the code signal DN_CD) at the other input. However, in delay element 615_0, the first NAND gate is connected to the node of the power supply potential Vcc at the other input.

[0132] The second NAND gate of delay element 615_γ receives the signal FOUTB_(γ+1) output from delay element 615_(γ+1) at one input. Additionally, the second NAND gate is connected to the node at the power supply potential Vcc at the other input. However, the second NAND gate of delay element 615_n is grounded at both inputs, i.e., connected to the node at the ground potential Vss.

[0133] The third NAND gate of delay element 615_γ accepts the output of the first NAND gate and the output of the second NAND gate, and outputs the signal FOUTB_γ.

[0134] When the value of the code signal DN_CDγ input to the first NAND gate is "0 (=L)", the delay element 615_γ outputs "0 (=L)" as the signal FOUTB_γ. On the other hand, when the value of the code signal DN_CDγ input to the first NAND gate is "1 (=H)" and the value of the code signal DN_CD(γ+1) is "0 (=L)", the signal FOUTB_ODD or FOUTB_EVN input to the first NAND gate is delayed by time 1.0Tw and used as the signal FOUTB_γ. When the value of the code signal DN_CDγ is "1 (=H)" and the value of the code signal DN_CD(γ+1) is "1 (=H)", the signal FOUTB_(γ+1) input to the second NAND gate is delayed by time 1.0Tw and used as the signal FOUTB_γ. The signal FOUTB_0 output from delay element 615_0 is used as the output clock CDLYOUT and is output from COARSE delay circuit 612.

[0135] The output clock CDLYOUT is logically inverted by an inverter and is output from the delay block circuit 61 as the delay clock CDLY_T.

[0136] Delay block circuit 62 has the same structure as delay block circuit 61 described above. However, the input and output signals are different from those of delay block circuit 61. That is, in delay block circuit 61, the input clock IN and the code signals DN_F and DN_C constituting signal DCA_CODE are received to generate the delayed clock CDLY_T. In contrast, in delay block circuit 62, the input clock IN and the code signals UP_F and UP_C constituting signal DCA_CODE are received to generate the delayed clock CDLY_B.

[0137] Waveform generation circuit 44 generates an output clock OUT that remains high throughout the entire period from the rising edge of the delayed clock CDLY_T to the rising edge of the delayed clock CDLY_B. Waveform generation circuit 44 is configured, for example, as a two-input one-output multiplexer (a logic AND multiplexer of the inverted signals of the output delayed clock CDLY_T and delayed clock CDLY_B) that takes the two signals CDLY_T and CDLY_B as inputs and the output clock OUT as the output.

[0138] (1-3-4. Structure of waveform generation circuit)

[0139] Figure 10 This is a block diagram illustrating an example of the waveform generation circuit configuration. The waveform generation circuit 44 in this embodiment consists of an inverter INV1, an inverter group INVG1 and INVG2 consisting of multiple inverters connected in series, PMOS transistors P1 and P2, NMOS transistors N1 and N2, and a latch circuit LAT1.

[0140] PMOS transistors P2 and P1, and NMOS transistors N1 and N2 are connected in series. The source of PMOS transistor P2 is connected to the power supply potential Vcc, and the source of NMOS transistor N2 is connected to ground potential Vss. The delayed clock CDLY_B is logically inverted via inverter IN1 and input to the gate of PMOS transistor P1 and inverter group INVG1. The output of inverter group INVG1 is input to the gate of PMOS transistor P2. The delayed clock CDLY_T is input to the gate electrode of NMOS transistor N2 and inverter group INVG2. The output of inverter group INVG2 is input to the gate of NMOS transistor N2.

[0141] The connection point between the drain of PMOS transistor P1 and the drain of NMOS transistor N2 is connected to the input of latch circuit LAT1. Latch circuit LAT2 has a structure that provides positive feedback for the two inverters.

[0142] When the delayed clock CDLY_B input to the waveform generation circuit 44 switches from low to high, PMOS transistors P1 and P2 become ON, and the power supply potential Vcc is input to the latch circuit LAT1. On the other hand, when the delayed clock CDLY_T input to the waveform generation circuit 44 switches from low to high, NMOS transistors N1 and N2 become ON, and the ground potential Vss is input to the latch circuit LAT1. Therefore, the signal output from the latch circuit LAT1 (=output clock OUT) becomes a clock signal that switches from low to high on the rising edge of the delayed clock CDLY_T and from high to low on the rising edge of the delayed clock CDLY_B.

[0143] The waveform generation circuit 44 outputs the signal from the latch circuit LAT1 as the output clock OUT. Additionally, it generates and outputs a signal that logically inverts the output clock OUT (output clock / OUT). Furthermore, the output clocks OUT and / OUT are output from the DCC circuit 20 and input to the DCD circuit 41. The output clock OUT is input to the DCD circuit 41 as the input clock DCD_IN, and the output clock / OUT is input to the DCD circuit 41 as the input clock / DCD_IN.

[0144] (2. Action)

[0145] (2-1. Operation of DCC circuit)

[0146] Figure 11 This is a timing diagram illustrating an example of the operation of a DCC circuit. For example... Figure 11 As shown, the input clock IN input to the DCC circuit 20 has a certain duty cycle. For example, the duty cycle is not 50%, and the high-level period (period CINH) is shorter than the low-level period (period CINL). The input clock IN has a period CIN, during which CINH is high and CINL is low. That is, the input clock IN has the relationship CIN = CINH + CINL and CINH < CINL.

[0147] For the input clock IN input to the DCC circuit 20, the duty cycle is detected in the DCD circuit 41 during the first few cycles (e.g., 12 cycles). The specific detection method is described below. First, in the first cycle of the input clock DCD_IN, the selector 56 of the edge detection circuit 53 is set to select the signal CLK_DETa1 output from the delay element 551 as the signal CLK_DETa. The DCD circuit 41 measures the pulse width (the high-level period) of the first cycle of the input clock DCD_IN, generates the signal DCD_CODE, and outputs it to the arithmetic circuit 42. In addition, the DCD circuit 41 measures the pulse width of the fourth cycle of the input clock DCD_IN, generates the signal DCD_CODE, and outputs it to the arithmetic circuit 42.

[0148] During the 7th cycle of the input clock / DCD_IN, the selector 56 of the edge detection circuit 53 is switched to select the signal CLK_DETa2 output from the delay element 551 and output it as the signal CLK_DETa. The DCD circuit 41 measures the pulse width (the high-level period) of the 8th cycle of the input clock DCD_IN, generates the signal DCD_CODE, and outputs it to the arithmetic circuit 42. Additionally, the DCD circuit 41 measures the pulse width of the 11th cycle of the input clock / DCD_IN, generates the signal DCD_CODE, and outputs it to the arithmetic circuit 42.

[0149] That is, in selector 56, whenever the signal to be output CLK_DETa is switched, the high-level periods of the input clock DCD_IN and the high-level periods of the input clock / DCD_IN are measured, and a signal DCD_CODE is generated and output to the arithmetic circuit 42. When the measurement of the high-level periods of the input clock DCD_IN and the high-level periods of the input clock / DCD_IN are grouped as 1, the measurement of group s is performed.

[0150] Furthermore, in the period prior to the correction of the duty cycle of the input clocks IN and / IN, the duty cycle of the output clocks OUT and / OUT is equal to that of the input clocks IN and / IN. Therefore, the duty cycle of the input clocks DCD_IN and / DCD_IN is equal to that of the input clocks IN and / IN. That is, in each group, the signal DCD_CODE output from the DCC circuit 20 is a value generated based on the detection result of the pulse width of the first cycle of clock IN during the period from the fall of the first cycle of input clock IN (= the rise of the first cycle of input clock / IN) to the fall of the fourth cycle of input clock / IN (= the rise of the fifth cycle of input clock IN), and is a value generated based on the detection result of the pulse width of the fourth cycle of input clock / IN during the period from the fall of the fourth cycle of input clock / IN (= the rise of the fifth cycle of input clock IN) to the fall of the eighth cycle of input clock IN (= the rise of the eighth cycle of input clock / IN).

[0151] That is, the signal DCD_CODE output from DCC circuit 20 is output in the following order: "the period of the high level of the input clock DCD_IN measured by signal CLK_DETa1 (= the period of the high level of the input clock DCD_IN in the first group)", "the period of the high level of the input clock / DCD_IN measured by signal CLK_DETa1 (= the period of the high level of the input clock / DCD_IN in the first group)", "the period of the high level of the input clock DCD_IN measured by signal CLK_DETa2 (= the period of the high level of the input clock DCD_IN in the second group)", and "the period of the high level of the input clock / DCD_IN measured by signal CLK_DETa2 (= the period of the high level of the input clock / DCD_IN in the second group)".

[0152] The arithmetic circuit 42 calculates the pulse width of the input clock IN using both the pulse width detection results measured by the signal CLK_DETa1 and the pulse width detection results measured by the signal CLK_DETa2, received via the signal DCD_CODE. Similarly, when receiving the pulse width detection results of the input clock / IN using both the signal CLK_DETa1 and the signal CLK_DETa2, it calculates the pulse width of the input clock / IN. Then, it compares the calculated pulse width of the input clock IN with the calculated pulse width of the input clock / IN. Based on the comparison result, it generates the signal DCA_CODE. For example, as described above, when receiving the pulse width detection result of the input clock / IN measured from the rise of the 12th cycle of the input clock IN using the signal CLK_DETa2, it generates and outputs the signal DCA_CODE during the 12th cycle of the input clock IN.

[0153] Furthermore, in the DCA circuit 43 and the waveform generation circuit 44, the duty cycle of the input clock IN and / IN is corrected based on the signal DCA_CODE and output as the output clock OUT and / OUT from the DCC circuit 20. Additionally, for the periods preceding the generation signal DCA_CODE (cycles 1 to 12), the input clock IN and / IN are not corrected and become the output clock OUT and / OUT. The duty cycle of the input clock IN is corrected based on the signal DCA_CODE received during the 12th cycle of the input clock IN. And, starting from the 13th cycle of the output clock OUT, the corrected clock signal is output from the DCC circuit 20.

[0154] The output clocks OUT and / OUT are fed back to the DCD circuit 41 as input clocks DCD_IN and / DCD_IN, respectively. The DCD circuit 41 measures the pulse widths of the input clocks DCD_IN and / DCD_IN at appropriate intervals and updates the signal DCD_CODE. When the signal DCD_CODE is updated, the arithmetic circuit 42 updates the signal DCA_CODE. Furthermore, in the DCA circuit 43 and the waveform generation circuit 44, based on the updated signal DCA_CODE, the duty cycle of the input clocks IN and / IN is corrected and output as the output clocks OUT and / OUT from the DCC circuit 20.

[0155] Thus, according to this embodiment, after correcting the duty cycle of the input clocks IN and / IN, the output clocks OUT and / OUT are also fed back to the DCD circuit 41 for continued monitoring, continuously updating the signal DCD_CODE. Therefore, even if the duty cycle of the input clocks IN and / IN changes due to temperature and voltage variations during the operation of the semiconductor memory device 2, these variations can be tracked, and the duty cycle can be appropriately corrected. Furthermore, when detecting the signal DCD_CODE, if temporary errors occur due to noise or other interference, continuous detection of the signal DCD_CODE increases the number of detections, averaging the errors and reducing their impact. Furthermore, errors caused by the characteristic difference between the delay element 521_α in the DCD circuit 41 and the delay element 615_γ in the DCA circuit 43 can be eliminated.

[0156] (2-1-1. Operation of DCD Circuit)

[0157] Figure 12 , Figure 13A as well as Figure 13B This is a timing diagram illustrating an example of the operation of a DCD circuit. Input clocks DCD_IN and / DCD_IN are input to DCD circuit 41. Signal generation circuit 51 detects the rise of the initial cycle of the input clock DCD_IN in each group, and maintains the signal CLK_DLY at a high level for the entire period from that rise until the rise of the next cycle of the input clock DCD_IN. Additionally, signal generation circuit 51 detects the rise of the fourth cycle of the input clock / DCD_IN in each group (= the fall of the fourth cycle of the input clock DCD_IN), and maintains the signal CLK_DLY at a high level for the entire period from that rise until the rise of the next cycle of the input clock / CLK_DLY.

[0158] That is, in the first group, the signal generation circuit 51 detects the rise of the first cycle of the input clock DCD_IN, and maintains the signal CLK_DLY at a high level for the entire period from that rise to the rise of the next cycle of the input clock DCD_IN. Additionally, the signal generation circuit 51 detects the rise of the fourth cycle of the input clock DCD_IN (= the fall of the fourth cycle of the input clock DCD_IN), and maintains the signal CLK_DLY at a high level for the entire period from that rise to the rise of the next cycle of the input clock DCD_IN.

[0159] Furthermore, the signal generation circuit 51 detects the rise of the 8th cycle and maintains the signal CLK_DLY at a high level for the entire period from this rise until the rise of the next cycle of the input clock DCD_IN. This 8th cycle is the initial cycle after the selector 56 of the edge detection circuit 53 is switched, the signal output as signal CLK_DETa is changed, i.e., after switching to the second group. In addition, the signal generation circuit 51 detects the rise of the 4th cycle of the input clock / DCD_IN of the second group, i.e., the 11th cycle of the input clock / DCD_IN (= the fall of the 11th cycle of the input clock / DCD_IN), and maintains the signal CLK_DLY at a high level for the entire period from this rise until the rise of the next cycle of the input clock / CLK_DLY.

[0160] The signal generation circuit 51 detects the fall of the initial cycle of the input clock DCD_IN in each group and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next cycle of the input clock DCD_IN. Additionally, the signal generation circuit 51 detects the fall of the fourth cycle of the input clock DCD_IN (which equals the rise of the fifth cycle of the input clock DCD_IN) and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next cycle of the input clock DCD_IN.

[0161] That is, in the first group, the signal generation circuit 51 detects the fall of the initial cycle of the input clock DCD_IN and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next cycle of the input clock DCD_IN. Additionally, the signal generation circuit 51 detects the fall of the fourth cycle of the input clock DCD_IN (which equals the rise of the fifth cycle of the input clock DCD_IN) and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next cycle of the input clock DCD_IN.

[0162] Furthermore, the signal generation circuit 51 detects the fall of the initial period (=8th period) of the input clock DCD_IN, and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next period of the input clock DCD_IN. The initial period of the input clock DCD_IN is the initial period after the selector 56 of the edge detection circuit 53 is switched and the signal output as signal CLK_DETa is changed, i.e., after switching to the second group. In addition, the signal generation circuit 51 detects the fall of the 4th period and the 11th period of the input clock / DCD_IN (= the rise of the 12th period of the input clock / DCD_IN) of the second group, and maintains the signal CLK_DET at a high level for the entire period from that fall until the fall of the next period of the input clock / DCD_IN.

[0163] Furthermore, the signal generation circuit 51 repeatedly performs the aforementioned operations on signals CLK_DLY and CLK_DET whenever a predetermined timing is reached or whenever the duty cycle is requested to be adjusted. Specifically, the high-level duration of signal CLK_DLY in odd-numbered periods is the same length as one cycle of the input clock CLK_IN, and the high-level duration of signal CLK_DLY in even-numbered periods is the same length as one cycle of the input clock CLK_IN. Similarly, the high-level duration of signal CLK_DET in odd-numbered periods is the same length as one cycle of the input clock CLK_IN, and the high-level duration of signal CLK_DET in even-numbered periods is the same length as one cycle of the input clock CLK_IN.

[0164] In the signals CLK_DLY and CLK_DET generated as described above, the period from the rise of the odd-numbered period of signal CLK_DLY to the rise of signal CLK_DET is the same as the pulse width of the input clock DCD_IN. Furthermore, the period from the rise of the even-numbered period of signal CLK_DLY to the rise of signal CLK_DET is the same as the pulse width of the input clock DCD_IN.

[0165] The delay element array circuit 52 takes the signal CLK_DLY received from the signal generation circuit 51 as signal D0, and generates and outputs signal Dα in each delay element 521_α based on signal D0. That is, the signal D(α-1) output by the delay element 521_α is delayed by time Tw and used as signal Dα. In this way, signals D1 to Dn delayed by time Tw are obtained in ascending order of the value of α. Figure 13A This shows a portion of the signals from signal D1 to signal D(k+1) (where k is a natural number less than or equal to n-1).

[0166] The clock signal CLK_DETa is delayed by time {1.0+(β-1) / m}×Tw and then provided as the clock signal DLK_DETβ to the delay line 53β of the edge detection circuit 53.

[0167] For example, Figure 6 As shown, when the edge detection circuit 53 has four delay lines (m=4), the clock signal CLK_DETa delayed by 1.0Tw (clock signal CLK_DET1) is provided to delay line 531. Similarly, the clock signal CLK_DET delayed by 1.25Tw (clock signal CLK_DET2) is provided to delay line 532, and the clock signal CLK_DET delayed by 1.5Tw (clock signal CLK_DET3) is provided to delay line 533. Furthermore, the clock signal CLK_DET delayed by 1.75Tw (clock signal CLK_DET4) is provided to delay line 534.

[0168] The flip-flop 53β_α set on the delay line 53β responds to the transition of the clock signal CLK_DETβ to a high level, latches the signal Dα, and outputs the latched signal Dα as the signal Fβα.

[0169] For example, Figure 13A As shown, in delay line 531, when the clock signal CLK_DET1 switches to a high level, when signals D1 to D(k-1) are high and signals Dk to Dn are low, high-level signals are output from flip-flops 531_1 to 531_(k-1) as signals F11 to F1(k-1), and low-level signals are output from flip-flops 531_k to 531_n as signals F1k to F1n.

[0170] In delay line 532, when the clock signal CLK_DET2 switches to a high level, and signals D1 to D(k-1) are high and signals Dk to Dn are low, high-level signals are output from flip-flops 532_1 to 532_(k-1) as signals F21 to F2(k-1). Low-level signals are output from flip-flops 532_k to 532_n as signals F2k to F2n.

[0171] In delay line 533, when the clock signal CLK_DET3 switches to a high level, and signals D1 to D(k-1) are high and signals Dk to Dn are low, although not illustrated, high-level signals are output from flip-flops 533_1 to 533_(k-1) as signals F31 to F3(k-1). Low-level signals are output from flip-flops 533_k to 533_n as signals F3k to F3n.

[0172] In delay line 534, when the clock signal CLK_DET4 switches to a high level, and signals D1 to Dk are high and signals D(k+1) to Dn are low, high-level signals are output from flip-flops 5343_1 to 534_k as signals F41 to F4k. Although not illustrated, low-level signals are output from flip-flops 534_(k+1) to 534_n as signals F4(k+1) to F4n.

[0173] The signal Fβα output from delay line 53β is output as signal DCD_CODE.

[0174] Here, as Figure 13B As shown, relative to the clock signal CLK_DETa (clock signal CLK_DETa1) in group 1, the clock signal CLK_DETa (=clock signal CLK_DETa2) in group 2 is delayed by {1 / (m×s)}×Tw. Therefore, compared to the clock signal DLK_DETβ in group 1, the clock signal DLK_DETβ in group 2 is delayed by {1 / (m×s)}×Tw. For example, when n=8 and k=5, in the clock signal CLK_DETa (clock signal CLK_DETa1) in group 1, according to... Figure 13A The timing diagram shown yields signal Fβα as follows: Signals F1n to F11 are "00001111", F2n to F21 are "00001111", F3n to F31 are "00001111", and F4n to F41 are "00011111", resulting in an 8-bit × 4 = 32-bit signal. Edge detection circuit 53 sequentially arranges signals Fβα to generate a 32-bit (n × m bits) signal DCD_CODE and outputs it. For example, in the above case, signal DCD_CODE becomes "00001111000011110000111100011111".

[0175] In the second group of clock signals CLK_DETa (clock signal CLK_DETa2), according to Figure 13AThe timing diagram shown yields signal Fβα as follows: Signals F1n to F11 are "00001111", F2n to F21 are "00001111", F3n to F31 are "00011111", and F4n to F41 are "00011111", totaling 8 bits × 4 = 32 bits. In other words, relative to the first group, the clock signal CLK_DETa of the second group is delayed by {1 / (m×s)}×Tw, therefore, signal F34 changes from "0" to "1". The edge detection circuit 53 sequentially arranges signals Fβα to generate a 32-bit (n×m bits) signal DCD_CODE and outputs it. For example, in the above case, the signal DCD_CODE becomes "0000111100001111000111110001111100011111".

[0176] (2-1-2. Operation of the operational circuit)

[0177] During the initial cycle of the clock signal CLK_DET for each group, the arithmetic circuit 42 counts the number of high-level bits (iδ) of the signal DCD_CODE received from the DCD circuit 41. For example, in the case of the signal DCD_CODE in the first group being "00001111000011110000111100011111", the number of high-level bits is counted as "i1 = 17". Furthermore, in the case of the signal DCD_CODE in the second group being "00001111000011110001111100011111", the number of high-level bits is counted as "i2 = 18".

[0178] In the next cycle of the clock signal CLK_DET for each group, the arithmetic circuit 42 counts the number of high-level bits (jδ) of the signal DCD_CODE received from the DCD circuit 41. For example, when the signal DCD_CODE for the first group is "01111111111111111111111111111111", the number of high-level bits is counted as "j1 = 31". Similarly, when the signal DCD_CODE for the second group is "01111111111111111111111111111111", the number of high-level bits is counted as "j2 = 31".

[0179] The number i represents the pulse width (the period of the high level) of the input clock IN. Specifically, the product of the average value of the numbers ik in each group divided by m and the delay time Tw represents the width of the high level of the input clock IN. For example, when s=2, m=4, i1=17, i2=18, the width of the high level of the input clock IN becomes {(17+18) / 2} / 4×Tw=4.375Tw.

[0180] The number j represents the pulse width (the period of the high level) of the input clock / IN. Specifically, the product of the average value of the numbers jk in each group divided by m and the delay time Tw represents the width of the high level of the input clock / IN. The width of the high level of the input clock / IN is equal to the width of the low level of the input clock IN. Therefore, the number j represents the width of the low level of the input clock IN. For example, when s = 2, m = 4, j1 = 31, j2 = 31, the width of the low level of the input clock IN becomes {(31+31) / 2} / 4 × Tw = 7.75Tw.

[0181] Figure 14 This is a flowchart explaining the operation of the arithmetic circuit. First, the arithmetic circuit 42 initializes various variables used in the calculation of numbers i and j (S1). Specifically, the variable k, representing the number of cycles of the clock signal CLK_DET, is set to 1; the variable isum, which stores the cumulative value of number ik, is set to 0; and the variable jsum, which stores the cumulative value of number jk, is set to 0. In the first cycle of the clock signal CLK_DET, the arithmetic circuit 42 counts the number of bits at the high level of the signal DCD_CODE and obtains the number ik as the counting result (S2). After adding the number ik obtained in S2 to the cumulative value isum of number ik and incrementing the number of cycles k by 1 (S3), in the next cycle of the clock signal CLK_DET, the arithmetic circuit 42 counts the number of bits at the high level of the signal DCD_CODE and obtains the number jk as the counting result (S4). After adding the accumulated value jsum of the logarithm jk to the number jk obtained in S4 and incrementing the number of cycles k by 1 (S5), the arithmetic circuit 42 determines whether the predetermined number of groups has been obtained, regarding the pulse width of the input clock DCD_IN and the pulse width of the input clock / DCD_IN (S6). Specifically, it determines whether the number obtained by dividing the number of cycles k of the next predetermined clock signal CLK_DET by 2 is greater than the set number of groups (s).

[0182] If the number obtained by dividing the number of cycles k by 2 is less than or equal to the set number of groups (s) (S6: No), return to S2 and repeat step S5 from S2 to obtain the data of the two cycles in the next group (the number of bits i and j of the high level of the signal DCD_CODE).

[0183] On the other hand, if the number obtained by dividing the number of cycles k by 2 is larger than the set number of groups (s) (S6: Yes), the cumulative value isum of number i and the cumulative value jsum of number j are divided by the number of groups s respectively to calculate the number i as the average of number ik and the number j as the average of number jk (S7). The arithmetic circuit 42 uses the number i and number j obtained in S7 to calculate Δ = (i - j) / 2 (S8). Figure 15 This is a waveform diagram illustrating an example of the input and output clocks of a DCC circuit. Together with the above, as... Figure 15 As shown, number i represents the period of the high level of the input clock IN, and number j represents the period of the low level of the input clock IN. Therefore, the difference i-j is the difference between the periods of the high and low levels of the input clock IN. Furthermore, Δ is equal to the difference between the period TOUTH of the high (or low) level in the target's output clock OUT and the period CINH (or CINL) of the high level of the input clock IN. The target's output clock OUT has the same period CIN as the input clock IN and has a 50% duty cycle. In addition, Figure 15 This represents examples where i and j are different.

[0184] return Figure 14 The arithmetic circuit 42 determines whether Δ is 0 (S9). If Δ is 0 (S9: Yes), the arithmetic circuit 42 does not change the signal DCA_CODE and directly outputs (S10). The signal DCA_CODE consists of code signals DN_F, DN_C and code signals UP_F, UP_C. Code signals DN_F and DN_C are signals that set the falling delay of the input clock IN, and code signals UP_F and UP_C are signals that set the rising delay of the input clock IN. Code signal DN_F is a (m×s+1) bit signal, indicating the delay for the falling of the input clock IN with a resolution of less than 1.0Tw time (specifically, {1.0 / (m×s)}Tw time units). Code signal DN_C is a 1-bit signal, indicating the delay for the falling of the input clock IN with a time unit of 1.0Tw. The code signal UP_F is an (m×s+1)-bit signal that indicates a delay of less than 1.0Tw time (specifically, {1.0 / (m×s)}Tw time units) for the rise of the input clock IN. The code signal UP_C is a 1-bit signal that indicates a delay of 1.0Tw time units for the rise of the input clock IN. The code signals DN_F, DN_C, UP_F, and UP_C are all set to "0" by default (this sets the delay of the minimum delay time Tf in the FINE delay circuit 611).

[0185] In this embodiment, the delay of the signal DCD_IN (=output clock OUT) is repeatedly adjusted in the DCC circuit 20. In the delay adjustment after the second time, when some delay has been set for the signal DCA_CODE (when more than one bit in any of the code signals DN_F, DN_C and UP_F, UP_C is set to "1"), in S10, the arithmetic circuit 42 does not restore the signal DCA_CODE to the default state, and outputs the unchanged signal DCA_CODE.

[0186] On the other hand, if Δ is not 0 (S9: No), the arithmetic circuit 42 determines whether Δ is positive (Δ > 0) (S11). If Δ is positive (S11: Yes), the arithmetic circuit 42 changes the code signals DN_F and DN_C to values ​​based on Δ (S12). Specifically, the code signals DN_F and DN_C are set to values ​​indicating the period during which the rise delay of the input clock IN is represented by Δ. Furthermore, the arithmetic circuit 42 outputs a signal DCA_CODE that includes the changed code signals DN_F and DN_C and the unchanged code signals UP_F and UP_C.

[0187] If Δ is not positive (Δ < 0) (S11: No), the arithmetic circuit 42 modifies the code signals UP_F and UP_C to values ​​based on Δ (S13). Specifically, the code signals UP_F and UP_C are set to values ​​indicating the period during which the fall delay of the input clock IN is represented by Δ. Furthermore, the arithmetic circuit 42 outputs a signal DCA_CODE that includes the modified code signals UP_F and UP_C and the unchanged code signals DN_F and DN_C.

[0188] In addition, although Figure 14 It is not recorded in the document, but in the second and subsequent delay adjustments, when some delay has been set for UP_F and UP_C under the condition that Δ>0, it is also possible to adjust the values ​​of UP_F and UP_C by reducing them.

[0189] Figure 16 An example representing the value of the code signal DN_F. Additionally... Figure 17 An example representing the value of the code signal DN_C. Furthermore... Figure 16 Examples involving the cases where s=2 and m=4, Figure 17 Examples involving the case where l is 7. For example... Figure 16As shown, the code signal DN_F consists of 4 bits. The value of each bit of the code signal DN_F indicates the time (u×Tw) obtained by multiplying the value u of the code signal in decimal by the rise delay of the input clock IN of the FINE delay circuit 611, which is input to the delay block circuit 61, by the unit delay time in the FINE delay circuit 611 (0.125Tw when s=2 and m=4).

[0190] For example, the value of code signal DN_F "0000" indicates that the rise of the input clock IN, which is input to the FINE delay circuit 611 of the delay block circuit 61, is delayed by 0.000Tw relative to the minimum delay time Tf. Similarly, the value of code signal DN_F "0001" indicates that the rise of the input clock IN, which is input to the FINE delay circuit 611 of the delay block circuit 61, is delayed by 0.125Tw relative to the minimum delay time Tf. Likewise, the values ​​of code signal DN_F "0010", "0011", and "0100" respectively indicate that the rise of the input clock IN, which is input to the FINE delay circuit 611 of the delay block circuit 61, is delayed by 0.250Tw, 0.375Tw, and 0.500Tw relative to the minimum delay time Tf. Furthermore, the values ​​of the code signal DN_F, "0101", "0110", "0111", and "1000", respectively indicate that the rise of the input clock IN of the FINE delay circuit 611, which is input to the delay block circuit 61, is delayed by 0.625Tw, 0.750Tw, 0.875Tw, and 1.000Tw relative to the minimum delay time Tf.

[0191] like Figure 17 As shown, the code signal DN_C consists of 3 bits. The value of each bit of the code signal DN_C indicates the time (v×Tw) obtained by multiplying the value v of the code signal (represented in decimal) of the rise delay of the clock signals (clock FOUTB_EVN and clock FOUTB_ODD) input to the CORSE delay circuit 612 by the unit delay time (=1Tw) in the COURSE delay circuit 612.

[0192] For example, the value "000" of the code signal DN_C indicates a rise delay of 0Tw for the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61. Similarly, the value "001" of the code signal DN_C indicates a rise delay of 1Tw for the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61. Likewise, the values ​​"010", "011", "100", "101", "110", and "111" of the code signal DN_C respectively indicate rise delays of 2Tw, 3Tw, 4Tw, 5Tw, 6Tw, and 7Tw for the clock signal input to the COURSE delay circuit 612 of the delay block circuit 61.

[0193] The code signal UP_F consists of bits of the same number of bits as the code signal DN_F. The value of each bit of the code signal UP_F indicates the time (u×Tw) obtained by multiplying the value u, which is the decimal representation of the rise delay of the input clock / IN input to the FINE delay circuit of the delay block circuit 62, by the unit delay time in the FINE delay circuit of the delay block circuit 62 (0.125Tw when s=2, m=4).

[0194] For example, the value of the code signal UP_F "0000" indicates that the rise of the input clock / IN, which is input to the FINE delay circuit of the delay block circuit 62, is delayed by 0.000Tw relative to the minimum delay time Tf. Similarly, the value of the code signal UP_F "0001" indicates that the rise of the input clock / IN, which is input to the FINE delay circuit of the delay block circuit 62, is delayed by 0.125Tw relative to the minimum delay time Tf. Likewise, the values ​​of the code signal UP_F "0010", "0011", and "0100" indicate that the rise of the input clock / IN, which is input to the FINE delay circuit of the delay block circuit 62, is delayed by 0.250Tw, 0.375Tw, and 0.500Tw relative to the minimum delay time Tf, respectively. Furthermore, the values ​​of the code signal UP_F, "0101", "0110", "0111", and "1000", respectively indicate that the rise of the input clock IN, which is input to the FINE delay circuit of the delay block circuit 62, is delayed by 0.625Tw, 0.750Tw, 0.875Tw, and 1.000Tw relative to the minimum delay time Tf.

[0195] The code signal UP_C consists of bits of the same number of bits as the code signal DN_C. The value of each bit in the code signal UP_C indicates the rise delay of the clock signals (clock FOUTB_EVN and clock FOUTB_ODD) input to the CORSE delay circuit. This rise delay is represented as a decimal number (v) multiplied by the unit delay time (=1Tw) in the COURSE delay circuit, resulting in a time (v×Tw). That is, the values ​​of the code signal UP_C, "000", "001", "010", "011", "100", "101", "110", and "111", respectively indicate the rise delays of 0Tw, 1Tw, 2Tw, 3Tw, 4Tw, 5Tw, 6Tw, and 7Tw for the clock signals input to the COURSE delay circuit of the delay block circuit 62.

[0196] Here, the method for setting the DCA_CODE signal based on Δ will be explained. First, the absolute value of the value obtained by multiplying Δ by s is divided by (m×s) to calculate the quotient (q) and remainder (r). Furthermore, when Δ > 0, the code signal UP_C is set based on the value q, and the code signal UP_F is set based on the value r. Conversely, when Δ < 0, the code signal DN_C is set based on the value q, and the code signal DN_F is set based on the value r. For example, when s = 2, m = 4, and Δ = 7.5, Δ×s = 15, 15 / (4×2) = 1 with a remainder of 7. Therefore, the code signal UP_C is set to the binary code "001" representing the decimal number "1", and the code signal UP_F is set to the binary code "0111" representing the decimal number "7". Additionally, for example, when m = 4 and Δ = -9, |(-9)×2| = 18, 18 / (4×2) = 2 with a remainder of 2. Therefore, the code signal DN_C is set to the binary code "010" representing the decimal number "2", and the code signal DN_F is set to the binary code "0010" representing the decimal number "2".

[0197] Furthermore, since the values ​​of i and j have a resolution of 0.125 Tw, the Δ calculated as Δ = (i - j) / 2 may have a resolution of 0.0625 Tw. In this case, by constructing a FINE delay circuit to increase the number of bits in DN_F and UP_F, a combination of 2 × (m × s) + 1 can be achieved, thereby enabling adjustment at a resolution of 0.0625 Tw.

[0198] (2-1-3. Operation of DCA Circuit)

[0199] The DCA circuit 43 receives the signal DCA_CODE output from the arithmetic circuit 42 and generates code signals DN_FD, DN_CD, and code signals UP_FD, UP_CD. Specifically, the delay block circuit 61 receives code signals DN_F, DN_C and sets code signals DN_FD, DN_CD. Additionally, the delay block circuit 62 receives code signals UP_F, UP_C and sets UP_FD, UP_CD. First, the code setting in the delay block circuit 61 will be explained.

[0200] use Figure 18 The setting of the code signal DN_FD in the code control circuit 613 is explained. Figure 18 An example representing the value of the code signal DN_FD. Furthermore... Figure 18 Examples involving the case where s = 2 and m = 4. For example... Figure 18As shown, the code signal DN_FD consists of 8 bits. Furthermore, the code signal DN_FD is represented by thermometer code. When the code signal DN_C is an even number (0, 2, 4, ...), the code signal DN_FD is set according to the value of the code signal DN_F as follows: That is, when the code signal DN_F is "0000", the code signal DN_FD is set to "00000000". Conversely, when the code signal DN_F is "0001", the code signal DN_FD is set to "00000001". Similarly, when the code signal DN_F is "0010", "0011", "0100", "0101", "0110", "0111", "1000", the code signal DN_FD is set to "00000011", "00000111", "00001111", "00011111", "00111111", "01111111", "11111111".

[0201] On the other hand, when the code signal DN_C is an odd number (1, 3, 5, ...), the code signal DN_FD is set according to the value of the code signal DN_F as follows. That is, when the code signal DN_F is "0000", the code signal DN_FD is set to "11111111". Furthermore, when the code signal DN_F is "0001", the code signal DN_FD is set to "01111111". Similarly, when the code signal DN_F is "0010", "0011", "0100", "0101", "0110", "0111", "1000", the code signal DN_FD is set to "00111111", "00011111", "00001111", "00000111", "00000011", "00000001", "00000000".

[0202] Next, use Figure 19 The setting of the code signal DN_CD in the code conversion circuit 616 of the COURSE delay circuit 612 is explained. Figure 19 An example representing the value of the code signal DN_CD. Furthermore... Figure 19 Examples involving the case where l is 7. For example... Figure 19As shown, the code signal DN_CD consists of 7 bits. The code signal DN_CD is configured to convert the decimal value represented by the binary code signal DN_C into a thermometer code. That is, when the code signal DN_C is "000", the code signal DN_CD is set to "0000000". Similarly, when the code signal DN_C is "001", the code signal DN_CD is set to "000001", "0000111", "0001111", "001111", "110", and "111", the code signal DN_CD is set to "0000011", "0000111", "0001111", "0011111", "0111111", and "1111111".

[0203] Delay block circuit 62, like delay block circuit 61, receives code signals UP_F and UP_C, and sets UP_FD and UP_CD. That is, in the above description, by replacing the code signals DC_F, DN_C, DN_FD, and DN_CD with code signals UP_F, UP_C, UP_FD, and UP_CD respectively, code signals UP_FD and UP_CD are set in delay block circuit 62.

[0204] Next, the operation of the FINE delay circuit 611 will be explained. First, the operation of the FINE delay circuit 611e will be explained. Figure 20 This is a timing diagram illustrating the operation of the FINE delay circuit. Furthermore, Figure 20 This involves the case where s=2 and m=4. In the FINE delay circuit 611e, the signal after the logical inversion of the input clock IN (clock INB) is input to the input terminal CKIN_A, and the signal after the clock INB is delayed by 1.0Tw time (clock INB1) is input to the input terminal CKIN_B. Additionally, in the FINE delay circuit 611e, the code signal DN_FD is input to the input terminal FI_T. Furthermore, the code signal DN_FDB, which is the logical inversion of the code signal DN_FD, is input to the input terminal FI_B.

[0205] The value of the first bit of the code signal DN_FD is input to input terminal FI_T1. Similarly, the value of the second bit of the code signal DN_FD is input to input terminal FI_T2. Likewise, the values ​​of the third, fourth, fifth, sixth, seventh, and eighth bits of the code signal DN_FD are input to input terminals FI_T3, FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, respectively.

[0206] The value of the first bit of the code signal DN_FDB is input to input terminal FI_B1. Similarly, the value of the second bit of the code signal DN_FDB is input to input terminal FI_B2. Likewise, the values ​​of the third, fourth, fifth, sixth, seventh, and eighth bits of the code signal DN_FDB are input to input terminals FI_B3, FI_B4, FI_B5, FI_B6, FI_B7, and FI_B8, respectively.

[0207] For example, when the value of the code signal DN_FD is "00000111", "1", "1", "0", "0", "0", "0", "0", and "0" are input to the input terminals FI_T1, FI_T2, FI_T3, FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, respectively. Conversely, when the value of the code signal DN_FD is "00000111", the value of the code signal DN_FDB is "11111000". Therefore, "0", "0", "0", "1", "1", "1", "1", and "1" are input to the input terminals FI_B1, FI_B2, FI_B3, FI_B4, FI_B5, FI_B6, FI_B7, and FI_B8, respectively.

[0208] During the period when clock INB is high, the first NMOS transistor of inverter circuit 614a and the second NMOS transistor of inverter circuit 614b are turned on. Similarly, during the period when clock INB1 is high, the second NMOS transistor of inverter circuit 614a and the first NMOS transistor of inverter circuit 614b are turned on. Therefore, during the period when both clock INB and clock INB1 are high, the N-side switch 72 of inverter circuit 614a and the N-side switch 72 of inverter circuit 614b are turned on, and thus, the signal PI_CLKB (the signal obtained by combining the output signals of inverter circuit 614a and inverter circuit 614b) becomes low.

[0209] At time t1, when the clock INB switches to a low level, the first NMOS transistor of inverter circuit 614a and the second NMOS transistor of inverter circuit 614b become off. That is, the N-side switch 72 of inverter circuit 614a and the N-side switch 74 of inverter circuit 614b switch off. In addition, the second PMOS transistors set at the four P-side switches 71_β of inverter circuit 614a become on.

[0210] Here, the first PMOS transistors, each configured on one of the eight P-side switches 71_β in the inverter circuit 614a, become on when their gates are input with a low-level signal ("0"). Therefore, in the code signal DN_FD, the same number of first PMOS transistors as the number of bits with a value of "0" become on. For example, when the value of the code signal DN_FD is "00000111", "1" is input to the input terminals FI_T1, FI_T2, and FI_T3, and therefore, the first PMOS transistors connected to these terminals become off. On the other hand, "0" is input to the input terminals FI_T4, FI_T5, FI_T6, FI_T7, and FI_T8, and therefore, the first PMOS transistors connected to these terminals become on.

[0211] Therefore, at time t1, the same number of switches among the four P-side switches 71_β as the number of bits with a value of "0" in the code signal DN_FD become active. Corresponding to the number of switches that are active, the level of the signal output at the output terminal CKOUT_T of the inverter circuit 614a rises. That is, the more P-side switches 71_β that are active, the greater the slope of the rise of the signal output at the output terminal CKOUT_T of the inverter circuit 614a.

[0212] When clock INB1 switches to a low level at time t2, which is Tw after time t1, the second NMOS transistor of inverter circuit 614a and the first NMOS transistor of inverter circuit 614b become off. Meanwhile, the second PMOS transistors of the four P-side switches 73_β in inverter circuit 614b become on.

[0213] The first MOS transistors of the eight P-side switches 73_β respectively located in the inverter circuit 614b become on when a low-level signal ("0") is input to their gates. Therefore, the same number of first PMOS transistors as the number of bits with a value of "0" in the code signal DN_FDB become on. For example, when the code signal DN_FDB is "11111000", "0" is input to input terminals FI_B1, FI_B2, and FI_B3, and therefore, the first PMOS transistors connected to these terminals become on. On the other hand, "1" is input to input terminals FI_B4 to FI_B8, and therefore, the first PMOS transistors connected to these terminals become off.

[0214] Therefore, at time t2, the same number of switches among the eight P-side switches 73_β that have the same number of "0" bits in the code signal DN_FDB become active. Corresponding to the number of switches that are active, the level of the signal input to the output terminal CKOUT_B of the inverter circuit 614b rises. That is, the more P-side switches 73_β that are active, the greater the slope of the rise of the signal output to the output terminal CKOUT_B of the inverter circuit 614b.

[0215] That is, the signal PI_CLKB obtained by combining the output signal from inverter circuit 614a and the output signal from inverter circuit 614b has a different rise time depending on the values ​​of the code signals DN_FD and DN_FDB.

[0216] Clock INB switches to high level at time t3. Here, the period from time t2 to time t3 is equal to the period CINH during which the input clock IN is high. Then, at time t4, after a time interval Tw from time t3, clock INB1 switches to high level. When both clocks INB and INB1 are high, the N-side switch 72 of inverter circuit 614a and the N-side switch 74 of inverter circuit 614b are turned on, and the signal PI_CLKB switches to low level.

[0217] also, Figure 20 The clock FOUTB_EVN shown is the signal after the signal PI_CLKB has been logically inverted by an inverter, and it is the signal output from the FINE delay circuit 611e.

[0218] Here, the relationship between the delay times of the code signals DN_FD and DN_FDB and the clock FOUTB_EVN in the FINE delay circuit 611e is summarized. First, when the value of the code signal DN_FD is "00000000" (the value of the code signal DN_FDB is "11111111"), all eight P-side switches 71 of the inverter circuit 614a are turned on, and all zero P-side switches 73 of the inverter circuit 614b are turned on. Therefore, the delay of the fall of the clock FOUTB_EVN becomes a value that reflects 100% of the delay of the clock INB in ​​the inverter circuit 614a. Therefore, the delay time of the fall of the clock FOUTB_EVN relative to the fall of the clock INB becomes the minimum delay time Tf.

[0219] When the value of code signal DN_FD is "00000001" (the value of code signal DN_FDB is "11111110"), all seven P-side switches 71 of inverter circuit 614a are turned on, and one P-side switch 73 of inverter circuit 614b is turned on. Therefore, the delay of the fall of clock FOUTB_EVN is the sum of 87.5% of the delay of clock INB when all P-side switches 71 of inverter circuit 614a are turned on, and 12.5% ​​of the delay of clock INB1 when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay time of the fall of clock FOUTB_EVN relative to the fall of clock INB is 0.875Tf + 0.125(Tw + Tf) = Tf + 0.125Tw.

[0220] When the value of code signal DN_FD is "00001111" (the value of code signal DN_FDB is "11110000"), the four P-side switches 71 of inverter circuit 614a are turned on, and the four P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay of the fall of clock FOUTB_EVN is the sum of 50% of the delay of clock INB when all P-side switches 71 of inverter circuit 614a are turned on and 50% of the delay of clock INB1 when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay time of the fall of clock FOUTB_EVN relative to the fall of clock INB is 0.500Tf + 0.500(Tw + Tf) = Tf + 0.500Tw.

[0221] When the value of code signal DN_FD is "00111111" (the value of code signal DN_FDB is "11000000"), the two P-side switches 71 of inverter circuit 614a are turned on, and the six P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay of the fall of clock FOUTB_EVN is the sum of 25% of the delay of clock INB when all P-side switches 71 of inverter circuit 614a are turned on and 75% of the delay of clock INB1 when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay time of the fall of clock FOUTB_EVN relative to the fall of clock INB is 0.250Tf + 0.750(Tw + Tf) = Tf + 0.750Tw.

[0222] When the value of code signal DN_FD is "11111111" (the value of code signal DN_FDB is "00000000"), the 0 P-side switches 71 of inverter circuit 614a are turned on, and the 8 P-side switches 73 of inverter circuit 614b are turned on. Therefore, the falling delay of clock FOUTB_EVN becomes a value that reflects 100% of the falling delay of clock INB1 in inverter circuit 614b. Therefore, the rising delay of clock FOUTB_EVN relative to the falling delay of clock INB1 is Tf+1.000Tw.

[0223] The rise of the clock FOUTB_EVN output from the FINE delay circuit 611e is timed independently of the values ​​of the code signals DN_FD and DN_FDB, with both clock INB and clock INB1 set to high level. That is, the rise of clock FOUTB_EVN is timed at the same time as the rise of clock INB1, therefore, the delay time relative to the rise of clock INB is Tw.

[0224] In this way, the FINE delay circuit 611e receives the clock IN, generates and outputs a clock FOUTB_EVN with a different falling delay time according to the value of the code signal DN_FD.

[0225] Next, the operation of the FINE delay circuit 6110 will be explained. In the FINE delay circuit 6110, the signal after the logical inversion of the input clock IN (clock INB) is input to the input terminal CKIN_B, and the signal after the clock INB is delayed by 1.0Tw time (clock INB1) is input to the input terminal CKIN_A. That is, the signal (clock INB) input to the input terminal CKIN_A in the FINE delay circuit 611e is input to the input terminal CKIN_B in the FINE delay circuit 6110, and the signal (clock INB1) input to the input terminal CKIN_B in the FINE delay circuit 611e is input to the input terminal CKIN_A in the FINE delay circuit 6110. Therefore, the relationship between the code signals DN_FD, DN_FDB and the delay time of the clock FOUTB_ODD generated in the FINE delay circuit 6110 is as follows.

[0226] First, with the code signal DN_FD valued at "00000000" (code signal DN_FDB valued at "11111111"), all eight P-side switches 71 of inverter circuit 614a are turned on, and all zero P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay in the fall of clock FOUTB_ODD reflects the delay of clock INB1 in 100% of inverter circuit 614a. Thus, the delay time of the fall of clock FOUTB_ODD relative to the fall of clock INB is Tf+1.00Tw.

[0227] When the value of code signal DN_FD is "00000011" (the value of code signal DN_FDB is "11111100"), all six P-side switches 71 of inverter circuit 614a are turned on, and all two P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay of the fall of clock FOUTB_ODD is the sum of 75% of the delay of clock INB1 when all P-side switches 71 of inverter circuit 614a are turned on and 25% of the delay of clock INB when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the delay time of the fall of clock FOUTB_ODD relative to the fall of clock INB is 0.75(Tw+Tf)+0.25Tf=Tf+0.75Tw.

[0228] When the value of the code signal DN_FD is "00001111" (the value of the code signal DN_FDB is "11110000"), the four P-side switches 71 of inverter circuit 614a are turned on, and the four P-side switches 73 of inverter circuit 614b are turned on. Therefore, the fall delay of clock FOUTB_ODD is the sum of 50% of the delay of clock INB1 when all P-side switches 71 of inverter circuit 614a are turned on and 50% of the delay of clock INB when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the fall delay of clock FOUTB_ODD relative to the rise delay of clock INB is 0.50(Tw+Tf)+0.50Tf=Tf+0.50Tw.

[0229] When the value of the code signal DN_FD is "00111111" (the value of the code signal DN_FDB is "11000000"), the two P-side switches 71 of inverter circuit 614a are turned on, and the six P-side switches 73 of inverter circuit 614b are turned on. Therefore, the fall delay of clock FOUTB_ODD is the sum of 25% of the delay of clock INB1 when all P-side switches 71 of inverter circuit 614a are turned on and 75% of the delay of clock INB when all P-side switches 73 of inverter circuit 614b are turned on. Therefore, the rise delay of clock FOUTB_ODD relative to the fall delay of clock INB is 0.25(Tw+Tf)+0.75Tf=Tf+0.25Tw.

[0230] When the value of the code signal DN_FD is "11111111" (the value of the code signal DN_FDB is "00000000"), the 0 P-side switches 71 of inverter circuit 614a are turned on, and the 8 P-side switches 73 of inverter circuit 614b are turned on. Therefore, the amount of delay in the fall of clock FOUTB_ODD becomes a value that reflects 100% of the delay of clock INB in ​​inverter circuit 614b. Therefore, the delay time of the fall of clock FOUTB_EVN relative to the fall of clock INB is called Tf.

[0231] The rise of the clock FOUTB_ODD output from the FINE delay circuit 611o becomes a timing event where both clock INB and clock INB1 are set to high level, regardless of the values ​​of the code signals DN_FD and DN_FDB. That is, the rise of clock FOUTB_EVN becomes the same timing event as the rise of clock INB1, therefore, the delay time relative to the rise of clock INB is called Tw.

[0232] exist Figure 21The diagram shows the relationship between the delay times of the code signals DN_FD and DN_FDB and the clock signals FOUTB_EVN and FOUTB_ODD. Specifically, when the value of the code signal DN_FD is "00000000", the fall delay time of clock FOUTB_EVN is Tf, and the fall delay time of clock FOUTB_ODD is Tf+1.00Tw. When the value of the code signal DN_FD is "00000011", the fall delay time of clock FOUTB_EVN is Tf+0.25Tw, and the fall delay time of clock FOUTB_ODD is Tf+0.75Tw. When the value of the code signal DN_FD is "00001111", the fall delay time of clock FOUTB_EVN is Tf+0.50Tw, and the fall delay time of clock FOUTB_ODD is Tf+0.50Tw. When the code signal DN_FD is "00111111", the fall delay time of clock FOUTB_EVN is Tf + 0.74Tw, and the fall delay time of clock FOUTB_ODD is Tf + 0.25Tw. When the code signal DN_FD is "11111111", the fall delay time of clock FOUTB_EVN is Tf + 1.00Tw, and the fall delay time of clock FOUTB_ODD is Tf.

[0233] Thus, clocks FOUTB_EVN and FOUTB_ODD are complementary, generated in a manner where the sum of their delay times is constant (1.00Tw), independent of the value of the input code signal DN_FD. Furthermore, the aforementioned "sum of delay times" refers to the sum of delay times excluding the longest delay time Tf. That is, when the fall delay time of clock FOUTB_EVN is set long, the delay time of FOUTB_ODD is set short. Conversely, when the fall delay time of clock FOUTB_EVN is set short, the delay time of FOUTB_ODD is set long.

[0234] Next, the operation of the COURSE delay circuit 612 will be explained. Figure 22 This represents an example of a state during the operation of the COURSE delay circuit. Additionally, Figure 23 Yes Figure 22 The timing diagram illustrates the operation of the COURSE delay circuit under the given conditions. Figure 22 The example shown represents a state where the high level of the input clock IN is 2.50Tw longer than the low level. Figure 22In the example, Δ is 1.25Tw. Therefore, the code signal DN_C has a value of "001". As a result, the code conversion circuit 616 outputs "0000001" as the code signal DN_CD. That is, only the code signal DN_CD1 is a high-level signal, while the code signals DN_CD2 to DN_CD1 are low-level signals. As a result, the fall of the clock FOUTB_ODD output from the FINE delay circuit 6110 is delayed by the delay elements 615_1 and 615_0. Therefore, the fall of the output clock CDLYOUT is delayed by 1Tw relative to the fall of the clock FOUTB_ODD, based on the minimum delay time Tc in the COURSE delay circuit 612 (i.e., the delay time of the delay element 615_0). Figure 23 (The path of the thick line).

[0235] On the other hand, for the rise of the output clock CDLYOUT, independent of the code signal DN_C, the rise of the clock FOUTB_EVN output from the FINE delay circuit 611e is delayed by the delay element 615_0. Therefore, the rise of the output clock CDLYOUT relative to the rise of the clock FOUTB_EVN is delayed by the minimum delay time Tc in the COURSE delay circuit 612 (refer to...). Figure 23 (The path of the thick dashed line).

[0236] With a Δ of 1.25Tw, the code signal DN_F has a value of "0010". The code signal DN_C is "001", i.e., an odd number. Therefore, the code control circuit 613 transforms the code signal DN_F and outputs "00111111" as the code signal DN_FD. When the value of the code signal DN_FD is "00111111", the signal output from the FINE delay circuit 611o is the clock IN delayed by 0.25Tw based on the minimum delay time Tf in the FINE delay circuit 611. Furthermore, when the value of the code signal DN_FD is "00111111", the signal output from the FINE delay circuit 611e is the clock IN delayed by 0.75Tw based on the minimum delay time Tf in the FINE delay circuit 611.

[0237] Based on the above, the falling edge of the output clock CDLYOUT becomes the signal of the clock IN delayed by 1.25Tw based on the minimum delay time (Tf+Tc). Furthermore, the rising edge of the output clock CDLYOUT becomes the signal of the input clock delayed by Tw+Tc. Additionally, in Figure 23 In this circuit, the minimum delay time Tf in the FINE delay circuit 611 is set to 0Tw, and the minimum delay time Tc in the COURSE delay circuit 612 is set to 1Tw, which represents the waveform of each signal.

[0238] Next, the operation of the COURSE delay circuit 612 will be explained using other specific examples. Figure 24 This represents an example of a state during the operation of the COURSE delay circuit. Additionally, Figure 25 Yes Figure 24 The timing diagram illustrates the operation of the COURSE delay circuit under the given conditions. Figure 24 The example shown represents a state where the high level of the input clock IN is 4.50Tw longer than the low level. Figure 24 In the example, Δ is 2.25Tw. Therefore, the code signal DN_C has a value of "010". As a result, the code conversion circuit 616 outputs "0000011" as the code signal DN_CD. That is, code signals DN_CD1 and DN_CD2 are high-level signals, and code signals DN_CD3 to DN_CD1 are low-level signals. As a result, the fall of the clock FOUTB_EVN output from the FINE delay circuit 611e is delayed by delay elements 615_2 to 615_0. Therefore, the fall of the output clock CDLYOUT is delayed by 2Tw relative to the fall of the clock FOUTB_EVN, based on the minimum delay time Tc in the COURSE delay circuit 612 (refer to...). Figure 24 (The path of the thick line).

[0239] On the other hand, for the rise of the output clock CDLYOUT, independent of the code signal DN_C, the rise of the clock FOUTB_EVN output from the FINE delay circuit 611e is delayed by the delay element 615_0. Therefore, the rise of the output clock CDLYOUT relative to the rise of the clock FOUTB_EVN is delayed by the minimum delay time Tc in the COURSE delay circuit 612 (refer to...). Figure 24 (The path of the thick dashed line).

[0240] With a Δ of 2.25Tw, the code signal DN_F has a value of "0010". The code signal DN_C is "010", i.e., an even number. Therefore, the code control circuit 613 transforms the code signal DN_F, outputting "00000011" as the code signal DN_FD. When the code signal DN_FD has a value of "00000011", the signal output from the FINE delay circuit 611e is the clock IN delayed by 0.25Tw based on the minimum delay time Tf in the FINE delay circuit 611. Furthermore, when the code signal DN_FD has a value of "00000011", the signal output from the FINE delay circuit 611e is the clock IN delayed by 0.75Tw based on the minimum delay time Tf in the FINE delay circuit 611.

[0241] Based on the above, the rising edge of the output clock CDLYOUT becomes the signal of the clock IN delayed by 2.25Tw based on the minimum delay time (Tf+Tc). Furthermore, the falling edge of the output clock CDLYOUT becomes the signal of the input clock delayed by Tw+Tc. Additionally, in Figure 25 In this circuit, the minimum delay time Tf in the FINE delay circuit 611 is set to 0Tw, and the minimum delay time Tc in the COURSE delay circuit 612 is set to 1Tw, which represents the waveform of each signal.

[0242] The output clock CDLYOUT from the COURSE delay circuit 612 is logically inverted by an inverter and used as the clock CDLY_T to be output from the delay block circuit 61.

[0243] The delay block circuit 62 receives the input clock / IN and the code signals UP_F and UP_C that constitute the signal DCA_CODE, and generates the delayed clock CDLY_B. The operation of each component of the delay block circuit 62 is the same as that of the delay block circuit 61. That is, in the above description, by replacing the code signals DC_F, DN_C, DN_FD, and DN_CD with the code signals UP_F, UP_C, UP_FD, and UP_CD respectively, the delay block circuit 62 generates and outputs the clock CDLY_B based on the input clock / IN.

[0244] (2-1-4. Operation of the waveform generation circuit)

[0245] The waveform generation circuit 44 receives two clocks (clock CDLY_T and CDLY_B) output from the DCA circuit 43 and generates an output clock OUT. Figure 26 This is a timing diagram illustrating an example of the operation in a waveform generation circuit. Furthermore, Figure 26 This is the timing diagram for the clock IN high-level period CINH being 8Tw and the low-level period CINL being 5.5Tw. Additionally, in... Figure 26 In this process, the minimum delay time Tf in the FINE delay circuit 611 is set to 0Tw, and the minimum delay time Tc in the COURSE delay circuit 612 is set to 1Tw.

[0246] In this case, the clock CDLY_T output from DCA circuit 43 is generated by delaying the rise and fall of clock IN by a predetermined amount using delay block 61. Specifically, Δ = (8 - 5.5) / 2 = 1.25Tw, therefore, the rise of clock CDLY_T is delayed by 2.25Tw (= Tf + Tc + 1.25Tw) relative to the rise of clock IN, and the fall of clock CDLY_T is delayed by 2Tw relative to the fall of clock IN.

[0247] Additionally, the clock CDLY_B is generated by delaying the rise and fall of the clock / IN by a predetermined amount using delay block 62. Specifically, the rise of the clock CDLY_B is delayed by 1Tw (=Tf+Tc) relative to the rise of the clock / IN, and the fall of the clock CDLY_B is delayed by 2Tw relative to the fall of the clock IN.

[0248] The waveform generation circuit 44 generates a timing rise signal that rises with the clock CDLY_T and a timing fall signal that rises with the clock CDLY_B to serve as the output clock OUT. That is, the output clock OUT becomes a signal that rises after 2.25Tw from the rise of the clock IN and falls after 1Tw from the rise of the clock / IN. Thus, the high-level period COUTH of the generated clock OUT is 6.75Tw, and the low-level period COUTL is also 6.75Tw. In other words, the output clock OUT has a 50% duty cycle. Furthermore, the waveform generation circuit 44 also generates a signal / OUT that logically inverts the output clock OUT, and outputs it together with the output clock OUT.

[0249] (3. Effect)

[0250] According to this embodiment, when measuring the pulse width of the input clock DCD_IN (as the period of the high level) and the pulse width of the input clock / DCD_IN in the edge detection circuit 53, the measurement can be performed with high resolution while suppressing the increase in area and current consumption.

[0251] Figure 27 This is a circuit diagram illustrating an example of an edge detection circuit for comparison. Figure 27 The edge detection circuit shown has the same characteristics as... Figure 6 The edge detection circuit 53 of the illustrated embodiment has the same measurement resolution. The edge detection circuit of the comparative example includes (m×s) delay lines 53m. In addition, the edge detection circuit 53 also includes (m×s) delay elements 54β. The delay amount of each delay element 54β is set to be time {1.0+(β-1) / (m×s)}×Tw.

[0252] For example, in the case of m=4 and s=2, such as Figure 27 As shown, the edge detection circuit of the comparative example has eight delay lines 531 to 538. The eight delay elements 541 to 548 disposed on the input side of each delay line 531 to 538 have their delay amounts set in increments of 0.125Tw.

[0253] According to the edge detection circuit configuration of the comparative example, in order to double the measurement resolution, the number of delay lines 53m needs to be doubled. The delay lines 53m are composed of a large number of flip-flops, therefore, the proprietary area is large, and the current consumption is also large. When improving the measurement resolution through the configuration of the comparative example, the area increases, and the current consumption also increases. Furthermore, with the increase in area, the difference in the length of the wiring for transmitting the signal CLK_DET to each delay element 54β also increases. For example, the difference in the length of the wiring for transmitting the signal CLK_DET to delay element 541 and the length of the wiring for transmitting the signal CLK_DET to delay element 548 also increases. When the difference in wiring length increases, the effect of wiring delay becomes non-negligible. Therefore, the signal CLK_DET output from each delay element 54β will have a wiring delay effect on the set delay amount, making it difficult to make the delay difference of the signal CLK_DET input to each delay line 53m equal.

[0254] On the other hand, the edge detection circuit 53 of this embodiment has a delay section 55 for generating a delay difference on the input side of the delay element 54β. The delay section 55 generates two signals, CLK_DETa1 and CLK_DETa2, with a delay difference of 0.125Tw. Either signal CLK_DETa1 or signal CLK_DETa2 is input to the delay element 54β. When signal CLK_DETa1 is used as input and the signal output from the delay element 541 (signal CLK_DETa1) is used as a reference, the delay of the signal output from the delay element 541 (signal CLK_DETa2) is 0.125Tw. Similarly, the delay of the signal (signal CLK_DET2) output from delay element 542 with signal CLK_DETa1 as input is 0.25Tw, and the delay of the signal (signal CLK_DET2) output from delay element 542 with signal CLK_DETa2 as input is 0.375Tw. Furthermore, the delay of the signal (signal CLK_DET3) output from delay element 543 with signal CLK_DETa1 as input is 0.500Tw, and the delay of the signal (signal CLK_DET3) output from delay element 543 with signal CLK_DETa2 as input is 0.625Tw. Furthermore, the delay of the signal (signal CLK_DET4) output from the delay element 544 with signal CLK_DETa1 as input is 0.750Tw, and the delay of the signal (signal CLK_DET4) output from the delay element 544 with signal CLK_DETa2 as input is 0.875Tw.

[0255] That is, the edge detection circuit 53 of the embodiment uses two stages of circuitry—delay element 54β and delay section 55—to generate the delay amount of the signal input to the delay line 53m. Therefore, the number of delay lines 53m remains unchanged, and by adding the delay section 55 (delay element 55δ and selector 56), signals with different delay differences can be multiplied in a time-division manner. As a result, the delay difference of the input signal to the delay element 54β can be reduced. Therefore, the measurement resolution can be improved while simultaneously increasing the suppression area and the current consumption associated with the increase in the number of triggers.

[0256] As described above, this embodiment can provide a semiconductor integrated circuit, a semiconductor memory device, and a memory system that can improve the measurement resolution of pulse signals while suppressing area and current consumption.

[0257] Furthermore, the DCC circuit 20 can be installed not only in the interface chip 2A, but also in the non-volatile memory 2B. Additionally, the signals to be corrected are not limited to the duty cycles of the read enable signals RE, / RE and the data strobe signals DQS, / DQS. They can be installed in locations where the duty cycle needs to be corrected with high precision using a high-speed clock.

[0258] (Second Implementation)

[0259] Next, the second embodiment will be described. Figure 28 This is a circuit diagram illustrating an example of the edge detection circuit of the second embodiment. Figure 28 The configuration of the delay section 57 in the second embodiment shown, which adjusts the delay amount of the signal input to the delay line 53β, is similar to... Figure 6 This differs from the first embodiment shown. For the same... Figure 6 The same components of the edge detection circuit shown in the first embodiment are given the same reference numerals, and their descriptions are omitted.

[0260] Figure 28 The edge detection circuit shown has a delay section 57 formed between the output side of delay element 54β and the input side of delay line 53β. Additionally, a delay element 54(m+1) is added to delay element 54β. The delay section 57 includes m PI (Phase Interpolator) circuits 57β. The output signal from delay element 54β and the output signal from delay element (β+1) are input to the PI circuits 57β. Furthermore, a control signal CTL for adjusting the delay amount is also input to the PI circuits 57β. According to the control signal CTL, a signal CLK_DETβ with the adjusted delay amount is output from the PI circuits 57β.

[0261] Figure 29This is a circuit diagram illustrating an example of a PI circuit. The PI circuit 57β includes two sets of inverter circuit groups 58a and 58b. Inverter circuit group 58a consists of *s* inverter circuits 58a_δ. Each inverter circuit 58a_δ is constructed by connecting two PMOS transistors and two NMOS transistors in series. The *s* inverter circuits 58a_δ are connected in parallel between the node at the power supply potential Vcc and the node at the ground potential Vss.

[0262] The gate of the PMOS transistor (hereinafter referred to as the 3rd PMOS transistor) of the two PMOS transistors constituting the inverter circuit 58a_δ, whose source is connected to the power supply potential Vcc, is input via an inverter to the gate of the s-bit code signal (= control signal CTL) input from the input terminal CTLA. The signal input from the delay element 54β via the input terminal IN_A (the signal CLK_DET after being delayed by the delay element 54β) is input to the gate of the other PMOS transistor (hereinafter referred to as the 4th PMOS transistor). The 1-bit set in the s-bit code signal (= control signal CTL) input from the input terminal CTLA is input to the gate of the NMOS transistor (hereinafter referred to as the 3rd NMOS transistor) of the two NMOS transistors constituting the inverter circuit 58a_δ, whose drain is connected to the ground potential Vss. The signal input from the delay element 54β via the input terminal IN_A (the signal CLK_DET after being delayed by the delay element 54β) is input to the gate of the other NMOS transistor (hereinafter referred to as the 4th NMOS transistor). That is, the set 1 bit of the s-bit code signal (= control signal CTL) input from the input terminal CTLA is input to the gates of the 3rd PMOS transistor and the 3rd NMOS transistor. In addition, the signal input from the delay element 54β via the input terminal IN_A (the signal CLK_DET after being delayed by the delay element 54β) is input to the gates of the 4th PMOS transistor and the 4th NMOS transistor.

[0263] The set bit of the s-bit code signal (= control signal CTL) input from the input terminal CTLB is input via an inverter to the gate of the PMOS transistor (hereinafter referred to as the 5th PMOS transistor) of the two PMOS transistors constituting the inverter circuit 58b_δ, whose source is connected to the power supply potential Vcc. The signal input from the delay element 54(β+1) via the input terminal IN_B (the signal CLK_DET is delayed by the delay element 54(β+1)) is input to the gate of the other PMOS transistor (hereinafter referred to as the 6th PMOS transistor). The set bit of the s-bit code signal (= control signal CTL) input from the input terminal CTLB is input to the gate of the NMOS transistor (hereinafter referred to as the 5th NMOS transistor) of the two NMOS transistors constituting the inverter circuit 58a_δ, whose drain is connected to the ground potential Vss. The signal input from delay element 54(β+1) via input terminal IN_B (the signal CLK_DET delayed by delay element 54(β+1)) is input to the gate of the other NMOS transistor (hereinafter referred to as the 6th NMOS transistor). That is, the set 1 bit of the s-bit code signal (= the signal after the control signal CTL is logically inverted) input from input terminal CTLB is input to the gates of the 5th PMOS transistor and the 5th NMOS transistor. In addition, the signal input from delay element 54(β+1) via input terminal IN_B (the signal CLK_DET delayed by delay element 54(β+1)) is input to the gates of the 6th PMOS transistor and the 6th NMOS transistor.

[0264] The output terminal OUT outputs the inverted signal obtained by combining the outputs from inverter circuit group 58a and inverter circuit group 58b. That is, the signal obtained by combining and inverting the outputs from inverter circuit 58a_δ and inverter circuit 58b_δ is output as the clock signal CLK_DETβ from the output terminal OUT.

[0265] use Figure 30A , Figure 30B as well as Figure 31 The operation of the PI circuit 57β described above will be explained. Figure 30A and Figure 30B This is a circuit diagram illustrating an example of the operation of a PI circuit. Furthermore, Figure 30A and Figure 30B This represents an example of a PI circuit when s = 2. Figure 31 This is a timing diagram illustrating an example of the operation of a PI circuit.

[0266] When s = 2, the PI circuit 57β has an inverter circuit group 58a consisting of two inverter circuits 58a_1 and 58a_2, and an inverter circuit group 58b consisting of two inverter circuits 58b_1 and 58b_2. The control signal CTL is a 2-bit code signal. The first bit of the control signal CTL is input to the two inverter circuits 58a_1 and 58b_1, and the second bit of the data is input to the two inverter circuits 58a_2 and 58b_2.

[0267] Figure 30A This indicates the case where the 2-bit control signal CTL is "11". When the control signal CTL is "11", it is input as a 2-bit code signal via input terminal CTLA. Specifically, "1" is input from input terminal CTLA_1 and "1" is input from input terminal CTLA_2. Alternatively, it can be used as a 2-bit code signal by inputting "00" from input terminal CTLB. Specifically, "0" is input from input terminal CTLB_1 and "0" is input from input terminal CTLB_2.

[0268] The value "0" (=L), which is the inverted value of the input value from input terminal CTLA_1, is input to the gate of the third PMOS transistor of inverter circuit 58a_1. Conversely, the value "1" (=H), which is the input value from input terminal CTLA_1, is input to the gate of the third NMOS transistor of inverter circuit 58a_1. That is, the third PMOS transistor and the third NMOS transistor of inverter circuit 58a_1 are turned on. Therefore, a clock signal is output that rises at the time the fourth PMOS transistor is turned on and falls at the time the N PMOS transistor is turned on. In other words, the inverter circuit 58a_1 outputs a signal that inverts the rise and fall of the signal input from delay element 54β via input terminal IN_A (the signal obtained by delaying the signal CLK_DET by delay element 54β). Similarly, the inverter circuit 58a_2 also outputs a signal that reverses the rising and falling sides of the signal input from the delay element 54β via the input terminal IN_A (the signal obtained by delaying the signal CLK_DET by the delay element 54β). This is because the third PMOS transistor and the third NMOS transistor are turned on.

[0269] On the other hand, the inverted value "1 (=H)" from the input terminal CTLB_1 is input to the gate of the third PMOS transistor in inverter circuit 58b_1. Conversely, the input value "0 (=L)" from the input terminal CTLB_1 is input to the gate of the third NMOS transistor in inverter circuit 58b_1. That is, the third PMOS transistor and the third NMOS transistor in inverter circuit 58b_1 are in the off state. Therefore, no signal is output from inverter circuit 58b_1. Similarly, inverter circuit 58b_2 also does not output a signal because the third PMOS transistor and the third NMOS transistor are in the off state.

[0270] Based on the above, when the value of the control signal CTL is "11", the signal input from the delay element 54β via the input terminal IN_A is output from the output terminal OUT of the PI circuit 57β (the signal obtained by delaying the signal CLK_DET by the delay element 54β).

[0271] Figure 30B This indicates the case where the 2-bit control signal CTL is "10". When the control signal CTL is "10", input "10" from the CTLA input terminal as the 2-bit code signal. Specifically, input "1" from CTLA_1 and input "0" from CTLA_2. Alternatively, input "01" from the CTLB input terminal as the 2-bit code signal. Specifically, input "0" from CTLB_1 and input "1" from CTLB_2.

[0272] The value "0" (=L), which is the inverted value of the input value from input terminal CTLA_1, is input to the gate of the third PMOS transistor of inverter circuit 58a_1. Conversely, the value "1" (=H), which is the input value from input terminal CTLA_1, is input to the gate of the third NMOS transistor of inverter circuit 58a_1. That is, the third PMOS transistor and the third NMOS transistor of inverter circuit 58a_1 are turned on. Therefore, a clock signal is output that rises at the time the fourth PMOS transistor is turned on and falls at the time the N PMOS transistor is turned on. In other words, the inverter circuit 58a_1 outputs a signal that inverts the rise and fall of the signal input from delay element 54β via input terminal IN_A (the signal obtained by delaying the signal CLK_DET by delay element 54β).

[0273] On the other hand, the inverted value "1 (=H)" from the input terminal CTLA_2 is input to the gate of the third PMOS transistor in inverter circuit 58a_2. Conversely, the input value "0 (=L)" from the input terminal CTLA_2 is input to the gate of the third NMOS transistor in inverter circuit 58a_2. That is, the third PMOS transistor and the third NMOS transistor in inverter circuit 58a_2 are in the off state. Therefore, no signal is output from inverter circuit 58a_2.

[0274] The inverted value "1" (=H) from input terminal CTLB_1 is input to the gate of the third PMOS transistor in inverter circuit 58b_1. Conversely, the input value "0" (=L) from input terminal CTLB_1 is input to the gate of the third NMOS transistor in inverter circuit 58b_1. That is, the third PMOS transistor and the third NMOS transistor in inverter circuit 58b_1 are in the off state. Therefore, no signal is output from inverter circuit 58b_1.

[0275] On the other hand, the inverted value "0 (=L)" from the input terminal CTLB_2 is input to the gate of the third PMOS transistor in inverter circuit 58b_2. Additionally, the input value "1 (=H)" from the input terminal CTLB_2 is input to the gate of the third NMOS transistor in inverter circuit 58b_2. That is, the third PMOS transistor and the third NMOS transistor in inverter circuit 58b_2 are turned on. In other words, inverter circuit 58b_2 outputs a signal that inverts the rising and falling edges of the signal input from delay element 54(β+1) via input terminal IN_B (the signal obtained by delaying the signal CLK_DET by delay element 54(β+1)).

[0276] Based on the above, when the value of the control signal CTL is "10", the signal output from inverter circuit 58a_1, which is the inverted signal obtained by delaying the signal CLK_DET via input terminal IN_A from delay element 54β, and the signal output from inverter circuit 58b_2, which is the inverted signal obtained by delaying the signal CLK_DET via input terminal IN_B from delay element 54(β+1), are combined. That is, the signal CLK_DET delayed by delay element 54β and the signal CLK_DET delayed by delay element 54(β+1) are combined at a 1:1 ratio. The combined signal is inverted by an inverter and output from the output terminal OUT of PI circuit 57β. As described above, based on the value of the control signal CTL of the PI circuit 57β, the delay time of the signal CLK_DET is adjusted and output between the delay time implemented by the delay element 54β and the delay time implemented by the delay element 54(β+1). Figure 31 As shown, when the difference between the delay time implemented by delay element 54β and the delay time implemented by delay element 54(β+1) is 0.25Tw, a signal CLK_DETβ with a delay time of 0.125Tw can be generated by setting the value of control signal CTL to "10".

[0277] As described above, the edge detection circuit of this embodiment uses a two-stage circuit consisting of a delay element 54β and a delay section 57 to generate the delay amount of the signal input to the delay line 53m. Therefore, without changing the number of delay lines 53m, by adding a delay section 57 (m PI circuits 57β), signals with different delay differences can be multiplied in a time-division manner. As a result, the delay difference of the input signal to the delay element 54β can be reduced. Therefore, it is possible to improve the measurement resolution while increasing the suppression area and the current consumption associated with the increase in the number of triggers.

[0278] Furthermore, by increasing the number of bits of the inverter circuit 58a_δ of the PI circuit 57β and the control signal CTL to more than 3 bits, and correspondingly increasing the number of inverter circuits 58b_γ, the measurement resolution can be further improved.

[0279] Alternatively, the PI circuit can also be constructed using the structure of the FINE delay circuit 611 in the DCA circuit.

[0280] (Third Implementation)

[0281] Next, the third embodiment will be described. In this embodiment, the edge detection circuit shown in the first and second embodiments will be used in a DLL (Delay Lock Loop) circuit.

[0282] Figure 32 This is a block diagram illustrating an example configuration of the DLL circuit in the third embodiment. The DLL circuit of this embodiment includes a DCD circuit 41, an arithmetic circuit 102, and a delay generation circuit 103. The DCD circuit 41 is a circuit that observes the clock signal at one-cycle width and two-cycle width, and calculates the difference between them into a delay element series of one-cycle values. The DCD circuit 41 outputs a signal DCD_CODE representing the width of one-cycle value of the input clock DCD_IN as the signal DCD_CODE.

[0283] The operational circuit 102 receives the signal DCD_CODE output from the DCD circuit 41 and compares it with the one-cycle width and two-cycle width of the input clock DCD_IN. Based on the comparison result, it converts the one-cycle length of the clock signal into the number of delay elements.

[0284] The delay generation circuit 103 calculates the number of delay elements required to delay the clock signal CLK_IN based on the number of delay elements output from the arithmetic circuit 102. Based on the calculation result, the clock signal CLK_IN is delayed to generate the output clock signal CLK_OUT.

[0285] Figure 33 This is a timing diagram illustrating an example of the operation of the DCD circuit in the third embodiment. The input clock DCD_IN is input to the DCD circuit 41. In each group, the signal generation circuit 51 detects the rise of the initial cycle of the input clock DCD_IN and maintains the signal CLK_DLY at a high level for the entire period from the rise of the initial cycle of the input clock DCD_IN to the rise of the second cycle of the input clock DCD_IN. That is, the signal CLK_DLY is maintained at a high level for the entire period from the rise of the initial cycle of the input clock DCD_IN to the rise of two cycles of the input clock DCD_IN. Furthermore, in each group, the signal generation circuit 51 detects the rise of the fourth cycle of the input clock DCD_IN and maintains the signal CLK_DLY at a high level for the entire period from the rise of the fourth cycle of the input clock DCD_IN to the rise of the third cycle of the input clock DCD_IN. That is, the signal CLK_DLY is kept high for the entire period from the rise of the 4th cycle of the input clock DCD_IN to the 3rd cycle of the input clock DCD_IN.

[0286] In each group, the signal generation circuit 51 detects the rise of the second cycle of the input clock DCD_IN and maintains the signal CLK_DET at a high level for the entire period coinciding with the rise of the next input clock cycle DCD_IN. Additionally, in each group, the signal generation circuit 51 detects the rise of the sixth cycle of the input clock DCD_IN and maintains the signal CLK_DET at a high level for the entire period coinciding with the rise of the next input clock cycle DCD_IN.

[0287] In the signals CLK_DLY and CLK_DET generated as described above, the period from the rise of the odd-numbered period of signal CLK_DLY to the rise of signal CLK_DET is the same as one cycle of the input clock DCD_IN. Furthermore, the period from the rise of the even-numbered period of signal CLK_DLY to the rise of signal CLK_DET is the same as two cycles of the input clock DCD_IN.

[0288] Using the generated signals CLK_DLY and CLK_DET, the edge detection circuit 53 generates the signal DCD_CODE and outputs it in groups.

[0289] The arithmetic circuit 102 uses the multiple groups of signals DCD_CODE output from the DCD circuit 41 to calculate the number of delay elements for one cycle of the input clock DCD_IN. Specifically, it accumulates the number of bits of the high level of the signal DCD_CODE in the odd-numbered cycles of the signal CLK_DET, corresponding to the number of groups, and calculates the average (first average). Additionally, it accumulates the number of bits of the high level of the signal DCD_CODE in the even-numbered cycles of the signal CLK_DET, corresponding to the number of groups, and calculates the average (second average). The difference between the second average and the first average is calculated, and the width of one cycle of the input clock is converted into the number of delay elements.

[0290] The delay generation circuit 103 calculates the number of delay elements that delay the clock signal CLK_IN based on the number of delay elements output from the arithmetic circuit 102. Figure 34 This is a timing diagram illustrating the phase adjustment of the clock signal in DDR communication. For example, in the case of DDR (Double Data Rate) communication in a semiconductor device, the phase of the clock needs to be adjusted so that the rising and falling points of the clock signal arrive at the center of the data. When a clock CLK_IN with equal rising timing and a data signal DATA_IN are input, the delay generation circuit 103 delays the clock CLK_IN by one-quarter of the number of delay elements output from the arithmetic circuit 102, generating an output clock CLK_OUT.

[0291] As described above, the edge detection circuit of the embodiment can be used not only in DCC circuits but also in DLL circuits, and can improve the measurement resolution of the period being measured while suppressing the increase in current consumption associated with the increase in the area and the increase in the number of triggers.

[0292] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor integrated circuit, comprising: A group of delay elements, which has multiple first delay elements having a first delay amount connected in series; A trigger group having multiple triggers, the triggers being input to the output of the corresponding first delay element among the multiple first delay elements of the delay element group; The second delay circuit generates a plurality of second clock signals from the first clock signal, each having a delay difference that is smaller than the first delay amount. as well as A variable delay circuit that can be set to a third delay amount smaller than the second delay amount. The second delay circuit and the variable delay circuit are connected in series between the output terminal of the third clock signal and the input terminal of the trigger group.

2. The semiconductor integrated circuit according to claim 1, The variable delay circuit has a plurality of second delay elements whose delay difference is set as the third delay amount and a selector, the plurality of second delay elements being connected in parallel between the input terminals of the variable delay circuit and the input terminals of the selector.

3. The semiconductor integrated circuit according to claim 1, The variable delay circuit is composed of a phase interpolation circuit, which takes as input the two second clock signals output from the second delay circuit that have a delay difference of the second delay amount.

4. The semiconductor integrated circuit according to claim 2, The second delay circuit has a difference in delay amount that is set as a plurality of third delay elements of the second delay amount. The number of the third delay elements is equal to the number of the triggers, and the output terminals of the third delay elements and the input terminals of the triggers are connected one-to-one. The number of the second delay element is less than the number of the third delay element.

5. A semiconductor memory device connected to a controller for transmitting commands, addresses, and data, said semiconductor memory device comprising: An interface chip comprising a semiconductor integrated circuit according to any one of claims 1 to 4, wherein the semiconductor integrated circuit measures the pulse width of a clock signal and adjusts the duty cycle of the clock signal; and A non-volatile memory chip, having formed a memory cell array with multiple memory cells, is connected to the interface chip. The semiconductor integrated circuit adjusts the duty cycle of the read enable signal or data strobe signal to be transmitted and received between the controller and the non-volatile memory chip.

6. A storage system comprising a controller and the semiconductor storage device of claim 5.

7. A semiconductor memory device for transmitting commands, addresses, and data between a controller and a non-volatile memory, said semiconductor memory device comprising: An interface chip comprising a semiconductor integrated circuit according to any one of claims 1 to 4, wherein the semiconductor integrated circuit measures the period of a clock signal and adjusts the phase of the clock signal; and A non-volatile memory chip, having formed a memory cell array with multiple memory cells, is connected to the interface chip. The semiconductor integrated circuit adjusts the phase of the transmit / receive read enable signal or data strobe signal between the controller and the non-volatile memory chip.

8. A storage system comprising a controller and the semiconductor storage device of claim 7.

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