Guided vias in microelectronic structures

Abstract

To provide microelectronic structures for reliably patterning small features.SOLUTION: A microelectronic structure 100 includes a metalization layer including a conductive via 166 in contact with a conductive line 120, where a center of a top surface of the conductive via 166 is laterally offset from a center of a bottom surface of the conductive via 166. An angle θ of the conductive via 166 is between 40 degrees and 90 degrees.SELECTED DRAWING: Figure 1A

Description

Background Art

[0001] Conventional microelectronic manufacturing techniques may not be able to reliably pattern particularly small features. As a result, the dimensions and performance of microelectronic devices have been limited.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by reading the following detailed description in conjunction with the accompanying drawings. For the sake of ease of explanation, like reference numerals refer to like structural elements. In the figures of the accompanying drawings, the embodiments are shown by way of example and not as a limitation.

[0003] [Figure 1A] Various diagrams of microelectronic structures including guided vias according to various embodiments. [Figure 1B] Various diagrams of microelectronic structures including guided vias according to various embodiments.

[0004] [Figure 2A] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 2B] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 3A] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 3B] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 4A] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 4B] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 5A] Shows the steps in an exemplary process for manufacturing the microelectronic structure of FIG. 1. [Figure 5B]Figure 1 shows the steps in an exemplary process for manufacturing the microelectronic structure. [Figure 6A] Figure 1 shows the steps in an exemplary process for manufacturing the microelectronic structure. [Figure 6B] Figure 1 shows the steps in an exemplary process for manufacturing the microelectronic structure. [Figure 7A] Figure 1 shows the steps in an exemplary process for manufacturing the microelectronic structure. [Figure 7B] Figure 1 shows the steps in an exemplary process for manufacturing the microelectronic structure.

[0005] [Figure 8A] These are various diagrams of another microelectronic structure including guided vias according to various embodiments. [Figure 8B] These are various diagrams of another microelectronic structure including guided vias according to various embodiments.

[0006] [Figure 9] This is a top view of a wafer and a die, which may include any of the microelectronic structures disclosed herein.

[0007] [Figure 10] This is a side cross-sectional view of a microelectronic device which may include any of the microelectronic structures disclosed herein.

[0008] [Figure 11] This is a side cross-sectional view of a microelectronic package which may include any of the microelectronic structures disclosed herein.

[0009] [Figure 12] This is a side cross-sectional view of a microelectronic device assembly which may include any of the microelectronic structures disclosed herein.

[0010] [Figure 13]This is a block diagram of an exemplary computing device which may include any of the microelectronic structures disclosed herein. [Modes for carrying out the invention]

[0011] Guided vias in a microelectronic structure are disclosed herein. For example, the microelectronic structure may include a metallized layer containing conductive vias in contact with a conductive wire, wherein the center of the upper surface of the conductive via is laterally offset from the center of the bottom surface of the conductive via.

[0012] Existing conventional lithography techniques, such as existing conventional extreme ultraviolet (EUV) technologies, may not be able to pattern features that are both small enough and low enough defects for use in commercial microelectronic devices. For example, conventional EUV lithography can suffer from problems with high roughness and excessive bridging defects at tight pitches (e.g., pitches less than 32 nanometers), which can limit or greatly hinder the development of EUV patterning techniques (e.g., spacer-based pitch splitting techniques with a resist "backbone" defined by EUV lithography). Conventional EUV lithography techniques also have the problem of a trade-off between EUV dose and resist thickness. While higher EUV doses may allow for patterning lines with lower roughness, such higher EUV doses typically require thinner resist layers to achieve the desired focal depth and avoid pattern collapse. However, these thinner resist layers typically cannot withstand etching transfer (i.e., transferring the resist pattern to one or more layers below) as much as thicker resists. These limitations are a major obstacle to the adoption of EUV technology in commercial microelectronics manufacturing processes.

[0013] Among the various embodiments disclosed in this specification, many can cure the drawbacks of conventional EUV lithography technology by using manufacturing techniques that include directed self-assembly (DSA) operations. DSA-based technologies may well utilize the property that some materials self-assemble into specific patterns under certain conditions, and these patterns may be utilized in various ways to fabricate small and accurate features in microelectronic devices.

[0014] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification. In the accompanying drawings, like reference numerals refer to like parts throughout, and exemplary embodiments that can be implemented are shown. It will be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description should not be construed in a limiting sense.

[0015] Various operations may be described in turn as a plurality of distinct operations or operations in a manner that is most helpful in understanding the subject matter recited in the claims. However, the order of the description should not be construed as suggesting that these operations necessarily depend on order. In particular, these operations may not be performed in the order presented. The operations described may be performed in a different order than the embodiments described. Various additional operations may be performed and / or the operations described may be omitted in additional embodiments.

[0016] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B) or (A and B). For the purposes of the present disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The phrase "A, B or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The drawings are not necessarily to scale. Many of the drawings show linear structures with flat walls and right-angled corners, which are for ease of illustration only, and actual devices made using these techniques will exhibit rounded corners, surface roughness and other features.

[0017] In the description, the phrases "in an embodiment" or "in embodiments" are used. Each such phrase may refer to one or more of the same or different embodiments. Further, the terms "comprising", "including", "having" and the like used in relation to embodiments of the present disclosure are synonyms. As used herein, the term "conductive" material refers to a material that is electrically conductive, unless otherwise specified. When used to describe a dimension range, the phrase "between X and Y" represents a range that includes X and Y. For convenience, the phrase "Figure 1" may be used to refer to the set of drawings from Figures 1A to 1B, the phrase "Figure 2" may be used to refer to the set of drawings from Figures 2A to 2B, and so on.

[0018] Figures 1A-1B show various diagrams of an exemplary microelectronic structure 100 including a guided via 166. The guided via 166 may extend through the upper dielectric layer 102-2 to contact a conductive structure 120 (e.g., a conductive wire) in the lower dielectric layer 102-1. Figure 1A is a side section view of the microelectronic structure 100 through section AA of Figure 1B, and Figure 1B is a top view of the microelectronic structure 100. The footprint of the conductive structure 120 of the microelectronic structure 100 in Figure 1A is shown by a dotted line in Figure 1B. In some embodiments, the microelectronic structure 100 of Figure 1 may be part of a metallized layer in a microelectronic device (as described later with reference to, for example, Figure 10).

[0019] One or more of the guided vias 166 in the microelectronic structure 100 may be oriented at an angle θ between 40 and 90 degrees (for example, between 40 and 45 degrees, between 40 and 50 degrees, between 40 and 55 degrees, between 40 and 60 degrees, between 40 and 65 degrees, between 40 and 70 degrees, between 40 and 75 degrees, between 40 and 80 degrees, or between 40 and 85 degrees). In the specific example in Figure 1, the leftmost guided via 166 may be oriented at an angle θ equal to 90 degrees (i.e., the leftmost guided via 166 has a longitudinal axis perpendicular to the plane of the conductive structure 120 and / or perpendicular to the plane of the lower dielectric layer 102-1 and / or perpendicular to the plane of the upper dielectric layer 102-2). In the specific example in Figure 1, the intermediate guided via 166 may be oriented at an angle θ of less than 90 degrees (i.e., the intermediate guided via 166 has a longitudinal axis that is not perpendicular to the plane of the conductive structure 120, and / or perpendicular to the plane of the lower dielectric layer 102-1, and / or perpendicular to the plane of the upper dielectric layer 102-2). In the specific example in Figure 1, the rightmost guided via 166 may be oriented at an angle θ of less than 90 degrees (and less than the angle θ of the intermediate guided via 166) (i.e., the rightmost guided via 166 has a longitudinal axis that is not perpendicular to the plane of the conductive structure 120, and / or perpendicular to the plane of the lower dielectric layer 102-1, and / or perpendicular to the plane of the upper dielectric layer 102-2). Different guided vias 166 in the microelectronic structure 100 (for example, different guided vias 166 in a single layer of dielectric layer 102) may have the same or different angles θ.

[0020] The guided vias 166 do not have to have straight sidewalls, but may have a portion that is somewhat curved relative to those sidewalls, resulting in one or more of the guided vias 166 being angled. In some embodiments, as shown in Figure 1, the non-vertical guided vias 166 (i.e., the middle and right-end guided vias 166) may have a top surface whose bottom surface is in contact with the top surface of the corresponding conductive structure 120 and whose center is laterally offset from the center of the bottom surface of the guided via 166. In some embodiments, as shown in Figure 1, the non-vertical guided vias 166 (i.e., the middle and right-end guided vias 166) may have a top surface whose bottom surface is in contact with the top surface of the corresponding conductive structure 120 and whose center is laterally offset from the center of the top surface of the corresponding conductive structure 120 (i.e., as shown in Figure 1B). In some embodiments, the center of the bottom surface of the guided via 166 may coincide with the center of the top surface of the corresponding conductive structure 120. In some embodiments, the sidewall of the bottom surface of the guided via 166 may be aligned with the sidewall of the top surface of the corresponding conductive structure 120 (for example, the bottom surface of the guided via 166 may be "self-aligned" with the top surface of the conductive structure 120 to which it is attached). Figure 1 shows the guided via 166 having a circular cross-section in a top view, but this is merely an example, and in other embodiments, the guided via 166 may have other cross-sectional shapes (for example, elliptical, as will be discussed later with reference to Figure 9).

[0021] The conductive structure 120 may contain any suitable material. The conductive structure 120 may contain one or more layers of various materials, such as one or more layers of linear material and filler material. In some embodiments, the linear material may contain tantalum, tantalum nitride, titanium, titanium nitride, cobalt, or ruthenium (e.g., combinations thereof), and the filler material may contain tungsten, cobalt (e.g., as cobalt silicide), ruthenium, molybdenum, copper, silver, nickel (e.g., as nickel silicide), gold, aluminum, other metals or alloys, or other combinations of materials.

[0022] The lower dielectric layer 102-1 and the upper dielectric layer 102-2 may contain any suitable dielectric material and may have the same or different material compositions. Furthermore, the lower dielectric layer 102-1 and / or the upper dielectric layer 102-2 may contain one or more layers or other configurations of different dielectric materials (for example, the upper dielectric layer 102-2 may contain one or more specific dielectric materials at the interface between the upper dielectric layer 102-2 and the lower dielectric layer 102-1, and different dielectric materials in the remaining region of the upper dielectric layer 102-2). For example, in some embodiments, the dielectric layer 102 may contain inorganic dielectric materials such as silicon oxide, carbon-doped oxides, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide, or insulating metal oxides such as hafnium oxide and zirconium oxide.

[0023] Figure 2-8 shows the steps of an exemplary process for manufacturing the microelectronic structure 100 of Figure 1 according to various embodiments. The operations of the method in Figure 2-8 may be shown by reference to specific embodiments of the microelectronic structure 100 disclosed herein, but the method in Figure 2-8 may be used to form any suitable microelectronic structure 100. The operations are shown once and in a specific order in Figure 2-8, but the operations may be reordered and / or repeated as appropriate (for example, different operations may be performed in parallel when manufacturing multiple microelectronic structures 100 simultaneously). In Figure 2-8, sub-drawing "A" is a side section view passing through section AA of sub-drawing "B", and sub-drawing "B" is a top view.

[0024] Figure 2 shows an assembly including a lower dielectric layer 102-1 having a conductive structure 120 inside. As described above, in some embodiments the conductive structure 120 may be a conductive wire, but the conductive structure 120 may include any suitable conductive structure (e.g., a transistor gate contact or a transistor source / drain contact, as will be described later with reference to Figure 10). The lower dielectric layer 102-1 may be part of a device layer or (e.g., part of a metallized layer, as will be described later with reference to Figure 10).

[0025] Figure 3 shows the assembly after the operation of depositing and patterning a resist material 112 on the assembly of Figure 2. The resist material 112 may comprise any suitable resist material (e.g., photoresist) and may be deposited on the assembly of Figure 2 in any desired manner (e.g., spin coating). The resist material 112 may be patterned (e.g., using a lithography technique such as EUV) to form openings that expose the lower dielectric layer 102-1 and the conductive structure 120. As shown, the openings may be wider than the conductive structure 120 itself and may not be centered on the conductive structure 120 (e.g., as shown for the middle and rightmost conductive structures 120) due to the constraints on the achievable precision of lithography. Consequently, if vias are formed at the center of the openings in the resist material 112, as is done using some existing processes, the vias may be offset from the conductive structure 120, and therefore the contact area with the conductive structure 120 may be limited or may completely "fail" to make contact with the conductive structure 120.

[0026] Figure 4 shows the assembly after the duplicate brush 192 has been formed on the assembly of Figure 3. The duplicate brush 192 may include a material that serves as a template for DSA of the block copolymer (BCP), as will be described later. The duplicate brush 192 may include a first duplicate brush component 156 and a second duplicate brush component 158. The first duplicate brush component 156 may preferentially adhere to the conductive structure 120, and the second duplicate brush component 158 ​​may preferentially adhere to the lower dielectric layer 102-2 and the resist material 112, thereby forming the self-assembled duplicate brush 192. In some embodiments, the first replica brush component 156 (metal-selective brush material) may have surface immobilization groups comprising phosphine, thiol, thiolic acid, thioacetic acid, disulfide, alkyl azide, aryl azide, nitrile, phosphate, silyl, alkyl and other phosphonic acid esters, phosphonamide, sulfonamide, sulfenic acid, sulfinic acid, sulfonic acid, boronic acid, phosphonic acid, carboxylic acid, phosphorus dichloride, alkene, or alkyne material. In some embodiments, the second replica brush component 158 ​​(dielectric-selective brush material) may have surface immobilization groups comprising hydroxy, amine, or carboxylic acid groups. As used herein, “brush” may refer to any material that facilitates self-assembly on itself of a DSA material, and may include large polymers, small polymers, self-assembled monolayers (SAMs), and other suitable materials. The replica brush 192 may be conformal to the assembly in Figure 3, as shown.

[0027] Figure 5 shows the assembly after the BCP has been deposited on the assembly of Figure 4 and the resulting assembly has been processed to allow the BCP to self-assemble into a first BCP component 116 and a second BCP component 118 according to a template provided by the replication brush 192. In the specific embodiment of Figure 5, the self-assembly of the BCP involves the BCP self-separating its first BCP component 116 and second BCP component 118 into concentric bands at the openings in the resist material 112. The BCP may be "stretchable" or "contractible" around a nominal "intrinsic" spacing of the self-assembled bands of the first BCP component 116 / second BCP component 118, allowing for some tolerance for deviation and allowing a range of dimensions for the self-assembled bands of the first BCP component 116 / second BCP component 118. The self-assembly of the first BCP component 116 and the second BCP component 118 may be guided in the openings of the resist material 112, together with the lower replicating brush 192, and therefore, if the openings of the resist material 112 are laterally offset from the conductive structure 120, the first BCP component 116 may be angled between the top plane of the resist material 112 and the bottom plane of the resist material 112. These angles may take the form of the angles of the guided vias 166, as described above. The BCP may include any suitable number of components and may take any suitable form. An example of a BCP that can function as a BCP in the operations disclosed herein is polystyrene-co-poly(methyl methacrylate) (PS-PMMA). When the BCP is PS-PMMA, the first BCP component 116 may be polystyrene (PS) and the second BCP component 118 may be poly(methyl methacrylate) (PMMA).

[0028] Figure 6 shows the assembly after the second BCP component 118 and the first replica brush component 156 of the assembly in Figure 5 have been replaced with conductive material (and other materials as appropriate) to form guided vias 166. The guided vias 166 may therefore be fixed onto the conductive structure 120 (for example, due to the preferential adhesion of the first replica brush component 156 to the conductive structure 120) and may be angled from their bottom surfaces to their top surfaces (for example, due to the angle of the second BCP component 118 between the chemoepitaxial force provided by the replica brush 192 and the graphoepitaxial force of the offset opening in the resist material 112). The second BCP component 118 and the first replica brush component 156 of the assembly in Figure 5 may be removed by any suitable selective etching technique, the material for the guided vias 166 may be deposited, and the resulting assembly may be planarized (for example, using chemomechanical planarization (CMP) technique) to become the assembly in Figure 6.

[0029] Figure 7 shows the assembly from Figure 6 after replacing the first BCP component 116, the second replica brush component 158, and the resist material 112 with the material of the upper dielectric layer 102-2. The first BCP component 116, the second replica brush component 158, and the resist material 112 may be removed using any suitable selective etching technique, and the material of the upper dielectric layer 102-2 may be deposited in any suitable manner. The assembly in Figure 7 may take the form of the microelectronic structure 100 of Figure 1. Subsequent manufacturing operations may be performed on the assembly in Figure 7 (for example, additional metallized layers may be formed, as will be described later).

[0030] As described above, in some embodiments, the guided via 166 does not have to have a circular upper cross-sectional shape. For example, Figure 8 shows a microelectronic structure 100 similar to that in Figure 1, but here the upper cross-sectional shape of the guided via 166 is elliptical (e.g., oblong). Figure 8A is a side cross-sectional view of the microelectronic structure 100 through cross-section AA in Figure 8B, and Figure 8B is a top view of the microelectronic structure 100. The elements of the microelectronic structure 100 in Figure 8 may take any form of the corresponding elements of the microelectronic structure 100 in Figure 1. The guided via 166 similar to that in Figure 8 may be formed using a suitable BCP known in the art, and as a result of its self-assembly, the cross-sectional shape of the second BCP component 118 becomes elliptical. More generally, the guided via 166 may have any suitable upper cross-sectional shape.

[0031] The microelectronic structures 100 disclosed herein may be included in any suitable electronic component. Figure 9-13 shows various examples of devices that may include any of the microelectronic structures 100 disclosed herein.

[0032] Figure 9 is a top view of a wafer 1500 and a die 1502 which may include one or more microelectronic structures 100 according to any embodiment disclosed herein. The wafer 1500 may be made of a semiconductor material and may include one or more dies 1502 having microelectronic structures formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product including any suitable microelectronic structures. After the manufacturing of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the dies 1502 are separated from each other to provide separate “chips” of the semiconductor product. The die 1502 may include, along with any other circuit components, one or more microelectronic structures 100, one or more transistors (e.g., some of the transistors 1640 in Figure 10 described later), and / or support circuits for routing electrical signals to the transistors. In some embodiments, the wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 in Figure 13) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0033] Figure 10 is a side cross-sectional view of a microelectronic device 1600 which may include one or more microelectronic structures 100 according to any embodiment disclosed herein. One or more of the microelectronic devices 1600 may be contained in one or more dies 1502 (Figure 9). The microelectronic devices 1600 may be formed on a substrate 1602 (e.g., wafer 1500 in Figure 9) and may be contained in a die (e.g., die 1502 in Figure 9). The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials that may or may not be combined with silicon, and these alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Furthermore, materials classified as Group II-VI, III-V, or IV may also be used to form the substrate 1602. A few examples of materials on which the substrate 1602 may be formed are described here, but any material that can function as the basis for the microelectronic device 1600 may be used. The substrate 1602 may be part of a singulation-treated die (e.g., die 1502 in Figure 9) or wafer (e.g., wafer 1500 in Figure 9).

[0034] The microelectronic device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include feature portions of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for routing electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional feature portions, such as device isolation regions, gate contacts, etc., which are not shown for clarity. The transistor 1640 is not limited to the type and configuration shown in Figure 10 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations of both. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0035] Each transistor 1640 may include a gate 1622 formed of at least two layers: a gate dielectric and a gate electrode. The gate dielectric may include one or more layers in a stack. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-k material is used, the gate dielectric may be annealed to improve its quality.

[0036] The gate electrode may be formed on a gate dielectric, and the gate electrode may include at least one p-type work function metal or an n-type work function metal, depending on whether the transistor 1640 is a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, one or more of which are work function metal layers, and at least one of which is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers. In the case of a PMOS transistor, the metals that may be used for the gate electrode are not limited to but include ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described later with reference to NMOS transistors (e.g., for work function tuning). In the case of NMOS transistors, the metals that may be used for the gate electrode are not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and (for example, for work function tuning) any of the metals mentioned above with reference to PMOS transistors.

[0037] In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom substantially parallel to the substrate plane and two sidewalls substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including sidewalls substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0038] In some embodiments, pairs of sidewall spacers flanking the gate stack may be formed on opposing sides of the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally involve deposition and etching steps. In some embodiments, multiple pairs of spacers may be used. For example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0039] The S / D region 1620 may be formed inside the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D region 1620 may be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, a dopant such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate 1602 to form the S / D region 1620. An annealing process to activate the dopant and diffuse it deep into the substrate 1602 may follow the ion implantation process. In the latter process, the substrate 1602 may first be etched to form a recess at the location of the S / D region 1620. Next, an epitaxial deposition process may be performed to fill the recess with the material used to manufacture the S / D region 1620. In some implementations, the S / D region 1620 may be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D region 1620.

[0040] Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from a device on the device layer 1604 (e.g., a transistor 1640) through one or more metallization layers (shown in Figure 10 as metallization layers 1606-1610) located on the device layer 1604. For example, conductive features on the device layer 1604 (e.g., a gate 1622 and an S / D contact 1624) may be electrically coupled to an interconnection structure 1628 of the metallization layers 1606-1610. One or more metallization layers 1606-1610 may form a metallization stack (also referred to as an "ILD" stack) 1619 of a microelectronic device 1600. Figure 10 shows a microelectronic structure 100 included in the "M0" metallized layer 1606 of the metallized stack 1619, but this is illustrative only, and any of the microelectronic structures 100 disclosed herein may be included in any of the metallized layers of the metallized stack 1619 as desired.

[0041] The interconnect structure 1628 may be configured to route electrical signals within the metallized layers 1606-1610 according to a variety of designs (in particular, such configurations are not limited to the specific configuration of the interconnect structure 1628 shown in Figure 10). While a certain number of metallized layers 1606-1610 are shown in Figure 10, embodiments of the present disclosure include microelectronic devices having more or fewer metallized layers than those shown.

[0042] In some embodiments, the interconnection structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as metal. The wires 1628a may be configured to route electrical signals in a plane substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a may route electrical signals in and out of the plane of the paper in the perspective view of Figure 10. The vias 1628b may be configured to route electrical signals in a plane substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple the wires 1628a of different metallized layers 1606-1610 together.

[0043] As shown in Figure 10, the metallized layers 1606-1610 may include a dielectric material 1626 disposed between interconnection structures 1628. In some embodiments, the dielectric material 1626 disposed between interconnection structures 1628 in different metallized layers 1606-1610 may have different compositions. In other embodiments, the composition of the dielectric material 1626 between different metallized layers 1606-1610 may be the same.

[0044] The first metallized layer 1606 may be formed above the device layer 1604. As shown, in some embodiments, the first metallized layer 1606 may include lines 1628a and / or vias 1628b. Lines 1628a of the first metallized layer 1606 may be coupled to contacts of the device layer 1604 (e.g., S / D contacts 1624). The first metallized layer 1606 may be referred to as the "M0" metallized layer. In some embodiments, the M0 metallized layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0045] The second metallized layer 1608 may be formed above the first metallized layer 1606. In some embodiments, the second metallized layer 1608 may include vias 1628b for connecting lines 1628a of the second metallized layer 1608 to lines 1628a of the first metallized layer 1606. For clarity, lines 1628a and vias 1628b are structurally depicted by lines within each metallized layer (e.g., within the second metallized layer 1608), but in some embodiments, lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process). The second metallized layer 1608 may be referred to as the "M1" metallized layer. In some embodiments, the M1 metallized layer may include any suitable portion of any of the microelectronic structures 100 disclosed herein.

[0046] The third metallization layer 1610 (and additional metallization layers as desired) may be formed continuously on the second metallization layer 1608 in accordance with the same techniques and configurations as those described in relation to the second metallization layer 1608 or the first metallization layer 1606. The third metallization layer 1610 may be referred to as the “M2” metallization layer. In some embodiments, the M2 metallization layer may comprise any suitable portion of any of the microelectronic structures 100 disclosed herein. In some embodiments, “higher” (i.e., further away from the device layer 1604) metallization layers in the metallization stack 1619 within the microelectronic device 1600 may be thicker.

[0047] The microelectronic device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) formed on the metallized layers 1606-1610 and one or more conductive contacts 1636. In Figure 10, the conductive contacts 1636 are shown as bonding pads. The conductive contacts 1636 may be electrically coupled to an interconnect structure 1628 and may be configured to route electrical signals from the transistor 1640 and other external devices. For example, solder joints may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple the chip containing the microelectronic device 1600 to another component (e.g., a circuit board). The microelectronic device 1600 may include additional or alternative structures for routing electrical signals from the metallized layers 1606-1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) for routing electrical signals to external components.

[0048] Figure 11 is a side cross-sectional view of an exemplary microelectronic package 1650 which may include one or more microelectronic structures 100 according to any embodiment disclosed herein. In some embodiments, the microelectronic package 1650 may be a system-in-package (SiP).

[0049] The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles inside, glass, organic, inorganic, combination of organic and inorganic, embedded portions formed of different materials, etc.) and may have conductive paths extending through the dielectric material between surfaces 1672 and 1674, or between different positions on surface 1672, and / or between different positions on surface 1674. These conductive paths may take any form of the interconnection structure 1628 described above with reference to Figure 10.

[0050] The package substrate 1652 may include conductive contacts 1663 that, by being coupled through the package substrate 1652 to a conductive path (not shown), allow circuits in the die 1656 and / or interposer 1657 to be electrically coupled to various conductive contacts 1664 (or to other devices (not shown) included in the package substrate 1652).

[0051] The microelectronic package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, a first-level interconnect 1665, and conductive contacts 1663 of the package substrate 1652. The first-level interconnect 1665 shown in Figure 11 is a solder bump, but any suitable first-level interconnect 1665 may be used. In some embodiments, the interposer 1657 may not be included in the microelectronic package 1650, and instead, a die 1656 may be directly coupled to the conductive contact 1663 on the surface 1672 by the first-level interconnect 1665. More generally, one or more dies 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, a wire bond, etc.).

[0052] The microelectronic package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the die 1656, a first-level interconnect 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660, coupled to a conductive path (not shown) through the interposer 1657, may allow circuits within the die 1656 to be electrically coupled to various conductive contacts 1661 (or to other devices (not shown) included in the interposer 1657). The first-level interconnect 1658 shown in Figure 11 is a solder bump, but any suitable first-level interconnect 1658 may be used. As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., metal) that functions as an interface between different components. The conductive contact may be recessed in a surface of a component, coplanar, or extended away from it, and may take any suitable shape (e.g., a conductive pad or socket).

[0053] In some embodiments, an underfill material 1666 may be placed between the package substrate 1652 and the interposer 1657 around the first level interconnect 1665, and a mold compound 1668 may be placed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. Exemplary materials that may be used for the underfill material 1666 and the mold compound 1668 are, as appropriate, epoxy mold materials. The second level interconnect 1670 may be coupled to the conductive contact 1664. The second level interconnect 1670 shown in Figure 11 is a solder ball (e.g., for a ball grid array configuration), but any suitable second level interconnect 16770 (e.g., a pin in a pin grid array configuration or a land in a land grid array configuration) may be used. The second level interconnect 1670 may be used to connect the microelectronic package 1650 to a circuit board (e.g., a motherboard), an interposer, or another component known in the art and described later with reference to Figure 12.

[0054] The die 1656 may take any form of the embodiment of the die 1502 described herein (for example, including any embodiment of the microelectronic device 1600). In embodiments in which the microelectronic package 1650 includes a plurality of dies 1656, the microelectronic package 1650 may be referred to as a multi-chip package (MCP). The die 1656 may include circuitry for performing any desired function. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of the dies 1656 may be memory dies (e.g., high-bandwidth memory).

[0055] The microelectronic package 1650 shown in Figure 11 is a flip-chip package, but other package architectures may be used. For example, the microelectronic package 1650 may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the microelectronic package 1650 may be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 1656 are shown in the microelectronic package 1650 in Figure 11, the microelectronic package 1650 may contain any desired number of dies 1656. The microelectronic package 1650 may include additional passive components such as surface-mount resistors, capacitors, and inductors located on either the first or second surface 1672 of the package substrate 1652 or the interposer 1657. More generally, the microelectronic package 1650 may include any other active or passive components known in the art.

[0056] Figure 12 is a side cross-sectional view of a microelectronic device assembly 1700 which may include one or more microelectronic packages or other electronic components (e.g., dies) containing one or more microelectronic structures 100 according to any embodiment disclosed herein. The microelectronic device assembly 1700 includes a number of components arranged on a circuit board 1702 (e.g., which may be a motherboard). The microelectronic device assembly 1700 includes a number of components arranged on a first surface 1740 of the circuit board 1702 and on an opposing second surface 1742 of the circuit board 1702, and generally the components may be arranged on one or both of surfaces 1740 and 1742. Any of the microelectronic packages described later with reference to the microelectronic device assembly 1700 may take the form of any embodiment of the microelectronic package 1650 described above with reference to Figure 11 (e.g., which may include one or more microelectronic structures 100 in a die).

[0057] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers may be formed with a desired circuit pattern to route electrical signals between components coupled to the circuit board 1702 (optionally in cooperation with other metal layers). In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0058] The microelectronic device assembly 1700 shown in Figure 12 includes a package-on-interposer structure 1736 bonded to the first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically bond the package-on-interposer structure 1736 to the circuit board 1702 and may include (as shown in Figure 12) solder balls, male and female parts of sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0059] The package-on-interposer structure 1736 may include a microelectronic package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the form described above with reference to coupling component 1716. Although a single microelectronic package 1720 is shown in Figure 12, multiple microelectronic packages may be coupled to the package interposer 1704, and in fact, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the microelectronic package 1720. The microelectronic package 1720 may be, for example, a die (die 1502 in Figure 9), a microelectronic device (e.g., microelectronic device 1600 in Figure 10), or any other suitable component, or may include them. Generally, the package interposer 1704 may spread connections to a wider pitch or reroute some connections to different connections. For example, the package interposer 1704 may couple a microelectronic package 1720 (e.g., a die) to a set of BGA conductive contacts of a coupling component 1716 for coupling to a circuit board 1702. In the embodiment shown in Figure 12, the microelectronic package 1720 and the circuit board 1702 are mounted on opposing sides of the package interposer 1704. In other embodiments, the microelectronic package 1720 and the circuit board 1702 may be mounted on the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0060] In some embodiments, the package interposer 1704 may be formed as a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of an epoxy resin, a glass fiber reinforced epoxy resin, an epoxy resin containing an inorganic filler, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer 1704 may be formed of an alternative rigid or flexible material. Such material may include the same materials used for semiconductor substrates as described above, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer 1704 may include a metal wire 1710 and vias 1708 including, but not limited to, through-silicon vias (TSVs) 1706. The package interposer 1704 may further include an embedded device 1714 which includes both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices, may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take any form of package-on-interposer structure known in the art.

[0061] The microelectronic device assembly 1700 may include a microelectronic package 1724 which is coupled to the first surface 1740 of a circuit board 1702 by a coupling component 1722. The coupling component 1722 may take any form of the embodiments described above with reference to coupling component 1716, and the microelectronic package 1724 may take any form of the embodiments described above with reference to microelectronic package 1720.

[0062] The microelectronic device assembly 1700 shown in Figure 12 includes a package-on-package structure 1734 coupled to the second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include microelectronic packages 1726 and 1732 coupled to each other by a coupling component 1730, so that the microelectronic package 1726 is positioned between the circuit board 1702 and the microelectronic package 1732. The coupling components 1728 and 1730 may take any form of the embodiments of the coupling component 1716 described above, and the microelectronic packages 1726 and 1732 may take any form of the embodiments of the microelectronic package 1720 described above. The package-on-package structure 1734 may be a configuration relating to any package-on-package structure known in the art.

[0063] Figure 13 is a block diagram of an exemplary computing device 1800, which may include one or more microelectronic structures 100 relating to any embodiment disclosed herein. For example, any suitable component of the computing device 1800 may include one or more microelectronic device assemblies 1700, microelectronic packages 1650, microelectronic devices 1600, or dies 1502 disclosed herein. Although numerous components are shown in Figure 13 as being included in the computing device 1800, one or more of these components may be omitted or duplicated as appropriate depending on the application. In some embodiments, some or all of the components included in the computing device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0064] Furthermore, in various embodiments, the computing device 1800 does not have to include one or more of the components shown in Figure 13, but it may include interface circuits for connecting one or more components. For example, the computing device 1800 does not have to include the display device 1806, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1806 can be connected. In another set of examples, the computing device 1800 does not have to include the audio input device 1824 or the audio output device 1808, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1824 or the audio output device 1808 can be connected.

[0065] The computing device 1800 may include processing devices 1802 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. Processing devices 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 1800 may include memory 1804, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, memory 1804 may include memory that shares a die with processing devices 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0066] In some embodiments, the computing device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for data transfer to and from the computing device 1800. The terms “wireless” and their derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The terms do not imply that the devices in question are completely wiring-free, although in some embodiments they may be wiring-free.

[0067] The 1812 communication chip may implement any of a number of wireless standards or protocols, including, but is not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and IEEE standards including the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2")). Broadband radio access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with GSM® Evolution Enhanced Data (EDGE), GSM® EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chip 1812 may operate in accordance with other radio protocols. The computing device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmission).

[0068] In some embodiments, the communication chip 1812 may manage wired communication such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 1812 may include multiple communication chips. For example, the first communication chip 1812 may be dedicated to short-range wireless communication such as Wi-Fi® or Bluetooth®, and the second communication chip 1812 may be dedicated to long-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, etc. In some embodiments, the first communication chip 1812 may be dedicated to wireless communication, and the second communication chip 1812 may be dedicated to wired communication.

[0069] The computing device 1800 may include a battery / power supply circuit 1814. The battery / power supply circuit 1814 may include circuits for connecting components of the computing device 1800 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the computing device 1800 (e.g., AC line power).

[0070] The computing device 1800 may include a display device 1806 (or a corresponding interface circuit as described above). The display device 1806 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0071] The computing device 1800 may include an audio output device 1808 (or a corresponding interface circuit as described above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headset, or earphone.

[0072] The computing device 1800 may include an audio input device 1824 (or a corresponding interface circuit as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI (musical instrument digital interface) output).

[0073] The computing device 1800 may include a GPS device 1818 (or a corresponding interface circuit as described above). The GPS device 1818 may communicate with a satellite-based system and receive the position of the computing device 1800 in a manner known in the art.

[0074] The computing device 1800 may include other output devices 1810 (or corresponding interface circuits as described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0075] The computing device 1800 may include other input devices 1820 (or corresponding interface circuits as described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0076] The computing device 1800 may have any desired form factor, such as a handheld or mobile computing device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop computing device, a server computing device or other network computing component, or a vehicle computing device (e.g., a vehicle control unit, laptop computing device, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device). In some embodiments, the computing device 1800 may be any other electronic device that processes data.

[0077] The following paragraphs provide various examples of embodiments disclosed herein.

[0078] Example 1 is a microelectronic structure that includes a metallized region containing conductive vias in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, and the longitudinal axis of the conductive via is not oriented perpendicular to the plane.

[0079] Example 2 includes the subject matter of Example 1 and further specifies that the conductive vias have a non-circular footprint.

[0080] Example 3 includes the subject matter of either Example 1-2 and further specifies that the conductive via has an elliptical footprint.

[0081] Example 4 includes the subject matter of any of Examples 1-3 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 90 degrees.

[0082] Example 5 includes the subject matter of any of Examples 1-4 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 85 degrees.

[0083] Example 6 includes the subject matter of any of Examples 1-5 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 80 degrees.

[0084] Example 7 includes the subject matter of any of Examples 1-6 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 75 degrees.

[0085] Example 8 includes the subject matter of any of Examples 1-7 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 70 degrees.

[0086] Example 9 includes the subject matter of any of Examples 1-8 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 65 degrees.

[0087] Example 10 includes the subject matter of any of Examples 1-9 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 60 degrees.

[0088] Example 11 includes the subject matter of any of Examples 1-10 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 55 degrees.

[0089] Example 12 includes the subject matter of any of Examples 1-11 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 50 degrees.

[0090] Example 13 includes the subject matter of any of Examples 1-12 and further specifies that the angle of the longitudinal axis of the conductive via is between 40 and 45 degrees.

[0091] Example 14 includes the subject matter of any of Examples 1-13, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, and the metallized region further includes a second conductive via in contact with the second conductive wire in the plane of the conductive wire, and the longitudinal axis of the second conductive via is not oriented perpendicular to the plane.

[0092] Example 15 includes the subject matter of Example 14 and further specifies that the second conductive via has a non-circular footprint.

[0093] Example 16 includes the subject matter of any of Examples 14-15 and further specifies that the second conductive via has an elliptical footprint.

[0094] Example 17 includes the subject matter of any of Examples 14-16 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 90 degrees.

[0095] Example 18 includes the subject matter of any of Examples 14-17 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 85 degrees.

[0096] Example 19 includes the subject matter of any of Examples 14-18 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 80 degrees.

[0097] Example 20 includes the subject matter of any of Examples 14-19 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 75 degrees.

[0098] Example 21 includes the subject matter of any of Examples 14-20 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 70 degrees.

[0099] Example 22 includes the subject matter of any of Examples 14-21 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 65 degrees.

[0100] Example 23 includes the subject matter of any of Examples 14-22 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 60 degrees.

[0101] Example 24 incorporates the subject matter of any of Examples 14-23 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 55 degrees.

[0102] Example 25 includes the subject matter of any of Examples 14-24 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 50 degrees.

[0103] Example 26 incorporates the subject matter of any of Examples 14-25 and further specifies that the angle of the longitudinal axis of the second conductive via is between 40 and 45 degrees.

[0104] Example 27 includes the subject matter of any of Examples 1-26 and further specifies that the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via.

[0105] Example 28 includes the subject matter of any of Examples 1-27 and further specifies that the center of the top surface of the conductive via is laterally offset from the center of the top surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire.

[0106] Example 29 includes the subject matter of any of Examples 1-28 and further specifies that the metallized region is an M0 metallized layer.

[0107] Example 30 includes the subject matter of any of Examples 1-29 and further includes a device layer and a metallized layer, the metallized region being between the device layer and the metallized layer.

[0108] Example 31 is a microelectronic structure that includes a metallized region containing a conductive via in contact with a conductive wire, wherein the center of the upper surface of the conductive via is laterally offset from the center of the bottom surface of the conductive via.

[0109] Example 32 includes the subject matter of Example 31 and further specifies that the conductive via has a non-circular footprint.

[0110] Example 33 includes the subject matter of any of Examples 31-32 and further specifies that the conductive via has an elliptical footprint.

[0111] Example 34 includes the subject matter of any of Examples 31-33 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 90 degrees.

[0112] Example 35 includes the subject matter of any of Examples 31-34 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 85 degrees.

[0113] Example 36 includes the subject matter of any of Examples 31-35 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 80 degrees.

[0114] Example 37 includes the subject matter of any of Examples 31-36 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 75 degrees.

[0115] Example 38 includes the subject matter of any of Examples 31-37 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 70 degrees.

[0116] Example 39 includes the subject matter of any of Examples 31-38 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 65 degrees.

[0117] Example 40 includes the subject matter of any of Examples 31-39 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 60 degrees.

[0118] Example 41 includes the subject matter of any of Examples 31-40 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 55 degrees.

[0119] Example 42 includes the subject matter of any of Examples 31-41 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 50 degrees.

[0120] Example 43 includes the subject matter of any of Examples 31-42 and further specifies that the conductive wire is in the plane of the conductive wire and the angle of the conductive via with respect to the plane is between 40 and 45 degrees.

[0121] Example 44 includes the subject matter of any of Examples 31-43, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire, the first and second conductive wires are in the plane of the conductive wires, and the center of the upper surface of the second conductive via is laterally offset from the center of the bottom surface of the second conductive via.

[0122] Example 45 includes the subject matter of Example 44 and further specifies that the second conductive via has a non-circular footprint.

[0123] Example 46 includes the subject matter of any of Examples 44-45 and further specifies that the second conductive via has an elliptical footprint.

[0124] Example 47 includes the subject matter of any of Examples 44-46 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 90 degrees.

[0125] Example 48 includes the subject matter of any of Examples 44-47 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 85 degrees.

[0126] Example 49 includes the subject matter of any of Examples 44-48 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 80 degrees.

[0127] Example 50 includes the subject matter of any of Examples 44-49 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 75 degrees.

[0128] Example 51 includes the subject matter from any of Examples 44-50 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 70 degrees.

[0129] Example 52 includes the subject matter of any of Examples 44-51 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 65 degrees.

[0130] Example 53 includes the subject matter of any of Examples 44-52 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 60 degrees.

[0131] Example 54 includes the subject matter of any of Examples 44-53 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 55 degrees.

[0132] Example 55 includes the subject matter of any of Examples 44-54 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 50 degrees.

[0133] Example 56 includes the subject matter of any of Examples 44-55 and further specifies that the angle of the second conductive via with respect to the plane is between 40 and 45 degrees.

[0134] Example 57 includes the subject matter of any of Examples 31-56 and further specifies that the angle of the first conductive via is different from the angle of the second conductive via.

[0135] Example 58 includes the subject matter of any of Examples 31-57 and further specifies that the center of the top surface of the conductive via is laterally offset from the center of the top surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire.

[0136] Example 59 includes the subject matter of any of Examples 31-58 and further specifies that the metallized region is an M0 metallized layer.

[0137] Example 60 includes the subject matter of any of Examples 31-59 and further includes a device layer and a metallized layer, the metallized region being between the device layer and the metallized layer.

[0138] Example 61 is a microelectronic structure including a metallized region containing conductive vias in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, the center of the upper surface of the conductive via is offset laterally from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire, and the conductive via is angled to be fixed onto the conductive wire.

[0139] Example 62 includes the subject matter of Example 61 and further specifies that the conductive via has a non-circular footprint.

[0140] Example 63 includes the subject matter of any of Examples 61-62 and further specifies that the conductive via has an elliptical footprint.

[0141] Example 64 includes the subject matter of any of Examples 61-63 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 90 degrees.

[0142] Example 65 includes the subject matter of any of Examples 61-64 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 85 degrees.

[0143] Example 66 incorporates the subject matter of any of Examples 61–65 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 80 degrees.

[0144] Example 67 includes the subject matter of any of Examples 61-66 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 75 degrees.

[0145] Example 68 includes the subject matter of any of Examples 61-67 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 70 degrees.

[0146] Example 69 includes the subject matter of any of Examples 61-68 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 65 degrees.

[0147] Example 70 includes the subject matter of any of Examples 61–69 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 60 degrees.

[0148] Example 71 includes the subject matter of any of Examples 61-70 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 55 degrees.

[0149] Example 72 includes the subject matter of any of Examples 61-71 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 50 degrees.

[0150] Example 73 includes the subject matter of any of Examples 61-72 and further specifies that the angle of the longitudinal axis of the conductive via with respect to the plane is between 40 and 45 degrees.

[0151] Example 74 comprises the subject matter of any of Examples 61-73, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further comprises a second conductive via in contact with the second conductive wire, the second conductive wire is in the plane of the conductive wire, the center of the upper surface of the second conductive via is laterally offset from the center of the upper surface of the second conductive wire in a cross section perpendicular to the longitudinal axis of the second conductive wire, and the second conductive via is angled to be fixed onto the second conductive wire.

[0152] Example 75 includes the subject matter of Example 74 and further specifies that the second conductive via has a non-circular footprint.

[0153] Example 76 includes the subject matter of any of Examples 74-75 and further specifies that the second conductive via has an elliptical footprint.

[0154] Example 77 includes the subject matter of any of Examples 74-76 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 90 degrees.

[0155] Example 78 includes the subject matter of any of Examples 74-77 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 85 degrees.

[0156] Example 79 includes the subject matter of any of Examples 74-78 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 80 degrees.

[0157] Example 80 includes the subject matter of any of Examples 74–79 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 75 degrees.

[0158] Example 81 includes the subject matter of any of Examples 74-80 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 70 degrees.

[0159] Example 82 includes the subject matter of any of Examples 74-81 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 65 degrees.

[0160] Example 83 includes the subject matter of any of Examples 74-82 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 60 degrees.

[0161] Example 84 includes the subject matter of any of Examples 74-83 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 55 degrees.

[0162] Example 85 includes the subject matter of any of Examples 74-84 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 50 degrees.

[0163] Example 86 includes the subject matter of any of Examples 74–85 and further specifies that the angle of the longitudinal axis of the second conductive via with respect to the plane is between 40 and 45 degrees.

[0164] Example 87 includes the subject matter of any of Examples 61-86 and further specifies that the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via.

[0165] Example 88 includes the subject matter of any of Examples 61-87 and further specifies that the center of the top surface of the conductive via is laterally offset from the center of the top surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire.

[0166] Example 89 includes the subject matter of any of Examples 61-88 and further specifies that the metallized region is an M0 metallized layer.

[0167] Example 90 includes the subject matter of any of Examples 61-89 and further includes a device layer and a metallized layer, the metallized region being between the device layer and the metallized layer.

[0168] Example 91 is a computing device comprising a die containing one of the microelectronic structures described in any of Examples 1-90 and a circuit board, wherein the die is communicatively coupled to the circuit board.

[0169] Example 92 includes the subject matter of Example 91 and further specifies that the die is contained in a package and the package is communicatively coupled to a circuit board.

[0170] Example 93 includes the subject matter of Example 92 and further specifies that the package is communicatively coupled to the circuit board by solder.

[0171] Example 94 includes the subject matter of any of Examples 91-93 and further specifies that the circuit board is a motherboard.

[0172] Example 95 includes the subject matter of any of Examples 91-94 and further specifies that the die is part of a processing device or a memory device.

[0173] Example 96 includes the subject matter of any of Examples 91-95 and further defines the computing device as a mobile computing device.

[0174] Example 97 includes the subject matter of any of Examples 91-95 and further specifies that the computing device is a laptop computing device.

[0175] Example 98 includes the subject matter of any of Examples 91-95 and further specifies that the computing device is a desktop computing device.

[0176] Example 99 includes the subject matter of any of Examples 91-95 and further defines the computing device as a wearable computing device.

[0177] Example 100 includes the subject matter of any of Examples 91-95 and further specifies that the computing device is a server computing device.

[0178] Example 101 includes the subject matter of any of Examples 91-95 and further specifies that the computing device is a vehicle computing device.

[0179] Example 102 includes the subject matter of any of Examples 91-101 and further specifies that the computing device further includes a display communicatively coupled to a circuit board.

[0180] Example 103 includes the subject matter of any of Examples 91-102 and further specifies that the computing device further includes an antenna communicatively coupled to a circuit board.

[0181] Example 104 includes the subject matter of any of Examples 91-103 and further specifies that the computing device further includes a housing around the die and circuit board.

[0182] Example 105 includes the subject matter of Example 104 and further specifies that the housing includes plastic material.

[0183] Example 106 includes any of the manufacturing methods disclosed herein. [Other possible forms] [Item 1] A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, and the longitudinal axis of the conductive via is not oriented perpendicular to the plane. [Item 2] The conductive via described above is a microelectronic structure as described in item 1, having a non-circular footprint. [Item 3] The conductive via described above is a microelectronic structure as described in item 1, having an elliptical footprint. [Item 4] The microelectronic structure described in item 1, wherein the angle of the longitudinal axis of the conductive via is between 40 and 90 degrees. [Item 5] The microelectronic structure according to item 1, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire in the plane of the conductive wire, and the longitudinal axis of the second conductive via is not oriented perpendicular to the plane. [Item 6] The microelectronic structure described in item 5, wherein the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via. [Item 7] The microelectronic structure according to Item 1, wherein the center of the upper surface of the conductive via is offset laterally from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire. [Item 8] The above-mentioned metallized region is the M0 metallized layer, which is the microelectronic structure described in item 1. [Item 9] The device layer, Metallized layer and Furthermore, The above-mentioned metallized region is a microelectronic structure as described in item 1, located between the above-mentioned device layer and the above-mentioned metallized layer. [Item 10] A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the center of the upper surface of the conductive via is laterally offset from the center of the bottom surface of the conductive via. [Item 11] The conductive via described above is a microelectronic structure as described in item 10, having a non-circular footprint. [Item 12] The conductive via described above is a microelectronic structure as described in item 10, having an elliptical footprint. [Item 13] The microelectronic structure according to item 10, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire, the first conductive wire and the second conductive wire are in the plane of the conductive wire, and the center of the upper surface of the second conductive via is laterally offset from the center of the bottom surface of the second conductive via. [Item 14] The above-mentioned second conductive via has a non-circular footprint, as described in item 13, for the microelectronic structure. [Item 15] A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, the center of the upper surface of the conductive via is laterally offset from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire, and the conductive via is angled to be fixed onto the conductive wire. [Item 16] The microelectronic structure according to item 15, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire, the second conductive wire is on the plane of the conductive wire, the center of the upper surface of the second conductive via is laterally offset from the center of the upper surface of the second conductive wire in a cross section perpendicular to the longitudinal axis of the second conductive wire, and the second conductive via is angled to be fixed onto the second conductive wire. [Item 17] The microelectronic structure described in item 16, wherein the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via. [Item 18] The microelectronic structure according to item 16, wherein the center of the upper surface of the conductive via is offset laterally from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire. [Item 19] The above-mentioned metallized region is the M0 metallized layer, as described in item 15, for the microelectronic structure. [Item 20] The device layer, Metallized layer and Furthermore, The above-mentioned metallized region is a microelectronic structure described in item 15, located between the above-mentioned device layer and the above-mentioned metallized layer.

Claims

1. A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, the conductive via is fixed to the conductive wire with its bottom surface positioned on the upper surface of the conductive wire, the side wall of the bottom surface of the conductive via aligns with the side wall of the upper surface of the conductive wire, and the longitudinal axis of the conductive via is not oriented perpendicular to the plane.

2. The microelectronic structure according to claim 1, wherein the conductive via has a non-circular footprint.

3. The microelectronic structure according to claim 1 or 2, wherein the conductive via has an elliptical footprint having a major axis parallel to the direction of extension of the conductive wire.

4. The microelectronic structure according to any one of claims 1 to 3, wherein the angle of the longitudinal axis of the conductive via is between 40 degrees and 90 degrees.

5. The microelectronic structure according to any one of claims 1 to 4, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire in the plane of the conductive wire, and the longitudinal axis of the second conductive via is not oriented perpendicular to the plane.

6. The microelectronic structure according to claim 5, wherein the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via.

7. The microelectronic structure according to any one of claims 1 to 6, wherein the center of the upper surface of the conductive via is offset laterally from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire.

8. The microelectronic structure according to any one of claims 1 to 7, wherein the metallized region is an M0 metallized layer.

9. The device layer, Metallized layer and Furthermore, The microelectronic structure according to any one of claims 1 to 8, wherein the metallized region is located between the device layer and the metallized layer.

10. A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the center of the upper surface of the conductive via is laterally offset from the center of the bottom surface of the conductive via, the conductive via is fixed to the conductive wire with its bottom surface positioned on the upper surface of the conductive wire, and the side wall of the bottom surface of the conductive via is aligned with the side wall of the upper surface of the conductive wire.

11. The microelectronic structure according to claim 10, wherein the conductive via has a non-circular footprint.

12. The microelectronic structure according to claim 10 or 11, wherein the conductive via has an elliptical footprint having a major axis parallel to the direction of extension of the conductive wire.

13. The microelectronic structure according to any one of claims 10 to 12, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire, the first conductive wire and the second conductive wire are in the plane of the conductive wire, and the center of the upper surface of the second conductive via is laterally offset from the center of the bottom surface of the second conductive via.

14. The microelectronic structure according to claim 13, wherein the second conductive via has a non-circular footprint.

15. A microelectronic structure comprising a metallized region including a conductive via in contact with a conductive wire, wherein the conductive wire is in the plane of the conductive wire, the center of the upper surface of the conductive via is laterally offset from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire, the conductive via is angled so as to be fixed to the conductive wire with its bottom surface positioned on the upper surface of the conductive wire, and the side wall of the bottom surface of the conductive via is aligned with the side wall of the upper surface of the conductive wire.

16. The microelectronic structure according to claim 15, wherein the conductive via is a first conductive via, the conductive wire is a first conductive wire, the metallized region further includes a second conductive via in contact with the second conductive wire, the second conductive wire is in the plane of the conductive wire, the center of the upper surface of the second conductive via is laterally offset from the center of the upper surface of the second conductive wire in a cross section perpendicular to the longitudinal axis of the second conductive wire, and the second conductive via is angled to be fixed onto the second conductive wire.

17. The microelectronic structure according to claim 16, wherein the angle of the longitudinal axis of the first conductive via is different from the angle of the longitudinal axis of the second conductive via.

18. The microelectronic structure according to claim 16 or 17, wherein the center of the upper surface of the conductive via is offset laterally from the center of the upper surface of the conductive wire in a cross section perpendicular to the longitudinal axis of the conductive wire.

19. The microelectronic structure according to any one of claims 16 to 18, wherein the metallized region is an M0 metallized layer.

20. The device layer, Metallized layer and Furthermore, The microelectronic structure according to any one of claims 16 to 19, wherein the metallized region is located between the device layer and the metallized layer.

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