Semiconductor substrate and processing method thereof, solar cell and manufacturing method thereof

Abstract

The present application relates to the technical field of solar cells, and more particularly to a semiconductor substrate and a processing method thereof, and a solar cell and a manufacturing method thereof. The processing method of the semiconductor substrate includes forming a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of the semiconductor substrate, and the area of ​​the smooth surface region is equal to or larger than the area of ​​the textured surface region. The present application forms a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of the semiconductor substrate, a transparent conductive film is located only on the smooth surface region, and grid lines are formed in at least a part of the transparent conductive film on the opposite side to the semiconductor substrate, thereby improving the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on November 4, 2022, with the application number 202211378975.9 and the title of the invention "Semiconductor Substrate and Its Processing Method, Solar Cell and Its Manufacturing Method", and the entire content thereof is incorporated herein by reference.

[0002] This application relates to the technical field of solar cells, specifically to semiconductor substrates and their processing methods, as well as solar cells and their manufacturing methods.

Background Art

[0003] A solar cell is a device that absorbs sunlight and directly or indirectly converts solar radiation energy into electrical energy through the photovoltaic effect or the photochemical effect. Solar cells are clean energy cells and are widely applied in life and production.

[0004] One of the semiconductor substrates commonly used in solar cells is a silicon substrate. In order to enhance the light absorption ability of the solar cell, usually, a texturing treatment is performed on the surface of the silicon substrate to form a textured surface, thereby enhancing the light trapping ability of the silicon substrate and improving the photovoltaic conversion efficiency of the solar cell. However, after the texturing treatment, a pyramid structure densely arranged on the surface of the silicon substrate is formed, and the height of these pyramid structures usually reaches 1 μm to 2 μm. Therefore, the uniformity of other material layers formed in subsequent processes deteriorates, the open-circuit voltage of the solar cell decreases, and the contact between each material layer also deteriorates, restricting the transport of carriers and increasing the series resistance. As a result, the photovoltaic conversion performance of solar energy deteriorates.

[0005] As is clear from this, a method for improving the photovoltaic conversion efficiency of solar cells is an urgent problem to be solved in the field of solar cells.

Summary of the Invention

Problems to be Solved by the Invention

[0006] Therefore, the technical problem that this application aims to solve is to provide a semiconductor substrate and a method for processing the same, a solar cell and a method for manufacturing the same, by overcoming the problem of low photoelectric conversion efficiency in conventional solar cells. [Means for solving the problem]

[0007] A first aspect of the present invention provides a method for processing a semiconductor substrate, which includes the step of forming a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of the semiconductor substrate, wherein the area of ​​the smooth surface region is equal to or greater than the area of ​​the textured surface region.

[0008] Selectable ratios of smooth surface area to textured surface area are 1:1 to 1.2:1.

[0009] The step of selectively forming a smooth surface region and a textured surface region adjacent to the smooth surface region on any one surface of a semiconductor substrate includes the steps of forming a protective layer on any one side surface of the semiconductor substrate, and installing a patterned cover layer on the side of the protective layer opposite to the semiconductor substrate, wherein the cover layer has a hollow region, and the protective layer includes a first region located at the bottom of the hollow region and a second region shielded by the cover layer, thickening the first region of the protective layer using the cover layer, removing the cover layer after thickening the first region of the protective layer, etching and removing the second region of the protective layer with respect to the first region of the protective layer after the cover layer has been removed, performing a textured treatment on one side of the semiconductor substrate exposed from the protective layer after the second region has been removed so that the one side of the semiconductor substrate exposed from the protective layer forms a textured surface region, and etching and removing the first region corresponding to the protective layer after the textured surface region has been formed so that a part of the surface on one side of the semiconductor substrate forms a smooth surface region.

[0010] Selectively, the hollow region includes at least a plurality of spaced-apart strip-shaped openings, and the strip-shaped openings are parallel to each other.

[0011] The step of selectively forming a protective layer on any one side of a semiconductor substrate includes the steps of coating the entire surface of any one side of the semiconductor substrate with a base film and performing a diffusion annealing treatment on the base film so that the base film and the surface of one side of the semiconductor substrate react to form an ion-doped protective layer and move impurities in the semiconductor substrate to the protective layer.

[0012] Selectively, the step of thickening a first region of the protective layer includes the steps of coating the surface of the first region with a surface film using a cover layer as a mask, and increasing the thickness of the first region by making the surface film part of the protective layer by performing a diffusion annealing treatment on the surface film.

[0013] The cover layer may optionally contain quartz material.

[0014] Selectively, the undercoat and surface film are liquid source films.

[0015] Selectively, the undercoat and surface film are phosphorus-containing liquid source films, and the phosphorus concentration of the surface film is greater than that of the undercoat.

[0016] Optionally, the diffusion annealing time for the surface film is longer than the diffusion annealing time for the undercoat film.

[0017] Selectively, the diffusion annealing temperature of the surface film is higher than the diffusion annealing temperature of the undercoat film.

[0018] For the optional steps of etching and removing the first region of the protective layer and etching and removing the second region of the protective layer, the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution and aqueous solvent, with the concentration of the hydrofluoric acid aqueous solution being 35% to 50% by mass, the concentration of the hydrochloric acid aqueous solution being 30% to 50% by mass, the volume percentage of the hydrofluoric acid aqueous solution being 1% to 4%, the volume percentage of the hydrochloric acid aqueous solution being 1% to 3%, and the etching time being 100 s to 300 s.

[0019] A second aspect of the present invention provides a semiconductor substrate having a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side, wherein the area of ​​the smooth surface region is equal to or greater than the area of ​​the textured surface region.

[0020] Selectable ratios of smooth surface area to textured surface area are 1:1 to 1.2:1.

[0021] A third aspect of the present invention provides a method for manufacturing a solar cell, comprising the steps of: providing a semiconductor substrate; processing the semiconductor substrate using the semiconductor substrate processing method described above so that at least one side of the semiconductor substrate has a smooth surface region and a textured surface region adjacent to the smooth surface region; forming a transparent conductive film located only in the smooth surface region on the side of the semiconductor substrate having the smooth surface region and the textured surface region; and forming grid lines in at least a portion of the transparent conductive film on the side opposite to the semiconductor substrate.

[0022] Optionally, the method for manufacturing a solar cell further includes the step of forming a doping semiconductor layer located between the semiconductor substrate and the transparent conductive film on the side of the semiconductor substrate having a smooth surface region and a textured surface region, before forming the transparent conductive film.

[0023] Selectively, before forming the doping semiconductor layer, an intrinsic semiconductor layer is formed on the side of the semiconductor substrate having both a smooth surface region and a textured surface region, positioned between the semiconductor substrate and the doping semiconductor layer.

[0024] In a fourth aspect of the present application, there is provided a solar cell including a semiconductor substrate having a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side, wherein the area of the smooth surface region is equal to or greater than the area of the textured surface region, a transparent conductive film located on the side having the smooth surface region and the textured surface region of the semiconductor substrate and only on the smooth surface region, and grid lines located in at least a part of the region on the opposite side of the transparent conductive film from the semiconductor substrate.

[0025] Optionally, the solar cell further includes a doped semiconductor layer located between the semiconductor substrate and the transparent conductive film.

[0026] Optionally, the solar cell further includes an intrinsic semiconductor layer located between the semiconductor substrate and the doped semiconductor layer.

Advantages of the Invention

[0027] The technical solution of the present application can achieve the following beneficial effects. 1. In the present application, the semiconductor substrate is processed such that at least one surface of the semiconductor substrate includes a smooth surface region and a textured surface region adjacent to the smooth surface region. The textured surface region can provide an excellent light trapping effect, and the smooth surface of the smooth surface region is advantageous for the uniform deposition of other material layers in this region. Thereby, better material film layer uniformity can be obtained, which is advantageous for improving the photoelectric conversion efficiency and the battery efficiency. 2. This invention is advantageous in reducing defects in the semiconductor substrate by forming a protective layer on the surface of the semiconductor substrate and moving impurity ions in the semiconductor substrate to the protective layer by diffusion annealing. Subsequently, by using a cover layer to thicken the first region of the protective layer, impurity ions from the semiconductor substrate can continue to diffuse into the first region of the protective layer, which is advantageous in further reducing defects in the region of the semiconductor substrate corresponding to the first region of the protective layer. Subsequently, when etching and removing the second region, at least a portion of the thickness of the first region of the protective layer can be left, ensuring that the region of the semiconductor substrate corresponding to the second region of the protective layer forms a textured surface region during the textured processing, and the first region of the protective layer can be prevented from etching the corresponding region of the semiconductor substrate. Subsequently, when the first region of the protective layer is etched and removed, the region of the semiconductor substrate corresponding to the first region of the protective layer forms a smooth surface region with a flat surface, and because the concentration of impurity ions in the smooth surface region of the semiconductor substrate is low, the defect density of the semiconductor substrate is low. 3. The cover layer used in this application is made of a high-temperature resistant quartz material, is low-cost, can be reused after cleaning, and protects the semiconductor substrate during the diffusion annealing process, thereby reducing the risk of silicon wafer damage. 4. In the solar cell according to the present invention, both the transparent conductive film and the grid lines are located only in the smooth surface region. Because the surface of the smooth surface region is smooth, it is advantageous for uniform deposition of the transparent conductive film and grid lines in the smooth surface region. The flat, smooth surface region is advantageous for sufficient contact between the transparent conductive film and the grid lines and for reducing series resistance, while the textured surface region can provide an excellent light trapping effect. The solar cell according to the present invention can achieve both a light trapping effect and low series resistance, which is advantageous for improving the photoelectric conversion efficiency of the solar cell.

[0028] To more clearly describe specific embodiments of the present application or technical solutions in the prior art, the following briefly describes the drawings that are necessary for describing specific embodiments or the prior art. However, the drawings in the following description represent only some embodiments of the present application, and it is clear that those skilled in the art can obtain other drawings based on these without expending any creative effort. [Brief explanation of the drawing]

[0029] [Figure 1] This is an illustrative flowchart showing how a smooth surface region and a textured surface region are formed on one side of a semiconductor substrate according to an embodiment of the present application. [Figure 2] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 3] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 4] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 5] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 6] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 7] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 8] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 9] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 10] This is a schematic diagram of the structure of a semiconductor substrate during the processing process according to an embodiment of the present application. [Figure 11] This is a schematic diagram of the structure of the cover layer according to the present invention. [Figure 12] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 13] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 14] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 15] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 16] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 17] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 18] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Figure 19] This is a schematic diagram of the structure during the manufacturing process of a solar cell according to the present invention. [Modes for carrying out the invention]

[0030] The technical solutions of the present application will be described clearly and completely below with reference to the drawings, but it will be clear that the embodiments described are only some, and not all, embodiments of the present application. All other embodiments obtained by a person skilled in the art without creative work based on the embodiments of the present application are within the scope of protection of the present application.

[0031] Furthermore, in the description of this application, the directions or positional relationships indicated by terms such as "up," "down," "left," and "right" are based on the directions or positional relationships shown in the drawings and are merely for the purpose of facilitating and simplifying the description of this application. They do not indicate or imply that the device or element must necessarily have a specific direction, or be composed of and operate in a specific direction, and therefore should not be understood as limiting this application. In addition, the terms "first" and "second" are used solely for explanatory purposes and should not be understood as indicating or implying relative importance.

[0032] Furthermore, the technical features of each embodiment of the present application described below may be combined with each other, as long as they do not contradict each other.

[0033] One or more embodiments of the present application provide a method for processing a semiconductor substrate, comprising the step of forming a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of the semiconductor substrate, wherein the area of ​​the smooth surface region is equal to or greater than the area of ​​the textured surface region.

[0034] This invention relates to processing a semiconductor substrate such that at least one side of the substrate includes a smooth surface region and a textured surface region adjacent to the smooth surface region. The textured surface region provides an excellent light trapping effect, and the smooth surface of the smooth surface region is advantageous for the uniform deposition of other material layers in that region, which is advantageous for improving photoelectric conversion efficiency and battery efficiency.

[0035] In one embodiment, the ratio of the area of ​​the smooth surface region to the area of ​​the textured surface region is 1:1 to 1.2:1. For example, the ratio of the area of ​​the smooth surface region to the area of ​​the textured surface region is 1:1, 1.12:1, 1.15:1, 1.17:1, or 1.2:1.

[0036] In one embodiment, the step of forming a smooth surface region and a textured surface region adjacent to the smooth surface region on any one surface of a semiconductor substrate is: Step S100 involves forming a protective layer on any one side of the semiconductor substrate, Step S200 is to install a patterned cover layer on the side of the protective layer opposite to the semiconductor substrate, wherein the cover layer has a hollow region, and the protective layer includes a first region located at the bottom of the hollow region and a second region shielded by the cover layer, Step S300 involves thickening the first region of the protective layer after installing the patterned cover layer, Step S400 involves thickening the first region of the protective layer, followed by removing the cover layer. Step S500 involves removing the cover layer, then etching and removing the second region of the protective layer while protecting the first region of the protective layer, Step S600 involves etching and removing the second region of the protective layer, and then performing a texture treatment on one side of the semiconductor substrate exposed from the protective layer, so that one side of the semiconductor substrate exposed from the protective layer forms a textured surface region. The method includes step S700, which involves etching and removing a first region of the protective layer after forming a textured surface region, so that a portion of one side surface of the semiconductor substrate forms a smooth surface region.

[0037] This invention is advantageous in reducing defects in a semiconductor substrate by forming a protective layer on the surface of the semiconductor substrate, thereby moving impurity ions within the semiconductor substrate to the protective layer. Subsequently, by using a cover layer to thicken the first region of the protective layer, impurity ions from the semiconductor substrate can continue to diffuse into the first region of the protective layer, which is advantageous in further reducing defects in the region of the semiconductor substrate corresponding to the first region of the protective layer. Subsequently, when etching and removing the second region, at least a portion of the thickness of the first region of the protective layer can be left, so that during the textured processing, the region of the semiconductor substrate corresponding to the second region of the protective layer forms a textured surface region, and the first region of the protective layer can be prevented from etching the corresponding region of the semiconductor substrate. Subsequently, when the first region of the protective layer is etched and removed, the region of the semiconductor substrate corresponding to the first region of the protective layer forms a smooth surface region, and because the concentration of impurity ions in the smooth surface region of the semiconductor substrate is low, the defect density of the semiconductor substrate is low.

[0038] In one embodiment of the present application, the hollow region includes at least a plurality of spaced-apart strip-shaped openings, the strip-shaped openings being parallel to each other. The hollow region can then be used to manufacture a main grid and form a structure without sub-grid electrodes.

[0039] In one embodiment, the step of forming a protective layer on any one side of a semiconductor substrate includes the steps of coating the entire surface of any one side of the semiconductor substrate with an undercoat and performing a diffusion annealing treatment on the undercoat so that the undercoat and one side surface of the semiconductor substrate react to form an ion-doped protective layer and move impurities in the semiconductor substrate to the protective layer.

[0040] To make it easier to understand, by performing diffusion annealing on the underlying film, impurity ions in the semiconductor substrate diffuse into the protective layer more quickly, allowing the reaction to be more complete.

[0041] In one embodiment, the step of thickening a first region of the protective layer includes the steps of coating the surface of the first region with a surface film using a cover layer as a mask, and increasing the thickness of the first region by performing a diffusion annealing treatment on the surface film.

[0042] To understand this, the cover layer can limit the coating position and area of ​​the surface film, and cover layers with different shapes and structures are used depending on the specific application scenario. Embodiments of this application do not specifically limit the shape or structure of the cover layer.

[0043] In one embodiment, the cover layer comprises a quartz material. Embodiments of the present application are not specifically limited to this, as long as the cover layer does not melt or deform under high-temperature conditions.

[0044] In one embodiment, the undercoat and surface film are liquid source films. In other embodiments, the undercoat and surface film may be formed by gas-phase deposition.

[0045] In one embodiment, the undercoat and surface film are phosphorus-containing liquid source films, and the phosphorus concentration of the surface film is greater than that of the undercoat.

[0046] To understand this, the protective layer has a sparse structure, the surface film can penetrate the protective layer made up of the underlying film, and come into contact with and react with the surface of the semiconductor substrate. Furthermore, the phosphorus concentration of the surface film is greater than that of the underlying film, which is advantageous for the phosphorus elements in the surface film to diffuse into the protective layer made up of the underlying film, and the protective layer made up of the underlying film can continue to react with the semiconductor substrate.

[0047] In one embodiment, the diffusion annealing treatment time for the surface film is longer than the diffusion annealing treatment time for the undercoat film.

[0048] In one embodiment, the diffusion annealing temperature of the surface film is higher than the diffusion annealing temperature of the undercoat film.

[0049] In one embodiment, the parameters for both the step of etching and removing a first region of the protective layer and the step of etching and removing a second region of the protective layer are as follows: the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution, and aqueous solvent; the concentration of the hydrofluoric acid aqueous solution is 35% to 50% by mass; the concentration of the hydrochloric acid aqueous solution is 30% to 50% by mass; the volume ratio of the hydrofluoric acid aqueous solution is 1% to 4%; the volume ratio of the hydrochloric acid aqueous solution is 1% to 3%; and the etching time is 100 s to 300 s.

[0050] In one or more embodiments of the present application, the step of forming a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of a semiconductor substrate includes the step of forming a first smooth surface region and a first textured surface region adjacent to the first smooth surface region on one side of the semiconductor substrate, wherein the area of ​​the first smooth surface region is equal to or greater than the area of ​​the first textured surface region, and / or the step of forming a second smooth surface region and a second textured surface region adjacent to the second smooth surface region on the other side of the semiconductor substrate, wherein the area of ​​the second smooth surface region is equal to or greater than the area of ​​the second textured surface region. The semiconductor substrate processing method of the present application will be described in detail below, with an example of forming a first smooth surface region and a first textured surface region on one side of the semiconductor substrate and a second smooth surface region and a second textured surface region on the other side.

[0051] The semiconductor substrate processing process will be explained in detail below with reference to Figures 2 to 10.

[0052] Figure 2 shows an untreated semiconductor substrate 100 according to an embodiment of the present invention.

[0053] The semiconductor substrate 100 is made of single-crystal silicon. In other embodiments, the semiconductor substrate is made of germanium or other semiconductor materials such as silicon-germanium. The semiconductor substrate may be made of yet another semiconductor material.

[0054] In this embodiment, the conductivity type of the semiconductor substrate 100 is N-type, and the semiconductor substrate is used in the manufacture of a solar cell.

[0055] Referring to Figure 3, a first protective layer is formed on one side of the semiconductor substrate 100.

[0056] Specifically, a first undercoat is coated over the entire surface of one side of the semiconductor substrate 100, and a first diffusion annealing treatment is performed so that the first undercoat reacts with the one side of the semiconductor substrate to form an ion-doped first protective layer, thereby moving impurities within the semiconductor substrate to the first protective layer.

[0057] Specifically, the first underlayer is a liquid source film. In one embodiment, the first underlayer is a phosphorus-containing liquid source film.

[0058] Specifically, the first diffusion annealing process is a high-temperature annealing process. The semiconductor substrate 100 coated with the first undercoat is placed in an oven or hot stage and baked to allow the phosphorus in the first undercoat to diffuse sufficiently into the semiconductor substrate 100 and react with impurities in the semiconductor substrate 100 to form a first protective layer 210 having a sparse structure. The baking temperature is 650°C to 900°C, for example, 650°C, 700°C, 800°C, 850°C, or 900°C, and the baking time is 120s to 1200s, for example, 120s, 150s, 200s, 250s, 300s, 350s, 400s, 450s, 500s, 600s, 700s, 800s, 900s, 950s, 1000s, 1050s, 1100s, 1150s, or 1200s.

[0059] Referring to Figure 4, a second protective layer is formed on the other side of the semiconductor substrate 100.

[0060] Specifically, the second undercoat is coated over the entire other side of the semiconductor substrate 100, and a third diffusion annealing treatment is performed to react the second undercoat with the other side of the semiconductor substrate, thereby forming an ion-doped second protective layer and moving impurities within the semiconductor substrate to the second protective layer.

[0061] Specifically, the second underlayer is a liquid source film, and is the same as or different from the first underlayer. In one embodiment, the second underlayer and the first underlayer are the same.

[0062] Specifically, the third diffusion annealing treatment is a high-temperature annealing process. To ensure understanding, the process method and effects of the third diffusion annealing treatment are basically the same as those of the first diffusion annealing treatment and will not be explained again here.

[0063] Referring to Figure 5, a patterned first cover layer is placed on the side of the first protective layer 210 opposite to the semiconductor substrate 100, the first cover layer has a first hollow region with a plurality of parallel strip-shaped openings, the first protective layer 210 includes a first region 310 located at the bottom of the first hollow region and a second region shielded by the first cover layer, and the first region 310 of the first protective layer 210 is thickened after the patterned first cover layer is placed.

[0064] Specifically, referring to Figure 11, the first cover layer includes a first cover body 810 and a first hollow region 820. In this embodiment, the first hollow region 820 is a hollow structure with a plurality of strip-shaped openings uniformly distributed in the first cover body 810. In other embodiments, the first hollow region 820 may have other shapes, for example, the first hollow region is a mesh-like hollow structure regularly arranged in the first cover body 810, in which case it is suitable for forming a grid electrode structure including main grids and sub-grids, where the plurality of main grids are parallel to each other, the main grids are set parallel to each other, the main grids and sub-grids are set vertically or at any angle, and the width and height of the sub-grids are smaller than the width and height of the main grids, respectively. Furthermore, the first hollow region may be a hollow structure irregularly arranged in the first cover body 810 or a hollow structure having a different shape, in which case it is suitable for forming grid lines having a special pattern. The shape and layout of the first hollow region 820 will match the shape and layout of the grid lines of the final solar cell, and the type of hollow structure of the cover layer used is not limited herein.

[0065] Specifically, the thickness of the first region 310 is increased by coating the surface of the first region 310 with a first surface film and performing a second diffusion annealing treatment, thereby making the first surface film part of the first protective layer 210. The components of the first surface film and the first undercoat film are the same. The phosphorus concentration of the first surface film is higher than that of the first undercoat film, which is advantageous for the phosphorus in the first surface film to sufficiently permeate the first protective layer 210 and react with impurities in the semiconductor substrate 100.

[0066] In the above embodiment, because the first protective layer 210 has a sparse structure, the first surface film can penetrate directly into the surface of the semiconductor substrate 100 through the first region 310 of the first protective layer 210 and diffuse into the semiconductor substrate 100, reacting with impurities in the semiconductor substrate 100. Furthermore, the phosphorus inside the first region 310 of the first protective layer 210 still participates in the gettering reaction, providing a high concentration of the first surface film and replenishing phosphorus in the first region 310 of the first protective layer 210. This allows the first region 310 of the first protective layer 210 to continue reacting with impurities in the semiconductor substrate 100, ultimately increasing the thickness of the first region 310 of the first protective layer 210. As can be understood, a portion of the first surface film can penetrate into the second region of the first protective layer 210, but the amount of the first surface film that penetrates into that region is very small and negligible compared to the first region 310 of the first protective layer 210.

[0067] Specifically, the second diffusion annealing process is a high-temperature annealing process. The process method for the second diffusion annealing process is the same as that for the first diffusion annealing process, differing only in temperature and time. The temperature of the second diffusion annealing process is higher than that of the first diffusion annealing process, and the duration of the second diffusion annealing process is longer than that of the first diffusion annealing process. This is advantageous for the phosphorus in the first surface film to sufficiently permeate the first protective layer 210 and react with impurities in the semiconductor substrate 100, and also improves the reaction activity between the phosphorus in the first surface film and the phosphorus in the first protective layer 210 and the impurities in the semiconductor substrate.

[0068] In one embodiment, the first cover layer is made of quartz material. The quartz first cover layer is inexpensive, can be reused after cleaning, and can act as a buffer during the second diffusion annealing process to protect the semiconductor substrate 100 and reduce the risk of silicon wafer damage.

[0069] Specifically, after forming the first protective layer, the first cover layer is placed on the side of the first protective layer opposite to the semiconductor substrate 100. During the subsequent second diffusion annealing process, the semiconductor substrate 100 can be protected because the first cover layer is present.

[0070] Referring to Figure 6, a patterned second cover layer is placed on the side of the second protective layer 220 opposite to the semiconductor substrate 100, the second cover layer has a second hollow region, and the second protective layer 220 includes a third region 320 located at the bottom of the second hollow region and a fourth region shielded by the second cover layer, and the third region 320 of the second protective layer 220 is thickened after the patterned second cover layer is placed.

[0071] Specifically, depending on the particular application scenario, the second cover layer may be the same as or different from the first cover layer. The shape and layout of the second hollow region of the second cover layer will match the shape and layout of the grid lines of the final formed solar cell.

[0072] Specifically, the second surface layer film is coated onto the surface of the third region 320, and a fourth diffusion annealing treatment is performed to make the second surface layer film part of the second protective layer, thereby increasing its thickness and forming the third region 320. The components of the second surface layer film and the second underlayer film are the same. The phosphorus concentration of the second surface layer film is higher than that of the second underlayer film, which is advantageous for the phosphorus in the second surface layer film to sufficiently permeate the second protective layer 220 and react with impurities in the semiconductor substrate 100.

[0073] In the above embodiment, because the second protective layer 220 has a sparse structure, the second surface film can penetrate directly into the surface of the semiconductor substrate 100 through the third region 320 of the second protective layer 220 and diffuse into the semiconductor substrate 100, reacting with impurities in the semiconductor substrate 100. Furthermore, the phosphorus inside the third region 320 of the second protective layer 220 still participates in the gettering reaction, providing a high concentration of the second surface film and replenishing phosphorus in the third region 320 of the second protective layer 220. This allows the third region 320 of the second protective layer 220 to continue reacting with impurities in the semiconductor substrate 100, ultimately increasing the thickness of the third region 320 of the second protective layer 220. As can be understood, a portion of the second surface film can penetrate into the fourth region of the second protective layer 220, but the amount of the second surface film that penetrates into that region is very small and negligible compared to the third region 320 of the second protective layer 220.

[0074] Specifically, the fourth diffusion annealing process is a high-temperature annealing process. The process method for the fourth diffusion annealing process is the same as that for the third diffusion annealing process, differing only in temperature and time. The temperature of the fourth diffusion annealing process is higher than that of the third diffusion annealing process, and the duration of the fourth diffusion annealing process is longer than that of the third diffusion annealing process. This is advantageous for the phosphorus in the second surface film to sufficiently permeate the second protective layer 220 and react with impurities in the semiconductor substrate 100, and it can also improve the reaction activity between the phosphorus in the second surface film and the phosphorus in the second protective layer 220 and the impurities in the semiconductor substrate.

[0075] In one embodiment, the second cover layer is made of quartz material. The quartz second cover layer is inexpensive, can be reused after cleaning, and can also act as a buffer during the fourth diffusion annealing process, protecting the semiconductor substrate 100 and reducing the risk of silicon wafer damage.

[0076] In this embodiment, after the second diffusion annealing treatment, the second cover layer is placed on the surface of the second protective layer, and during the fourth diffusion annealing treatment, the second cover layer is not removed and continues to act as a buffer, protecting the semiconductor layer substrate 100 and reducing the risk of silicon wafer damage.

[0077] Referring to Figure 7, the first region 310 of the first protective layer 210 is thickened, then the first cover layer is removed, and after the first cover layer is removed, the second region of the first protective layer 210 is etched and removed, with the first region 310 of the first protective layer 210 serving as protection.

[0078] Specifically, for etching and removing the second region of the first protective layer 210, the etching solution used is a mixture of hydrofluoric acid aqueous solution, hydrochloric acid aqueous solution, and aqueous solvent, with the concentration of the hydrofluoric acid aqueous solution being 35% to 50% by mass, the concentration of the hydrochloric acid aqueous solution being 30% to 50% by mass, the volume ratio of the hydrofluoric acid aqueous solution being 1% to 4%, the volume ratio of the hydrochloric acid aqueous solution being 1% to 3%, and the etching time being 100 s to 300 s. For example, for etching and removing the second region of the first protective layer 210, the etching solution is a 48% hydrofluoric acid aqueous solution and a 37% hydrochloric acid aqueous solution, with the volume ratio of the hydrofluoric acid aqueous solution being 3%, the volume ratio of the hydrochloric acid aqueous solution being 2%, and the etching time being 150 s.

[0079] Referring to Figure 8, the third region 320 of the second protective layer 220 is thickened, then the second cover layer is removed, and after the second cover layer is removed, the fourth region of the second protective layer 220 is removed, with the third region 320 of the second protective layer 220 being used as protection.

[0080] Specifically, the parameters for etching and removing the fourth region of the second protective layer 220 are the same as the parameters for etching and removing the second region of the first protective layer 210, and will not be explained again here.

[0081] In this embodiment, the second region of the first protective layer 210 of the semiconductor substrate 100 is etched and removed, and then the fourth region of the second protective layer 220 of the semiconductor substrate 100 is etched and removed. In another embodiment, the fourth region of the second protective layer 220 of the semiconductor substrate 100 is etched and removed, and then the second region of the first protective layer 210 of the semiconductor substrate 100 is etched and removed. In yet another embodiment, the second region of the first protective layer 210 and the fourth region of the second protective layer 220 of the semiconductor substrate 100 are etched and removed simultaneously.

[0082] Referring to Figure 9, a texture processing is performed on the semiconductor substrate 100 exposed from the first region 310 to form a first textured surface region 111 of the semiconductor substrate 100, and a texture processing is performed on the semiconductor substrate 100 exposed from the third region 320 to form a second textured surface region 121 of the semiconductor substrate 100. In one embodiment, first a texture processing is performed on the semiconductor substrate 100 exposed from the first region 310 to form a first textured surface region 111 of the semiconductor substrate 100, and then a texture processing is performed on the semiconductor substrate 100 exposed from the third region 320 to form a second textured surface region 121 of the semiconductor substrate 100. In another embodiment, first a texture processing is performed on the semiconductor substrate 100 exposed from the third region 320 to form a second textured surface region 121 of the semiconductor substrate 100, and then a texture processing is performed on the semiconductor substrate 100 exposed from the first region 310 to form a first textured surface region 111 of the semiconductor substrate 100. In yet another embodiment, the steps of performing a texture processing on the semiconductor substrate 100 exposed from the first region 310 to form a first textured surface region 111 of the semiconductor substrate 100 and performing a texture processing on the semiconductor substrate 100 exposed from the third region 320 to form a second textured surface region 121 of the semiconductor substrate 100 are performed simultaneously.

[0083] Specifically, the texturing process includes treatment with a texturing agent. In one embodiment, the texturing agent is a 2% to 5% aqueous potassium hydroxide solution, for example, a 2% aqueous potassium hydroxide solution, a 3% aqueous potassium hydroxide solution, a 4% aqueous potassium hydroxide solution, or a 5% aqueous potassium hydroxide solution, the texturing process time is 150s to 300s, for example, 150s, 180s, 200s, 250s, 280s, or 300s, and the temperature is 60°C to 70°C, for example, 60°C, 62°C, 65°C, 67°C, or 70°C.

[0084] Referring to Figure 10, the first region 310 is etched and removed to form the first smooth surface region 112 of the semiconductor substrate 100, and the third region 320 is etched and removed to form the second smooth surface region 122 of the semiconductor substrate 100. In one embodiment, after etching and removing the first region 310 to form the first smooth surface region 112 of the semiconductor substrate 100, the third region 320 is etched and removed to form the second smooth surface region 122 of the semiconductor substrate 100. In another embodiment, after etching and removing the third region 320 to form the second smooth surface region 122 of the semiconductor substrate 100, the first region 310 is etched and removed to form the first smooth surface region 112 of the semiconductor substrate 100. In yet another embodiment, the steps of etching and removing the first region 310 to form the first smooth surface region 112 of the semiconductor substrate 100 and etching and removing the third region 320 to form the second smooth surface region 122 of the semiconductor substrate 100 are performed simultaneously.

[0085] Specifically, the first region 310 and the third region 320 are etched and removed. The parameters for etching and removing the first region 310 and the third region 320 are the same as the parameters for etching and removing the second region of the first protective layer 210 and the parameters for etching and removing the fourth region of the second protective layer 220, and will not be explained again here.

[0086] In another embodiment of the present invention, one side of the semiconductor substrate 100 is processed to form a first smooth surface region 112 and a first textured surface region 111 adjacent to the first smooth surface region 112, and then the other side of the semiconductor substrate 100 is processed to form a second smooth surface region 122 and a second textured surface region 121 adjacent to the second smooth surface region 122.

[0087] Specifically, a first region 310 and a second region of the first protective layer 210 are formed on one side of the semiconductor substrate 100. The first region 310 of the first protective layer 210 is used for protection, and the second region of the first protective layer 210 is etched and removed. A textured treatment is performed on the semiconductor substrate 100 exposed from the first region 310 of the first protective layer 210 to form a first textured surface region 111. The first region 310 of the first protective layer 210 is then etched and removed to form a first smooth surface region 112. Subsequently, the third region 320 and fourth region of the second protective layer 220 are formed on the other side of the semiconductor substrate 100. The third region 320 of the second protective layer 220 is used for protection, the fourth region of the second protective layer 220 is etched and removed, and the semiconductor substrate 100 exposed from the third region 320 of the second protective layer 220 is subjected to a textured treatment to form a second textured surface region 121. The third region 320 of the second protective layer 220 is etched and removed to form a second smooth surface region 122.

[0088] One or more embodiments of the present application further provide a semiconductor substrate having a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side, wherein the area of ​​the smooth surface region is equal to or greater than the area of ​​the textured surface region.

[0089] Referring to Figure 10, in one embodiment, one side of the semiconductor substrate 100 has a first smooth surface region 112 and a first textured surface region 111 adjacent to the first smooth surface region 112, and / or the other side of the semiconductor substrate 100 has a second smooth surface region 122 and a second textured surface region 121 adjacent to the second smooth surface region 122.

[0090] To ensure understanding, the semiconductor substrate 100 in the above embodiment is manufactured by the semiconductor substrate processing method described above, and has similar beneficial effects, which will not be repeated here.

[0091] In one embodiment, the area of ​​the first smooth surface region 112 is greater than or equal to the area of ​​the first textured surface region 111, for example, the ratio of the area of ​​the first smooth surface region 112 to the area of ​​the first textured surface region 111 is 1:1 to 1.2:1, for example, the ratio of the area of ​​the first smooth surface region 112 to the area of ​​the first textured surface region 111 is 1:1, 1.05:1, 1.1:1, 1.15:1, or 1.2:1, and / or, the area of ​​the second smooth surface region 122 is greater than or equal to the area of ​​the second textured surface region 121, for example, the ratio of the area of ​​the second smooth surface region 122 to the area of ​​the second textured surface region 121 is 1:1 to 1.2:1, for example, the ratio of the area of ​​the second smooth surface region 122 to the area of ​​the second textured surface region 121 is 1:1, 1.05:1, 1.1:1, 1.15:1, or 1.2:1.

[0092] To make it easier to understand, in a solar cell, the first smooth surface region 112 or the second smooth surface region 122 corresponds to the transparent conductive film and grid lines, and by increasing the area of ​​the first smooth surface region 112 or the second smooth surface region 122, the above functional layers can make sufficient contact, which is advantageous for reducing the series resistance of the solar cell, increasing the current, reducing unnecessary power loss, and improving the photoelectric conversion performance of the solar cell. Furthermore, both the first smooth surface region 112 and the second smooth surface region 122 have flat surfaces, which is advantageous for the uniform deposition of other material layers in these regions, and the concentration of impurity ions inside the first smooth surface region 112 and the second smooth surface region 122 is low, which reduces the probability that photogenerated carriers will be trapped in defects on the semiconductor substrate, and is advantageous for further improving the photoelectric conversion efficiency.

[0093] One or more embodiments of the present application further provide a method for manufacturing a solar cell, comprising the steps of: providing a semiconductor substrate; processing the semiconductor substrate using the semiconductor substrate processing method such that at least one side of the semiconductor substrate has a smooth surface region and a textured surface region adjacent to the smooth surface region; forming a transparent conductive film located only in the smooth surface region on the side of the semiconductor substrate having the smooth surface region and the textured surface region; and forming grid lines in at least a portion of the transparent conductive film on the side opposite to the semiconductor substrate.

[0094] Specifically, the transparent conductive film is placed opposite the smooth surface region, meaning that the orthographic projection area of ​​the transparent conductive film in the textured surface region is 0.

[0095] In one embodiment, the method for manufacturing a solar cell further includes the step of forming a doping semiconductor layer located between the semiconductor substrate and the transparent conductive film on the side of the semiconductor substrate having a smooth surface region and a textured surface region, before forming the transparent conductive film.

[0096] In one embodiment, before forming the doped semiconductor layer, an intrinsic semiconductor layer is formed on the side of the semiconductor substrate having a smooth surface region and a textured surface region, positioned between the semiconductor substrate and the doped semiconductor layer.

[0097] In the solar cell according to the present invention, both the transparent conductive film and the grid lines are located only in the smooth surface region. Because the surface of the smooth surface region is smooth, it is advantageous for uniform deposition of the transparent conductive film and grid lines in the smooth surface region. The flat, smooth surface region is advantageous for sufficient contact between the transparent conductive film and the grid lines and for reducing series resistance, while the textured surface region can provide an excellent light trapping effect. The solar cell according to the present invention can achieve both a light trapping effect and low series resistance, which is advantageous for improving the photoelectric conversion efficiency of the solar cell.

[0098] To make it easier to understand, a smooth surface region and a textured surface region may be formed on only one side of the semiconductor substrate, and a solar cell may be manufactured, or a smooth surface region and a textured surface region may be formed on both sides of the semiconductor substrate, and a solar cell may be manufactured. Below, the method for manufacturing a solar cell of the present invention will be described in detail, using the example of simultaneously forming solar cells on both sides of the semiconductor substrate.

[0099] The manufacturing process of solar cells will be explained in detail below, with reference to Figures 12 to 19.

[0100] Referring to Figures 12 and 13, a first intrinsic semiconductor layer 410 is formed on the side of the semiconductor substrate 101 having a first smooth surface region and a first textured surface region, and a second intrinsic semiconductor layer 420 is formed on the side of the semiconductor substrate 101 having a second smooth surface region and a second textured surface region. For example, the first intrinsic semiconductor layer 410 and the second intrinsic semiconductor layer 420 contain amorphous silicon or microcrystalline silicon and play a passivation role.

[0101] As can be understood, because the first smooth surface region has a flat surface, the first intrinsic semiconductor layer 410 can be uniformly deposited in the first smooth surface region, thereby improving the uniformity of the first intrinsic semiconductor layer 410, further improving the passivation effect, and ultimately achieving the objective of improving the photoelectric conversion efficiency of the solar cell.

[0102] Referring to Figures 14 and 15, the first doping semiconductor layer 510 is formed on the side of the first intrinsic semiconductor layer 410 opposite to the semiconductor substrate 101, and the second doping semiconductor layer 520 is formed on the side of the second intrinsic semiconductor layer 420 opposite to the semiconductor substrate 101. For example, the first doping semiconductor layer 510 is N-type doped amorphous silicon or N-type doped microcrystalline silicon, and the second doping semiconductor layer 520 is P-type doped amorphous silicon or P-type doped microcrystalline silicon, or vice versa.

[0103] Referring to Figures 16 and 17, a first transparent conductive film 610 is formed in a portion of the first doping semiconductor layer 510 opposite to the first smooth surface region, and a second transparent conductive film 620 is formed in a portion of the second doping semiconductor layer 520 opposite to the second. For example, the first transparent conductive film 610 and the second transparent conductive film 620 are indium-doped tin oxide.

[0104] Specifically, the first transparent conductive film 610 is placed opposite the first smooth surface region, and the orthographic area of ​​the first transparent conductive film 610 in the first textured surface region is 0. The second transparent conductive film 620 is placed opposite the second smooth surface region, and the orthographic area of ​​the second transparent conductive film 620 in the second textured surface region is 0.

[0105] Referring to Figures 18 and 19, the first grid line 710 is formed on the side of the first transparent conductive film 610 opposite to the first doping semiconductor layer 510, and the second grid line 720 is formed on the side of the second transparent conductive film 620 opposite to the second doping semiconductor layer 520. Exemplarily, the first grid line 710 and the second grid line 720 are made of silver.

[0106] In another embodiment, the method for manufacturing a solar cell includes the steps of sequentially forming a first intrinsic semiconductor layer 410, a first doping semiconductor layer 510, a first transparent conductive film 610, and a first grid line 710 on the side of the semiconductor substrate 101 having a first smooth surface region 112 and a first textured surface region 111, and then sequentially forming a second intrinsic semiconductor layer 420, a second doping semiconductor layer 520, a second transparent conductive film 620, and a second grid line 720 on the side of the semiconductor substrate 101 having a second smooth surface region 122 and a second textured surface region 121.

[0107] Specifically, the method for manufacturing a solar cell in this embodiment differs from the method for manufacturing a solar cell in the above embodiment only in the order in which each functional layer is formed on both sides of the semiconductor substrate 101; all other parameters are the same and will not be described again here.

[0108] One or more embodiments of the present application further provide a solar cell comprising: a semiconductor substrate having a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side, wherein the area of ​​the smooth surface region is equal to or greater than the area of ​​the textured surface region; a transparent conductive film located on the side of the semiconductor substrate having the smooth surface region and the textured surface region, and located only in the smooth surface region; and grid lines located in at least a portion of the transparent conductive film on the side opposite to the semiconductor substrate, and located only in the transparent conductive film.

[0109] In one embodiment, the semiconductor substrate includes a first smooth surface region located on one side of the semiconductor substrate and a first textured surface region adjacent to the first smooth surface region, and / or a second smooth surface region located on the other side of the semiconductor substrate and a second textured surface region adjacent to the second smooth surface region, and a doping semiconductor layer located between the semiconductor substrate and a transparent conductive film. Optionally, the solar cell further includes an intrinsic semiconductor layer located between the semiconductor substrate and the doping semiconductor layer. The above structure is a key structure for generating photogenerated carriers.

[0110] In one specific example of the present application, a solar cell comprises a first intrinsic semiconductor layer and a second intrinsic semiconductor layer, wherein the first intrinsic semiconductor layer is located between a first doping semiconductor layer and the side of the semiconductor substrate having a first smooth surface region and a first textured surface region, and the second intrinsic semiconductor layer is located between a second doping semiconductor layer and the side of the semiconductor substrate having a second smooth surface region and a second textured surface region, and a first doping semiconductor layer and a second doping semiconductor layer, wherein the first doping semiconductor layer is located on the opposite side of the semiconductor substrate from the first intrinsic semiconductor layer, and the second doping semiconductor layer is located on the opposite side of the semiconductor substrate from the second intrinsic semiconductor layer, and a first transparent conductive film and a second transparent conductive film, wherein the first transparent conductive film is the first doping semiconductor layer A first transparent conductive film and a second transparent conductive film are located on the opposite side of the first intrinsic semiconductor layer of the body layer, and the first transparent conductive film is located only in the first smooth surface region, and the second transparent conductive film is located on the opposite side of the second intrinsic semiconductor layer of the second doping semiconductor layer, and the second transparent conductive film is located only in the second smooth surface region; and a first grid line and a second grid line are included, wherein the first grid line is located on the opposite side of the first doping semiconductor layer of the first transparent conductive film, the first grid line is located only in the first smooth surface region, and the area of ​​the first grid line is less than or equal to the area of ​​the first transparent conductive film, and the second grid line is located on the opposite side of the second doping semiconductor layer of the second transparent conductive film, the second grid line is located only in the second smooth surface region, and the area of ​​the second grid line is less than or equal to the area of ​​the second transparent conductive film.

[0111] To ensure understanding, the solar cell of the above embodiment includes the semiconductor substrate obtained in the above embodiment, and therefore can achieve the same beneficial effects as the above semiconductor substrate, which will not be repeated here.

[0112] The solar cell of this application will be described below with reference to specific embodiment test examples and comparative examples.

[0113] Test example: A semiconductor substrate is provided, the semiconductor substrate material being single-crystal silicon with a thickness of 100 μm to 180 μm, one side of the semiconductor substrate having a first smooth surface region and a first textured surface region adjacent to the first smooth surface region, and the other side of the semiconductor substrate having a second smooth surface region and a second textured surface region adjacent to the second smooth surface region. A first intrinsic semiconductor layer is formed on the side of the semiconductor substrate having the first smooth surface region and the first textured surface region, the material of the first intrinsic semiconductor layer being amorphous silicon with a thickness of 5 nm to 10 nm, and a second intrinsic semiconductor layer is formed on the side of the semiconductor substrate having the second smooth surface region and the second textured surface region, the material of the second intrinsic semiconductor layer being amorphous silicon with a thickness of 5 nm to 10 nm. A first doped semiconductor layer was formed on a first intrinsic semiconductor layer, the material of the first doped semiconductor layer being N-type doped amorphous silicon with a thickness of 5 nm to 15 nm, and a second doped semiconductor layer was formed on a second intrinsic semiconductor layer, the material of the second doped semiconductor layer being P-type doped amorphous silicon with a thickness of 5 nm to 15 nm. A first transparent conductive film was formed on the first doped semiconductor layer, the material of the first transparent conductive film being ITO with a thickness of 80 nm to 100 nm, the first transparent conductive film being placed opposite a first smooth surface region and having an orthographic projection area of ​​0 in the first texture surface region, and a second transparent conductive film was formed on the second doped semiconductor layer, the material of the second transparent conductive film being ITO with a thickness of 80 nm to 100 nm, the second transparent conductive film being placed opposite a second smooth surface region and having an orthographic projection area of ​​0 in the second texture surface region. A first grid line was formed by depositing silver paste onto a first transparent conductive film, with a thickness of 10 μm to 20 μm. A second grid line was formed by depositing silver paste onto a second transparent conductive film, with a thickness of 10 μm to 20 μm.

[0114] Comparative example: Aside from both sides of the semiconductor substrate being textured surfaces, the manufacturing method and parameters of this comparative example are the same as those of the test example.

[0115] Photoelectric conversion performance conversion tests were performed on the solar cells manufactured using the above test examples and comparative examples, and the data in Table 1 was obtained. [Table 1]

[0116] Here, I SC : Short-circuit current, U OC :Open circuit voltage, FF:Curve factor, E ta : Photoelectric conversion efficiency, R ser : Series resistor, R shunt :Parallel resistance.

[0117] From the data in Table 1, it was found that compared to the solar cell using a conventional semiconductor substrate with a double-sided textured surface in the comparative example, the curve factor of the solar cell in the test example was 0.84% ​​higher, the short-circuit current increased by 5 mA, the open-circuit voltage increased by 1 mV, the series resistance decreased by 0.56 mΩ, and the photoelectric conversion efficiency increased by 0.2604%.

[0118] As will be clear from this, in the test example, a semiconductor substrate having a smooth surface region and a textured surface region is used, and the first grid line and the first transparent conductive film are positioned opposite the first smooth surface region and designed not to cover the first textured surface region, and the second grid line and the second transparent conductive film are positioned opposite the second smooth surface region and designed not to cover the second textured surface region. As a result, the deposition of each functional layer becomes more uniform, which is advantageous for reducing series resistance and increasing open-circuit voltage, and the contact resistance between the polished region (smooth surface region) and the metallized electrode becomes lower, and the series resistance (R ser This also significantly reduces the short-circuit current, which is advantageous for improving the extraction efficiency of photogenerated carriers by the first and second grid lines. Even if the area of ​​the texture surface region is reduced, the short-circuit current can still be increased, ultimately improving the photoelectric conversion efficiency of the solar cell and increasing battery efficiency.

[0119] Clearly, the above-described test examples are merely illustrative for clarity and do not limit the embodiments. Those skilled in the art can make various other forms of changes or modifications based on the above description. It is not necessary, nor is it possible, to cover all embodiments here. And any obvious changes or modifications derived in this manner are also within the scope of protection of the present invention. [Explanation of Symbols]

[0120] 100 semiconductor substrates 101 Semiconductor substrate 210 1st protective layer 220 Second protective layer 310 1st area 320 Third area 111 First Texture Surface Region 112 1st smooth surface area 121 Second Texture Surface Region 122 2nd smooth surface area 410 First intrinsic semiconductor layer 420 Second intrinsic semiconductor layer 510 First doping semiconductor layer 520 Second doping semiconductor layer 610 First transparent conductive film 620 Second transparent conductive film 710 First grid line 720 Second grid line 810 First Cover Body 820 1st hollow area

Claims

1. A method for processing semiconductor substrates, The step includes forming a smooth surface region and a textured surface region adjacent to the smooth surface region on at least one side of the semiconductor substrate, The area of ​​the smooth surface region is greater than or equal to the area of ​​the textured surface region. The step of forming a smooth surface region and a textured surface region adjacent to the smooth surface region on any one surface of the semiconductor substrate is: The steps include forming a protective layer on any one side of the semiconductor substrate, and the step of forming a protective layer on any one side of the semiconductor substrate comprising coating the entire surface of any one side of the semiconductor substrate with a base film, and performing a diffusion annealing treatment on the base film so that the base film and the surface of the semiconductor substrate react to form an ion-doped protective layer, thereby moving impurities in the semiconductor substrate to the protective layer. A step of installing a patterned cover layer on the side of the protective layer opposite to the semiconductor substrate, wherein the cover layer has a hollow region, and the protective layer includes a first region located at the bottom of the hollow region and a second region shielded by the cover layer. A step of using the cover layer to thicken the first region of the protective layer, The steps include: thickening the first region of the protective layer, and then removing the cover layer; The steps include: removing the first region of the protective layer after removing the cover layer, and etching and removing the second region of the protective layer, The steps include: performing a textured treatment on one surface of the semiconductor substrate exposed from the protective layer after removing the second region, so that one surface of the semiconductor substrate exposed from the protective layer forms the textured surface region; A method for processing a semiconductor substrate, comprising the step of, after forming the textured surface region, etching and removing the first region corresponding to the protective layer so that a part of one side surface of the semiconductor substrate forms the smooth surface region.

2. The semiconductor substrate processing method according to claim 1, characterized in that the ratio of the area of ​​the smooth surface region to the area of ​​the textured surface region is 1:1 to 1.2:

1.

3. The aforementioned cover layer contains quartz material, The method for processing a semiconductor substrate according to claim 1, characterized in that the underlayer film and the surface layer film are liquid source films.

4. The semiconductor substrate processing method according to claim 1, characterized in that the step of thickening the first region of the protective layer includes the steps of coating the surface of the first region with a surface film using the cover layer as a mask, and increasing the thickness of the first region by performing a diffusion annealing treatment on the surface film so that the surface film becomes part of the protective layer.

5. The semiconductor substrate processing method according to claim 1, characterized in that the underlayer film and the surface film are phosphorus-containing liquid source films, and the phosphorus concentration of the surface film is greater than the phosphorus concentration of the underlayer film.

6. The diffusion annealing treatment time for the surface film is longer than the diffusion annealing treatment time for the undercoat film. The method for processing a semiconductor substrate according to claim 1, characterized in that the temperature of the diffusion annealing treatment of the surface layer film is higher than the temperature of the diffusion annealing treatment of the underlayer film.

7. The steps include providing a semiconductor substrate and The steps include processing the semiconductor substrate using the semiconductor substrate processing method described in any one of claims 1 to 6, such that at least one side of the semiconductor substrate has a smooth surface region and a textured surface region adjacent to the smooth surface region, The steps include forming a transparent conductive film located only in the smooth surface region on the side of the semiconductor substrate having the smooth surface region and the textured surface region, A method for manufacturing a solar cell, comprising the step of forming grid lines in at least a portion of the transparent conductive film on the side opposite to the semiconductor substrate.

8. The method for manufacturing a solar cell according to claim 7, further comprising the step of forming a doping semiconductor layer located between the semiconductor substrate and the transparent conductive film on the side of the semiconductor substrate having the smooth surface region and the textured surface region, before forming the transparent conductive film.

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