Power semiconductor device protection circuit

Abstract

To provide a protective circuit for power semiconductor elements that can suppress the enlargement of semiconductor elements constituting the soft shutdown circuit even in a configuration in which a soft shutdown circuit and a precharge power supply share the same output terminal.SOLUTION: In a protective circuit 23, comparators 16 and 17 detect a short circuit between the collector and emitter of IGBT1 and an overcurrent flowing between the collector and emitter as abnormal, respectively. When the logic 10S determines that the abnormality has been detected, the soft shutdown section 7 operates to draw the charge charged on the gate of IGBT1 at a slower rate than during normal off. In the drive IC2, the terminal 6 connecting the gate of IGBT1 to the soft shutdown section 7 and the precharge power supply 8 is common, and logic 10 stops the supply of voltage by the precharge power supply 8 before the operation to lower the gate potential by the soft shutdown section 7 is started.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit for protecting a power semiconductor device that constitutes a power conversion device.

Background Art

[0002] As a configuration for protecting a power semiconductor device, there is, for example, what is disclosed in Patent Documents 1 and 2. In Patent Document 1, when a short circuit occurs in the power semiconductor device, a gate potential change circuit is provided that can quickly cut off the current flowing through the power semiconductor device even when charge is being injected into the gate by the feedback capacitance. In Patent Document 2, a soft cut-off circuit for turning off the power semiconductor device at a slower speed than normal and a precharge power supply as a gate potential control circuit share the output terminal of the IC.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the configuration of Patent Document 1, with the provision of a gate potential change circuit, separate terminals are required for it, resulting in a problem that the circuit becomes larger. Also, in Patent Document 2, since the output terminal is shared by the soft cut-off circuit and the precharge power supply, during the soft cut-off operation, the current for discharging the charge stored in the gate capacitance of the power semiconductor device and the current flowing from the precharge power supply into the gate of the power semiconductor device are superimposed. Therefore, there is a problem that the semiconductor device constituting the soft cut-off circuit has to be made larger.

[0005] The present invention has been made in view of the above circumstances, and its purpose is to provide a power semiconductor element protection circuit that can suppress the increase in size of the semiconductor elements constituting the soft cutoff circuit, even in a configuration in which the output terminals of the soft cutoff circuit and the precharge power supply are common. [Means for solving the problem]

[0006] According to the power semiconductor element protection circuit described in claim 1, the current abnormality detection unit (16, 17) detects either a short circuit between the conductive terminals of the power semiconductor element (1), or an overcurrent flowing between the conductive terminals, or both, as an abnormality. A power semiconductor element is a semiconductor element that is capable of switching relatively large amounts of power, such as those that constitute a power conversion circuit like an inverter. When the soft interruption unit (7, 10S) determines that an abnormality has been detected, it operates to withdraw the charge stored in the conductive control terminals of the power semiconductor element at a slower rate than when it is normally off.

[0007] The precharge power supply (8) suppresses the voltage rise at the conduction control terminal to protect against the short circuit. The terminal (6) connecting the conduction control terminal, the soft interruption unit, and the precharge power supply is common, and the power supply control unit (10) stops supplying voltage from the precharge power supply before the operation by the soft interruption unit to reduce the voltage at the conduction control terminal is completed.

[0008] With this configuration, the output voltage from the precharge power supply stops by the time the soft interruption unit detects an abnormality and completes the operation of extracting charge from the conduction control terminal of the power semiconductor element. Therefore, the increase in the power capacity of the circuit elements constituting the charge extraction path can be suppressed to some extent in the soft interruption unit. Consequently, it becomes possible to suppress the increase in the cost of constructing the protection circuit. Furthermore, according to the power semiconductor element protection circuit described in claim 1, when the power control unit stops the voltage output from the precharge power supply, it cuts off the tail current supplied to the differential input of the operational amplifier (12) that constitutes the precharge power supply. Therefore, it becomes possible to stop the operation of the precharge power supply simply by adding a configuration to cut off the tail current inside the operational amplifier.

[0009] According to the power semiconductor element protection circuit described in claim 2, the soft cutoff unit (10S) waits for a determination waiting period to elapse between the time the current abnormality detection unit detects an abnormality and the time it makes the determination. This prevents false determinations caused, for example, by noise superimposed on the terminal that receives input from the current abnormality detection unit. Furthermore, since the power control unit stops the output of the voltage from the precharge power supply before the soft cutoff unit starts operating, the increase in the power capacity of the circuit elements constituting the soft cutoff unit can be suppressed to a greater extent. [Brief explanation of the drawing]

[0011] [Figure 1] In the first embodiment, a diagram showing the configuration of the IGBT protection circuit. [Figure 2] Circuit diagram showing the internal configuration of the operational amplifier that makes up the precharge power supply. [Figure 3] A flowchart illustrating the logic's processing steps. [Figure 4] This diagram shows the voltage waveforms of each component when the precharge power supply output is not stopped and when it is stopped. [Figure 5] This figure shows an operational image corresponding to the case in the upper section of Figure 4. [Figure 6] This figure shows an operational image corresponding to the case in the lower section of Figure 4. [Figure 7] In the second embodiment, a diagram showing the configuration of the IGBT protection circuit. [Figure 8] In the third embodiment, a diagram showing the configuration of the IGBT protection circuit. [Modes for carrying out the invention]

[0012] (First Embodiment) This embodiment is based on the configuration disclosed in Patent Document 2, and the configuration other than the gist of the embodiment is the same as that disclosed in Figure 38 of Patent Document 2, for example. As shown in Figure 1, the IGBT (Insulated Gate Bipolar Transistor) 1, which is a power semiconductor element, constitutes a power conversion device such as an inverter, and is connected in series with another IGBT (not shown) between the power supply and ground. The IGBT 1 is provided with a sense emitter, and a current sensing resistor 1a is connected between the sense emitter and the emitter.

[0013] The gate, which is the conduction control terminal of IGBT1, is driven by the drive IC2, but the configuration for driving IGBT1 on and off in normal control is not shown in the diagram. The gate of IGBT1 is connected to ground via a series circuit of diode 3 and capacitor 4. The common connection point of diode 3 and capacitor 4 is connected to terminal 6 of drive IC2 via resistor element 5.

[0014] Inside the drive IC2, terminal 6 is connected to a soft-shutdown unit 7 and the output terminal of the pre-charge power supply 8. The soft-shutdown unit 7 includes an N-channel MOSFET 9 connected between terminal 6 and ground, and the gate of the FET 9 is driven by the logic 10 via the driver 11. The resistance value of the resistor element 5 is set to be greater than the resistance value of the gate resistor provided in the discharge path when the IGBT1 is turned off under normal control.

[0015] The pre-charge power supply 8 includes an operational amplifier 12. The output terminal of the operational amplifier 12 is connected to terminal 6 and also to ground via resistors 13 and 14. The common connection point of resistors 13 and 14 is connected to the non-inverting input terminal of the operational amplifier 12, and a reference voltage Vref is applied to the inverting input terminal. The operation of the pre-charge power supply 8 is controlled by logic 10 controlling the operational amplifier 12. Logic 10 corresponds to the power supply control unit.

[0016] The sense emitter of IGBT1 is connected to terminal 15 of drive IC2. Inside drive IC2, the non-inverting input terminals of comparator 16 for overcurrent detection and comparator 17 for short-circuit detection are connected to terminal 15, and the inverting input terminals of each are given the threshold voltages Vth_oc and Vth_s for overcurrent detection and short-circuit detection. The output terminals of each of comparators 16 and 17 are connected to the input terminals of logic 10. Note that "short circuit" refers to a short circuit between the collector and emitter, which are the conducting terminals of IGBT1. Comparators 16 and 17 correspond to the current abnormality detection section.

[0017] As shown in FIG. 2, the differential input section of operational amplifier 12 includes a mirror pair of P-channel MOSFETs 18a and 18b whose sources are connected to the power supply. The drains of N-channel MOSFETs 19a and 19b are connected to the drains of FETs 18a and 18b, respectively. N-channel MOSFET 20b is connected between the sources of FETs 19a and 19b and the ground. FET 20b forms a mirror pair with N-channel MOSFET 20a, and FET 20a is connected in series between the power supply and the ground together with reference current source 21. An N-channel MOSFET 22 is connected between the gates of FETs 20a and 20b and the ground, and the gate of FET 22 is controlled by logic 10.

[0018] If logic 10 turns off FET 22, a tail current flows through the differential input section via the mirror pair of FETs 20a and 20b. When logic 10 turns on FET 22, the supply of the tail current to the differential input section is stopped, causing the operation of operational amplifier 12 to stop, the operation of precharge power supply 8 to stop, and the voltage output to stop. The above constitutes protection circuit 23.

[0019] Next, the operation of this embodiment will be described. As shown in FIG. 3, when the comparator 16 or 17 detects the occurrence of an overcurrent or a short circuit (S2a, S2b) from the normal state where no abnormality occurs (S1), the logic 10 sets a determination waiting time corresponding to each detection (S3a, S3b). The determination waiting time is set to avoid misjudgment due to, for example, noise being superimposed on the terminals of the logic 10 to which the signals output by the comparators 16 and 17 are input. The determination waiting time for a short circuit is set shorter than the determination waiting time for an overcurrent.

[0020] Before the respective determination waiting times elapse, if the detection states by the comparators 16 and 17 are resolved, the normal state is entered. On the other hand, if the detection states by the comparators 16 and 17 are maintained even after the respective determination waiting times have elapsed, the logic 10 determines that an overcurrent or a short circuit has been detected (S4a, S4b). Then, the logic 10 first stops the operation of the precharge power supply 8 (S5), and then turns off the FET 9 of the soft cut-off section 7 shown as the "soft cut-off element" in the figure (S6).

[0021] The upper part of FIG. 4 assumes a case where the logic 10 does not control the operation of the precharge power supply 8. It is assumed that a short circuit occurs between the collector and emitter of the IGBT 1 while the drive IC 2 drives the gate of the IGBT 1 to a high level. When the gate voltage rises through the Miller capacitance of the IGBT 1 due to the occurrence of the short circuit and exceeds the threshold voltage Vth_s, the output signal of the comparator 17 becomes high level. Thereby, when the logic 10 detects the occurrence of a short circuit, it waits for the elapse of the determination time Ts1 for short circuit determination. If the state of detecting the occurrence of a short circuit continues even when the determination time Ts1 has elapsed, the logic 10 determines that a short circuit has occurred. Then, the logic 10 turns on the FET 9 of the soft cut-off section 7. The drain potential of the FET 9 is a potential that has decreased by the forward voltage of the diode 3 from the gate potential of the IGBT 1, but when the FET 9 is turned on, it changes to a low level. The logic 10 also constitutes a soft cut-off section, and after waiting for the elapse of the above determination time Ts1, the configuration of the functional part that determines the occurrence of a short circuit is denoted as 10S.

[0022] In contrast, the lower part of Figure 4 shows the operation of this embodiment, where the judgment time Ts2 for short-circuit detection is set to be shorter than the judgment time Ts1 mentioned above. Logic 10 stops the operation of the pre-charge power supply 8 when the judgment time Ts2 has elapsed (S4b → S5). After that, it turns on the FET9 of the soft interruption unit 7 (S6). Although not reflected in the flowchart shown in Figure 3, when the discharge of the gate of IGBT1 is complete and the gate potential becomes low level, logic 10 restarts the operation of the pre-charge power supply 8.

[0023] Figures 5 and 6 conceptually illustrate the operations corresponding to the upper and lower sections of Figure 4, respectively. In the case shown in the upper section of Figure 4, when the FET9 of the soft interruption unit 7 is turned on, the current (1) discharged from the gate of the IGBT1 and the current (2) supplied from the precharge power supply 8 merge and flow through the FET9. In contrast, in the case shown in the lower section of Figure 4, when the FET9 of the soft interruption unit 7 is turned on, the precharge power supply 8 has stopped operating, so only current (1) flows through the FET9.

[0024] As described above, according to this embodiment, in the protection circuit 23, comparators 16 and 17 detect a short circuit between the collector and emitter of IGBT1 and an overcurrent flowing between the collector and emitter as abnormalities, respectively. When logic 10S determines that the abnormality has been detected, the soft interruption unit 7 operates to withdraw the charge stored in the gate of IGBT1 at a slower rate than during normal off-mode operation. In the drive IC 2, terminal 6 connecting the gate of IGBT1 to the soft interruption unit 7 and the precharge power supply 8 is shared, and logic 10 stops the output of the voltage from the precharge power supply 8 before the soft interruption unit 7 starts the operation to lower the gate potential.

[0025] With this configuration, the voltage output from the precharge power supply 8 stops before the logic 10S detects an abnormality and the soft interruption unit 7 starts the operation to extract charge from the gate. Therefore, the increase in the power capacity of the FET 9 that constitutes the charge extraction path in the soft interruption unit 7 can be suppressed. Consequently, it becomes possible to suppress the increase in the cost of constructing the protection circuit 23.

[0026] Furthermore, logic 10S waits for a judgment waiting period to elapse between the time comparators 16 and 17 detect an abnormality and the time it makes a judgment. This prevents misjudgment caused by, for example, noise superimposed on the terminals that accept input from comparators 16 and 17. Also, since logic 10 stops the output of the voltage from the precharge power supply before the soft cutoff section starts operating, the increase in the power capacity of the circuit elements constituting the soft cutoff section can be suppressed to a greater extent.

[0027] Furthermore, when logic 10 stops supplying voltage from the precharge power supply 8, it cuts off the tail current supplied to the differential input of the operational amplifier 12 that constitutes the precharge power supply 8. Therefore, by simply adding an FET 22 inside the operational amplifier 12 to cut off the tail current, it becomes possible to stop the operation of the precharge power supply 8.

[0028] (Second Embodiment) In the following description, parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted, while the differences are described. As shown in Figure 7, the protection circuit 24 of the second embodiment replaces the precharge power supply 8 that constitutes the protection circuit 23 with a precharge power supply 25. The precharge power supply 25 includes an operational amplifier 26 that replaces the operational amplifier 12. The operational amplifier 26 has a normal configuration, like the operational amplifier 12, without an internal FET 22. A normally closed switch 27 is placed between the output terminal of the operational amplifier 26 and the terminal 6 of the drive IC 2. When the logic 10 stops supplying voltage by the precharge power supply 25, it switches the switch 27 from on to off.

[0029] (Third embodiment) As shown in Figure 8, the third embodiment differs from the first embodiment in the external configuration of the drive IC 2. A resistor 31 is connected in parallel to the capacitor 4. A series circuit of a resistor 32 and a diode 33 is connected between the anode of the diode 3 and terminal 6, and a series circuit of a diode 34 and a resistor 35 is connected between terminal 6 and the cathode of the diode 3.

[0030] (Other embodiments) The timing for stopping the operation of the precharge power supply 8 is not necessarily limited to before turning on the FET 9 of the soft interruption unit 7; it is sufficient to stop it after turning it on and before the discharge of the charge stored in the gate of the IGBT 1 is complete. The power semiconductor element is not limited to IGBTs; power MOSFETs and other types can also be used. Short-circuit and overcurrent detection may be performed by only one of them. The output signals from comparators 16 and 17 may be directly input to the soft cutoff unit 7, allowing the soft cutoff unit 7 to perform the judgment waiting period and subsequent judgment in the event of an abnormality. The configuration for stopping the supply of tail current in the differential input section is not limited to that shown in Figure 2.

[0031] This case includes the invention described in the claims, as well as the following inventions: [1] A current abnormality detection unit (16, 17) detects either a short circuit between the conductive terminals of the power semiconductor element (1), or an overcurrent flowing between the conductive terminals, or both, as an abnormality. Upon detecting the aforementioned abnormality, a soft interruption unit (7, 10S) operates to withdraw the charge stored in the conduction control terminal of the power semiconductor element at a slower rate than during normal off-mode operation. To protect against the aforementioned short circuit, the system includes a precharge power supply (8) that suppresses the voltage rise at the conduction control terminal, The terminal (6) connecting the aforementioned conductivity control terminal, the soft cutoff unit, and the precharge power supply is common to all terminals. A protection circuit for a power semiconductor element further comprising a power control unit (10) that stops supplying voltage from the precharge power supply before the operation of reducing the voltage of the conduction control terminal by the soft interruption unit is completed. [2] The soft interruption unit (10S) waits for the determination waiting time to elapse between the current abnormality detection unit detecting an abnormality and the determination being made. The power supply control unit stops supplying the voltage before the soft cutoff unit starts operating.[1] A power semiconductor element protection circuit as described above. [3] The aforementioned precharge power supply includes an operational amplifier (12), The power supply control unit is a power semiconductor element protection circuit according to [1] or [2], which interrupts the tail current supplied to the differential input of the operational amplifier when it stops supplying the voltage. [4] The system includes a normally closed switch (27) positioned between the precharge power supply and the conduction control terminal, The power supply control unit opens the switch when stopping the supply of the voltage, a protection circuit for the power semiconductor element as described in [1] or [2]. [5] The circuit comprises a series circuit of a diode (3) and a capacitor (4) connected between the conduction control terminal and the low-potential reference point. The output terminal of the pre-charge power supply is connected to the common connection point of the diode and the capacitor, and is a protection circuit for the power semiconductor element described in any one of [1] to [4].

[0032] This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]

[0033] In the diagram, 1 is an IGBT, 2 is a driver IC, 3 is a diode, 4 is a capacitor, 6 is a terminal, 7 is a soft cutoff section, 8 is a precharge power supply, 9 is an N-channel MOSFET, 10 is a logic circuit, 12 is an operational amplifier, 16 and 17 are comparators, 18a and 18b are MOSFETs, and 23 is a protection circuit.

Claims

1. A current abnormality detection unit (16, 17) detects either a short circuit between the conductive terminals of the power semiconductor element (1), or an overcurrent flowing between the conductive terminals, or both, as an abnormality. Upon detecting the aforementioned abnormality, a soft interruption unit (7, 10S) operates to withdraw the charge stored in the conduction control terminal of the power semiconductor element at a slower rate than during normal off-mode operation. To protect against the aforementioned short circuit, the system includes a precharge power supply (8) that suppresses the voltage rise at the conduction control terminal, The terminal (6) connecting the aforementioned conductivity control terminal, the soft cutoff unit, and the precharge power supply is common to all terminals. The power control unit (10) further comprises stopping the supply of voltage by the precharge power supply before the operation of reducing the voltage of the conduction control terminal by the soft interruption unit is completed, The aforementioned precharge power supply includes an operational amplifier (12), The power supply control unit includes a power semiconductor element protection circuit that cuts off the tail current supplied to the differential input of the operational amplifier when the voltage supply is stopped.

2. The soft interruption unit (10S) waits for the determination waiting time to elapse between the time the current abnormality detection unit detects an abnormality and the determination is made. The power supply control unit stops supplying the voltage before the soft cutoff unit starts operating, a power semiconductor element protection circuit according to claim 1.

3. The circuit comprises a series circuit of a diode (3) and a capacitor (4) connected between the conduction control terminal and the low-potential reference point. The power semiconductor element protection circuit according to claim 1 or 2, wherein the output terminal of the precharge power supply is connected to the common connection point of the diode and the capacitor.

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