Display device and electronic instrument

Abstract

The purpose of the present invention is to provide a display device that reduces the transmission amount of image data and maintains a high display quality.　This display device (DP) has a display unit (DIS), a light-emitting unit (SHB), and a light-receiving unit (SJB). The display unit has a first display region (ALP) and a first circuit region that overlap with each other. In addition, the first display region has a plurality of first display pixels, and the first circuit region has a first driver circuit (DRV). The first driver circuit is electrically connected to the plurality of first display pixels via a plurality of first wires extending in the first display region. The light-emitting unit has a function of emitting first light. The light-receiving unit has a function of receiving second light reflected by irradiating a subject with the first light and a function of generating information on the basis of the second light. The first driver circuit has a function of either one of: transmitting a plurality of image signals to the plurality of first wires in accordance with the information; or transmitting the same image signal to two or more wires continuously adjacent to each other, among the plurality of first wires.

Description

Display device and electronic device

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, or an inspection method thereof.

[0003] In recent years, improvements have been made in various aspects in display devices included in electronic devices for XR (Extended Reality or Cross Reality), such as VR (Virtual Reality) and AR (Augmented Reality), mobile phones such as smartphones, tablet information terminals, notebook PCs (personal computers), etc. For example, display devices have been developed that have higher screen resolution, improved color reproducibility (NTSC ratio), smaller drive circuits, and reduced power consumption.

[0004] In particular, in electronic devices for XR, by increasing the pixel density (resolution) and color reproducibility of the display device, the displayed image becomes clearer and the sense of reality can be enhanced. Furthermore, Patent Document 1 discloses a display device with a high number of pixels and high resolution that is equipped with a light-emitting device including an organic EL.

[0005] Furthermore, eye tracking technology has been attracting attention in XR electronic devices. Eye tracking is a method of measuring the movement of a user's eyeballs and tracking the user's gaze. Eye tracking is expected to be applied to, for example, sports, education, marketing, hazard detection, health management, and user interfaces for electronic devices. Therefore, various eye tracking methods have been proposed in recent years. For example, Patent Literature 2 discloses a technology that improves on the corneal reflex method (PCCR method), which irradiates light onto the cornea and calculates eyeball movement from images of the light reflection point and the pupil.

[0006] Furthermore, display devices that have new functions added by providing circuits other than display pixel circuits in the display area of ​​the display device are also being developed. For example, Patent Document 3 discloses a display device that includes an imaging pixel circuit in addition to the display pixel circuit in the display area, and a method for detecting an eye or the area around the eye as an image using the display device.

[0007] International Publication No. WO 2019 / 220278 U.S. Patent Application Publication No. 2006 / 0238707 International Publication No. WO 2019 / 243955

[0008] As the resolution of a display device increases, the number of pixels included in the display device also increases. To display an image on the display device, image data must be written to each pixel included in the display device, and therefore the number of image signals including image data input to the display device also increases. In other words, the greater the number of pixels in the display device, the greater the transmission volume of image data input to the display device, which may increase the load on the interface that inputs image data to the display device.

[0009] An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a display device that can reduce the amount of image data transmitted.An object of one embodiment of the present invention is to provide an electronic device that includes the above-described display device.An object of one embodiment of the present invention is to provide a novel display device or a novel electronic device.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems.

[0011] (1) One aspect of the present invention is a display device including a display unit, a light-emitting unit, a light-receiving unit, and a controller. The display unit includes a first display region and a first circuit region, and the first display region is located in a region overlapping the first circuit region. The first display region includes a plurality of first display pixels, and the first circuit region includes a first driver circuit. The first driver circuit is electrically connected to a plurality of first wirings extending in the first display region, and each of the plurality of first display pixels is electrically connected to the plurality of first wirings. The light-receiving unit is electrically connected to the controller, and the controller is electrically connected to the first driver circuit. The light-emitting unit has a function of emitting first light. The light-receiving unit has a function of detecting second light reflected by an object when the first light is irradiated onto the object, and a function of generating information based on the second light and transmitting the information to the controller. The controller has a function of generating a first signal based on the information and transmitting the first signal to the first driver circuit. In addition, the first driver circuit has a function of either transmitting a plurality of image signals to each of the plurality of first wirings, or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of first wirings, in response to the first signal.

[0012] (2) Alternatively, according to one aspect of the present invention, in the above-described (1), the display unit may have a second display region and a second circuit region. In particular, the second display region is preferably located in a region overlapping the second circuit region. The second display region preferably has a plurality of second display pixels, and the second circuit region preferably has a second driver circuit. The second driver circuit is preferably electrically connected to a plurality of second wirings extending into the second display region, each of the plurality of second display pixels being electrically connected to the plurality of second wirings, and the control unit is preferably electrically connected to the second driver circuit. The control unit preferably has a function of generating a second signal based on information and transmitting the second signal to the second driver circuit. The second driver circuit preferably has a function of either transmitting a plurality of image signals to each of the plurality of second wirings or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of second wirings, in response to the first signal. In addition, in the first display area, the number of first display pixels to which one image signal is written is different from the number of second display pixels to which one image signal transmitted to the second display area is written.

[0013] (3) Another embodiment of the present invention is a display device including a display unit, a light-emitting unit, a light-receiving unit, and a controller. The display unit includes a first display region and a first circuit region, and the first display region is located in a region overlapping the first circuit region. The first display region includes a plurality of first display pixels, and the first circuit region includes a first driver circuit. The first driver circuit is electrically connected to a plurality of first wirings extending in the first display region, and each of the plurality of first display pixels is electrically connected to the plurality of first wirings. The light-receiving unit is electrically connected to the controller, and the controller is electrically connected to the first driver circuit. The light-emitting unit has a function of emitting first light. The light-receiving unit has a function of detecting second light reflected by an object when the first light is irradiated with the object, and a function of generating information based on the second light and transmitting the information to the controller. The controller has a function of generating a first signal based on the information and transmitting the first signal to the first driver circuit. The first driver circuit also has a function of transmitting an image signal to each of the plurality of first wirings at a first frame frequency according to the first signal.

[0014] (4) Alternatively, in one aspect of the present invention, in the above-described (3), the display unit may have a second display region and a second circuit region. In particular, the second display region is preferably located in a region overlapping the second circuit region. The second display region preferably has a plurality of second display pixels, and the second circuit region preferably has a second driver circuit. The second driver circuit is preferably electrically connected to a plurality of second wirings extending into the second display region, each of the plurality of second display pixels being electrically connected to the plurality of second wirings, and the control unit is preferably electrically connected to the second driver circuit. The control unit preferably has a function of generating a second signal based on information and transmitting the second signal to the second driver circuit, and the second driver circuit preferably has a function of transmitting an image signal to each of the plurality of second wirings at a second frame frequency corresponding to the second signal. Note that the first frame frequency is different from the second frame frequency.

[0015] (5) Alternatively, according to one embodiment of the present invention, in any one of (1) to (4), the first driver circuit may include a transistor having a channel formation region containing silicon, and the first display pixel may include a transistor having a channel formation region containing metal oxide.

[0016] (6) Alternatively, in one aspect of the present invention, in any one of the above (1) to (5), the first display pixel may have a light-emitting device including an organic EL material.

[0017] (7) Alternatively, in one aspect of the present invention, in any one of (1) to (6) above, the first light and the second light may be visible light, or the first light and the second light may be infrared light.

[0018] (8) Another embodiment of the present invention is an electronic device including the display device according to any one of (1) to (7) above and a housing. The housing has a shape that allows it to be worn on a user's head.

[0019] According to one embodiment of the present invention, a display device with high display quality can be provided. Alternatively, according to one embodiment of the present invention, a display device capable of reducing the amount of image data transmitted can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the above-described display device can be provided. Alternatively, according to one embodiment of the present invention, a novel display device or a novel electronic device can be provided.

[0020] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0021] FIGS. 1A and 1B are block diagrams showing an example of the configuration of a display device. FIGS. 2A to 2C are schematic cross-sectional views showing an example of the configuration of a display unit of a display device. FIG. 3A is a schematic plan view showing an example of the display unit of a display device, and FIG. 3B is a schematic plan view showing an example of a drive circuit region of the display device. FIGS. 4A and 4B are schematic plan views showing an example of the configuration of the display unit of a display device. FIG. 5 is a block diagram showing an example of a circuit included in the display device. FIG. 6 is a block diagram showing an example of a circuit included in the display device. FIG. 7 is a block diagram showing an example of a display region included in the display device. FIGS. 8A and 8B are circuit diagrams showing an example of a circuit included in the display device. FIG. 9 is a circuit diagram showing an example of a circuit included in the display device. FIGS. 10A and 10B are diagrams showing an example of a display surface of a display device divided into multiple regions. FIG. 11A is a diagram showing an example of a plane of the display unit of a display device divided into multiple regions, and FIG. 11B is a diagram showing an example of a plane of the display unit of a display device. 12A and 12C are diagrams showing a portion of the plane of the display unit of a display device, and FIGS. 12B and 12D are graphs showing an example of the transmission amount of image data sent to each display area of ​​the display device. FIGS. 13A and 13B are diagrams showing an example of dividing the display surface of a display device into multiple regions. FIG. 14A is a diagram showing an example of dividing the plane of the display unit of a display device into multiple regions, and FIG. 14B is a diagram showing an example of the plane of the display unit of a display device. FIG. 15 is a block diagram showing an example of the configuration of a display unit. FIG. 16 is a graph showing an example of the amount of image data input to the display device. FIG. 17 is a diagram showing an example of the timing at which image data is input to each circuit of the display device. FIGS. 18A and 18B are diagrams showing an example of an electronic device incorporating a display device. FIG. 19A is a diagram showing an example of an electronic device incorporating a display device, and FIGS. 19B and 19C are diagrams explaining an example of the optical path between the display unit of the electronic device and the user's eye. FIG. 20 is a schematic cross-sectional view showing an example of the configuration of a display device. 21A to 21C are cross-sectional views showing a partial region of a configuration example of a display device, Fig. 22 is a cross-sectional view showing a configuration example of a display device, and Fig. 23 is a cross-sectional view showing a configuration example of a display device.FIG. 24 is a cross-sectional view showing a configuration example of a display device. FIG. 25 is a cross-sectional view showing a configuration example of a display device. FIG. 26 is a cross-sectional view showing a configuration example of a display device. FIG. 27 is a cross-sectional view showing a configuration example of a display device. FIG. 28 is a cross-sectional view showing a configuration example of a display device. FIGS. 29A to 29F are diagrams showing a configuration example of a light-emitting device. FIGS. 30A to 30C are diagrams showing a configuration example of a light-emitting device. FIG. 31A is a circuit diagram showing a configuration example of a pixel circuit included in a display device, and FIG. 31B is a perspective view showing a configuration example of a pixel circuit included in a display device. FIGS. 32A to 32D are circuit diagrams showing a configuration example of a pixel circuit included in a display device. FIGS. 33A to 33D are circuit diagrams showing a configuration example of a pixel circuit included in a display device. FIGS. 34A to 34G are plan views showing an example of a pixel. FIGS. 35A to 35F are plan views showing an example of a pixel. FIGS. 36A to 36H are plan views showing an example of a pixel. 37A to 37D are plan views showing an example of a pixel. FIG. 38A is a schematic plan view showing an example of a transistor configuration, and FIGS. 38B and 38C are schematic cross-sectional views showing an example of a transistor configuration. FIGS. 39A and 39B are views showing an example of a display module configuration. FIGS. 40A to 40F are views showing an example of an electronic device configuration. FIGS. 41A to 41D are views showing an example of an electronic device configuration. FIGS. 42A to 42C are views showing an example of an electronic device configuration. FIGS. 43A to 43E are views showing an example of an electronic device configuration. FIG. 44 is a cross-sectional photograph of a display device used in the examples. FIG. 45 is a graph showing the gate-source voltage-drain current characteristics of a transistor provided in the display device used in the examples. FIG. 46 is a schematic perspective view of the display device used in the examples. FIG. 47 is a photograph of an image displayed on the display device used in the examples. Fig. 48A is a block diagram showing the configuration of a display unit used in the example, and Fig. 48B is a diagram showing the display area of ​​the display unit used in the example. Fig. 49 is a graph showing the power consumption of the display device estimated in the example.

[0022] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (e.g., a transistor, a diode, and a photodiode), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are each an example of a semiconductor device. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device or may include a semiconductor device.

[0023] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0024] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, and a load) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.

[0025] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-analog conversion circuit, an analog-digital conversion circuit, and a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit such as a step-up circuit or a step-down circuit, or a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0026] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0027] This specification also deals with a circuit configuration in which multiple elements are electrically connected to wiring (a wiring that supplies a constant potential or a wiring that transmits a signal). For example, if X and a wiring are directly connected and Y and the wiring are directly connected, this specification may state that X and Y are directly electrically connected.

[0028] For example, it can be expressed as follows: "X, Y, the source (sometimes referred to as either the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y." Or, it can be expressed as follows: "The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to specify the order of connections in the circuit configuration, it is possible to distinguish between the source and drain of the transistor and determine the technical scope. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

[0029] Note that even when independent components are shown electrically connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0030] Furthermore, in this specification, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, a "resistance element" includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, terms such as "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0031] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, or a transistor gate capacitance. Terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitor element," "parasitic capacitance," or "gate capacitance." A "capacitance" (including a "capacitance" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in "capacitance" can be replaced with terms such as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Terms such as "one of a pair of terminals" and "the other of a pair of terminals" may be referred to as a first terminal or a second terminal, respectively. The capacitance value can be, for example, 0.05 fF to 10 pF. It can also be, for example, 1 pF to 10 μF.

[0032] Furthermore, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" may be interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of a transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification.

[0033] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Alternatively, when operating in the saturation region, the multi-gate structure can provide voltage-current characteristics with a flat slope, such that the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0034] Furthermore, in this specification, circuit elements such as a "light-emitting device" and a "light-receiving device" may have polarities referred to as an "anode" and a "cathode." In the case of a "light-emitting device," applying a forward bias (applying a positive potential relative to the "cathode" to the "anode") may cause the "light-emitting device" to emit light. In the case of a "light-receiving device," applying zero bias or a reverse bias (applying a negative potential relative to the "cathode" to the "anode") and irradiating the "light-receiving device" with light may generate a current between the "anode" and the "cathode." As described above, the "anode" and the "cathode" may be treated as input / output terminals in circuit elements such as a "light-emitting device" and a "light-receiving device." In this specification, the "anode" and the "cathode" in circuit elements such as a "light-emitting device" and a "light-receiving device" may be referred to as terminals (first terminal, second terminal, etc.). For example, one of the "anode" or the "cathode" may be referred to as a first terminal, and the other of the "anode" or the "cathode" may be referred to as a second terminal.

[0035] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is shown on a circuit diagram, this includes two or more resistors electrically connected in series. For example, when a single capacitor is shown on a circuit diagram, this includes two or more capacitors electrically connected in parallel. For example, when a single transistor is shown on a circuit diagram, this includes two or more transistors electrically connected in series, with the gates of the respective transistors electrically connected to each other. Similarly, when a single switch is shown on a circuit diagram, this includes two or more transistors, with the switch including two or more transistors electrically connected in series or parallel, and the gates of the respective transistors electrically connected to each other.

[0036] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region depending on the circuit configuration and device structure. A terminal or a wiring can also be referred to as a node.

[0037] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0038] Furthermore, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0039] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, or complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, or vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0040] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0041] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0042] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0043] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0044] Furthermore, in this specification, wiring electrically connecting components arranged in a matrix can extend in the row direction or the column direction. For example, when this specification describes that "wiring A extends in the row direction," wiring A may also extend in the column direction. Conversely, when this specification describes that "wiring A extends in the column direction," wiring A may also extend in the row direction. In other words, the direction in which wiring electrically connecting components arranged in a matrix extends is not limited to the directions described in this specification, and may be the row direction or the column direction.

[0045] Furthermore, in this specification and the like, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Or, in some cases or depending on the situation, the terms "film" and "layer" may not be used and may be replaced with other terms. For example, the terms "conductive layer" or "conductive film" may be changed to the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator."

[0046] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0047] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." Vice versa, the term "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, the term "signal" may be changed to the term "potential."

[0048] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0049] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0050] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. When the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0051] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals through which a current flows, in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0052] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0053] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls conduction and non-conduction.

[0054] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0055] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0056] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device preferably has one light-emitting unit between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers may be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light may be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers may be combined to produce a configuration in which the entire light-emitting device emits white light.

[0057] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0058] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0059] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0060] In this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0061] In addition, the content (or even a part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even a part of the content) described in that embodiment and one or more other content (or even a part of the content) described in another embodiment.

[0062] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0063] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0064] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0065] In addition, in the drawings of this specification, plan views may be used to explain the configuration of each embodiment. A plan view, for example, may be a view showing a configuration viewed from a direction perpendicular to a horizontal plane, or a view showing a horizontally cut surface (cut surface) of the configuration (either of these may be referred to as a plan view). Hidden lines (e.g., dashed lines) may be included in the plan view to indicate the relative positions of multiple elements included in the configuration or the overlapping relationship of the multiple elements. Note that in this specification, the term "plan view" may be interchangeable with the terms "projection view," "top view," or "bottom view." Depending on the situation, a plan view may refer to a cut surface (cut surface) of a configuration cut in a direction other than the horizontal direction, rather than a horizontally cut surface (cut surface).

[0066] In addition, in the drawings of this specification, cross-sectional views may be used to explain the configuration of each embodiment. A cross-sectional view, for example, is a view showing a surface of a configuration viewed from a direction perpendicular to a horizontal plane, or a view showing a surface (cut) of a configuration cut in a direction perpendicular to a horizontal plane (either of these may be referred to as a cross-sectional view). Note that in this specification, the term "cross-sectional view" may be replaced with the terms "front view" or "side view." Depending on the situation, a cross-sectional view may refer to a surface (cut) of a configuration cut in a direction other than the vertical direction, rather than a surface (cut) cut in the vertical direction.

[0067] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0068] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0069] Embodiment 1 In this embodiment, a display device according to one embodiment of the present invention will be described.

[0070] <Configuration Example of Display Device> FIG. 1A is a block diagram showing a configuration example of a display device DP according to one embodiment of the present invention.

[0071] The display device DP includes, for example, a display unit DIS, an image-capturing light-emitting unit SHB, an image-capturing light-receiving unit SJB, and a control unit CTL.

[0072] The display unit DIS also includes, for example, a pixel array ALP, a drive circuit region DRV, and an interface IF.

[0073] The pixel array ALP is electrically connected to a drive circuit region DRV, which is electrically connected to an interface IF and a control unit CTL, and the image-capturing light-receiving unit SJB is electrically connected to the control unit CTL.

[0074] The pixel array ALP has, for example, a plurality of display pixels (for example, display pixels PX[1,1] to PX[m,n] in FIG. 5, which will be described later).

[0075] The drive circuit region DRV has, as an example, a drive circuit for driving a plurality of display pixels included in the pixel array ALP. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0076] The interface IF has a function for inputting image data for displaying an image on the display device DP, which is output from a device located outside the display device DP, into the drive circuit region DRV. Examples of the external device include a non-volatile storage device such as a recording media player, a hard disk drive (HDD), and a solid state drive (SSD).

[0077] A GPU (Graphics Processing Unit) may be provided between the drive circuit region DRV and an external device. The GPU may be provided inside the display device DP or outside the display device DP. When the GPU is provided inside the display device DP, the GPU may be incorporated inside the interface IF.

[0078] As an example, the imaging light receiving unit SJB has a function of capturing an image of a subject. Therefore, the imaging light receiving unit SJB has a light receiving device such as a photoelectric conversion element (a pn-type or pin-type photodiode). In particular, when the display device DP is applied to an XR electronic device, the subject can be the eye of a user wearing the electronic device. That is, the imaging light receiving unit SJB has a function of capturing an image of the user's eye. Furthermore, the imaging light receiving unit SJB has a function of transmitting information about the captured image (e.g., current amount or potential) to the control unit CTL. As an example, the light receiving device of the imaging light receiving unit SJB generates an electric charge corresponding to the amount of light incident on the light receiving device, and the amount of current corresponding to the electric charge is transmitted to the control unit CTL.

[0079] The imaging light-emitting unit SHB functions as a light source for irradiating light onto a subject of the imaging light-receiving unit SJB, for example, and therefore includes a light-emitting device.

[0080] Furthermore, the light emitted by the imaging light-emitting unit SHB may be visible light or infrared light (sometimes referred to as IR). The light-receiving device included in each imaging light-receiving unit SJB can be determined according to the light emitted by the light-emitting device of the imaging light-emitting unit SHB. For example, if the light-emitting device of the imaging light-emitting unit SHB emits visible light, the light-receiving device may be a light-receiving device capable of receiving visible light. For example, if the light-emitting device of the imaging light-emitting unit SHB emits infrared light, the light-receiving device may be a light-receiving device capable of receiving infrared light.

[0081] For example, the control unit CTL has a function of performing image analysis on the image (user's eye) captured by the imaging light receiving unit SJB. Since the image contains one or more of the crystalline lens, pupil, cornea, macula, and fovea, performing the image analysis can determine which part of the pixel array ALP the user is looking at.

[0082] One example of a method for determining the direction of a user's gaze by image analysis is the PCCR method.

[0083] The control unit CTL also has a function of acquiring the area of ​​the pixel array ALP in front of the user's line of sight (which may be rephrased as "the area the user is looking at") or an address through the image analysis described above. The control unit CTL also has a function of generating a signal corresponding to the area of ​​the pixel array ALP in front of the user's line of sight or the address, and transmitting the signal to the drive circuit region DRV.

[0084] The circuit included in the drive circuit region DRV receives a signal sent from the control unit CTL and changes the method of writing image data to the plurality of display pixels included in the pixel array ALP according to the content of the signal (the user's line of sight). Specifically, the circuit included in the drive circuit region DRV changes the method of writing image data to the plurality of display pixels included in the pixel array ALP so as to improve the display quality in the area of ​​the pixel array ALP that is the user's line of sight.

[0085] Note that, in the display device DP of FIG. 1A , the imaging light-emitting unit SHB and the imaging light-receiving unit SJB are configured to be provided outside the display unit DIS, but one embodiment of the present invention is not limited thereto. For example, a display device of one embodiment of the present invention may be configured such that the imaging light-emitting unit SHB and the imaging light-receiving unit SJB are provided in the pixel array ALP, as shown in FIG. 1B . In the display device DP of FIG. 1B , the imaging light-emitting unit SHB can be, for example, an imaging light-emitting pixel included in the pixel array ALP. Furthermore, the imaging light-receiving unit SJB can be, for example, an imaging pixel included in the pixel array ALP. In other words, as shown in FIG. 1B , the display device DP may be configured such that the pixel array ALP includes the above-described imaging light-emitting pixel and imaging pixel in addition to the display pixel that displays an image.

[0086] Next, a specific configuration example of the display unit DIS will be described. Fig. 2A is a schematic cross-sectional view showing an example of the configuration of the display unit DIS. As an example, the display unit DIS has a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0087] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including the drive circuit region DRV.

[0088] The circuit layer SICL has a substrate BS and a drive circuit region DRV.

[0089] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). In addition to semiconductor substrates, the substrate BS can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, or base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device DP includes heat treatment, it is preferable to select a material with high heat resistance for the substrate BS.

[0090] In this embodiment, the substrate BS is described as a semiconductor substrate made of silicon, and therefore, the transistors included in the driver circuit region DRV can be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors).

[0091] The drive circuit region DRV is provided on the substrate BS.

[0092] The wiring layer LINL is provided with wiring, for example. The wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in a drive circuit region DRV provided below and a circuit included in a pixel layer PXAL provided above.

[0093] The pixel layer PXAL has, as an example, the above-mentioned pixel array ALP.

[0094] Fig. 3A is an example of a plan view of the display unit DIS. Note that the display unit DIS shown in Fig. 3A is a plan view of the pixel layer PXAL, and can be a plan view of the pixel array ALP.

[0095] 3A is divided into regions of p rows and q columns (p is an integer greater than or equal to 1, and q is an integer greater than or equal to 1), for example. Therefore, the display unit DIS has display regions ARA[1,1] to ARA[p,q]. In addition, in Figure 3A, as an example, display area ARA[1,1], display area ARA[2,1], display area ARA[p-1,1], display area ARA[p,1], display area ARA[1,2], display area ARA[2,2], display area ARA[p-1,2], display area ARA[p,2], display area ARA[1,q-1], display area ARA[2,q-1], display area ARA[p-1,q-1], display area ARA[p,q-1], display area ARA[1,q], display area ARA[2,q], display area ARA[p-1,q], and display area ARA[p,q] are each shown in excerpt form.

[0096] For example, if it is desired to divide the pixel array ALP into 32 regions, p = 4 and q = 8, and this can be applied to Figure 3A. Incidentally, if the resolution of the display unit DIS is 8K4K, the number of display pixels is 7680 x 4320. Furthermore, if the sub-display pixels included in the display pixels are of three colors, red (R), green (G), and blue (B), the total number of sub-display pixels included in the pixel array ALP is 7680 x 4320 x 3. Here, if the pixel array ALP of the display device DP having an 8K4K resolution is divided into 32 regions, the number of display pixels per region is 960 x 1080. Furthermore, if the sub-display pixels included in the pixels are of three colors, red (R), green (G), and blue (B), the number of sub-display pixels per region is 960 x 1080 x 3.

[0097] Here, consider the drive circuit region DRV included in the circuit layer SICL in the case where the pixel array ALP is divided into regions of p rows and q columns in FIG. 3A.

[0098] FIG. 3B is an example of a plan view of the display unit DIS, and shows only the drive circuit region DRV included in the circuit layer SICL.

[0099] 3A, the pixel array ALP is divided into regions with p rows and q columns, and therefore, a corresponding drive circuit is required for each of the divided display regions ARA[1,1] to ARA[p,q]. Specifically, the drive circuit region DRV may also be divided into regions with p rows and q columns, and a drive circuit may be provided in each divided region.

[0100] 3B shows a configuration in which the driver circuit region DRV is divided into regions of p rows and q columns, and therefore the driver circuit region DRV has circuit regions ARD[1,1] to ARD[p,q]. In addition, in Figure 3B, as an example, circuit areas ARD[1,1], circuit area ARD[2,1], circuit area ARD[p-1,1], circuit area ARD[p,1], circuit area ARD[1,2], circuit area ARD[2,2], circuit area ARD[p-1,2], circuit area ARD[p,2], circuit area ARD[1,q-1], circuit area ARD[2,q-1], circuit area ARD[p-1,q-1], circuit area ARD[p,q-1], circuit area ARD[1,q], circuit area ARD[2,q], circuit area ARD[p-1,q], and circuit area ARD[p,q] are each shown in excerpt form.

[0101] Each of the circuit areas ARD[1,1] to ARD[p,q] includes a column driver circuit CLM, a row driver circuit RWD, and a frame memory FM. For example, the column driver circuit CLM and the row driver circuit RWD included in the circuit area ARD[h,k] (not shown in FIG. 3B ) located in the hth row and the kth column (h is an integer from 1 to p, and k is an integer from 1 to q) can drive a plurality of pixels included in the display area ARA[h,k] located in the hth row and the kth column of the display unit DIS.

[0102] The column driver circuit CLM may include, for example, a source driver circuit that transmits image signals to a plurality of pixels included in the corresponding display area ARA. The column driver circuit CLM may also include an amplifier circuit for amplifying the image signals. The column driver circuit CLM may also include a memory device such as a register for temporarily storing image signal data. Therefore, the display section DIS of FIG. 2A preferably includes wiring for electrically connecting the corresponding column driver circuit CLM to the pixels included in the display area ARA. The column driver circuit CLM may also include a digital-to-analog conversion circuit that converts digital image signals into analog data.

[0103] The row driver circuit RWD has, for example, a gate driver circuit for selecting a plurality of display pixels to which an image signal is to be sent in the corresponding display area ARA. Therefore, it is preferable that the display unit DIS in Fig. 2A is provided with wiring for electrically connecting the row driver circuit RWD and the pixels included in the corresponding display area ARA.

[0104] The frame memory FM has a function of holding, as an electric potential, an image signal to be transmitted to a display pixel included in the corresponding display area ARA, for example.

[0105] 2A , 3A , and 3B , the display area ARA[h,k] and the circuit area ARD[h,k] overlap each other, but the display device of one embodiment of the present invention is not limited to this. In the display device of one embodiment of the present invention, the display area ARA[h,k] and the circuit area ARD[h,k] do not necessarily overlap each other.

[0106] For example, as shown in FIG. 2B, the display unit DIS may have a configuration in which not only the drive circuit region DRV but also the region LIA is provided on the substrate BS.

[0107] As an example, wiring is provided in the region LIA. The wiring included in the region LIA may be electrically connected to wiring included in the wiring layer LINL. In this case, the display unit DIS may be configured such that the circuit included in the drive circuit region DRV and the circuit included in the pixel layer PXAL are electrically connected by the wiring included in the region LIA and the wiring included in the wiring layer LINL. The display unit DIS may be configured such that the circuit included in the drive circuit region DRV and the wiring included in the region LIA or the circuit are electrically connected via the wiring included in the wiring layer LINL.

[0108] The area LIA may also include, for example, a GPU. If the display unit DIS includes a touch panel, the area LIA may also include a sensor controller that controls the touch sensors included in the touch panel. If liquid crystal elements are used as the display elements of the display unit DIS, the area LIA may also include a gamma correction circuit. The area LIA may also include a controller that processes input signals from outside the display unit DIS. The area LIA may also include the above-mentioned circuits and a voltage generation circuit for generating voltages to be supplied to the drive circuits included in the circuit area ARD.

[0109] Furthermore, when a light-emitting device using an organic EL material is used as the display element of the display unit DIS, an EL correction circuit may be included. For example, it has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. Because the brightness of a light-emitting device containing an organic EL material when emitting light is proportional to the current, if the characteristics of the drive transistor electrically connected to the light-emitting device are poor, the brightness of the light emitted by the light-emitting device may be lower than the desired brightness. For example, the EL correction circuit can monitor the amount of current flowing through the light-emitting device and, when the amount of current is smaller than the desired amount, increase the amount of current flowing through the light-emitting device to increase the brightness of the light emitted by the light-emitting device. Conversely, when the amount of current is larger than the desired amount, it can adjust the amount of current flowing through the light-emitting device to be smaller.

[0110] 4A is an example of a plan view of the display unit DIS shown in FIG. 2B, showing the drive circuit region DRV indicated by a solid line and the display unit DIS indicated by a dotted line. Also, in the display unit DIS of FIG. 4A, as an example, the drive circuit region DRV is surrounded by the region LIA (an example of a plan view of the display device DP showing only the circuit layer SICL is shown in FIG. 4B). Therefore, as shown in FIG. 4A, the drive circuit region DRV is arranged so as to overlap the inside of the pixel array ALP in a plan view.

[0111] In addition, in the display unit DIS shown in Figure 4A, similar to Figure 3A, the pixel array ALP is divided into display areas ARA[1,1] to ARA[p,q], and the drive circuit area DRV is also divided into circuit areas ARD[1,1] to ARD[p,q].

[0112] 4A, as an example, the correspondence between the display area ARA and the circuit area ARD including the drive circuits that drive the pixels included in the display area ARA is illustrated by thick arrows. Specifically, the drive circuits included in the circuit area ARD[1,1] drive the pixels included in the display area ARA[1,1], and the drive circuits included in the circuit area ARD[2,1] drive the pixels included in the display area ARA[2,1]. The drive circuits included in the circuit area ARD[p-1,1] drive the pixels included in the display area ARA[p-1,1], and the drive circuits included in the circuit area ARD[p,1] drive the pixels included in the display area ARA[p,1]. The drive circuits included in the circuit area ARD[1,q] drive the pixels included in the display area ARA[1,q], and the drive circuits included in the circuit area ARD[2,q] drive the pixels included in the display area ARA[2,q]. Further, the drive circuit included in the circuit area ARD[p-1,n] drives the pixels included in the display area ARA[p-1,q], and the drive circuit included in the circuit area ARD[p,q] drives the pixels included in the display area ARA[p,q]. In other words, although not shown in Figure 4A, the drive circuit included in the circuit area ARD[h,k] located in row h and column k drives the pixels included in the display area ARA[h,k].

[0113] 2B, the drive circuit included in the circuit region ARD in the circuit layer SICL and the pixels included in the display region ARA in the pixel layer PXAL are electrically connected by wiring included in the wiring layer LINL, so that the display region ARA[h, k] and the circuit region ARD[h, k] do not necessarily overlap each other in the configuration of the display unit DIS. Therefore, the positional relationship of the drive circuit region DRV is not limited to the plan view of the display device DP shown in FIG. 4A, and the arrangement of the drive circuit region DRV can be freely determined.

[0114] 2A and 2B has a configuration in which a wiring layer LINL is provided, but one embodiment of the present invention is not limited thereto. For example, the display device of one embodiment of the present invention may have a configuration in which a pixel layer PXAL is provided over a circuit layer SICL, as shown in FIG.

[0115] 3B and 4A, the arrangement of the column driver circuits CLM and the row driver circuits RWD in each of the circuit regions ARD[1,1] to ARD[p,q] is not limited to the configuration of the display device of one embodiment of the present invention. In Figures 3B and 4A, the column driver circuits CLM and the row driver circuits RWD are arranged to intersect with each other (to form a cross), but within one circuit region ARD, the column driver circuits CLM and the row driver circuits RWD may be arranged in various shapes.

[0116] Next, a configuration example of the display area ARA[h, k] and the circuit area ARD[h, k] will be described. Fig. 5 is a block diagram showing an excerpt of the display area ARA[h, k] and the circuit area ARD[h, k] in the display device DP shown in Fig. 1A and Fig. 3A to Fig. 4B.

[0117] 5, the display area ARA[h,k] has a plurality of display pixels PX. The plurality of display pixels PX are arranged in a matrix of m rows and n columns (m is an integer equal to or greater than 1, and n is an integer equal to or greater than 1) within the display area ARA[h,k]. Note that in FIG. 5, only display pixel PX[1,1], display pixel PX[m,1], display pixel PX[1,n], display pixel PX[m,n], and display pixel PX[i,j] (i is an integer equal to or greater than 1 and equal to or less than m, and j is an integer equal to or greater than 1 and equal to or less than n) are illustrated in the display area ARA[h,k].

[0118] 3B and 4A, the circuit area ARD[h,k] includes a row driver circuit RWD, a column driver circuit CLM, and a frame memory FM. In addition to the display area ARA[h,k] and the circuit area ARD[h,k], Fig. 5 also illustrates a drive circuit area DRV and an interface IF and a control unit CTL included in the drive circuit area DRV.

[0119] For example, the row driver circuit RWD is electrically connected to each of the wirings GL[1] to GL[m]. For example, the column driver circuit CLM is electrically connected to the wirings SL[1] to SL[n]. The frame memory FM is electrically connected to the row driver circuit RWD and the column driver circuit CLM. The interface IF is electrically connected to the control unit CTL and the frame memory FM. The control unit CTL is electrically connected to the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM in the drive circuit region DRV. The display pixel PX[i,j] is electrically connected to the wiring SL[j] and the wiring GL[i].

[0120] Each of the display pixels PX[1,1] to PX[m,n] can be, for example, a pixel to which one or both of a liquid crystal display device and a light-emitting device are applied. Examples of the light-emitting device include a light-emitting device including an organic EL element (OLED (Organic Light Emitting Diode)), an inorganic EL element, an LED (including micro LED), a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser. In this embodiment, a light-emitting device including an organic EL is applied to the display pixel PX. The luminance of light emitted from a light-emitting device capable of emitting particularly high luminance light is, for example, 500 cd / m ２ or more, preferably 1000 cd / m ２ More than 10000cd / m ２ or less, more preferably 2000 cd / m ２ More than 5000cd / m ２ It can be as follows:

[0121] As described above, the row driver circuit RWD includes a circuit that has the function of selecting at least one of the first to m-th rows of the display area ARA[h, k] to which the image data signal is to be supplied, and transmitting a selection signal to the plurality of display pixels PX arranged in the selected row. Note that the selection signal can be, for example, an analog potential, a digital potential (high-level potential or low-level potential), or a pulse potential.

[0122] The row driver circuit RWD may have a function not only to select one of the wirings GL[1] to GL[m] and transmit a selection signal to the selected wiring, but also to transmit the same selection signal to two or more consecutively adjacent wirings among the wirings GL[1] to GL[m]. That is, the row driver circuit RWD can simultaneously select display pixels PX arranged in two or more consecutively adjacent rows. The row driver circuit RWD may also have a function to change the frame frequency of the row driver circuit RWD in response to a signal from a control unit CTL (described later).

[0123] As described above, the column driver circuit CLM includes a circuit that transmits image data signals to the display pixels PX included in the display area ARA[h, k]. The image data signals may be, for example, analog potentials, digital potentials (high-level potentials or low-level potentials), or pulse potentials.

[0124] The column driver circuit CLM may have a function not only to select one of the wirings SL[1] to SL[n] and transmit a selection signal to that wiring, but also to transmit the same selection signal to two or more consecutively adjacent wirings among the wirings SL[1] to SL[n]. In other words, the column driver circuit CLM can simultaneously transmit the same image signal to the display pixels PX arranged in two or more consecutively adjacent columns. The column driver circuit CLM may also have a function to change the frame frequency of the column driver circuit CLM in response to a signal from a control unit CTL, which will be described later.

[0125] As described above, the interface IF has a function of inputting image data for displaying an image on the display device DP from a device external to the display device DP into the drive circuit region DRV. Also, in Fig. 5, the interface IF has a function of inputting the image data into the frame memory FM. The interface IF also has a function of inputting command signals input from a device external to the display device DP to the control unit CTL for controlling the display device DP.

[0126] The frame memory FM has a function of temporarily storing image data transmitted from the interface IF, a function of temporarily storing the addresses of the display pixels PX to which the image data is written, and a function of changing the frame frequency of the frame memory FM in response to a signal from a control unit CTL (described later).

[0127] 5, the control unit CTL has a function of controlling the number of rows to which the row driver circuit RWD sends a selection signal at one time. Similarly, the control unit CTL has a function of controlling the number of columns to which the column driver circuit CLM sends the same image signal. In this case, the control unit CTL can send control signals to each of the row driver circuit RWD and the column driver circuit CLM to perform the above operations.

[0128] Furthermore, for example, the control unit CTL may have a function of controlling the frame frequencies of the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM, respectively. In this case, the control unit CTL is capable of transmitting a signal to each of the row driver circuit RWD, the column driver circuit CLM, and the frame memory FM to change the frame frequency.

[0129] Furthermore, when the display device DP has the configuration of FIG. 1B, that is, when the pixel array ALP includes an imaging light-emitting unit SHB and an imaging light-receiving unit SJB, the block diagram of FIG. 5 can be rewritten as the block diagram of FIG. 6, for example.

[0130] The block diagram of Figure 6 differs from the block diagram of Figure 5 in that the display area ARA[h,k] includes imaging pixels PV[1,1] to PV[m,n], and the drive circuit area DRV includes a sensor row driver circuit TXD and a sensor column driver circuit POD.

[0131] In addition, Figure 6 illustrates only the imaging pixels PV[1,1], PV[m,1], PV[1,n], PV[m,n], and PV[i,j] from the imaging pixels PV[1,1] to PV[m,n].

[0132] 6, the display area ARA[h,k] has pixels PU[1,1] to PU[m,n]. Note that pixel PU[1,1] includes a display pixel PX[1,1] and an imaging pixel PV[1,1], pixel PU[m,1] includes a display pixel PX[m,1] and an imaging pixel PV[m,1], pixel PU[1,n] includes a display pixel PX[1,n] and an imaging pixel PV[1,n], pixel PU[m,n] includes a display pixel PX[m,1] and an imaging pixel PV[m,n], and pixel PU[i,j] includes a display pixel PX[i,j] and an imaging pixel PV[i,j]. That is, in the display area ARA[h,k], the pixels PU[1,1] to PU[m,n] are arranged in a matrix of m rows and n columns, similar to the display area ARA[h,k] in FIG.

[0133] In Figure 6, pixel PU[1,1], pixel PU[m,1], pixel PU[1,n], pixel PU[m,n], and pixel PU[i,j] are selected from pixels PU[1,1] to PU[m,n].

[0134] For example, the sensor row driver circuit TXD is electrically connected to each of the wirings TXL[1] to TXL[m]. The sensor column driver circuit POD is electrically connected to each of the wirings POL[1] to POL[n]. The imaging pixel PV[i,j] is electrically connected to the wirings TXL[i] and POL[j].

[0135] Each of the imaging pixels PV[1,1] to PV[m,n] shown in Fig. 6 corresponds to the imaging light receiving unit SJB in Fig. 1A and Fig. 1B. Therefore, each of the imaging pixels PV[1,1] to PV[m,n] can be a pixel having a light receiving device such as a photoelectric conversion element (for example, a pn-type or pin-type photodiode).

[0136] 6 includes a light-emitting device, each of the display pixels PX[1,1] to PX[m,n] can also be used as an image-capturing light-emitting pixel. That is, each of the display pixels PX[1,1] to PX[m,n] shown in FIG. 6 can be used not only to display an image but also to emit light necessary for capturing an image. In this case, each of the display pixels PX[1,1] to PX[m,n] corresponds to the image-capturing light-emitting unit SHB in FIGS. 1A and 1B. Furthermore, the display area ARA[h,k] may include an image-capturing light-emitting pixel (not shown) in addition to the display pixels PX[1,1] to PX[m,n].

[0137] The sensor row driver circuit TXD has a function of selecting a row to be imaged in the display area ARA[h, k], for example. Note that the image capturing method in the configuration example of FIG. 6 may be a rolling shutter method or a global shutter method.

[0138] For example, the sensor column driver circuit POD has a function of reading out data captured by the imaging pixels PV in the display unit DIS. For this reason, the sensor column driver circuit POD is sometimes referred to as a readout circuit. The sensor column driver circuit POD may also include an amplifier circuit for amplifying the data and an analog-to-digital conversion circuit.

[0139] In the configuration example shown in FIG. 6, the sensor row driver circuit TXD and the sensor column driver circuit POD are provided outside the circuit area ARD[h, k], but the sensor row driver circuit TXD and the sensor column driver circuit POD may also be provided inside the circuit area ARD[h, k].

[0140] As described above, by applying the configuration example shown in Figure 6 to the display device DP, it is possible to configure the display device DP of Figure 1B in which an imaging light-emitting unit SHB and an imaging light-receiving unit SJB are provided within the pixel array ALP.

[0141] One aspect of the present invention is a display device that divides a pixel array into multiple regions and can change the display quality of each region according to the position of a user's line of sight. In particular, in a region far from the position of the user's line of sight, the amount of image data transmitted to the pixel array can be reduced by lowering the display quality. Note that examples of methods for changing the display quality include changing the screen resolution and changing the frame frequency.

[0142] Changing the Screen Resolution First, a method for changing the screen resolution in each divided region of the pixel array of the display device will be described, using the display unit DIS of the display device DP shown in Figures 3A to 4B.

[0143] For example, if the screen resolution of the display unit DIS of the display device DP is 8K4K, the number of display pixels PX included in the display unit DIS is 7680 x 4320. Here, if the screen resolution of the display unit DIS of the display device DP is changed to 4K2K (3840 x 2160), the matrix of display pixels PX of the display unit DIS is divided into areas of 2 rows and 2 columns, and four display pixels PX included in each area are treated as one pixel, and the same image signal is sent to the four display pixels PX included in the same area, thereby making it possible to drive the display device DP as a display device with a screen resolution of 4K2K. Furthermore, when the screen resolution of the display unit DIS of the display device DP is changed to FHD (1920 x 1080 pixels), the matrix of display pixels PX of the display unit DIS is divided into regions of 4 rows and 4 columns, with 16 display pixels PX included in each region being treated as one pixel, and the same image signal is sent to four display pixels PX included in the same region, thereby enabling the 8K4K display device DP to be driven as a display device with an FHD screen resolution. Furthermore, when the screen resolution of the display unit DIS of the display device DP is changed to HD (1280 x 720 pixels), the matrix of display pixels PX of the display unit DIS is divided into regions of 6 rows and 6 columns, with 36 display pixels PX included in each region being treated as one pixel, and the same image signal is sent to the 36 display pixels PX included in the same region, thereby enabling the 8K4K display device DP to be driven as a display device with an HD screen resolution.

[0144] The above is an explanation of an example in which the screen resolution of the display unit DIS of the display device DP is changed, but as mentioned above, in the display device DP, the screen resolution can be changed for each display area ARA.

[0145] 7 is a block diagram of a display area ARA[h,k] including a plurality of display pixels PX. Note that Fig. 7 excerpts display pixel PX[1,1], display pixel PX[2,1], display pixel PX[3,1], display pixel PX[4,1], display pixel PX[1,2], display pixel PX[2,2], display pixel PX[3,2], display pixel PX[4,2], display pixel PX[1,3], display pixel PX[2,3], display pixel PX[3,3], display pixel PX[4,3], display pixel PX[1,4], display pixel PX[2,4], display pixel PX[3,4], and display pixel PX[4,4].

[0146] When the screen resolution of the display unit DIS of the display device DP is 8K4K and the display unit DIS is divided into display areas of 4 rows and 8 columns (that is, when p = 4 and q = 8 in Figures 3A to 4B), the number of display pixels PX included in one display area ARA is 960 x 1080. In this case, in Figure 7, the display area ARA[h, k] displays an image, with the area PSR surrounded by the dotted line counting as one pixel.

[0147] Here, consider a case where the matrix in which the display pixels PX are arranged in the display area ARA[h,k] in FIG. 7 is divided into two rows and two columns of regions PSR_HF (regions surrounded by solid lines). In this case, four display pixels PX included in each region PSR_HF are considered to be one pixel, and by transmitting the same image signal to the four display pixels PX included in the same region PSR_HF, the display area ARA[h,k] can display an image with the region PSR_HF considered to be one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered to be 480 x 540 pixels. Furthermore, because the same image signal is written to the four display pixels PX in the two rows and two columns of the region PSR_HF, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 480 x 540 pixels is one-fourth the amount of image data transmitted at the normal screen resolution.

[0148] Similarly, consider the case where the matrix in which the display pixels PX are arranged in the display area ARA[h,k] in FIG. 7 is divided into a 4-row, 4-column area PSR_QT (area surrounded by a dashed line). In this case, by transmitting the same image signal to the 16 display pixels PX included in the same area PSR_QT, the display area ARA[h,k] can display an image with the area PSR_QT including the 16 display pixels PX as one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered to be 240 x 270 pixels. Furthermore, because the same image signal is written to the 16 display pixels PX in the 4-row, 4-column area PSR_QT, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 240 x 270 pixels is 1 / 16 of the amount of image data transmitted at the normal screen resolution.

[0149] Also, although not shown, consider a case in which the matrix in which the display pixels PX are arranged in the display area ARA[h,k] in FIG. 7 is divided into 6-row, 6-column regions. In this case, by transmitting the same image signal to 36 display pixels PX included in the same region, the display area ARA[h,k] can display an image with the region including the 36 display pixels PX as one pixel. In other words, the screen resolution of the display area ARA[h,k] can be considered to be 160 x 180 pixels. Furthermore, because the same image signal is written to the 36 display pixels PX included in the 6-row, 6-column region, the amount of image data transmitted to the display area ARA[h,k] with a reduced screen resolution of 160 x 180 pixels is 1 / 36 of the amount of image data transmitted at the normal screen resolution.

[0150] As described above, by lowering the screen resolution of the display area ARA[h,k], the amount of image data written to the display area ARA[h,k] can be reduced. In other words, the load on the interface IF that handles image data input from outside the display device DP can be reduced. Furthermore, because the amount of image data displayed on the display device DP is reduced, the load on each circuit in the drive circuit area DRV can be reduced.

[0151] <<Configuration Examples of Column Driver Circuit CLM and Row Driver Circuit RWD>> Next, configuration examples of the column driver circuit CLM and row driver circuit RWD included in the circuit area ARD corresponding to the display area ARA where the screen resolution can be changed will be described.

[0152] 8A shows an example of the configuration of a column driver circuit CLM that can be applied to the circuit area ARD of the display device DP described above. Note that in order to show the connection with the column driver circuit CLM, a frame memory FM is also shown in FIG.

[0153] FIG. 8B shows an example of the configuration of a row driver circuit RWD that can be applied to the circuit area ARD of the display device DP described above.

[0154] The column driver circuit CLM in FIG. 8A includes, for example, a driver circuit SD, switches SWa[1] to SWa[n], and switches SWb[1] to SWb[n-1].

[0155] The driver circuit SD includes, for example, circuits SDa[1] to SDa[n].

[0156] Moreover, the row driver circuit RWD in FIG. 8B includes, for example, a driver circuit GD, switches SWc[1] to SWc[n], and switches SWd[1] to SWd[n-1].

[0157] 8A and 8B may be implemented by electrical switches such as analog switches or transistors. In particular, the above-described transistors are preferably used as electrical switches for the switches shown in FIGS. 8A and 8B, and OS transistors are more preferable. Alternatively, mechanical switches may be used for the switches shown in FIGS. 8A and 8B.

[0158] 8A and 8B, the control of switching between the on and off states of the switches SWa[1] to SWa[n], the switches SWb[1] to SWb[n-1], the switches SWc[1] to SWc[n], and the switches SWd[1] to SWd[n-1] is performed by the control unit CTL. Specifically, the control unit CTL can determine whether to turn on or off each of the switches SWa[1] to SWa[n], the switches SWb[1] to SWb[n-1], the switches SWc[1] to SWc[n], and the switches SWd[1] to SWd[n-1], depending on the result of image analysis of an image captured by the imaging light receiving unit SJB (e.g., a user's eye). For this reason, the control unit CTL has a function of transmitting control signals to the switches included in each of the column driver circuit CLM and the row driver circuit RWD.

[0159] The input terminals of the circuits SDa[1] to SDa[n] are electrically connected to the frame memory FM.

[0160] The output terminal of the circuit SDa[1] is electrically connected to the first terminal of the switch SWa[1]. The output terminal of the circuit SDa[n] is electrically connected to the first terminal of the switch SWa[n]. When J is an integer between 2 and n-1, the output terminal of the circuit SDa[J] is electrically connected to the first terminal of the switch SWa[J].

[0161] The second terminal of the switch SWa[1] is electrically connected to the first terminal of the switch SWb[1] and the wiring SL[1]. The second terminal of the switch SWa[J] is electrically connected to the second terminal of the switch SWb[J-1], the first terminal of the switch SWb[J], and the wiring SL[J]. The second terminal of the switch SWa[n] is electrically connected to the second terminal of the switch SWb[n] and the wiring SL[n].

[0162] The driver circuit SD functions as a source driver circuit, for example. Specifically, each of the circuits SDa[1] to SDa[n] has a function of acquiring digital data corresponding to an image to be displayed on the pixel array ALP from the frame memory FM, converting the digital data into analog data, and outputting the analog data to the corresponding output terminal.

[0163] The drive circuit GD functions as a gate driver circuit, for example. Specifically, the drive circuit GD has a function of receiving a signal including a row (address) of the display pixel PX for which an image is to be rewritten from the control unit CTL or the frame memory FM, and transmitting a selection signal to the selected row.

[0164] Next, a method for driving the column driver circuit CLM and the row driver circuit RWD will be described.

[0165] First, for example, consider a case where the display area ARA has a normal screen resolution and an image is displayed in the display area ARA.

[0166] In this case, in the column driver circuit CLM, all of the switches SWa[1] to SWa[n] are turned on, and all of the switches SWb[1] to SWb[n-1] are turned off.

[0167] This allows one of the circuits SDa[1] to SDa[n] to transmit an image signal to a corresponding one of the wirings SL[1] to SL[n].

[0168] In addition, in the row driver circuit RWD, all of the switches SWc[1] to SWc[n] are turned on, and all of the switches SWd[1] to SWd[n-1] are turned off.

[0169] This allows the driver circuit GD to transmit a selection signal to a corresponding one of the wirings GL[1] to GL[n].

[0170] Through the above operation, the column driver circuit CLM can select, one by one, the rows of the pixel array ALP in which the display pixels PX to which an image is written are arranged. Furthermore, the row driver circuit RWD can transmit corresponding image signals to each of the display pixels PX[1,1] to PX[m,n] included in the pixel array ALP. In other words, through this operation, the display area ARA can display an image at a normal screen resolution.

[0171] Next, consider a case where an image is displayed in the display area ARA with a screen resolution that is one-fourth of the normal screen resolution, where m and n are each a multiple of two.

[0172] In this case, in the column driver circuit CLM, the switches SWa[J+1] and SWb[J+1] are turned on, and the switches SWa[J+2] and SWb[J+2] are turned off, where J is 0 or an even number between 1 and n-1.

[0173] This allows the circuit SDa[J+1] to transmit the same image signal to each of the wirings SL[J+1] and SL[J+2], i.e., the same image signal can be transmitted to each of the plurality of display pixels PX arranged in the J+1th column and the plurality of display pixels PX arranged in the J+2th column.

[0174] In the row driver circuit RWD, the switches SWc[K+1] and SWd[K+1] are turned on, and the switches SWc[K+2] and SWd[K+2] are turned off, where K is 0 or an even number between 1 and m-1.

[0175] This allows the driver circuit GD to transmit image signals to the wirings GL[K+1] and GL[K+2], i.e., to transmit the same selection signal to the plurality of display pixels PX arranged in the K+1th row and the plurality of display pixels PX arranged in the K+2th row.

[0176] Therefore, by the above operation, the m-row, n-column matrix of the pixel array ALP can be divided into 2-row, 2-column regions, and the same image signal and the same selection signal can be transmitted to the four display pixels PX included in each region. Also, by regarding the four display pixels PX included in the 2-row, 2-column region as one pixel as described above, the screen resolution of the display area ARA can be reduced to one-fourth.

[0177] Next, consider a case where an image is displayed in the display area ARA with a screen resolution that is 1 / 16 of the normal screen resolution, where m and n are each a multiple of 4.

[0178] In this case, in the column driver circuit CLM, the switch SWa[J+1] and the switches SWb[J+1] to SWb[J+3] are turned on, and the switches SWa[J+2] to SWa[J+4] and the switch SWb[J+4] are turned off, where J is 0 or a multiple of 4 between 1 and n-1.

[0179] As a result, the circuit SDa[J+1] can transmit the same image signal to each of the wirings SL[J+1] to SL[J+4]. That is, the circuit SDa[J+1] can transmit the same image signal to each of the display pixels PX arranged in the J+1th column, the display pixels PX arranged in the J+2th column, the display pixels PX arranged in the J+3th column, and the display pixels PX arranged in the J+4th column.

[0180] In the row driver circuit RWD, the switches SWc[K+1] and SWd[K+1] to SWd[K+3] are turned on, and the switches SWc[K+2] to SWc[K+4] and SWd[K+4] are turned off, where K is 0 or a multiple of 4 between 1 and m-1.

[0181] This allows the driver circuit GD to transmit image signals to the wirings GL[K+1] to GL[K+4]. That is, the driver circuit GD can transmit the same selection signal to the plurality of display pixels PX arranged in the K+1th row, the plurality of display pixels PX arranged in the K+2th row, the plurality of display pixels PX arranged in the K+3th row, and the plurality of display pixels PX arranged in the K+4th row.

[0182] Therefore, by the above operation, the m-row, n-column matrix of the pixel array ALP can be divided into 4-row, 4-column regions, and the same image signal and the same selection signal can be transmitted to the 16 display pixels PX included in each region. Also, by regarding the 16 display pixels PX included in the 4-row, 4-column region as one pixel as described above, the screen resolution of the display area ARA can be reduced to 1 / 16.

[0183] Next, consider a case where an image is displayed in the display area ARA with a screen resolution that is 1 / 36 of the normal screen resolution, where m and n are each a multiple of 6.

[0184] In this case, in the column driver circuit CLM, the switch SWa[J+1] and the switches SWb[J+1] to SWb[J+5] are turned on, and the switches SWa[J+2] to SWa[J+6] and the switch SWb[J+6] are turned off, where J is 0 or a multiple of 6 between 1 and n-1.

[0185] This allows the circuit SDa[J+1] to transmit the same image signal to each of the wirings SL[J+1] to SL[J+6]. That is, the circuit SDa[J+1] can transmit the same image signal to each of the display pixels PX arranged in the J+1th column, the display pixels PX arranged in the J+2th column, the display pixels PX arranged in the J+3th column, the display pixels PX arranged in the J+4th column, the display pixels PX arranged in the J+6th column, and the display pixels PX arranged in the J+6th column.

[0186] In the row driver circuit RWD, the switches SWc[K+1] and SWd[K+1] to SWd[K+5] are turned on, and the switches SWc[K+2] to SWc[K+6] and SWd[K+6] are turned off, where K is 0 or a multiple of 6 between 1 and m-1.

[0187] This allows the driver circuit GD to transmit image signals to the wirings GL[K+1] to GL[K+6]. That is, the driver circuit GD can transmit the same selection signal to the plurality of display pixels PX arranged in the K+1th row, the plurality of display pixels PX arranged in the K+2th row, the plurality of display pixels PX arranged in the K+3th row, the plurality of display pixels PX arranged in the K+4th row, the plurality of display pixels PX arranged in the K+5th row, and the plurality of display pixels PX arranged in the K+6th row.

[0188] Therefore, by the above operation, the m-row, n-column matrix of the pixel array ALP can be divided into 6-row, 6-column regions, and the same image signal and the same selection signal can be transmitted to the 36 display pixels PX included in each region. Also, by regarding the 36 display pixels PX included in the 6-row, 6-column region as one pixel as described above, the screen resolution of the display area ARA can be reduced to 1 / 36.

[0189] In the above example of operation for lowering the screen resolution, the row driver circuit RWD is described as transmitting selection signals to multiple rows simultaneously, but the row driver circuit RWD may also transmit selection signals sequentially, one row at a time, rather than to multiple rows.

[0190] Furthermore, the configuration of one or both of the column driver circuit CLM and the row driver circuit RWD described above is not limited to one aspect of the present invention. For example, the column driver circuit CLM of FIG. 8A may be configured without one or more switches selected from switches SWb[1] to SWb[n-1]. As a specific example, the column driver circuit CLM may have the configuration shown in FIG. 9. The column driver circuit CLM of FIG. 9 differs from the column driver circuit CLM of FIG. 8A in that it does not include switch SWb[J] (where J is a multiple of 4 and is equal to or greater than 1). Note that in the column driver circuit CLM of FIG. 9, n is a multiple of 4 and is equal to or greater than 1. By using the column driver circuit CLM of FIG. 9, the same image signal can be transmitted to a maximum of four columns of wiring.

[0191] <<Changing Screen Resolution Based on User's Line of Sight>> The above describes how the display device DP can change the screen resolution for each display area ARA. Here, we will explain the operation of detecting which area of ​​the pixel array ALP the user's line of sight is looking at and changing the screen resolution for each display area ARA. Line of sight detection (eye tracking) will be described later.

[0192] FIG. 10A shows an example in which the display unit DIS of the display device DP is divided into display areas of 16 rows and 16 columns (that is, in FIGS. 3A to 4B, p=16, q=16).

[0193] The display device DP is also assumed to have a function for detecting the user's line of sight. Therefore, the display device DP can determine which part of the pixel array ALP the user is looking at. For example, in FIG. 10A , the area ASU is the area determined by the eye tracking function of the display device DP to be the area the user is looking at (the area where the user is looking).

[0194] Because area ASU is in the user's line of sight, the user can clearly see area ASU. On the other hand, it becomes difficult for the user to clearly see areas away from area ASU (areas that are included in the user's field of view but are not in the user's line of sight, or areas that the user is not focusing on). Conversely, because the user is not consciously paying attention to an image displayed in display area ARA that is away from area ASU, there is little need to improve the display quality of that display area ARA.

[0195] Here, as shown in Fig. 10A, the display device DP sets an area ALPa around the area ASU based on the area ASU detected by the eye tracking function, sets an area ALPb to surround the periphery of the area ALPa, sets an area ALPc to surround the periphery of the area ALPb, and sets an area ALPd to surround the periphery of the area ALPc. Then, the display device DP sets the screen resolution in each of the display areas ARA included in the areas ALPa to ALPd. Here, the screen resolution of the display area ARA included in the area ALPa is set to R ａ The screen resolution of the display area ARA included in the area ALPb is R ｂ The screen resolution of the display area ARA included in the area ALPc is R ｃ The screen resolution of the display area ARA included in the area ALPd is R ｄ In particular, R ａ is R ｂ Higher than R ｂ is R ｃ Higher than R ｃ is R ｄ It is preferable to set it higher than

[0196] As described above, by increasing the screen resolution of the display area ARA around the area ASU, which is the user's line of sight, and decreasing the screen resolution of the display area ARA away from the area ASU, the amount of image data transmitted to the display unit DIS of the display device DP can be reduced. This eliminates the need to increase the performance of the interface for transmitting image data to the display device DP, thereby reducing power consumption and costs. Furthermore, the amount of image data transmitted to the display area ARA by the circuits included in the circuit area ARD that drives the display pixels PX included in the display area ARA with a low screen resolution can also be reduced, thereby reducing power consumption.

[0197] It is difficult for the user to clearly see the display area ARA that is away from the area ASU, so even if the screen resolution of the display area ARA that is away from the area ASU is lowered and the display quality of the image displayed on the entire pixel array ALP is reduced, the impact is small when the user views the image displayed on the pixel array ALP.

[0198] Furthermore, when the user's line of sight moves and the position of area ASU changes, the positions and ranges of areas ALPa, ALPb, ALPc, and ALPd may also change. For example, as shown in FIG. 10B or FIG. 11A, when the area in front of the user's line of sight changes from area ASU to area ASU_AF, the positions of areas ALPa, ALPb, ALPc, and ALPd change. Note that in the example change shown in FIG. 10B, the ranges (sizes) of areas ALPa and ALPb remain unchanged, while the range of area ALPc shrinks and the range of area ALPd expands. Also, FIG. 11A shows an example change when the area in front of the user's line of sight changes from area ASU to area ASU_AF, which is near the edge of the pixel array ALP, where the ranges of areas ALPa, ALPb, and ALPc shrink and the range of area ALPd expands.

[0199] Furthermore, if the eye tracking function of the display device DP does not detect the user's gaze, the display device DP may set the entire pixel array ALP to the area ALPe, as shown in FIG. 11B . Examples of cases in which the user's gaze is not detected include when the user's eyelids are closed or when the user is sleeping. The screen resolution of the display area ARA included in the area ALPe may be lower than that of the area ALPd, for example. Alternatively, the display device DP may perform an operation of not transmitting image signals to the display pixels PX of the display area ARA included in the area ALPe. In other words, the display device DP may perform an operation of transmitting image signals for black display to the display pixels PX of the display area ARA included in the area ALPe.

[0200] 10A and 10B show a configuration in which the display unit DIS is divided into four regions, ALPa, ALPb, ALPc, and ALPd, and different screen resolutions are set for the regions ALPa, ALPb, ALPc, and ALPd, respectively. However, the display device of one embodiment of the present invention is not limited to this. For example, the display unit DIS of the display device DP may be divided into two, three, five, or more regions, and different screen resolutions may be set for each region.

[0201] <Changing the Frame Frequency> Next, a method for changing the frame frequency in each divided region of the pixel array of the display device will be described, using the display unit DIS of the display device DP shown in Figures 3A to 4B.

[0202] For example, if the frame frequency of the pixel array ALP of the display device DP is 120 Hz (sometimes referred to as fps), the display device DP writes images 120 times per second. If the frame frequency of the pixel array ALP of the display device DP is changed to 60 Hz, the display device DP writes images 60 times per second. In this case, the image data (transmission amount) per second transmitted to the pixel array ALP is half the image data transmitted per second at 120 Hz. Furthermore, if the frame frequency of the pixel array ALP of the display device DP is changed to 30 Hz, the image data (transmission amount) per second transmitted to the pixel array ALP is one-fourth the image data transmitted per second at 120 Hz.

[0203] When the frame frequency of the pixel array ALP of the display device DP is changed to 180 Hz, the image data (transmission amount) per second required to rewrite the image displayed on the pixel array ALP becomes 1.5 times the image data per second transmitted at 120 Hz. When the frame frequency of the pixel array ALP of the display device DP is changed to 240 Hz, the image data (transmission amount) per second required to rewrite the image displayed on the pixel array ALP becomes twice the image data per second transmitted at 120 Hz.

[0204] The above is a description of an example in which the frame frequency of the pixel array ALP of the display device DP is changed, but the frame frequency may be changed for each display area ARA in the display device DP.

[0205] The display device DP in FIG. 12A has, as an example, a pixel array ALP including a display area ARA[1,1], a display area ARA[2,1], a display area ARA[1,2], and a display area ARA[2,2].

[0206] When the frame frequency of each of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] included in the display unit DIS is 120 Hz, the amount of image data transmitted to each of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] is equal to each other (see FIG. 12B). Note that, here, the amount of image data transmitted to each of the display areas ARA[1,1], ARA[2,1], ARA[1,2], and ARA[2,2] is represented by D ＰＳ Let's say.

[0207] Here, as shown in FIG. 12C, the frame frequency of the display area ARA[1,1] is changed to 30 Hz, and the frame frequency of the display area ARA[2,1] is changed to 60 Hz.

[0208] In the display area ARA[1,1], by lowering the frame frequency from 120 Hz to 30 Hz, the amount of image data transmitted to the display area ARA[1,1] is reduced by D ＰＳ That is, by lowering the frame frequency from 120 Hz to 30 Hz, the amount of image data transmitted to the display area ARA[1,1] is reduced to 3D. ＰＳ It can be reduced by 4.

[0209] In addition, by lowering the frame frequency from 120 Hz to 60 Hz in the display area ARA[2,1], the amount of image data transmitted to the display area ARA[2,1] is reduced to D ＰＳ That is, by lowering the frame frequency from 120 Hz to 60 Hz, the amount of image data transmitted to the display area ARA[2,1] is reduced to D ＰＳ It can be reduced by 2.

[0210] Here, the transmission volume reduced in each of the display areas ARA[1,1] and ARA[2,1] can be allocated to one or more areas selected from the display area ARA[1,2] and ARA[2,2].

[0211] For example, the reduced transmission amount 3D in the display area ARA[1,1]ＰＳ In this case, the amount of image data transmitted to the display area ARA[2,2] is 7D / 4. ＰＳ / 4, and by increasing the frame frequency of the display area ARA[2,2] to 210 Hz, it becomes possible to transmit image data to the display area ARA[2,2] (see FIGS. 12C and 12D).

[0212] Also, for example, the reduced transmission amount D ＰＳ / 2 may be increased to the amount of image data transmitted to the display area ARA[1,2]. In this case, the amount of image data transmitted to the display area ARA[1,2] is 3D. ＰＳ / 2, and by increasing the frame frequency of the display area ARA[1,2] to 180 Hz, it becomes possible to transmit image data to the display area ARA[1,2] (see FIGS. 12C and 12D).

[0213] <<Changing Frame Frequency Based on User's Line of Sight>> The above describes how the display device DP can change the frame frequency for each display area ARA. Here, we will explain an operation of detecting which area of ​​the pixel array ALP the user's line of sight is looking at and changing the frame frequency for each display area ARA. Gaze detection (eye tracking) will be described later.

[0214] Note that explanations of parts that overlap with the above-mentioned "changing screen resolution" may be omitted.

[0215] Similar to FIG. 10A, FIG. 13A shows an example in which the pixel array ALP of the display device DP is divided into display areas of 16 rows and 16 columns (i.e., in FIGS. 3A to 4B, p=16, q=16).

[0216] 10A, the display device DP is also provided with a function for detecting the user's line of sight. Therefore, the display device DP shown in FIG. 13A can determine which part of the pixel array ALP the user is looking at. Regarding the area ASU shown in FIG. 13A, the description of FIG. 10A should be taken into consideration.

[0217] 10A , the user can clearly see area ASU, and does not consciously pay attention to areas away from area ASU (areas that are within the user's field of view but are not in the user's line of sight, or areas to which the user is not gazing). For this reason, the user does not consciously pay attention to an image displayed in display area ARA that is away from area ASU, and therefore there is little need to improve the display quality of that display area ARA.

[0218] Here, based on the area ASU detected by the eye tracking function, the display device DP sets an area ALPa around the area ASU, sets an area ALPb to surround the periphery of the area ALPa, sets an area ALPc to surround the periphery of the area ALPb, and sets an area ALPd to surround the periphery of the area ALPc, as shown in Figure 13A. Then, a frame frequency is set in each of the display areas ARA included in the areas ALPa to ALPd. Here, the frame frequency of the display area ARA included in the area ALPa is set to f ａ The frame frequency of the display area ARA included in the area ALPb is f ｂ The frame frequency of the display area ARA included in the area ALPc is f ｃ The frame frequency of the display area ARA included in the area ALPd is f ｄ In particular, f ａ is f ｂ higher than f ｂ is f ｃ higher than f ｃ is f ｄ It is preferable to set it higher than

[0219] Specifically, as explained in Figures 12A to 12D, the amount of image data transmitted to the display area ARA included in area ALPa should be greater than the amount of image data transmitted to the display area ARA included in area ALPb, the amount of image data transmitted to the display area ARA included in area ALPb should be greater than the amount of image data transmitted to the display area ARA included in area ALPc, and the amount of image data transmitted to the display area ARA included in area ALPc should be greater than the amount of image data transmitted to the display area ARA included in area ALPd.

[0220] A specific example will be described below. Fig. 15 is an example of a block diagram of the display device DP shown in Figs. 3A to 4B. In addition, as an example, the interface IF here is assumed to be capable of inputting image data to all circuit areas ARD at a frame frequency of 120 Hz. Furthermore, the maximum value of image data that the interface IF can transmit to all circuit areas ARD at a frame frequency of 120 Hz is set to D ＭＡＸ Let's say.

[0221] 16 is a graph showing the amount of image data input to the interface IF from outside the display device DP. For example, when all of the pixel array ALP of the display device DP is driven at a frame frequency of 120 Hz (referred to as normal in FIG. 16), the interface IF receives a D ＭＡＸ This indicates that the amount of image data is input.

[0222] Figure 17 also shows the timing at which image data is input to the interface IF, the timing at which image data is input to the frame memory FM of each of areas ALPa to ALPd, and the timing at which image data is input to the display area ARA of each of areas ALPa to ALPd.

[0223] 13A, consider a case where the display device DP is driven with the frame frequency of the display area ARA of area ALPa set to 240 Hz, the frame frequency of the display area ARA of area ALPb set to 120 Hz, the frame frequency of the display area ARA of area ALPc set to 60 Hz, and the frame frequency of the display area ARA of area ALPd set to 30 Hz. In this case, control signals are given from the control unit CTL so that the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPa is driven at 240 Hz, the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPb is driven at 120 Hz, the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPc is driven at 60 Hz, and the frame memory FM of the circuit area ARD corresponding to the display area ARA of area ALPd is driven at 30 Hz.

[0224] In the first frame, data Da, data Db, data Dc, and data Dd are input to the interface IF, which operates at a frame frequency of 120 Hz (see interface IF in FIGS. 16 and 17). Data Da is image data to be displayed in the display area ARA included in the area ALPa, data Db is image data to be displayed in the display area ARA included in the area ALPb, data Dc is image data to be displayed in the display area ARA included in the area ALPc, and data Dd is image data to be displayed in the display area ARA included in the area ALPd.

[0225] 16 and 17, data Da and data Db are input to the interface IF in the second frame, data Da, data Db, and data Dc are input to the interface IF in the third frame, and data Da and data Db are input to the interface IF in the fourth frame.

[0226] It should be noted that from the fifth frame onwards, image data is repeatedly input in the same manner as in the first to fourth frames.

[0227] Since the frame frequency of the display area ARA of the area ALPa is 240 Hz, the amount of data Da input to the interface in the first to fourth frames is twice the amount of data transmitted when the frame frequency is 120 Hz. For this reason, two pieces of data Da are shown in Fig. 16 for each frame.

[0228] 17, in the second frame, the frame memory FM in area ALPa (referred to as FM(ALPa) in FIG. 17) receives the two pieces of data Da input to the interface IF in the first frame. The frame memory FM in area ALPb (referred to as FM(ALPb) in FIG. 17) receives the data Db input to the interface IF in the first frame. The frame memory FM in area ALPc (referred to as FM(ALPc) in FIG. 17) receives the data Dc input to the interface IF in the first frame. The frame memory FM in area ALPd (referred to as FM(ALPd) in FIG. 17) receives the data Dd input to the interface IF in the first frame.

[0229] 17, in the third frame, the display area ARA of area ALPa (denoted as ARA(ALPa) in FIG. 17) receives the two pieces of data Da that were input to the frame memory FM of area ALPa in the second frame. The display area ARA of area ALPb (denoted as ARA(ALPb) in FIG. 17) receives the data Db that was input to the frame memory FM of area ALPb in the second frame. The display area ARA of area ALPc (denoted as ARA(ALPc) in FIG. 17) receives the data Dc that was input to the frame memory FM of area ALPc in the second frame. The display area ARA of area ALPd (denoted as ARA(ALPd) in FIG. 17) receives the data Dd that was input to the frame memory FM of area ALPd in ​​the second frame.

[0230] Similarly, the data Da and data Db input to the interface IF in the second frame are input to the display areas ARA of the areas ALPa and ALPb, respectively, at the timing two frames ahead.

[0231] Similarly, the data Da to Dc input to the interface IF in the third frame are input to the display areas ARA of the areas ALPa to ALPc, respectively, at the timing two frames ahead.

[0232] Similarly, the data Da and data Db input to the interface IF in the fourth frame are input to the display areas ARA of the areas ALPa and ALPb, respectively, at the timing two frames ahead.

[0233] To summarize the above, in the display area ARA included in area ALPa, the image is rewritten twice per frame, in the display area ARA included in area ALPb, the image is rewritten once per frame, in the display area ARA included in area ALPc, the image is rewritten once per two frames, and in the display area ARA included in area ALPa, the image is rewritten once per four frames.

[0234] In other words, by performing the above operations, as shown in Figure 17, the display area ARA included in area ALPa can display images at a frame frequency of 240 Hz, the display area ARA included in area ALPb can display images at a frame frequency of 120 Hz, the display area ARA included in area ALPc can display images at a frame frequency of 60 Hz, and the display area ARA included in area ALPa can display images at a frame frequency of 30 Hz.

[0235] In FIG. 16, when the display device DP is operated at a frame frequency of 120 Hz, the interface IF receives a D ＭＡＸ On the other hand, by causing the display device DP to perform the above-described operation, it is possible to reduce the amount of image data input to the interface by data Dv2 in the second frame, data Dv3 in the third frame, and data Dv4 in the fourth frame.

[0236] As described above, by increasing the frame frequency of the display area ARA around the area ASU, which is the user's line of sight, and decreasing the frame frequency of the display area ARA away from the area ASU, the amount of image data transmitted to the display unit DIS of the display device DP can be reduced. This eliminates the need to increase the performance of the interface for transmitting image data to the display device DP, thereby reducing power consumption and costs. Furthermore, because it is difficult for the user to clearly see the display area ARA away from the area ASU, even if the screen resolution of the display area ARA away from the area ASU is reduced and the display quality of the image displayed on the entire display unit DIS is reduced, the impact on the user's viewing of the image displayed on the display unit DIS is small.

[0237] Furthermore, when the user's line of sight moves and the position of area ASU changes, the positions and ranges of areas ALPa, ALPb, ALPc, and ALPd may also change. For example, as shown in Figure 13B or 14A, when the area where the user's line of sight changes from area ASU to area ASU_AF, the positions of areas ALPa, ALPb, ALPc, and ALPd change. Note that in the example change in Figure 13B, the ranges (sizes) of areas ALPa and ALPb remain unchanged, while the range of area ALPc shrinks and the range of area ALPd expands. Also, Figure 14A shows an example change when the area where the user's line of sight changes from area ASU to area ASU_AF, which is near the edge of the display unit DIS, where the ranges of areas ALPa, ALPb, and ALPc shrink and the range of area ALPd expands.

[0238] Furthermore, if the eye tracking function of the display device DP does not detect the user's gaze, the display device DP may set the entire display unit DIS to the area ALPe, as shown in FIG. 14B . Examples of cases in which the user's gaze is not detected include when the user's eyelids are closed or when the user is sleeping. The frame frequency of the display area ARA included in the area ALPe may be lower than that of the area ALPd, for example. Alternatively, the frame frequency of the area ALPe may be set to 0. In other words, the display device DP may stop transmitting image signals to the display pixels PX of the display area ARA included in the area ALPe.

[0239] 13A and 13B show a configuration in which the display unit DIS is divided into four regions, ALPa, ALPb, ALPc, and ALPd, and different frame frequencies are set for the regions ALPa, ALPb, ALPc, and ALPd, respectively. However, the display device of one embodiment of the present invention is not limited to this. For example, the display unit DIS of the display device DP may be divided into two, three, five, or more regions, and different frame frequencies may be set for the respective regions.

[0240] <Configuration Example of Electronic Device Capable of Line-of-Sight Detection (Eye Tracking)> Here, a configuration example of an electronic device capable of line-of-sight detection (eye tracking) will be described.

[0241] Fig. 18A shows an electronic device (head-mounted display) to which the display device DP of Fig. 1A is applied. The electronic device HMD has a housing KYT. The housing KYT has a shape that allows it to be worn on a human head. The housing KYT is provided with display devices DP_L and DP_R, which correspond to the display device DP described above. Note that Fig. 18A illustrates the left eye ME_L and the right eye ME_R of a user wearing the electronic device HMD.

[0242] Specifically, the display device DP_L is provided on the housing KYT so as to be positioned in front of the left eye ME_L of the user wearing the electronic device HMD. That is, when viewed from the front, the user's left eye ME_L and the display device DP_L have overlapping areas. Furthermore, the display device DP_R is provided on the housing KYT so as to be positioned in front of the right eye of the user wearing the electronic device HMD. That is, when viewed from the front, the user's right eye ME_R and the display device DP_R have overlapping areas.

[0243] The electronic device HMD also has an image-capturing light-emitting unit SHB_L, an image-capturing light-emitting unit SHB_R, an image-capturing light-receiving unit SJB_L, and an image-capturing light-receiving unit SJB_R, each of which is provided in a housing KYT. Note that the image-capturing light-emitting unit SHB_L and the image-capturing light-emitting unit SHB_R correspond to the image-capturing light-emitting unit SHB in FIG. 1A, and the image-capturing light-receiving unit SJB_L and the image-capturing light-receiving unit SJB_R correspond to the image-capturing light-receiving unit SJB in FIG. 1A.

[0244] The imaging light-emitting unit SHB_L and the imaging light-receiving unit SJB_L function as devices for tracking the line of sight of the user's left eye ME_L. Specifically, the imaging light-emitting unit SHB_L has a function of irradiating the user's left eye ME_L with imaging light LGTI_L, and the imaging light-receiving unit SJB_L has a function of detecting light LGTR_L reflected from the user's left eye ME_L.

[0245] The imaging light receiving unit SJB_L can acquire an image of the user's left eye ME_L by detecting light LGTR_L from the user's left eye ME_L. Because the image contains the crystalline lens, pupil, cornea, macula, or fovea, the electronic device HMD can perform image analysis on the image to determine which part of the display device DP_L the user's left eye ME_L is looking at. This allows the line of sight of the user's left eye ME_L to be detected.

[0246] The imaging light-emitting unit SHB_R and the imaging light-receiving unit SJB_R also function as devices for tracking the line of sight of the user's right eye ME_R. Specifically, the imaging light-emitting unit SHB_R has a function of irradiating the user's right eye ME_R with imaging light LGTI_R, and the imaging light-receiving unit SJB_R has a function of detecting light LGTR_R reflected from the user's right eye ME_R.

[0247] Similarly, the imaging light receiving unit SJB_R can obtain an image of the user's right eye ME_R by detecting light LGTR_R from the user's right eye ME_R. Since the image contains the crystalline lens, pupil, cornea, macula, or fovea, the electronic device HMD can perform image analysis on the image to determine which part of the display device DP_R the user's right eye ME_R is looking at. This allows the line of sight of the user's right eye ME_R to be detected.

[0248] The light emitted by one or both of the imaging light-emitting unit SHB_L and the imaging light-emitting unit SHB_R may be visible light or infrared light (sometimes referred to as IR). The light-receiving devices included in the imaging light-receiving unit SJB_L and the imaging light-receiving unit SJB_R can be determined according to the light emitted by the imaging light-emitting unit SHB_L and the imaging light-receiving unit SHB_R. For example, if the imaging light-emitting unit SHB_L (imaging light-emitting unit SHB_R) emits visible light, the light-receiving device may be a light-receiving device capable of receiving visible light. For example, if the imaging light-emitting unit SHB_L (imaging light-emitting unit SHB_R) emits infrared light, the light-receiving device may be a light-receiving device capable of receiving infrared light.

[0249] Furthermore, the gaze detection performed by the electronic device HMD may be performed on either the left or right eye, rather than on both eyes. For example, if it is desired to perform gaze detection on only the left eye, the electronic device HMD may be configured to have an image-capturing light-emitting unit SHB_L and an image-capturing light-receiving unit SJB_L provided around the display device DP_L, as shown in FIG. 18B , and capture an image of the user's left eye ME_L. Furthermore, if it is not necessary to capture an image of the user's right eye ME_R, the electronic device HMD may be configured not to have an image-capturing light-emitting unit SHB_R and an image-capturing light-receiving unit SJB_R provided around the display device DP_R, as shown in FIG. 18B .

[0250] 18A and 18B are configured such that one image-capturing light-emitting unit and one image-capturing light-receiving unit are provided to sandwich one display device between them. However, one embodiment of the present invention is not limited to this configuration. The electronic device of one embodiment of the present invention may have a configuration in which the positions of the image-capturing light-emitting unit and the image-capturing light-receiving unit are swapped in FIGS. 18A and 18B . The electronic device of one embodiment of the present invention may have a configuration in which one image-capturing light-emitting unit and one image-capturing light-receiving unit are provided to sandwich one display device between them. The electronic device of one embodiment of the present invention may have a configuration in which multiple image-capturing light-emitting units are provided around the display device. The electronic device of one embodiment of the present invention may have a configuration in which multiple image-capturing light-receiving units are provided around the display device.

[0251] Furthermore, the image capturing light emitting section and the image capturing light receiving section may be provided inside the display device, rather than outside the display device.

[0252] The electronic device HMD shown in Fig. 19A is a head-mounted display to which the display device of Fig. 1B is applied. Specifically, the pixels included in the display device include light-emitting pixels that function as image-capturing light-emitting units and image-capturing pixels that function as image-capturing light-receiving units. As an example, in the electronic device HMD of Fig. 19A, the display device DP_L has pixels PU_L that include display pixels that display images, light-emitting pixels, and image-capturing pixels, and the display device DP_R has pixels PU_R that include display pixels that display images, light-emitting pixels, and image-capturing pixels.

[0253] The light-emitting pixel included in pixel PU_L has a function of irradiating light LGTI_L to the user's left eye ME_L, and the imaging pixel included in pixel PU_L has a function of detecting light LGTR_L reflected from the user's left eye ME_L. Similarly, the light-emitting pixel included in pixel PU_R has a function of irradiating light LGTI_R to the user's right eye ME_R, and the imaging pixel included in pixel PU_R has a function of detecting light LGTR_R reflected from the user's right eye ME_R.

[0254] Next, we will explain the path of light LGTI_L (light LGTI_R) that is irradiated from the light-emitting pixel included in pixel PU_L (pixel PU_R) to the user's left eye ME_L (user's right eye ME_R), and the path of light LGTR_L (light LGTR_R) from the user's left eye ME_L (user's right eye ME_R) that is detected by the light-receiving device included in pixel PU_L (pixel PU_R).

[0255] 19B and 19C are cross-sectional views showing, as an example, a display device DP corresponding to the display device DP_L or the display device DP_R and a user's eye ME corresponding to the user's left eye ME_L or the user's right eye ME_R. Note that, in FIGS. 19B and 19C, cross-sectional views of a lens LNS that functions as an optical system are also shown.

[0256] 19B and 19C, the display device DP includes, as an example, a plurality of pixels PU. The plurality of pixels PU are preferably arranged regularly, for example, in a matrix form.

[0257] Each of the imaging light-emitting pixels included in the plurality of pixels PU has a function of emitting light that can be captured by the light-receiving device included in the pixel PU onto the display surface of the display device DP. For example, Fig. 19B shows how light LGTI is emitted from the imaging light-emitting pixel included in the pixel PU onto the display surface of the display device DP.

[0258] In addition, the lens LNS has a function of refracting light emitted from the display device DP and emitting the light in the direction of the user's eye ME. For example, Fig. 19B shows the lens LNS refracting light LGTI and emitting the light in the direction of the user's eye ME.

[0259] The display pixels included in the plurality of pixels PU have the function of emitting light based on an image signal input to the display device DP onto the display surface of the display device DP. The path of the light based on the image signal can be considered to be the same as the path of the light LGTI emitted by the imaging light-emitting pixel. In particular, the user can recognize the light (image) focused on the macula YH on the retina MM as a point or area in front of the line of sight.

[0260] Also, in FIG. 19B, the user's eye ME has a cornea KM, a ciliary body MYT (in this specification, the ciliary body zonules (Zunn's zonules) are also included in the ciliary body MYT), a lens SST, a vitreous body GT, a retina MM, a choroid MRM, a sclera KYM, and an optic nerve SK.

[0261] Furthermore, a portion of the retina MM includes the macula YH. The macula YH contains a large concentration of cells capable of recognizing fine details and colors. The macula YH also contains the fovea CSK. The user recognizes the light (image) focused on the macula YH in the user's eye as a point or area in front of the line of sight.

[0262] For example, FIG. 19B shows how light LGTI emitted from an imaging light-emitting pixel included in a pixel PU of a display device DP is focused on the macula YH via a lens LNS and a crystalline lens SST.

[0263] The crystalline lens SST of the user's eye ME, for example, functions as a lens for focusing light on the fovea CSK described above. The ciliary body MYT also has the function of changing the thickness of the crystalline lens SST. The degree of focusing of light on the fovea CSK can be adjusted by changing the thickness of the crystalline lens SST. In other words, the crystalline lens SST and the ciliary body MYT can adjust the focus of light incident on the user's eye ME.

[0264] In addition, the distance between the display device DP and the lens LNS (or the distance between the lens LNS and the user's eye ME) can be freely determined, and for example, it is preferable that the distance between the display device DP and the lens LNS is a distance at which light emitted from the display pixel circuit is focused on the retina MM of the user's eye ME.

[0265] As described above, by changing at least one of the thickness of the crystalline lens SST and the distance between the display device DP and the lens LNS, light from multiple display pixels included in the display device DP or multiple imaging light-emitting pixels can be focused onto the retina MM.

[0266] When light is incident on an object in a perpendicular direction, the light is reflected in a direction 180 degrees from the direction of incidence. In other words, the path of light that is incident on an object in a perpendicular direction and the path of light reflected by the object are approximately the same.

[0267] Therefore, the light LGTR, which is reflected light from the macula YH, reaches the pixel PU via substantially the same path as the light LGTI, as shown in Fig. 19B. Specifically, the light LGTR is received by an imaging pixel included in the pixel PU.

[0268] For this reason, in the display device DP, by performing an imaging operation using the imaging pixels included in all pixels PU, it is possible to capture an image of the retina MM and the macula YH, which is a partial area of ​​the retina MM, as a pixel. Furthermore, since the user recognizes the light (image) incident on the macula YH as a point or area at the front of the line of sight, the position (coordinates) at which the macula YH is captured in the image can tell which area of ​​the image displayed on the display device DP the user is directing their gaze to.

[0269] Specifically, the address of the imaging pixel that captured the macular lutea YH is obtained from the image, and the display pixel included in the same pixel group as the imaging pixel is determined. Light emitted from the display pixel included in the same pixel group as the imaging pixel that captured the macular lutea YH reaches the macular lutea YH. As a result, the display image displayed by the display pixel included in the same pixel group as the imaging pixel that captured the macular lutea YH is the area toward which the user is directing their gaze, among the display images on the display device DP.

[0270] In the present embodiment, as an example, gaze detection is performed by a control unit CTL provided in the display device DP, but one aspect of the present invention is not limited to this. For example, image analysis by gaze detection related to the display device DP may be performed by an external server (control computer) rather than the control unit CTL of the display device DP. In other words, an image acquired by the display device DP may be temporarily sent to an external server, which may perform image analysis and send the analysis results to the display device DP, and the display device may operate according to the results of gaze detection.

[0271] Similarly, processing related to the electronic device HMD (such as image processing) may also be performed by an external server (control computer). A system in which processing is performed by a server (control computer) external to the display device DP (or electronic device HMD), the processing results are transmitted to the display device DP (or electronic device HMD), and the display device DP (or electronic device HMD) operates may be called a thin client system. In this case, the display device DP (or electronic device HMD) may be called a thin client terminal.

[0272] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0273] Embodiment 2 In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0274] <Structural Example 1 of Display Device> Figure 20 is a cross-sectional view illustrating an example of a display device of one embodiment of the present invention. As an example, a display device 1000 illustrated in Figure 20 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310. Note that the structure of the display device DP in Figure 1A or the like in the above-described embodiment can be the structure of the display device 1000 in Figure 20. Note that the pixel circuit described in this embodiment can be the display pixel described in the above embodiment.

[0275] Furthermore, for example, the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL shown in the display device DP of FIG. 2A can each be configured as in the display device 1000 of FIG. 20. As an example, the circuit layer SICL has a substrate 310, and a transistor 300 is formed on the substrate 310. Furthermore, a wiring layer LINL is provided above the transistor 300, and the wiring layer LINL is provided with wiring that electrically connects the transistor 300, a transistor 500 described later, and a light-emitting device 130R, a light-emitting device 130G, and a light-emitting device 130B described later. Furthermore, a pixel layer PXAL is provided above the wiring layer LINL, and the pixel layer PXAL has, as an example, the transistor 500 and a light-emitting device 130 (in FIG. 16, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B).

[0276] The substrate 310 can be, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Examples of the substrate 310 include, but are not limited to, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as an acrylic resin. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. Note that if the manufacturing process of the display device 1000 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate 310.

[0277] The diagonal size of the display device can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less for use in an XR device, a wearable information terminal, or the like, a semiconductor substrate may be used as the substrate 310.

[0278] Furthermore, there are no particular limitations on the screen ratio (aspect ratio) of the display device 1000. For example, the display device 1000 can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0279] In this embodiment, the substrate 310 is described as a semiconductor substrate made of silicon.

[0280] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a Si transistor. Note that although FIG. 20 illustrates a configuration in which one of the source and drain of the transistor 300 is electrically connected to a conductor 330 and a conductor 356 (described later) via a conductor 328 (described later), the electrical connection configuration of the display device of one embodiment of the present invention is not limited thereto. For example, the display device of one embodiment of the present invention may have a configuration in which the gate of the transistor 300 is electrically connected to the conductor 330 and the conductor 356 via the conductor 328.

[0281] The transistor 300 can be a Fin type transistor by, for example, covering the top surface and the side surfaces in the channel width direction of the semiconductor region 313 with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a Fin type transistor, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0282] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0283] The region in the semiconductor region 313 where the channel is formed, the region nearby, and the low-resistance region 314a and low-resistance region 314b that become the source region or drain region preferably contain a semiconductor such as a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the above-mentioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Alternatively, a configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be, for example, a high electron mobility transistor (HEMT) using gallium arsenide and aluminum gallium arsenide.

[0284] The conductor 316, which functions as a gate electrode, can be made of a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron or aluminum, or can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material.

[0285] Note that the work function is determined by the material of the conductor, and therefore the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use one or both of titanium nitride and tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use one or both of tungsten and aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0286] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0287] 20 is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0288] In the transistor 300 shown in FIG. 20, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0289] The insulators 320, 322, and 326 may be formed using, for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0290] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0291] The insulator 322 may function as a planarizing film that planarizes steps caused by the insulator 320 and the transistor 300 covered with the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0292] Furthermore, it is preferable to use an insulating film (referred to as a barrier insulating film) for the insulator 324 that has barrier properties to prevent impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to a region above the insulator 324 (for example, a region where the transistor 500, the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided). Therefore, it is preferable to use an insulating material for the insulator 324 that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (the impurities are less likely to permeate). Depending on the situation, the insulator 324 may be made of a material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (a material that is less likely to permeate the impurities). Furthermore, depending on the situation, the insulator 324 may be made of a material that has barrier properties to prevent the diffusion of impurities such as nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO, and NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (i.e., that the oxygen is less likely to permeate), or that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0293] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD (Chemical Vapor Deposition) method.

[0294] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, in the TDS analysis, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. and the amount of desorption converted into hydrogen atoms is 10×10 １５ atoms / cm ２ Below 5 × 10, preferably １５ atoms / cm ２ The following is fine.

[0295] The insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0296] Furthermore, conductors 328, 330, etc., which connect to a light-emitting device or the like provided above the insulator 326, are embedded in the insulators 320, 322, 324, and 326. The conductors 328, 330, etc., function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0297] The material for each plug and wiring (conductor 328 or conductor 330) can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0298] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductors 328 and 330.

[0299] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 352 and 354 also function as interlayer insulating films and planarizing films. The conductor 356 preferably includes a conductor having barrier properties against one or more selected from hydrogen, oxygen, and water.

[0300] Note that, for example, tantalum nitride is preferably used as the conductor having a barrier property against hydrogen. Furthermore, by stacking tantalum nitride and highly conductive tungsten, the diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0301] In addition, an insulator 512 is provided above the insulator 354 and the conductor 356 .

[0302] 20 , the transistor 500 is provided over an insulator 512. A substance having a barrier property against oxygen or hydrogen is preferably used for the insulator 512. Specifically, the insulator 512 can be formed using one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride, for example.

[0303] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor (e.g., the transistor 500) may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0304] For example, the insulator 512 can be made of a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film or a silicon oxynitride film.

[0305] An insulator 514 is provided over the insulator 512, and the transistor 500 is provided over the insulator 514. An insulator 574 is formed over the transistor 500, and an insulator 581 is formed over the insulator 574.

[0306] The insulator 574 and the insulator 581 will be described in detail in Embodiment 3.

[0307] For the insulator 514, a film (a film having a barrier property) that suppresses impurities such as water and hydrogen is preferably used from a region where circuit elements are provided below the substrate 310 or the insulator 512 to a region where the transistor 500 is provided. Therefore, for example, silicon nitride formed by a CVD method can be used for the insulator 514.

[0308] 20 is an OS transistor including a metal oxide in a channel formation region, as described above. Note that the OS transistor will be described in detail in Embodiment 3.

[0309] An insulator 592 and an insulator 594 are formed in this order over the insulator 581. A conductor 596 is embedded in the insulator 592 and the insulator 594. The conductor 596 functions as a plug or wiring connected to the transistor 300. Note that the conductor 596 can be formed using a material similar to that of the conductors 328 and 330.

[0310] Note that, for example, the insulator 592 is preferably an insulator having a barrier property against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. Similarly to the insulator 326, the insulator 594 is preferably an insulator having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulator 594 also functions as an interlayer insulating film and a planarizing film. The conductor 596 preferably includes a conductor having a barrier property against one or more selected from hydrogen, oxygen, and water.

[0311] An insulator 598 and an insulator 599 are formed over the insulator 594 and the conductor 597 .

[0312] For example, the insulator 598 is preferably an insulator having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulator 324. As the insulator 599, it is preferably an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings, similar to the insulator 326. The insulator 599 also functions as an interlayer insulating film and a planarizing film.

[0313] On the insulator 599, the light emitting device 130R, the light emitting device 130G, the light emitting device 130B, and the connection portion 140 are formed.

[0314] The connection portion 140 may be referred to as a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting devices 130R, 130G, and 130B. In Fig. 20, the connection portion 140 has one or more conductors selected from conductors 112a to 112c described below, one or more conductors selected from conductors 126a to 126c described below, one or more conductors selected from conductors 129a to 129c described below, a common layer 114 described below, and a common electrode 115 described below.

[0315] The connection section 140 may be provided so as to surround the four sides of the display section, or may be provided within the display section (for example, between adjacent light-emitting devices 130).

[0316] The light-emitting device 130R has a conductor 112a, a conductor 126a on the conductor 112a, and a conductor 129a on the conductor 126a. The conductors 112a, 126a, and 129a may all be called pixel electrodes, or some of them may be called pixel electrodes.

[0317] The light-emitting device 130G has a conductor 112b, a conductor 126b on the conductor 112b, and a conductor 129b on the conductor 126b. As with the light-emitting device 130R, all of the conductors 112b, 126b, and 129b may be referred to as pixel electrodes, or only some of them may be referred to as pixel electrodes.

[0318] The light-emitting device 130B has a conductor 112c, a conductor 126c on the conductor 112c, and a conductor 129c on the conductor 126c. As with the light-emitting devices 130R and 130G, the conductors 112c, 126c, and 129c may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes.

[0319] The conductors 112a to 112c and the conductors 126a to 126c can be, for example, conductive layers functioning as reflective electrodes. For the conductive layers functioning as reflective electrodes, conductors with high reflectivity to visible light, such as silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), can be used. Furthermore, the conductors 112a to 112c and the conductors 126a to 126c can be, for example, a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order) or a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order).

[0320] Alternatively, for example, a conductive layer functioning as a reflective electrode may be used for the conductors 112a to 112c, and a conductor with high light-transmitting properties may be used for the conductors 126a to 126c. Examples of a conductor with high light-transmitting properties include an alloy of silver and magnesium and indium tin oxide (sometimes referred to as ITO).

[0321] The conductors 129a to 129c can be, for example, a conductive layer that functions as a transparent electrode. The conductive layer that functions as a transparent electrode can be, for example, the above-described conductor with high light-transmitting properties.

[0322] Furthermore, a microcavity structure (a microresonator structure) may be provided in the light-emitting device 130, which will be described in detail later. The microcavity structure refers to a structure in which the distance between the bottom surface of a light-emitting layer and the top surface of a lower electrode is set to a thickness that corresponds to the wavelength of the color of light emitted by the light-emitting layer. In this case, it is preferable to use a light-transmitting and light-reflective conductive material for the conductors 129a to 129c, which are upper electrodes (common electrodes), and a light-reflective conductive material for the conductors 112a to 112c and 126a to 126c, which are lower electrodes (pixel electrodes).

[0323] A microcavity structure refers to a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the light emission to be amplified). As a result, light reflected by the lower electrode and returned (reflected light) causes significant interference with light that is directly incident on the upper electrode from the light-emitting layer (incident light). This allows the phases of the reflected light and incident light, each of which has a wavelength λ, to be matched, thereby further amplifying the light emission from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, the phases will no longer match, resulting in attenuation without resonance.

[0324] The conductor 112a is connected to the conductor 596 embedded in the insulator 594 through an opening provided in the insulator 599. The end of the conductor 126a is located outside the end of the conductor 112a. The end of the conductor 126a and the end of the conductor 129a are aligned or approximately aligned.

[0325] Conductors 112b, 126b, and 129b in light-emitting device 130G, and conductors 112c, 126c, and 129c in light-emitting device 130B are similar to conductors 112a, 126a, and 129a in light-emitting device 130R, and therefore detailed explanations are omitted.

[0326] Recesses are formed in the conductors 112a, 112b, and 112c so as to cover the openings provided in the insulator 519. A layer 128 is embedded in the recesses.

[0327] The layer 128 has a function of planarizing the recessed portions of the conductor 112a, the conductor 112b, and the conductor 112c. Conductors 126a, 126b, and 126c, which are electrically connected to the conductors 112a, 112b, and 112c, are provided over the conductors 112a, 112b, and 112c and the layer 128. Therefore, regions overlapping with the recessed portions of the conductors 112a, 112b, and 112c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.

[0328] The layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 128. In particular, the layer 128 is preferably formed using an insulating material.

[0329] An insulating layer containing an organic material can be suitably used for the layer 128. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be used for the layer 128. Alternatively, a photosensitive resin can be used for the layer 128. Examples of the photosensitive resin include positive-type materials and negative-type materials.

[0330] By using a photosensitive resin, the layer 128 can be formed only through exposure and development steps, and the influence of dry etching or wet etching on the surfaces of the conductors 112 a, 112 b, and 112 c can be reduced. Furthermore, by forming the layer 128 using a negative photosensitive resin, the layer 128 can be formed using the same photomask (exposure mask) as that used to form the opening in the insulator 519 in some cases.

[0331] 20 shows an example in which the top surface of the layer 128 has a flat portion, but there is no particular limitation on the shape of the layer 128. Figures 21A to 21C show modified examples of the layer 128.

[0332] As shown in FIGS. 21A and 21C, the top surface of layer 128 can be configured to have a recessed shape in the center and its vicinity in cross section, that is, a shape having a concave curved surface.

[0333] As shown in FIG. 21B, the upper surface of layer 128 may have a shape in which the center and its vicinity bulge in cross section, that is, a shape having a convex curve.

[0334] The upper surface of layer 128 may have one or both of a convex curved surface and a concave curved surface. The number of convex curved surfaces and the number of concave curved surfaces that the upper surface of layer 128 has are not limited, and may be one or more.

[0335] Furthermore, the height of the upper surface of the layer 128 and the height of the upper surface of the conductor 112a may be the same or approximately the same, or may be different from each other. For example, the height of the upper surface of the layer 128 may be lower or higher than the height of the upper surface of the conductor 112a.

[0336] 21A can also be considered an example in which layer 128 is contained within a recess formed in conductor 112a. On the other hand, as shown in FIG. 21C, layer 128 may be present outside the recess formed in conductor 112a, that is, the width of the top surface of layer 128 may be wider than the recess.

[0337] Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0338] The first layer 113a is formed so as to cover the top and side surfaces of the conductor 126a and the conductor 129a. Similarly, the second layer 113b is formed so as to cover the top and side surfaces of the conductor 126b and the conductor 129b. Similarly, the third layer 113c is formed so as to cover the top and side surfaces of the conductor 126c and the conductor 129c. Therefore, the entire regions where the conductors 126a, 126b, and 126c are provided can be used as light-emitting regions for the light-emitting devices 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0339] In the light-emitting device 130R, the first layer 113a and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 can be collectively referred to as an EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 can be collectively referred to as an EL layer.

[0340] The structure of the light emitting device of this embodiment is not particularly limited, and may be a single structure or a tandem structure.

[0341] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island shapes by photolithography. Therefore, the angles between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c are close to 90 degrees at their edges. On the other hand, for example, an organic film formed using FMM (Fine Metal Mask) tends to become gradually thinner toward the edge, and the top surface is formed in a sloped shape over a range of, for example, 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0342] The first layer 113a, the second layer 113b, and the third layer 113c have a clear distinction between the top surface and the side surface. As a result, in adjacent first and second layers 113a and 113b, one side surface of the first layer 113a and one side surface of the second layer 113b are arranged opposite each other. This is true for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0343] Each of the first layer 113 a, the second layer 113 b, and the third layer 113 c has at least a light-emitting layer. For example, it is preferable that the first layer 113 a has a light-emitting layer that emits red light, the second layer 113 b has a light-emitting layer that emits green light, and the third layer 113 c has a light-emitting layer that emits blue light. Furthermore, the respective light-emitting layers may be of colors other than those mentioned above, such as cyan, magenta, yellow, or white.

[0344] Furthermore, the first layer 113a, the second layer 113b, and the third layer 113c may each have one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer.

[0345] For example, the first layer 113a, the second layer 113b, and the third layer 113c may each include a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer. Alternatively, an electron blocking layer may be provided between the hole transport layer and the light-emitting layer. Alternatively, an electron injection layer may be provided on the electron transport layer.

[0346] For example, each of the first layer 113a, the second layer 113b, and the third layer 113c may include an electron injection layer, an electron transport layer, a light-emitting layer, and a hole transport layer. In particular, each of the first layer 113a, the second layer 113b, and the third layer 113c preferably includes an electron injection layer, an electron transport layer, a light-emitting layer, and a hole transport layer stacked in this order. A hole blocking layer may be provided between the electron transport layer and the light-emitting layer. A hole injection layer may be provided on the hole transport layer.

[0347] The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. The surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device. Therefore, by providing the carrier transport layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface, and damage to the light-emitting layer can be reduced. This can improve the reliability of the light-emitting device and the light-receiving device.

[0348] The first layer 113a, the second layer 113b, and the third layer 113c may each have, for example, a first light-emitting unit, a charge generation layer, and a second light-emitting unit. For example, it is preferable that the first layer 113a has two or more light-emitting units that emit red light, the second layer 113b has two or more light-emitting units that emit green light, and the third layer 113c has two or more light-emitting units that emit blue light.

[0349] The second light-emitting unit preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surface of the second light-emitting unit is exposed during the manufacturing process of the display device, providing the carrier transport layer on the light-emitting layer can prevent the light-emitting layer from being exposed on the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting device.

[0350] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 114 is shared by the light-emitting devices 130R, 130G, and 130B.

[0351] The common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. As shown in Fig. 20 , the common electrode 115 shared by the plurality of light-emitting devices is electrically connected to a conductor included in the connection portion 140.

[0352] The side surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are covered with an insulator 125 and an insulator 127, respectively. A mask layer 118a is located between the first layer 113a and the insulator 125. Furthermore, a mask layer 118a is located between the second layer 113b and the insulator 125, and a mask layer 118a is located between the third layer 113c and the insulator 125. A common layer 114 is provided on the first layer 113a, the second layer 113b, the third layer 113c, the insulator 125, and the insulator 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to a plurality of light-emitting devices.

[0353] The insulator 125 can be an insulating layer containing an inorganic material. The insulator 125 can be, for example, one or more inorganic insulating films selected from an insulating oxide film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. The insulator 125 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film or an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film or an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Aluminum oxide is particularly preferable because it has a high etching selectivity with respect to the EL layer and functions to protect the EL layer in the formation of the insulator 127, which will be described later. In particular, by using an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by an atomic layer deposition (ALD) method as the insulator 125, it is possible to form an insulator 125 with few pinholes and excellent protection of the EL layer. The insulator 125 may also have a stacked structure of a film formed by an ALD method and a film formed by a sputtering method. For example, the insulator 125 may have a stacked structure of an aluminum oxide film formed by an ALD method and a silicon nitride film formed by a sputtering method.

[0354] The insulator 125 preferably functions as a barrier insulating layer against water and / or oxygen. The insulator 125 preferably has a function of suppressing diffusion of water and / or oxygen. The insulator 125 preferably has a function of capturing or fixing (also referred to as gettering) water and / or oxygen.

[0355] The insulator 125 has a function as a barrier insulating layer or a gettering function, which can suppress the intrusion of impurities (typically, one or both of water and oxygen) that can diffuse into each light-emitting device from the outside. With this structure, a highly reliable light-emitting device and further a highly reliable display panel can be provided.

[0356] The insulator 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulator 125 and causing deterioration of the EL layer. Furthermore, a low impurity concentration in the insulator 125 can improve the barrier properties against water and / or oxygen. For example, it is desirable that the insulator 125 has a sufficiently low hydrogen concentration and / or carbon concentration.

[0357] An insulating layer containing an organic material can be suitably used as the insulator 127. A photosensitive organic resin is preferably used as the organic material, and for example, a photosensitive resin composition containing an acrylic resin can be used. The viscosity of the material of the insulator 127 may be 1 cP or more and 1500 cP or less, and preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulator 127 within the above range, the insulator 127 having a tapered shape, as described below, can be formed relatively easily. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0358] As described below, the insulator 127 may have a tapered side surface, and the organic material that can be used for the insulator 127 is not limited to the above. For example, the insulator 127 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenolic resin, or a precursor of these resins. The insulator 127 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The insulator 127 may be made of a photosensitive resin such as a photoresist. The photosensitive resin may be a positive-type material or a negative-type material.

[0359] The insulator 127 may be made of a material that absorbs visible light. The insulator 127 absorbs light emitted from the light-emitting device, thereby suppressing light leakage (stray light) from the light-emitting device to an adjacent light-emitting device through the insulator 127. This improves the display quality of the display panel. Furthermore, since the display quality can be improved without using a polarizing plate in the display panel, the display panel can be made lighter and thinner.

[0360] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed is preferable because it can enhance the visible light blocking effect. In particular, mixing three or more color filter materials makes it possible to obtain a black or nearly black resin layer.

[0361] The insulator 127 can be formed by a wet film formation method such as spin coating, dipping, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating. In particular, it is preferable to form the organic insulating film that becomes the insulator 127 by spin coating.

[0362] The insulator 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature when forming the insulator 127 is typically 200° C. or lower, preferably 180° C. or lower, more preferably 160° C. or lower, more preferably 150° C. or lower, and more preferably 140° C. or lower.

[0363] Below, the structure of the insulator 127 and the like will be described using the structure of the insulator 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same can be said for the insulator 127 between the light-emitting device 130G and the light-emitting device 130B, and the insulator 127 between the light-emitting device 130B and the light-emitting device 130R. Furthermore, below, the end of the insulator 127 on the second layer 113b may be used as an example for description, but the same can be said for the end of the insulator 127 on the first layer 113a and the end of the insulator 127 on the third layer 113c.

[0364] The insulator 127 preferably has a tapered shape with a taper angle θ1 on the side surface in a cross-sectional view of the display device. The taper angle θ1 is the angle between the side surface of the insulator 127 and the substrate surface. However, the angle is not limited to the substrate surface, and may be the angle between the side surface of the insulator 127 and the upper surface of the flat portion of the insulator 125, the upper surface of the flat portion of the second layer 113b, or the upper surface of the flat portion of the pixel electrode 111b. Furthermore, by tapering the side surface of the insulator 127, the side surface of the insulator 125 and the side surface of the mask layer 118a may also be tapered.

[0365] The taper angle θ1 of the insulator 127 is less than 90°, preferably 60° or less, and more preferably 45° or less. By forming the side end of the insulator 127 in such a forward tapered shape, the common layer 114 and the common electrode 115 provided on the side end of the insulator 127 can be formed with good coverage without causing discontinuities or local thinning of the film. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby improving the display quality of the display device.

[0366] In addition, in a cross-sectional view of the display device, the upper surface of the insulator 127 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulator 127 preferably has a shape that bulges gently toward the center. Furthermore, it is preferable that the convex curved portion at the center of the upper surface of the insulator 127 smoothly connects to the tapered portion at the side edge. By forming the insulator 127 in such a shape, the common layer 114 and the common electrode 115 can be formed with good coverage over the entire insulator 127.

[0367] The insulator 127 is formed in a region between two EL layers (for example, a region between the first layer 113a and the second layer 113b), with part or all of the insulator 127 being disposed at a position sandwiched between a side edge of one EL layer (for example, the first layer 113a) and a side edge of the other EL layer (for example, the second layer 113b).

[0368] It is also preferable that one end of the insulator 127 overlaps the pixel electrode 111a, and the other end of the insulator 127 overlaps the pixel electrode 111b. This structure allows the end of the insulator 127 to be formed on a substantially flat region of the first layer 113a (second layer 113b). This makes it relatively easy to process the tapered shape of the insulator 127 as described above.

[0369] As described above, by providing the insulator 127 or the like, it is possible to prevent discontinuities and locally thin portions from being formed in the common layer 114 and the common electrode 115 from the substantially flat region of the first layer 113 a to the substantially flat region of the second layer 113 b. This makes it possible to prevent poor connection between the light-emitting devices in the common layer 114 and the common electrode 115 due to discontinuities and an increase in electrical resistance due to locally thin portions.

[0370] The display device of this embodiment can reduce the distance between light-emitting devices. Specifically, the distance between light-emitting devices, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably a region where the distance is 0.5 μm (500 nm) or less, and more preferably a region where the distance is 100 nm or less. In this way, by reducing the distance between each light-emitting device, a display device with high definition and a large aperture ratio can be provided.

[0371] A protective layer 131 is provided on each of the light-emitting devices 130R, 130G, and 130B. The protective layer 131 is a film that functions as a passivation film that protects the light-emitting device 130. By providing the protective layer 131 that covers the light-emitting device, it is possible to prevent impurities such as water and oxygen from entering the light-emitting device, thereby improving the reliability of the light-emitting device 130.

[0372] The protective layer 131 may include, for example, aluminum oxide, silicon nitride, or silicon nitride oxide.

[0373] The protective layer 131 and the substrate 110 are bonded via an adhesive layer 107. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device. In FIG. 20 , the space between the substrate 310 and the substrate 110 is filled with the adhesive layer 107, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 107 may be provided so as not to overlap with the light-emitting device. Alternatively, the space may be filled with a resin different from the frame-shaped adhesive layer 107.

[0374] The adhesive layer 107 can be made of various curable adhesives, such as ultraviolet-curable photocurable adhesives, reactive curable adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Epoxy resins with low moisture permeability are particularly preferred. Two-component resins may also be used. An adhesive sheet may also be used.

[0375] The display device 1000 is a top-emission type. Light emitted by the light-emitting device is emitted toward the substrate 110. Therefore, it is preferable to use a material that is highly transparent to visible light for the substrate 110. For example, a substrate that is highly transparent to visible light may be selected for the substrate 110 from among substrates that can be used for the substrate 310 and the substrate BS. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0376] By applying the above configuration example to a display device, a display device with high resolution and high definition can be realized. Specifically, for example, display devices with resolutions of HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), and 8K (7680 x 4320 pixels) can be realized. Furthermore, specifically, for example, display devices with resolutions of 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more can be realized.

[0377] Note that the display device of one embodiment of the present invention is not limited to the configuration of the display device 1000 shown in Fig. 20. The display device of one embodiment of the present invention may have an appropriately modified configuration of the display device 1000 shown in Fig. 20. Modifications of the display device of one embodiment of the present invention shown in Fig. 20 will be described below.

[0378] <Configuration example 2 of display device> For example, the pixel layer PXAL of the display device 1000 shown in Fig. 20 may have a configuration in which two or more layers of transistors 500 are stacked. A display device 1000A shown in Fig. 22 is a configuration example in which two layers of transistors 500 included in the pixel layer PXAL of the display device 1000 of Fig. 20 are stacked. Note that the display device 1000A shown in Fig. 22 illustrates only the pixel layer PXAL, and the configuration of the display device 1000 in Fig. 22 can be referred to for the circuit layer SICL and the wiring layer LINL.

[0379] When it is desired to increase the number of transistors included in a pixel in the display device 1000, the configuration shown in a display device 1000A in FIG. 22 may be applied.

[0380] <Configuration Example 3 of Display Device> Furthermore, for example, the circuit layer SICL of the display device 1000 shown in Fig. 20 may have a configuration in which an OS transistor is stacked above the transistor 300. A display device 1000B1 shown in Fig. 23 is a configuration example in which the circuit layer SICL of the display device 1000 shown in Fig. 20 has a transistor 300OS, which is an OS transistor, stacked above the transistor 300. Note that the display device 1000B1 shown in Fig. 23 only illustrates layers including the circuit layer SICL, the wiring layer LINL, and the pixel layer PXAL including the transistor 500, and the configuration of the display device 1000 in Fig. 20 can be referred to for layers including a light-emitting device in the pixel layer PXAL.

[0381] Because it is difficult to fabricate a p-type semiconductor using metal oxide in terms of mobility and reliability, circuits formed with OS transistors are often n-channel unipolar circuits. Therefore, in the display device 1000B1 of FIG. 23, the transistor 300OS can be an n-type transistor, the transistor 300 can be a p-type transistor, and the circuit included in the circuit layer SICL of FIG. 23 can be configured as a CMOS circuit. In particular, a circuit formed with an OS transistor as an n-type transistor and a Si transistor as a p-type transistor is sometimes called an LTPO.

[0382] 20 may have a configuration in which an OS transistor is formed in place of the transistor 300 in the circuit layer SICL of the display device 1000. A display device 1000B2 shown in Fig. 24 is an example configuration in which a transistor 300OS, which is an OS transistor, is formed in place of the transistor 300 in the circuit layer SICL of the display device 1000 of Fig. 20.

[0383] 24, a substrate other than a semiconductor substrate can be used for the substrate 310. For example, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film can be used for the substrate 310. If a heat treatment is included in the manufacturing process of the display device, it is preferable to select a material with high heat resistance for the substrate 310.

[0384] Furthermore, for example, the circuit layer SICL of the display device 1000 shown in Fig. 20 may be configured by bonding a plurality of substrates together. The circuit layer SICL of the display device 1000B4 shown in Fig. 25 includes a substrate 310 and a substrate 310A, and is configured by bonding the upper surface of the substrate 310 to the lower surface of the substrate 310A. Note that Fig. 25 only illustrates the circuit layer SICL and the layer including the transistor 500 of the pixel layer PXAL, and for the wiring layer LINL and the layer including the light-emitting device of the pixel layer PXAL, the configuration of the display device 1000 in Fig. 20 can be referred to.

[0385] In the display device 1000B4 of FIG. 25, the configuration from the substrate 310 to the insulator 326 and the conductor 330 is to be referred to the description of the display device 1000 of FIG.

[0386] Similar to the display device 1000 of FIG. 20, an insulator 350 and an insulator 352 are formed in this order on the insulator 326 and the conductor 330 .

[0387] Furthermore, openings are formed in the insulators 350 and 352 in regions that overlap with a portion of the conductor 330, and a conductor 358 is provided to fill the openings. The conductor 358 is also formed on the insulator 352. Thereafter, the conductor 358 is patterned into a shape such as a wiring, a terminal, or a pad by an etching process or the like.

[0388] For example, copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, etc. can be used as the conductor 358. Note that the conductor 358 is preferably made of the same components as the material used for the conductor 319A described below.

[0389] Next, an insulator 380 is formed to cover the insulator 372 and the conductor 376, and then planarization treatment using a chemical mechanical polishing (CMP) method or the like is performed until the conductor 376 is exposed. In this way, the conductor 376 can be formed on the substrate 310 as a wiring, a terminal, or a pad.

[0390] The insulator 380 is preferably a film (a film having barrier properties) that suppresses the diffusion of impurities such as water and hydrogen. That is, it is preferable to use a material that can be used for the insulator 324 as the insulator 380. Alternatively, for example, similar to the insulator 326, an insulator with a relatively low dielectric constant may be used for the insulator 380 in order to reduce the parasitic capacitance that occurs between wirings. That is, the insulator 380 may be made of a material that can be used for the insulator 326. Furthermore, it is preferable that the insulator 380 be made of the same components as the material used for the insulator 382 described below.

[0391] Next, the substrate 310A will be described. For the substrate 310A, for example, a semiconductor substrate that can be used for the substrate 310 can be used.

[0392] Moreover, transistors, insulators, and conductors are formed on the substrate 310A in the same manner as the substrate 310. Specifically, a transistor 300A is formed on the substrate 310A, an insulator 320A is formed to cover the transistor 300A, and insulators 322A, 324A, 326A, and 350A are formed in this order on the insulator 320A. Note that the insulator 320A can be made of a material that can be used for the insulator 320. Similarly, the insulator 322A can be made of a material that can be used for the insulator 322, the insulator 324A can be made of a material that can be used for the insulator 324, the insulator 326A can be made of a material that can be used for the insulator 326, and the insulator 350A can be made of a material that can be used for the insulator 350.

[0393] Furthermore, a conductor 328A that functions as a plug or wiring is embedded in the insulators 320A and 322A, similar to the conductor 328. Furthermore, a conductor 330A that functions as a plug or wiring is embedded in the insulators 324A and 326A, similar to the conductor 330. Note that a material applicable to the conductor 328 can be used for the conductor 328, and a material applicable to the conductor 330 can be used for the conductor 330A.

[0394] The description of the display device 1000 can be referred to for the configuration above the insulator 350A of the display device 1000B4.

[0395] An insulator 382 is formed on the surface of the substrate 310A opposite to the surface on which the transistor 300A is formed. As described above, the insulator 382 can be made of any of the materials that can be used for the insulator 380.

[0396] In addition to the opening in which the conductor 328A is formed, the insulators 320A and 322A also have openings in regions overlapping the conductor 358. An insulator 318A is formed on the side of the opening formed in the region overlapping the conductor 358, and a conductor 319A is formed in the remaining opening. In particular, the conductor 319A may be called a TSV (Through Silicon Via).

[0397] As described above, the conductor 319A can be made of a material that can be used for the conductor 358. The insulator 318A has a function of insulating the substrate 310A from the conductor 319A, for example. Note that it is preferable to use a material that can be used for the insulator 320 or the insulator 324, for example, as the insulator 318A.

[0398] The insulator 380 and the conductor 358 function as a bonding layer on the substrate 310 side, and the insulator 382 and the conductor 319A function as a bonding layer on the substrate 310A side. That is, the insulator 380 and the conductor 358 formed on the substrate 310 and the insulator 382 and the conductor 319A formed on the substrate 310A can be bonded together by a bonding process, for example.

[0399] As a pre-process before the bonding process, for example, planarization is performed on the substrate 310 side to make the heights of the surfaces of the insulator 380 and the conductor 358 uniform. Similarly, planarization is performed on the substrate 310 side to make the heights of the insulator 382 and the conductor 319A uniform.

[0400] In the bonding process, when bonding the insulator 380 and the insulator 382, ​​that is, bonding the insulating layers together, a hydrophilic bonding method can be used in which high flatness is achieved by polishing (e.g., chemical mechanical polishing (CMP)), and then surfaces that have been hydrophilically treated with oxygen plasma or the like are brought into contact with each other to temporarily bond them, and then the final bonding is performed by dehydrating them through heat treatment. The hydrophilic bonding method also produces bonds at the atomic level, so it is possible to obtain excellent mechanical bonding.

[0401] Furthermore, when bonding conductor 358 and conductor 319A, i.e., bonding conductors together, a surface activation bonding method can be used, in which oxide films and impurity adsorption layers on the surfaces are removed by sputtering or other methods, and cleaned and activated surfaces are brought into contact and bonded. Alternatively, a diffusion bonding method can be used, in which surfaces are bonded using a combination of temperature and pressure. Both methods involve bonding at the atomic level, resulting in excellent bonding not only electrically but also mechanically.

[0402] By performing the above-described bonding process, the conductor 358 on the substrate 310 side can be electrically connected to the conductor 319A on the substrate 310A side. Also, a connection with sufficient mechanical strength can be obtained between the insulator 380 on the substrate 310 side and the insulator 382 on the substrate 310A side.

[0403] When bonding the substrates 310 and 310A, since the bonding surfaces of each substrate contain a mixture of insulating and metal layers, a surface activated bonding method and a hydrophilic bonding method may be combined. For example, a bonding method may be used in which the surfaces are polished and then cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment, followed by a hydrophilic treatment. Alternatively, the surface of the metal layer may be made of a resistant metal such as gold and then subjected to a hydrophilic treatment.

[0404] Note that bonding methods other than those described above may be used to bond the substrates 310 and 310A. For example, flip-chip bonding may be used to bond the substrates 310 and 310A. Furthermore, when using flip-chip bonding, connection terminals such as bumps may be provided above the conductor 358 on the substrate 310 side or below the conductor 319A on the substrate 310A side. Examples of flip-chip bonding include a method in which a resin containing anisotropic conductive particles is injected between the insulators 380 and 382 and between the conductors 358 and 319A to form a bond, or a method in which silver-tin solder is used to form a bond. Alternatively, when the bumps and the conductors connected to the bumps are both made of gold, ultrasonic bonding may be used. Furthermore, in order to reduce physical stress such as impact or thermal stress, in addition to the above flip-chip bonding method, an underfill agent may be injected between insulator 380 and insulator 382 and between conductor 358 and conductor 319A. Furthermore, for example, a die bonding film may be used to bond substrate 310 and substrate 310A together.

[0405] <Configuration Example 4 of Display Device> Furthermore, for example, the protective layer 131 of the display device 1000 shown in FIG. 20 may have a stacked structure of two or more layers instead of a single layer. The protective layer 131 may have a three-layer stacked structure, for example, where an inorganic insulator is used as the first layer, an organic insulator is used as the second layer, and an inorganic insulator is used as the third layer. FIG. 26 illustrates a cross-sectional view of a portion of a display device 1000E in which the protective layer 131 has a multilayer structure including the protective layer 131a, the protective layer 131b, and the protective layer 131c, where the protective layer 131a is an insulator of an inorganic material, the protective layer 131b is an insulator of an organic material, and the protective layer 131c is an insulator of an inorganic material. As shown in FIG. 26, by using an organic insulator for the protective layer 131b, the protective layer 131b can be provided as a planarizing film.

[0406] <Configuration Example 5 of Display Device> For example, the display device 1000 of FIG. 20 may include a color layer (color filter). As an example, the display device 1000F of FIG. 27 includes color layers 166a, 166b, and 166c between the adhesive layer 107 and the substrate 110. The color layers 166a to 166c can be formed on the substrate 110, for example. In addition, when the light-emitting device 130R has a light-emitting layer that emits red (R), the light-emitting device 130G has a light-emitting layer that emits green (G), and the light-emitting device 130B has a light-emitting layer that emits blue (B), the color layer 166a is red, the color layer 166b is green, and the color layer 166c is blue.

[0407] <Configuration Example 6 of Display Device> Furthermore, for example, the display device 1000 in Fig. 20 may include an imaging pixel. For example, a display device 1000G shown in Fig. 28 is configured to have a light receiving device 150 that detects light L and is included in the imaging pixel.

[0408] For example, a pn-type or pin-type photodiode can be used as the light-receiving device 150. The light-receiving device 150 functions as a photoelectric conversion device that detects light incident on the light-receiving device 150 and generates electric charges. The amount of electric charges generated by the photoelectric conversion element is determined according to the amount of incident light.

[0409] In particular, it is preferable to use an organic photodiode having a layer containing an organic compound as the light-receiving device 150. Organic photodiodes can be easily made thin, lightweight, and large in area, and have a high degree of freedom in shape and design, making them applicable to a variety of devices.

[0410] The light receiving device 150 has a conductor 112d, a conductor 126d on the conductor 112d, and a conductor 129d on the conductor 126d. All of the conductors 112d, 126d, and 129d can be called pixel electrodes, or some of them can be called pixel electrodes.

[0411] The light-receiving device 150 also has a conductor 112 d on the insulator 599 , a layer 113 d on the conductor 112 d , a common layer 114 on the layer 113 d , and a common electrode 115 on the common layer 114 .

[0412] The layer 113d includes a photoelectric conversion layer having sensitivity to a wavelength region of visible light or infrared light. The wavelength region to which the photoelectric conversion layer of the layer 113d is sensitive may include one or more of the wavelength region of the light emitted by the first layer 113a, the wavelength region of the light emitted by the second layer 113b, and the wavelength region of the light emitted by the third layer 113c.

[0413] As in the display device 1000G shown in FIG. 28, the display device DP in FIG. 1B can be configured by providing a light receiving device 150 in the pixel layer PXAL.

[0414] <Configuration Example of Light-Emitting Device> Next, a configuration example of a light-emitting device that can be applied to the above-described display device will be described.

[0415] 29A, the light-emitting device has an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 can include a layer 780, a light-emitting layer 771, and a layer 790.

[0416] The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

[0417] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layer 780 includes one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a substance with high hole-transporting properties (hole-transporting layer), and a layer containing a substance with high electron-blocking properties (electron-blocking layer). The layer 790 also includes one or more of a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing a substance with high electron-transporting properties (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer). When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780 and 790 have the opposite structures to those described above.

[0418] A structure including the layer 780, the light-emitting layer 771, and the layer 790 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 29A is referred to as a single structure in this specification.

[0419] 29B shows a modified example of the EL layer 763 of the light-emitting device shown in Fig. 29A. Specifically, the light-emitting device shown in Fig. 29B has a layer 781 on a lower electrode 761, a layer 782 on the layer 781, a light-emitting layer 771 on the layer 782, a layer 791 on the light-emitting layer 771, a layer 792 on the layer 791, and an upper electrode 762 on the layer 792.

[0420] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 781 can be a hole injection layer, the layer 782 can be a hole transport layer, the layer 791 can be an electron transport layer, and the layer 792 can be an electron injection layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layer 781 can be an electron injection layer, the layer 782 can be an electron transport layer, the layer 791 can be a hole transport layer, and the layer 792 can be a hole injection layer. Such a layer structure allows carriers to be efficiently injected into the light-emitting layer 771, and the efficiency of carrier recombination in the light-emitting layer 771 can be increased.

[0421] 29C and 29D, a variation of the single structure is a configuration in which multiple light-emitting layers (light-emitting layer 771, light-emitting layer 772, and light-emitting layer 773) are provided between layer 780 and layer 790. While an example having three light-emitting layers is shown in FIGS. 29C and 29D, the number of light-emitting layers in a single-structure light-emitting device may be two, or may be four or more. Furthermore, a light-emitting device with a single structure may have a buffer layer between the two light-emitting layers.

[0422] 29E and 29F, a configuration in which a plurality of light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785 (also referred to as an intermediate layer) is referred to as a tandem structure in this specification. Note that the tandem structure may also be referred to as a stack structure. By using a tandem structure, a light-emitting device capable of emitting high-luminance light can be obtained. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same luminance, thereby improving reliability.

[0423] 29D and 29F are examples of display devices having a layer 764 overlapping with the light-emitting device. Fig. 29D is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 29C, and Fig. 29F is an example in which the layer 764 overlaps with the light-emitting device shown in Fig. 29E.

[0424] The layer 764 can be a color conversion layer, a color filter (coloring layer), or both.

[0425] 29C and 29D , the light-emitting layers 771, 772, and 773 may be made of light-emitting materials that emit light of the same color, or even the same light-emitting material. For example, the light-emitting layers 771, 772, and 773 may be made of a light-emitting material that emits blue light. In the subpixel that emits blue light, blue light emitted by the light-emitting device can be extracted. In the subpixel that emits red light and the subpixel that emits green light, a color conversion layer is provided as the layer 764 shown in FIG. 29D to convert blue light emitted by the light-emitting device into light with a longer wavelength, thereby allowing red or green light to be extracted.

[0426] Furthermore, light-emitting materials emitting light of different colors may be used for the light-emitting layers 771, 772, and 773. When the lights emitted by the light-emitting layers 771, 772, and 773 are complementary in color, white light can be obtained. For example, a light-emitting device with a single structure preferably has a light-emitting layer containing a light-emitting material emitting blue light and a light-emitting layer containing a light-emitting material emitting visible light with a wavelength longer than blue.

[0427] For example, when a light-emitting device with a single structure has three light-emitting layers, it preferably has a light-emitting layer containing a light-emitting material that emits red (R) light, a light-emitting layer containing a light-emitting material that emits green (G) light, and a light-emitting layer containing a light-emitting material that emits blue (B) light. The stacking order of the light-emitting layers can be, for example, red (R), green (G), and blue (B) from the anode side, or red (R), green (B), and blue (G) from the anode side. In this case, a buffer layer may be provided between the red (R) and the green (G) or blue (B) layers.

[0428] Furthermore, for example, when a light-emitting device with a single structure has two light-emitting layers, a structure having one light-emitting layer containing a light-emitting substance that emits blue (B) light and another light-emitting layer containing a light-emitting substance that emits yellow (Y) light is preferred. This structure is sometimes referred to as a BY single structure.

[0429] A color filter may be provided as layer 764 shown in Figure 29D. When white light passes through the color filter, light of a desired color can be obtained.

[0430] A light-emitting device that emits white light preferably contains two or more types of light-emitting materials. To obtain white light emission, light-emitting materials can be selected so that the light emitted from each of the two or more light-emitting materials has a complementary color relationship. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a light-emitting device that emits white light as a whole can be obtained. The same applies to a light-emitting device having three or more light-emitting layers.

[0431] 29E and 29F, the light-emitting layer 771 and the light-emitting layer 772 may be made of a light-emitting material that emits light of the same color, or even the same light-emitting material.

[0432] For example, in the light-emitting devices included in the subpixels emitting light of each color, light-emitting materials emitting blue light may be used for the light-emitting layers 771 and 772. In the subpixel emitting blue light, the blue light emitted by the light-emitting device can be extracted. In the subpixel emitting red light and the subpixel emitting green light, a color conversion layer is provided as the layer 764 shown in FIG. 29F to convert the blue light emitted by the light-emitting device into light with a longer wavelength, thereby allowing red or green light to be extracted.

[0433] Furthermore, when the light-emitting devices having the configurations shown in FIG. 29E or 29F are used for the subpixels emitting light of each color, different light-emitting materials may be used for each subpixel. Specifically, in a light-emitting device included in a subpixel emitting red light, light-emitting layers 771 and 772 may each contain a light-emitting material that emits red light. Similarly, in a light-emitting device included in a subpixel emitting green light, light-emitting layers 771 and 772 may each contain a light-emitting material that emits green light. In a light-emitting device included in a subpixel emitting blue light, light-emitting layers 771 and 772 may each contain a light-emitting material that emits blue light. A display device having such a configuration can be said to employ a tandem-structure light-emitting device and also have an SBS structure. Therefore, it can have the advantages of both the tandem structure and the SBS structure. This allows for a highly reliable light-emitting device to be realized.

[0434] 29E and 29F, light-emitting materials that emit light of different colors may be used for the light-emitting layer 771 and the light-emitting layer 772. When the light emitted by the light-emitting layer 771 and the light emitted by the light-emitting layer 772 are complementary colors, white light can be obtained. A color filter may be provided as the layer 764 shown in FIG. 29F. When white light passes through the color filter, light of a desired color can be obtained.

[0435] 29E and 29F show an example in which the light-emitting unit 763a has one light-emitting layer 771 and the light-emitting unit 763b has one light-emitting layer 772, but this is not limiting. Each of the light-emitting unit 763a and the light-emitting unit 763b may have two or more light-emitting layers.

[0436] 29E and 29F show examples of light emitting devices having two light emitting units, but the present invention is not limited to this. The light emitting device may have three or more light emitting units.

[0437] Specifically, the light-emitting device configurations shown in FIGS. 30A to 30C can be given.

[0438] 30A shows a configuration having three light-emitting units. Note that a configuration having two light-emitting units may be called a two-stage tandem structure, and a configuration having three light-emitting units may be called a three-stage tandem structure.

[0439] 30A , a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series via charge generation layers 785 (charge generation layers 785a-b and charge generation layers 785b-c). Specifically, the light-emitting device shown in FIG. 30A has a configuration in which light-emitting unit 763a, charge generation layers 785a-b, light-emitting unit 763b, charge generation layers 785b-c, and light-emitting unit 763c are stacked in this order. Furthermore, light-emitting unit 763a has layer 780a, light-emitting layer 771, and layer 790a; light-emitting unit 763b has layer 780b, light-emitting layer 772, and layer 790b; and light-emitting unit 763c has layer 780c, light-emitting layer 773, and layer 790c.

[0440] Note that the description of the charge generation layer 785 described above can be referred to for the charge generation layers 785a-b and 785b-c.

[0441] 30A , it is preferable that the light-emitting layers 771, 772, and 773 each contain a light-emitting material that emits light of the same color. Specifically, the light-emitting layers 771, 772, and 773 may each contain a red (R) light-emitting material (a so-called R\R\R three-stage tandem structure), the light-emitting layers 771, 772, and 773 may each contain a green (G) light-emitting material (a so-called G\G\G three-stage tandem structure), or the light-emitting layers 771, 772, and 773 may each contain a blue (B) light-emitting material (a so-called B\B\B three-stage tandem structure).

[0442] Note that the light-emitting materials that emit light of the same color are not limited to the above configuration. For example, as shown in FIG. 30B , a tandem light-emitting device may be used in which light-emitting units having a plurality of light-emitting materials are stacked. FIG. 30B shows a configuration in which a plurality of light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785. Furthermore, light-emitting unit 763a includes layer 780a, light-emitting layer 771a, light-emitting layer 771b, light-emitting layer 771c, and layer 790a. Light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b.

[0443] In the structure shown in FIG. 30B , light-emitting layers 771a, 771b, and 771c are configured to emit white light (W) by selecting light-emitting materials that are complementary to each other. Light-emitting layers 772a, 772b, and 772c are configured to emit white light (W) by selecting light-emitting materials that are complementary to each other. That is, the structure shown in FIG. 30C has a W\W two-tier tandem structure. Note that the stacking order of the light-emitting materials that are complementary to each other in light-emitting layers 771a, 771b, and 771c is not particularly limited. The implementer can select the optimal stacking order as appropriate. Although not shown, a W\W\W three-tier tandem structure or a four-tier or more tier tandem structure may also be used.

[0444] In addition, when a light-emitting device with a tandem structure is used, there are a B\Y two-stage tandem structure having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, a RG\B two-stage tandem structure having a light-emitting unit that emits red (R) and green (G) light and a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, and a light-emitting unit that emits blue (B) light. and a B\Y\B three-stage tandem structure having, in this order, a light-emitting unit that emits blue (B) light, a light-emitting unit that emits yellow-green (YG) light, and a light-emitting unit that emits blue (B) light; and a B\G\B three-stage tandem structure having, in this order, a light-emitting unit that emits blue (B) light, a light-emitting unit that emits green (G) light, and a light-emitting unit that emits blue (B) light.

[0445] Furthermore, as shown in FIG. 30C, a light-emitting unit having one light-emitting substance and a light-emitting unit having a plurality of light-emitting substances may be combined.

[0446] 30C , a plurality of light-emitting units (light-emitting unit 763 a, light-emitting unit 763 b, and light-emitting unit 763 c) are connected in series via charge generation layers (charge generation layers 785 a-b and charge generation layers 785 b-c). Light-emitting unit 763 a includes layer 780 a, light-emitting layer 771, and layer 790 a. Light-emitting unit 763 b includes layer 780 b, light-emitting layer 772 a, light-emitting layer 772 b, light-emitting layer 772 c, and layer 790 b. Light-emitting unit 763 c includes layer 780 c, light-emitting layer 773, and layer 790 c.

[0447] For example, in the configuration shown in Figure 30C, a three-stage tandem structure of B\R·G·YG\B can be applied, in which light-emitting unit 763a is a light-emitting unit that emits blue (B) light, light-emitting unit 763b is a light-emitting unit that emits red (R), green (G), and yellow-green (YG) light, and light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0448] For example, the order of the number of layers of the light-emitting units and the colors can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B. The order of the number of layers of the light-emitting layers in light-emitting unit X and the colors can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. Furthermore, another layer can be provided between the two light-emitting layers.

[0449] 29C and 29D, the layer 780 and the layer 790 may each independently have a laminated structure made up of two or more layers, as shown in FIG. 29B.

[0450] 29E and 29F, the light-emitting unit 763a includes a layer 780a, a light-emitting layer 771, and a layer 790a, and the light-emitting unit 763b includes a layer 780b, a light-emitting layer 772, and a layer 790b.

[0451] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, the layers 780a and 780b each have one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. The layers 790a and 790b each have one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, the layers 780a and 790a have the opposite structures to those described above, and the layers 780b and 790b also have the opposite structures to those described above.

[0452] When the lower electrode 761 is an anode and the upper electrode 762 is a cathode, for example, the layer 780a may have a hole injection layer, a hole transport layer on the hole injection layer, and an electron blocking layer on the hole transport layer. The layer 790a may have an electron transport layer and a hole blocking layer between the light-emitting layer 771 and the electron transport layer. The layer 780b may have a hole transport layer and an electron blocking layer on the hole transport layer. The layer 790b may have an electron transport layer, an electron injection layer on the electron transport layer, and a hole blocking layer between the light-emitting layer 772 and the electron transport layer. When the lower electrode 761 is a cathode and the upper electrode 762 is an anode, for example, the layer 780a may have an electron injection layer, an electron transport layer on the electron injection layer, and an electron blocking layer on the electron transport layer. Layer 790a has a hole transport layer and may further have an electron blocking layer between light-emitting layer 771 and the hole transport layer. Layer 780b has an electron transport layer and may further have a hole blocking layer on the electron transport layer. Layer 790b has a hole transport layer and a hole injection layer on the hole transport layer and may further have an electron blocking layer between light-emitting layer 772 and the hole transport layer.

[0453] When a light-emitting device having a tandem structure is fabricated, two light-emitting units are stacked via a charge generation layer 785. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes.

[0454] Next, materials that can be used in light-emitting devices will be described.

[0455] Of the lower electrode 761 and the upper electrode 762, a conductive film that transmits visible light is used for the electrode from which light is extracted. A conductive film that reflects visible light is preferably used for the electrode from which light is not extracted. When the display device has a light-emitting device that emits infrared light, a conductive film that transmits visible light and infrared light is preferably used for the electrode from which light is extracted, and a conductive film that reflects visible light and infrared light is preferably used for the electrode from which light is not extracted.

[0456] A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, the electrode is preferably disposed between the reflective layer and the EL layer 763. That is, light emitted from the EL layer 763 may be reflected by the reflective layer and extracted from the display device.

[0457] Materials for forming the pair of electrodes of a light-emitting device can include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing appropriate combinations of these metals. Examples of such materials include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Examples of such materials include aluminum-containing alloys (aluminum alloys). Examples of aluminum-containing alloys include, for example, alloys of aluminum (Al), nickel (Ni), and lanthanum (La) (Al-Ni-La). Examples of such materials include an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).Other examples of such materials include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these elements, and graphene.

[0458] The light-emitting device preferably has a micro-optical resonator (microcavity) structure. Therefore, one of a pair of electrodes of the light-emitting device preferably has a transmissive and reflective electrode for visible light, and the other preferably has a reflective electrode for visible light. By having the light-emitting device have a microcavity structure, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting device.

[0459] The semi-transmitting / semi-reflective electrode is preferably made of, for example, a conductor that is transmissive and reflective to visible light. Alternatively, the semi-transmitting / semi-reflective electrode may have a stacked structure of a conductive layer that can be used as a reflective electrode and a conductive layer that can be used as an electrode that is transmissive to visible light (also referred to as a transparent electrode).

[0460] The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of a light-emitting device. The visible light reflectance of the semi-transmissive / semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is 1×10 −２ Preferably, it is Ωcm or less.

[0461] The light-emitting device has at least a light-emitting layer. The light-emitting device may further include a layer containing a substance with high hole-injection properties, a substance with high hole-transport properties, a hole-blocking material, a substance with high electron-transport properties, an electron-blocking material, a substance with high electron-injection properties, or a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) as a layer other than the light-emitting layer. For example, the light-emitting device may have a configuration including, in addition to the light-emitting layer, one or more layers selected from a hole-injection layer, a hole-transport layer, a hole-blocking layer, a charge-generating layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer.

[0462] The light-emitting device can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting device can be formed by a method such as vapor deposition (including vacuum vapor deposition), a transfer method, a printing method, an inkjet method, or a coating method.

[0463] The light-emitting layer contains one or more light-emitting materials. For example, a material that emits light of blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a material that emits near-infrared light can also be used as the light-emitting material.

[0464] The luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0465] Examples of fluorescent materials include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0466] Examples of phosphorescent materials include organometallic complexes (particularly iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; organometallic complexes (particularly iridium complexes) having a phenylpyridine derivative having an electron-withdrawing group as a ligand; platinum complexes; and rare earth metal complexes.

[0467] The light-emitting layer may contain one or more organic compounds (e.g., a host material and an assist material) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used. As the hole-transporting material, a material with high hole transport properties that can be used in a hole-transporting layer, which will be described later, can be used. As the electron-transporting material, a material with high electron transport properties that can be used in an electron-transporting layer, which will be described later, can be used. Furthermore, as the one or more organic compounds, a bipolar material or a TADF material may be used.

[0468] The light-emitting layer preferably includes, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material that are a combination that easily forms an exciplex. This configuration allows for efficient emission using Exciplex-Triple Energy Transfer (ExTET), which is energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest-energy absorption band of the light-emitting material, the energy transfer becomes smooth, allowing for efficient emission. This configuration allows for high efficiency, low-voltage operation, and a long life of the light-emitting device to be achieved simultaneously.

[0469] The hole injection layer is a layer that injects holes from the anode into the hole transport layer and contains a material with high hole injection properties, such as an aromatic amine compound and a composite material containing a hole transport material and an acceptor material (electron acceptor material).

[0470] As the hole transporting material, a material having high hole transporting properties that can be used for the hole transport layer, which will be described later, can be used.

[0471] As the acceptor material, for example, an oxide of a metal belonging to Groups 4 to 8 of the periodic table can be used. Specific examples of the metal oxide include molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide, and rhenium oxide. Among these, molybdenum oxide is particularly preferred because it is stable in the air, has low hygroscopicity, and is easy to handle. Alternatively, an organic acceptor material containing fluorine can be used. Alternatively, an organic acceptor material such as a quinodimethane derivative, a chloranil derivative, or a hexaazatriphenylene derivative can be used.

[0472] For example, as a material with high hole injection properties, a material containing a hole transporting material and an oxide of a metal belonging to Groups 4 to 8 of the periodic table (typically, molybdenum oxide) may be used.

[0473] The hole transport layer is a layer that transports holes injected from the anode by the hole injection layer to the light emitting layer. The hole transport layer is a layer that contains a hole transport material. The hole transport material is a material having a concentration of 1×10 −６ cm ２ A substance having a hole mobility of 1 / Vs or more is preferred. Note that other substances can also be used as long as they have a higher hole transporting property than electron transporting property. As the hole transporting material, a material having a high hole transporting property, such as a π-electron-rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, and a furan derivative) or an aromatic amine (a compound having an aromatic amine skeleton), is preferred.

[0474] The electron blocking layer is provided in contact with the light-emitting layer. The electron blocking layer is a layer containing a material that has hole transport properties and can block electrons. The electron blocking layer can be made of a material that has electron blocking properties among the hole transport materials described above.

[0475] The electron blocking layer has hole transport properties and can therefore also be called a hole transport layer. Furthermore, a layer of the hole transport layer that has electron blocking properties can also be called an electron blocking layer.

[0476] The electron transport layer is a layer that transports electrons injected from the cathode by the electron injection layer to the light emitting layer. The electron transport layer is a layer that contains an electron transporting material. The electron transporting material is a material having a molecular weight of 1×10 −６ cm ２ / Vs or more is preferred. Note that other materials can also be used as long as they have a higher electron transporting property than holes. Examples of the electron-transporting material include metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, and metal complexes having a thiazole skeleton, as well as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives having a quinoline ligand, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, and π-electron-deficient heteroaromatic compounds including nitrogen-containing heteroaromatic compounds.

[0477] The hole-blocking layer is provided in contact with the light-emitting layer. The hole-blocking layer is a layer containing a material that has electron transport properties and can block holes. The hole-blocking layer can be made of a material that has hole-blocking properties and is selected from the above electron-transporting materials.

[0478] The hole blocking layer has electron transport properties and can therefore also be called an electron transport layer. Furthermore, a layer of the electron transport layer that has hole blocking properties can also be called a hole blocking layer.

[0479] The electron injection layer is a layer that injects electrons from the cathode to the electron transport layer and contains a material with high electron injection properties. Examples of the material with high electron injection properties include alkali metals, alkaline earth metals, and compounds thereof. Examples of the material with high electron injection properties include a composite material containing an electron transport material and a donor material (electron donor material).

[0480] Furthermore, it is preferable that the lowest unoccupied molecular orbital (LUMO) level of the material having high electron injection properties has a small difference (specifically, 0.5 eV or less) from the work function value of the material used for the cathode.

[0481] The electron injection layer may contain, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ｘ , where X is an arbitrary number), 8-(quinolinolato)lithium (abbreviation: Liq), 2-(2-pyridyl)phenolatolithium (abbreviation: LiPP), 2-(2-pyridyl)-3-pyridinolatolithium (abbreviation: LiPPy), 4-phenyl-2-(2-pyridyl)phenolatolithium (abbreviation: LiPPP), lithium oxide (LiO ｘ The electron injection layer may be formed of an alkali metal, such as lithium fluoride, cesium carbonate, or an alkaline earth metal, or a compound thereof. The electron injection layer may have a stacked structure of two or more layers. For example, the stacked structure may include a structure in which lithium fluoride is used as a first layer and ytterbium is provided as a second layer.

[0482] The electron injection layer may contain an electron transporting material. For example, a compound having an unshared electron pair and an electron-deficient heteroaromatic ring can be used as the electron transporting material. Specifically, a compound having one or more rings selected from a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

[0483] The LUMO level of an organic compound having an unshared electron pair is preferably −3.6 eV or more and −2.3 eV or less. Generally, the highest occupied molecular orbital (HOMO) level and the LUMO level of an organic compound can be estimated by CV (cyclic voltammetry), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

[0484] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalen-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviation: HATNA), or 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz) can be used as the organic compound having an unshared electron pair. Note that NBPhen has a higher glass transition temperature (Tg) and is more heat resistant than BPhen.

[0485] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably contains an acceptor material, for example, a hole transport material and an acceptor material applicable to the hole injection layer.

[0486] The charge generation layer preferably includes a layer containing a material with high electron injection properties. This layer may also be called an electron injection buffer layer. The electron injection buffer layer is preferably provided between the charge generation region and the electron transport layer. By providing the electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be alleviated, so that electrons generated in the charge generation region can be easily injected into the electron transport layer.

[0487] The electron injection buffer layer preferably contains an alkali metal or an alkaline earth metal, and may contain, for example, an alkali metal compound or an alkaline earth metal compound. Specifically, the electron injection buffer layer preferably contains an inorganic compound containing an alkali metal and oxygen, or an inorganic compound containing an alkaline earth metal and oxygen, and may contain an inorganic compound containing lithium and oxygen (for example, lithium oxide (Li ２ In addition, the electron injection buffer layer can be suitably made of the materials applicable to the electron injection layer described above.

[0488] The charge generation layer preferably has a layer containing a material with high electron transport properties. This layer can also be called an electron relay layer. The electron relay layer is preferably provided between the charge generation region and the electron injection buffer layer. When the charge generation layer does not have an electron injection buffer layer, the electron relay layer is preferably provided between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing interaction between the charge generation region and the electron injection buffer layer (or the electron transport layer) and smoothly transferring electrons.

[0489] For the electron relay layer, it is preferable to use a phthalocyanine-based material such as copper (II) phthalocyanine (abbreviated as CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0490] It should be noted that the charge generation region, electron injection buffer layer, and electron relay layer may not be clearly distinguishable from one another depending on their cross-sectional shapes or characteristics.

[0491] The charge generation layer may contain a donor material instead of an acceptor material. For example, the charge generation layer may contain a layer containing an electron transport material and a donor material that can be used for the electron injection layer.

[0492] When light-emitting units are stacked, an increase in driving voltage can be suppressed by providing a charge generating layer between two light-emitting units.

[0493] <Configuration Example of Pixel Circuit> Here, a configuration example of a pixel circuit that can be provided in the pixel layer PXAL will be described.

[0494] 31A and 31B show a configuration example of a pixel circuit that can be provided in the pixel layer PXAL and a light-emitting device 130 connected to the pixel circuit. Also, FIG. 31A is a diagram showing the connections of each circuit element included in the pixel circuit 400 provided in the pixel layer PXAL, and FIG. 31B is a diagram schematically showing the hierarchical relationship of a circuit layer SICL including a drive circuit 410, a layer OSL including multiple transistors of the pixel circuit, and a layer EML including a light-emitting device 130. Note that the pixel layer PXAL of the display device 1000 shown in FIG. 31B includes, as an example, a layer OSL and a layer EML. Also, the transistors 500A, 500B, and 500C included in the layer OSL shown in FIG. 31B correspond to the transistor 500 in FIG. 20. Also, the light-emitting device 130 included in the layer EML shown in FIG. 31B corresponds to the light-emitting device 130R, the light-emitting device 130G, or the light-emitting device 130B in FIG. 20.

[0495] 31A and 31B includes a pixel circuit 400 including a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. The transistors 500A, 500B, and 500C can be transistors applicable to the transistor 200 described above, for example. That is, the transistors 500A, 500B, and 500C can be Si transistors or Si transistors. Alternatively, the transistors 500A, 500B, and 500C can be transistors applicable to the transistor 500 described above, for example. That is, the transistors 500A, 500B, and 500C can be OS transistors or Si transistors. In particular, when the transistors 500A, 500B, and 500C are OS transistors, each of the transistors 500A, 500B, and 500C preferably includes a back gate electrode. In this case, the back gate electrode may be supplied with the same signal as the gate electrode, or may be supplied with a different signal from the gate electrode. Note that although the transistors 500A, 500B, and 500C each include a back gate electrode in FIGS. 31A and 31B, the transistors 500A, 500B, and 500C may not include a back gate electrode.

[0496] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light-emitting device 130, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for applying a potential for supplying a current to the light-emitting device 130.

[0497] The transistor 500A has a first terminal electrically connected to the gate electrode of the transistor 500B, a second terminal electrically connected to the wiring SL that functions as a source line, and a gate electrode that has the function of controlling the on / off state based on the potential of the wiring GL1 that functions as a gate line.

[0498] The transistor 500C includes a first terminal electrically connected to a wiring V0, a ​​second terminal electrically connected to the light-emitting device 130, and a gate electrode having a function of controlling the on / off state based on the potential of a wiring GL2 functioning as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 400 to the driver circuit 410.

[0499] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0500] The light-emitting device 130 includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for applying a potential for supplying a current to the light-emitting device 130.

[0501] This allows the intensity of light emitted by light-emitting device 130 to be controlled in accordance with an image signal applied to the gate electrode of transistor 500B. Furthermore, the reference potential of wiring V0 applied via transistor 500C can suppress variations in the gate-source voltage of transistor 500B.

[0502] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 500B or the current flowing through the light-emitting device 130 to the outside. The current output to the wiring V0 is converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, the current can be converted into a digital signal by, for example, an A-D converter or the like and output to a circuit that performs color adjustment or dimming (sometimes called a correction circuit) or a GPU.

[0503] In the configuration shown as an example in FIG. 31B , the wiring electrically connecting the pixel circuit 400 and the driver circuit 410 can be shortened, thereby reducing the wiring resistance of the wiring. Therefore, data can be written at high speed, allowing the display device 1000 to be driven at high speed. This allows a sufficient frame period to be ensured even if the display device 1000 has a large number of pixel circuits 400, thereby increasing the pixel density of the display device 1000. Furthermore, increasing the pixel density of the display device 1000 can increase the resolution of the image displayed by the display device 1000. For example, the pixel density of the display device 1000 can be set to 1000 ppi or more, 5000 ppi or more, or 7000 ppi or more. Therefore, the display device 1000 can be used as a display device for AR or VR, for example, and can be suitably applied to electronic devices in which the display unit is close to the user, such as a head-mounted display.

[0504] 31A and 31B show an example of the pixel circuit 400 including three transistors in total, but the pixel circuit of the electronic device of one embodiment of the present invention is not limited to this. Below, a configuration example of a pixel circuit that can be applied to the pixel circuit 400 will be described.

[0505] The pixel circuit 400A shown in Fig. 32A includes a transistor 500A, a transistor 500B, and a capacitor 600. Fig. 32A also illustrates a light-emitting device 130 connected to the pixel circuit 400A. The pixel circuit 400A is electrically connected to a wiring SL, a wiring GL, a wiring ANO, and a wiring VCOM.

[0506] The transistor 500A has a gate electrically connected to a wiring GL, one of its source and drain electrically connected to a wiring SL, and the other electrically connected to the gate of the transistor 500B and one electrode of the capacitor 600. The transistor 500B has one of its source and drain electrically connected to a wiring ANO, and the other electrically connected to the anode of the light-emitting device 130. The capacitor 600 has the other electrode electrically connected to the anode of the light-emitting device 130. The light-emitting device 130 has a cathode electrically connected to a wiring VCOM.

[0507] 32B has a configuration in which a transistor 500C is added to the pixel circuit 400A. A wiring V0 is electrically connected to the pixel circuit 400B.

[0508] The pixel circuit 400C shown in FIG. 32C is an example in which the transistors 500A and 500B in the pixel circuit 400A are transistors whose gates and back gates are electrically connected. The pixel circuit 400D shown in FIG. 32D is an example in which the same transistors are used in the pixel circuit 400B. This allows the current that the transistors can pass to be increased. Note that, although all the transistors in this example have a pair of gates electrically connected, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to a source.

[0509] 33A has a configuration in which a transistor 500D is added to the pixel circuit 400B described above. The pixel circuit 400E is electrically connected to three wirings (a wiring GL1, a wiring GL2, and a wiring GL3) that function as gate lines.

[0510] The gate of the transistor 500D is electrically connected to a wiring GL3, one of the source and drain of the transistor 500D is electrically connected to the gate of the transistor 500B, and the other is electrically connected to a wiring V0. The gate of the transistor 500A is electrically connected to a wiring GL1, and the gate of the transistor 500C is electrically connected to a wiring GL2.

[0511] By simultaneously turning on the transistors 500C and 500D, the source and gate of the transistor 500B have the same potential, and the transistor 500B can be turned off. This forcibly cuts off the current flowing through the light-emitting device 130. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0512] 33B is an example in which a capacitor 600A is added to the pixel circuit 400E. The capacitor 600A functions as a storage capacitor.

[0513] 33C and 33D are examples in which transistors whose gates and back gates are electrically connected are applied to the pixel circuit 400E or 400F, respectively. Transistors whose gates and back gates are electrically connected are applied to transistors 500A, 500C, and 500D, and a transistor whose gate is electrically connected to its source is applied to transistor 500B.

[0514] <Pixel Layout> Here, the pixel layout will be described. There are no particular limitations on the arrangement of sub-pixels, and various methods can be applied. Examples of the arrangement of sub-pixels include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0515] Examples of the top surface shape of the subpixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, a polygon with rounded corners, an ellipse, and a circle. Here, the top surface shape of the subpixel corresponds to the top surface shape of the light-emitting region of the light-emitting device.

[0516] A stripe arrangement is applied to the pixel 80 shown in Fig. 34A. The pixel 80 shown in Fig. 34A is composed of three subpixels: subpixel 80a, subpixel 80b, and subpixel 80c. For example, as shown in Fig. 35A, the subpixel 80a may be a red subpixel R, the subpixel 80b may be a green subpixel G, and the subpixel 80c may be a blue subpixel B.

[0517] An S-stripe arrangement is applied to the pixel 80 shown in Fig. 34B. The pixel 80 shown in Fig. 34B is composed of three subpixels: subpixel 80a, subpixel 80b, and subpixel 80c. For example, as shown in Fig. 35B, the subpixel 80a may be a blue subpixel B, the subpixel 80b may be a red subpixel R, and the subpixel 80c may be a green subpixel G.

[0518] 34C shows an example in which subpixels of each color are arranged in a zigzag pattern. Specifically, when viewed from above, the positions of the upper edges of two subpixels aligned in the column direction (e.g., subpixels 80a and 80b, or subpixels 80b and 80c) are misaligned. For example, as shown in FIG. 35C , subpixel 80a may be a red subpixel R, subpixel 80b may be a green subpixel G, and subpixel 80c may be a blue subpixel B.

[0519] The pixel 80 shown in FIG. 34D includes a subpixel 80a having a generally trapezoidal top surface shape with rounded corners, a subpixel 80b having a generally triangular top surface shape with rounded corners, and a subpixel 80c having a generally rectangular or hexagonal top surface shape with rounded corners. Furthermore, the subpixel 80a has a larger light-emitting area than the subpixel 80b. In this manner, the shape and size of each subpixel can be determined independently. For example, the more reliable the light-emitting device, the smaller the size can be. For example, as shown in FIG. 35D, the subpixel 80a may be a green subpixel G, the subpixel 80b may be a red subpixel R, and the subpixel 80c may be a blue subpixel B.

[0520] The pixel 70A and pixel 70B shown in Figure 34E are arranged in a Pentile array. Figure 34E shows an example in which pixel 70A having subpixels 80a and 80b and pixel 70B having subpixels 80b and 80c are arranged alternately. For example, as shown in Figure 35E, subpixel 80a may be a red subpixel R, subpixel 80b may be a green subpixel G, and subpixel 80c may be a blue subpixel B.

[0521] Pixels 70A and 70B shown in Figures 34F and 34G are arranged in a delta configuration. Pixel 70A has two subpixels (subpixels 80a and 80b) in the top row (first row) and one subpixel (subpixel 80c) in the bottom row (second row). Pixel 70B has one subpixel (subpixel 80c) in the top row (first row) and two subpixels (subpixels 80a and 80b) in the bottom row (second row). For example, as shown in Figure 35F, subpixel 80a may be a red subpixel R, subpixel 80b may be a green subpixel G, and subpixel 80c may be a blue subpixel B.

[0522] FIG. 34F shows an example in which each subpixel has a substantially rectangular top surface shape with rounded corners, and FIG. 34G shows an example in which each subpixel has a circular top surface shape.

[0523] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This reduces the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, it is likely to have rounded corners. As a result, the top surface shape of the subpixel may become a polygon with rounded corners, an ellipse, or a circle.

[0524] Furthermore, in a manufacturing method of a display device according to one embodiment of the present invention, the EL layer is processed into an island shape using a resist mask. The resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the material for the EL layer and the curing temperature of the resist material, the resist film may not be cured sufficiently. A resist film that is not cured sufficiently may have a shape that deviates from the desired shape during processing. As a result, the top surface shape of the EL layer may become a polygon with rounded corners, an ellipse, a circle, or the like. For example, when a resist mask with a square top surface shape is formed, a resist mask with a circular top surface shape may be formed, resulting in a circular top surface shape of the EL layer.

[0525] In order to form the top surface of the EL layer into a desired shape, a technique for correcting a mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used so that the design pattern and the transfer pattern coincide with each other. Specifically, the OPC technique adds a correction pattern to the corners of figures on the mask pattern.

[0526] The pixel 80 shown in FIGS. 36A to 36C is configured in a stripe arrangement.

[0527] Figure 36A shows an example in which each subpixel has a rectangular top surface shape, Figure 36B shows an example in which each subpixel has a top surface shape that is a combination of two semicircles and a rectangle, and Figure 36C shows an example in which each subpixel has an elliptical top surface shape.

[0528] The pixels 80 shown in FIGS. 36D to 36F are arranged in a matrix.

[0529] Figure 36D is an example in which each sub-pixel has a square top surface shape, Figure 36E is an example in which each sub-pixel has an approximately square top surface shape with rounded corners, and Figure 36F is an example in which each sub-pixel has a circular top surface shape.

[0530] The pixel 80 shown in Figures 36A to 36F is composed of four subpixels: subpixel 80a, subpixel 80b, subpixel 80c, and subpixel 80d. The subpixels 80a, subpixel 80b, subpixel 80c, and subpixel 80d each emit light of a different color. For example, the subpixels 80a, subpixel 80b, subpixel 80c, and subpixel 80d can be red, green, blue, and white subpixels, respectively. For example, as shown in Figures 37A and 37B, the subpixels 80a, subpixel 80b, subpixel 80c, and subpixel 80d can be red, green, blue, and white subpixels, respectively. Alternatively, the subpixels 80a, subpixel 80b, subpixel 80c, and subpixel 80d can be red, green, blue, and white subpixels of an imaging light-emitting pixel, respectively.

[0531] The subpixel 80d includes a light-emitting device. The light-emitting device includes, for example, a pixel electrode, an EL layer, and a common electrode. Note that the pixel electrode may be formed using a material similar to that of the conductors 112a to 112c or the conductors 126a to 126c. The EL layer may be formed using a material similar to that of the first layer 113a, the second layer 113b, or the third layer 113c, for example.

[0532] The sub-pixel 80d may also be, for example, an imaging pixel. In this case, the sub-pixel 80d has a light-receiving device. For example, the light-receiving device has a pixel electrode, an active layer functioning as a photoelectric conversion layer, and a common electrode. It is preferable to use an organic light-receiving device having a layer containing an organic compound as the light-receiving device. Organic light-receiving devices can be easily made thin, lightweight, and large-area, and have a high degree of freedom in shape and design, making them applicable to a variety of display devices.

[0533] FIG. 36G shows an example in which one pixel 80 is configured with two rows and three columns. The pixel 80 has three subpixels (subpixels 80a, 80b, and 80c) in the top row (first row) and three subpixels 80d in the bottom row (second row). In other words, the pixel 80 has subpixels 80a and 80d in the left column (first column), subpixels 80b and 80d in the center column (second column), and subpixels 80c and 80d in the right column (third column). As shown in FIG. 36G, by aligning the subpixels in the top row and bottom row, it is possible to efficiently remove dust and other impurities that may occur during the manufacturing process. Therefore, a display device with high display quality can be provided.

[0534] Note that the three sub-pixels 80d shown in FIG. 36G may be applied as either or both of an imaging light-emitting pixel and an imaging pixel.

[0535] 36H shows an example in which one pixel 80 is configured with two rows and three columns. The pixel 80 has three subpixels (subpixels 80a, 80b, and 80c) in the top row (first row) and one subpixel (subpixel 80d) in the bottom row (second row). In other words, the pixel 80 has the subpixel 80a in the left column (first column), the subpixel 80b in the center column (second column), the subpixel 80c in the right column (third column), and further has the subpixel 80d across these three columns.

[0536] In the pixel 80 shown in Figures 36G and 36H, for example, as shown in Figures 37C and 37D, the subpixel 80a can be a red subpixel R, the subpixel 80b can be a green subpixel G, the subpixel 80c can be a blue subpixel B, and the subpixel 80d can be a white subpixel W.

[0537] The insulators, conductors, and semiconductors disclosed in this specification and the like can be formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method. Examples of PVD methods include sputtering, resistance heating evaporation, electron beam evaporation, molecular beam epitaxy (MBE), and pulsed laser deposition (PLD). Examples of CVD methods include plasma CVD and thermal CVD. In particular, examples of thermal CVD methods include metal organic chemical vapor deposition (MOCVD) and ALD.

[0538] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0539] In the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into a chamber, the chamber is kept at atmospheric pressure or reduced pressure, and the reaction occurs near or on a substrate, resulting in deposition on the substrate, thereby forming a film.

[0540] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases for reaction into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases are sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). An inert gas (e.g., argon or nitrogen) is introduced simultaneously with or after the first source gas to prevent mixing of the multiple source gases, followed by the introduction of the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the introduction of the second source gas. The first source gas adsorbs on the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, resulting in the second thin layer being deposited on the first thin layer to form a thin film. Repeating this gas introduction sequence multiple times while controlling the gas introduction sequence until the desired thickness is achieved allows the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0541] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, when forming an In—Ga—Zn—O film, trimethylindium (In(CH ３ ) ３ ), trimethylgallium (Ga(CH ３ ) ３ ), and dimethylzinc (Zn(CH ３ ) ２ In addition, the combination is not limited to these, and trimethylgallium may be replaced with triethylgallium (Ga(C ２ H ５ ) ３ ) can also be used, and diethyl zinc (Zn(C) ２ H ５ ) ２ ) can also be used.

[0542] For example, when a hafnium oxide film is formed using a film forming apparatus that uses the ALD method, a solvent and a liquid containing a hafnium precursor compound (e.g., hafnium alkoxide, tetrakisdimethylamidohafnium (TDMAH), Hf[N(CH ３ ) ２ ] ４ The raw material gas is a vaporized hafnium amide (such as ozone) as an oxidizer. ３ ) Two types of gases are used. Other materials include tetrakis(ethylmethylamido)hafnium.

[0543] For example, when an aluminum oxide film is formed using a film forming apparatus that uses the ALD method, a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA, Al(CH ３ ) ３ )) as a raw material gas, and H as an oxidant. ２ Two types of gases are used: O. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0544] For example, when a silicon oxide film is formed using a film forming apparatus that uses the ALD method, hexachlorodisilane is adsorbed on the film forming surface, and an oxidizing gas (O ２ , nitrous oxide) radicals are supplied to react with the adsorbate.

[0545] For example, when a tungsten film is formed using a film forming apparatus that uses the ALD method, WF ６ Gas and B ２ H ６ The gases are introduced repeatedly in sequence to form an initial tungsten film, and then WF ６ Gas and H ２ The gases are introduced repeatedly in sequence to form a tungsten film. ２ H ６ Instead of gas, SiH ４ A gas may also be used.

[0546] For example, when an In—Ga—Zn—O film is formed as an oxide semiconductor film by a film formation apparatus using the ALD method, a precursor (generally, it may be called, for example, a precursor or a metal precursor) and an oxidizing agent (generally, it may be called, for example, a reactant or a non-metal precursor) are sequentially and repeatedly introduced to form the oxide semiconductor film. Specifically, for example, a precursor, In(CH ３ ) ３ gas and oxidizer O ３ The gas is introduced to form an In—O layer, and then the precursor Ga(CH ３ ) ３ gas and oxidizer O ３ The gas is introduced to form a GaO layer, and then the precursor Zn(CH ３ ) ２ gas and oxidizer O ３ The gas is introduced to form a ZnO layer. The order of these layers is not limited to this example. Mixed oxide layers such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may also be formed using these gases. ３ H obtained by bubbling water with an inert gas (e.g., argon) instead of gas ２ O gas may be used, but O gas containing no H ３ It is preferable to use In(CH ３ ) ３ Instead of gas, In(C ２ H ５ ) ３ Gas may also be used. ３ ) ３ Instead of gas, Ga(C ２ H ５ ) ３ Gas may also be used. ３ ) ２ Instead of gas, Zn(C ２ H ５ ) 2 gases may also be used.

[0547] The screen ratio (aspect ratio) of the display unit included in the electronic device of one embodiment of the present invention is not particularly limited. For example, the display unit can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.

[0548] The shape of the display unit included in the electronic device of one embodiment of the present invention is not particularly limited. For example, the display unit can have various shapes such as a rectangular shape, a polygonal shape (e.g., an octagonal shape), a circular shape, or an elliptical shape.

[0549] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0550] Embodiment 3 In this embodiment, a transistor that can be used for a semiconductor device according to one embodiment of the present invention, specifically the transistor 500 described in Embodiment 2, will be described.

[0551] 38A, 38B, and 38C are a plan view and a cross-sectional view of a transistor 500 that can be used in a semiconductor device according to one embodiment of the present invention. The transistor 500 can be used in a semiconductor device according to one embodiment of the present invention.

[0552] FIG. 38A is a plan view of the transistor 500. Also, FIGS. 38B and 38C are cross-sectional views of the transistor 500. Here, FIG. 38B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 38A and is also a cross-sectional view of the transistor 500 in the channel length direction. Also, FIG. 38C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in FIG. 38A and is also a cross-sectional view of the transistor 500 in the channel width direction. Note that some elements are omitted from the plan view of FIG. 38A for clarity.

[0553] 38A to 38C , the transistor 500 includes a metal oxide 531a disposed on a substrate (not shown), a metal oxide 531b disposed on the metal oxide 531a, conductors 542a and 542b spaced apart from each other on the metal oxide 531b, an insulator 580 disposed on the conductors 542a and 542b and having an opening formed between the conductors 542a and 542b, a conductor 560 disposed in the opening, and an insulator 550 disposed between the metal oxide 531b, the conductors 542a and 542b, and the insulator 580 and the conductor 560. Here, as shown in FIGS. 38B and 38C , the top surface of the conductor 560 preferably substantially coincides with the top surfaces of the insulators 550 and 580. Note that hereinafter, the metal oxides 531a and 531b may be collectively referred to as metal oxides 531. In addition, the conductor 542a and the conductor 542b may be collectively referred to as the conductor 542.

[0554] 38A to 38C , the side surfaces of the conductors 542a and 542b facing the conductor 560 have a substantially vertical shape. Note that the transistor 500 shown in FIGS. 38A to 38C is not limited to this, and the angle formed between the side surface and the bottom surface of the conductors 542a and 542b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductors 542a and 542b may have multiple surfaces.

[0555] Note that the transistor 500 has a structure in which two layers of the metal oxide 531a and the metal oxide 531b are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this. For example, the metal oxide 531b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the metal oxide 531a and the metal oxide 531b may have a stacked structure of two or more layers.

[0556] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and the region sandwiched between the conductors 542a and 542b. Here, the arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be arranged between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing a margin for alignment, thereby reducing the area occupied by the transistor 500. This allows for a high-resolution display device. Furthermore, the display device can have a narrow frame.

[0557] As shown in Figure 38B, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560b provided so as to be embedded inside the conductor 560a. While Figures 38B and 38C show the conductor 560 as having a two-layer laminated structure, the present invention is not limited to this. For example, the conductor 560 may have a single-layer structure or a laminated structure of three or more layers.

[0558] The transistor 500 preferably includes an insulator 514 disposed on a substrate (not shown), an insulator 516 disposed on the insulator 514, a conductor 505 disposed so as to be embedded in the insulator 516, an insulator 522 disposed on the insulator 516 and the conductor 505, and an insulator 524 disposed on the insulator 522. A metal oxide 531a is preferably disposed on the insulator 524.

[0559] 38B and 38C , it is preferable that an insulator 554 be disposed between the insulator 522, the insulator 524, the metal oxide 531a, the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 550 and the insulator 580. Here, it is preferable that the insulator 554 be in contact with the side surface of the insulator 550, the top and side surfaces of the conductor 542a, the top and side surfaces of the conductor 542b, the side surfaces of the metal oxide 531a, the metal oxide 531b, and the insulator 524, and the top surface of the insulator 522, as shown in FIG.

[0560] An insulator 574 functioning as an interlayer film and an insulator 581 are preferably provided over the transistor 500. Here, the insulator 574 is preferably provided in contact with top surfaces of the conductor 560, the insulator 550, and the insulator 580.

[0561] The insulators 522, 554, and 574 preferably have the function of suppressing the diffusion of hydrogen (e.g., hydrogen atoms and / or hydrogen molecules). For example, the insulators 522, 554, and 574 preferably have lower hydrogen permeability than the insulators 524, 550, and 580. The insulators 522 and 554 preferably have the function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules). For example, the insulators 522 and 554 preferably have lower oxygen permeability than the insulators 524, 550, and 580.

[0562] A conductor 540 (conductor 540a and conductor 540b) that is electrically connected to the transistor 500 and functions as a plug is preferably provided. Note that an insulator 541 (insulator 541a and insulator 541b) is provided in contact with the side surface of the conductor 540 that functions as a plug. That is, the insulator 541 is provided in contact with the inner walls of the openings of the insulators 554, 580, 574, and 581. Alternatively, a first conductor of the conductor 540 may be provided in contact with the side surface of the insulator 541, and a second conductor of the conductor 540 may be provided further inside. Here, the height of the top surface of the conductor 540 and the height of the insulator 581 can be made approximately the same. Note that, although the transistor 500 illustrates a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by assigning an ordinal number to indicate the order of formation.

[0563] In the transistor 500, a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 531 (the metal oxide 531a and the metal oxide 531b) including the channel formation region. For example, a metal oxide that serves as the channel formation region of the metal oxide 531 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more.

[0564] The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable that indium (In) and zinc (Zn) are contained. Furthermore, in addition to these, it is preferable that the element M is contained. The element M can be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), or cobalt (Co). In particular, the element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Furthermore, it is more preferable that the element M contains one or both of gallium (Ga) and tin (Sn).

[0565] Furthermore, the thickness of the metal oxide 531b in a region that does not overlap with the conductor 542 may be thinner than the thickness of the region that overlaps with the conductor 542. This is formed by removing part of the top surface of the metal oxide 531b when forming the conductors 542a and 542b. When a conductive film that will become the conductor 542 is formed on the top surface of the metal oxide 531b, a low-resistance region may be formed near the interface with the conductive film. In this way, removing the low-resistance region located between the conductors 542a and 542b on the top surface of the metal oxide 531b can prevent a channel from being formed in that region.

[0566] According to one embodiment of the present invention, a display device having high definition and a small transistor can be provided. Alternatively, a display device having high luminance and a transistor with high on-state current can be provided. Alternatively, a display device having high-speed operation and a transistor with stable electrical characteristics can be provided. Alternatively, a display device having low power consumption and a transistor with low off-state current can be provided.

[0567] A detailed structure of a transistor 500 that can be used in a display device according to one embodiment of the present invention will be described.

[0568] The conductor 505 is arranged to have a region overlapping with the metal oxide 531 and the conductor 560. The conductor 505 is preferably embedded in the insulator 516.

[0569] The conductor 505 includes a conductor 505a and a conductor 505b. The conductor 505a is provided in contact with the bottom surface and sidewall of an opening provided in the insulator 516. The conductor 505b is provided so as to be embedded in a recess formed in the conductor 505a. Here, the height of the upper surface of the conductor 505b is approximately the same as the height of the upper surface of the conductor 505a and the height of the upper surface of the insulator 516.

[0570] The conductor 505a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (e.g., N ２ O, NO, or NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms or copper atoms, or a conductive material that has a function of suppressing the diffusion of oxygen (for example, oxygen atoms and / or oxygen molecules).

[0571] By using a conductive material that can reduce hydrogen diffusion for the conductor 505a, it is possible to prevent impurities such as hydrogen contained in the conductor 505b from diffusing to the metal oxide 531 via the insulator 524. Furthermore, by using a conductive material that can reduce oxygen diffusion for the conductor 505a, it is possible to prevent the conductor 505b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can reduce oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 505a may have a single layer or a stacked layer structure of the above conductive materials. For example, titanium nitride may be used for the conductor 505a.

[0572] The conductor 505b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0573] Here, the conductor 560 may function as a first gate (e.g., also referred to as a top gate) electrode. The conductor 505 may function as a second gate (e.g., also referred to as a bottom gate) electrode. In this case, the potential applied to the conductor 505 may be changed independently of the potential applied to the conductor 560, thereby controlling the V ｔｈ In particular, applying a negative potential to the conductor 505 can control the V ｔｈ Therefore, when a negative potential is applied to the conductor 505, the drain current when the potential applied to the conductor 560 is 0 V can be made smaller than when no negative potential is applied.

[0574] The conductor 505 is preferably larger than the channel formation region of the metal oxide 531. In particular, as shown in Fig. 38C, the conductor 505 preferably extends also in a region outside the end portion intersecting with the channel width direction of the metal oxide 531. In other words, the conductor 505 and the conductor 560 preferably overlap with each other with an insulator interposed therebetween on the outside of the side surface of the metal oxide 531 in the channel width direction.

[0575] With the above structure, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560 that functions as a first gate electrode and the electric field of the conductor 505 that functions as a second gate electrode.

[0576] 38C, the conductor 505 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 505.

[0577] The insulator 514 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 500 from the substrate side. Therefore, the insulator 514 does not contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, or nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms or copper atoms (i.e., the impurities are less likely to permeate through the insulating material). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., the oxygen is less likely to permeate through the insulating material).

[0578] For example, aluminum oxide or silicon nitride is preferably used for the insulator 514. This can prevent impurities such as water or hydrogen from diffusing from the substrate side of the insulator 514 to the transistor 500 side. Alternatively, it can prevent oxygen contained in the insulator 524 from diffusing from the insulator 514 to the substrate side.

[0579] The insulators 516, 580, and 581, which function as interlayer films, preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 516, 580, and 581 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies, as appropriate.

[0580] The insulators 522 and 524 function as gate insulators.

[0581] Here, the insulator 524 in contact with the metal oxide 531 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 524 may be formed using silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing oxygen in contact with the metal oxide 531, oxygen vacancies in the metal oxide 531 can be reduced, and the reliability of the transistor 500 can be improved.

[0582] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 524. The oxide from which oxygen is released by heating is an oxide having an oxygen atom content of 1.0×10 or more as determined by thermal desorption spectroscopy (TDS). １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３ More preferably, 2.0 × 10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

[0583] Like the insulator 514, the insulator 522 preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the transistor 500 from the substrate side. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524. By surrounding the insulator 524, the metal oxide 531, and the insulator 550 with the insulators 522, 554, and 574, impurities such as water and hydrogen can be prevented from entering the transistor 500 from the outside.

[0584] Furthermore, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., the oxygen is less likely to permeate). For example, the insulator 522 preferably has lower oxygen permeability than the insulator 524. The insulator 522 preferably has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the metal oxide 531 toward the substrate. Furthermore, the conductor 505 can be prevented from reacting with oxygen contained in the insulator 524 and the metal oxide 531.

[0585] The insulator 522 may be an insulator containing an oxide of one or both of insulating materials, such as aluminum and hafnium. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing an oxide of one or both of aluminum and hafnium. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the metal oxide 531 and the intrusion of impurities such as hydrogen from the periphery of the transistor 500 into the metal oxide 531.

[0586] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0587] The insulator 522 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), or strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ Insulators containing so-called high-k materials such as BST may be used in a single layer or a multilayer configuration. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0588] Note that the insulator 522 and the insulator 524 may have a stacked structure of two or more layers. In this case, the insulators are not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials. For example, an insulator similar to the insulator 524 may be provided under the insulator 522.

[0589] The metal oxide 531 includes a metal oxide 531a and a metal oxide 531b on the metal oxide 531a. By providing the metal oxide 531a below the metal oxide 531b, it is possible to suppress diffusion of impurities from structures formed below the metal oxide 531a to the metal oxide 531b.

[0590] Note that the metal oxide 531 preferably has a stacked structure of multiple oxide layers with different atomic ratios of the respective metal atoms. For example, when the metal oxide 531 contains at least indium (In) and the element M, the ratio of the number of atoms of the element M contained in the metal oxide 531a to the number of atoms of all elements constituting the metal oxide 531a is preferably higher than the ratio of the number of atoms of the element M contained in the metal oxide 531b to the number of atoms of all elements constituting the metal oxide 531b. Furthermore, the atomic ratio of the element M contained in the metal oxide 531a to In is preferably higher than the atomic ratio of the element M contained in the metal oxide 531b to In.

[0591] The energy of the conduction band minimum of the metal oxide 531a is preferably higher than the energy of the conduction band minimum of the metal oxide 531b. In other words, the electron affinity of the metal oxide 531a is preferably smaller than the electron affinity of the metal oxide 531b.

[0592] Here, the energy level of the conduction band minimum changes smoothly at the junction between the metal oxide 531a and the metal oxide 531b. In other words, the energy level of the conduction band minimum at the junction between the metal oxide 531a and the metal oxide 531b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the metal oxide 531a and the metal oxide 531b.

[0593] Specifically, when the metal oxide 531a and the metal oxide 531b have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the metal oxide 531b is an In—Ga—Zn oxide, the metal oxide 531a may be an In—Ga—Zn oxide, a Ga—Zn oxide, or a gallium oxide.

[0594] Specifically, the metal oxide 531a may have an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5, and the metal oxide 531b may have an atomic ratio of In:Ga:Zn=1:1:1, 4:2:3, or 3:1:2.

[0595] In this case, the main carrier path is the metal oxide 531b. By configuring the metal oxide 531a as described above, the defect state density at the interface between the metal oxide 531a and the metal oxide 531b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve high on-state current and high frequency characteristics.

[0596] A conductor 542 (conductor 542a and conductor 542b) functioning as a source electrode and a drain electrode is provided on the metal oxide 531b. The conductor 542 is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, or lanthanum, or an alloy containing the above metal element, or an alloy combining two or more selected from the above metal elements. For example, the conductor 542 is preferably made of tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain their conductivity even when they absorb oxygen.

[0597] By providing the conductor 542 so as to be in contact with the metal oxide 531, the oxygen concentration may be reduced in the vicinity of the conductor 542 of the metal oxide 531. Furthermore, a metal compound layer containing a metal contained in the conductor 542 and components of the metal oxide 531 may be formed in the vicinity of the conductor 542 of the metal oxide 531. In such a case, the carrier density increases in the region of the metal oxide 531 in the vicinity of the conductor 542, and the region becomes a low-resistance region.

[0598] Here, the region between the conductor 542a and the conductor 542b is formed to overlap the opening of the insulator 580. This allows the conductor 560 to be arranged in a self-aligned manner between the conductor 542a and the conductor 542b.

[0599] The insulator 550 functions as a gate insulator. The insulator 550 is preferably disposed in contact with the top surface of the metal oxide 531b. The insulator 550 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable to heat.

[0600] The insulator 550 preferably has a reduced concentration of impurities such as water or hydrogen, similar to the insulator 524. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0601] An insulator may be provided between the insulator 580, the insulator 554, the conductor 542, and the metal oxide 531b and the insulator 550. Aluminum oxide, hafnium oxide, or the like is preferably used as the insulator. Providing the insulator can suppress release of oxygen from the metal oxide 531b, excessive supply of oxygen to the metal oxide 531b, oxidation of the conductor 542, and the like.

[0602] A metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen...

Claims

1. The device has a display unit, a light emitting unit, a light receiving unit, and a control unit, the display unit has a first display area and a first circuit area, the first display area is located in an area overlapping the first circuit area, the first display region has a plurality of first display pixels; the first circuit area includes a first driver circuit; the first driver circuit is electrically connected to a plurality of first wirings extending to the first display area; the plurality of first display pixels are electrically connected to the plurality of first wirings, the light-emitting unit has a function of emitting a first light, the light receiving unit has a function of detecting second light reflected by a subject when the first light is irradiated onto the subject, and a function of generating information based on the second light and transmitting the information to the control unit; the control unit has a function of generating a first signal based on the information and transmitting the first signal to the first driver circuit; the first driver circuit has a function of either transmitting a plurality of image signals to each of the plurality of first wirings in response to the first signal, or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of first wirings; the first display pixel includes a transistor including a metal oxide in a channel formation region and a light emitting device; The light-emitting device comprises: a first conductive film electrically connected to the transistor through an opening in a flat lower layer covering the transistor; an insulating layer disposed on a recess of the first conductive film in a region overlapping the opening; a second conductive film having a region in contact with an upper surface of the first conductive film, a region in contact with an upper surface of the insulating layer, and a region in contact with a side surface of the first conductive film; a third conductive film having a region in contact with an upper surface of the second conductive film; and an EL layer having a region in contact with the upper surface of the third conductive film, a region in contact with a side surface of the second conductive film, and a region in contact with a side surface of the third conductive film. Display device.

2. In claim 1, the display unit has a second display area and a second circuit area, the second display area is located in an area overlapping the second circuit area, the second display region has a plurality of second display pixels; the second circuit area includes a second driver circuit; the second driver circuit is electrically connected to a plurality of second wirings extending to the second display area; the second display pixels are electrically connected to the second wirings, the control unit is electrically connected to the second driver circuit; the control unit has a function of generating a second signal based on the information and transmitting the second signal to the second driver circuit; the second driver circuit has a function of either transmitting a plurality of image signals to each of the plurality of second wirings in response to the second signal, or transmitting the same image signal to two or more consecutively adjacent wirings among the plurality of second wirings; the number of first display pixels to which one image signal is written in the first display area is different from the number of second display pixels to which one image signal transmitted to the second display area is written; Display device.

3. The device has a display unit, a light emitting unit, a light receiving unit, and a control unit, the display unit has a first display area and a first circuit area, the first display area is located in an area overlapping the first circuit area, the first display region has a plurality of first display pixels; the first circuit area includes a first driver circuit; the first driver circuit is electrically connected to a plurality of first wirings extending to the first display area; the plurality of first display pixels are electrically connected to the plurality of first wirings, the light-emitting unit has a function of emitting a first light, the light receiving unit has a function of detecting second light reflected by a subject when the first light is irradiated onto the subject, and a function of generating information based on the second light and transmitting the information to the control unit; the control unit has a function of generating a first signal based on the information and transmitting the first signal to the first driver circuit; the first driver circuit has a function of transmitting an image signal to each of the plurality of first wirings at a first frame frequency corresponding to the first signal; the first display pixel includes a transistor including a metal oxide in a channel formation region and a light emitting device; The light-emitting device comprises: a first conductive film electrically connected to the transistor through an opening in a flat lower layer covering the transistor; an insulating layer disposed on a recess of the first conductive film in a region overlapping the opening; a second conductive film having a region in contact with an upper surface of the first conductive film, a region in contact with an upper surface of the insulating layer, and a region in contact with a side surface of the first conductive film; a third conductive film having a region in contact with an upper surface of the second conductive film; and an EL layer having a region in contact with the upper surface of the third conductive film, a region in contact with a side surface of the second conductive film, and a region in contact with a side surface of the third conductive film. Display device.

4. In claim 3, the display unit has a second display area and a second circuit area, the second display area is located in an area overlapping the second circuit area, the second display region has a plurality of second display pixels; the second circuit area includes a second driver circuit; the second driver circuit is electrically connected to a plurality of second wirings extending to the second display area; the second display pixels are electrically connected to the second wirings, the control unit is electrically connected to the second driver circuit; the control unit has a function of generating a second signal based on the information and transmitting the second signal to the second driver circuit; the second driver circuit has a function of transmitting an image signal to each of the plurality of second wirings at a second frame frequency corresponding to the second signal; the first frame frequency is different from the second frame frequency; Display device.

5. In any one of claims 1 to 4, the first driver circuit has a transistor including silicon in a channel formation region; Display device.

6. In any one of claims 1 to 4, the light emitting device comprises an organic electroluminescent material; Display device.

7. In any one of claims 1 to 4, the first light and the second light are visible light, or the first light and the second light are infrared light; Display device.

8. A display device comprising: a display device according to any one of claims 1 to 4; and a housing; The housing has a shape that can be worn on a user's head. electronic equipment.