Indication device

Abstract

Provided is a novel semiconductor device. The present invention provides a semiconductor device including a first component, a second component, and an instruction unit, wherein: the first component includes a first storage circuit that has a function for storing first setting information in a state in which power is supplied and a second storage circuit that has a function for storing the first setting information in the state in which power is not supplied; the second component includes a third storage circuit that has a function for storing second setting information in a state in which power is supplied and a fourth storage circuit that that has a function for storing the second setting information in a state in which power is not supplied; the instruction unit has a function for ON / OFF control of the supply of power to each of the first component and the second component; and each of the second storage circuit and the fourth storage circuit includes a transistor that contains a metal oxide in a semiconductor layer in which a channel is formed.

Description

Semiconductor Devices

[0001] TECHNICAL FIELD One embodiment of the present invention relates to a semiconductor device, particularly to a semiconductor device having a memory device, and particularly to a semiconductor device having a nonvolatile memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, electronic computers, electronic devices, and driving methods thereof or manufacturing methods thereof.

[0003] A CPU (Central Processing Unit), MPU (Micro Processing Unit), or MCU (Micro Controller Unit) executes a series of processes by sequentially executing processes according to programs (data) stored in a program memory. Data required for the processes or data obtained by the processes is received from or transmitted to peripheral circuits. Various peripheral circuits are used according to user needs. Examples of peripheral circuits include a DRAM (Dynamic Random Access Memory) interface, a PCI (Peripheral Component Interface), a DMA (Direct Memory Access), a network interface, and an audio interface.

[0004] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0005] Furthermore, Patent Document 3 discloses a display device with a high number of pixels and high definition, which is equipped with a light-emitting device including an organic EL.

[0006] JP 2012-257187 A JP 2011-151383 A International Publication No. 2019 / 220278

[0007] During CPU processing, when transmitting and receiving data to and from a specific peripheral circuit, other peripheral circuits that do not contribute to the processing are in an idle state. Therefore, power gating, which stops the supply of power to other peripheral circuits that do not contribute to the processing, can reduce power consumption. However, in order to use a peripheral circuit, various settings must be made, and the setting data must be stored in a setting register provided in the peripheral circuit. Therefore, when the peripheral circuit returns from power gating, the setting data must be stored again in the setting register. Such operations result in energy loss when power gating is performed, and therefore the power consumption reduction effect is reduced even when power gating is implemented.

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with increased operating speed.An object of one embodiment of the present invention is to provide a miniaturized semiconductor device.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0009] The present invention has been made in consideration of the above-mentioned problems, and provides a semiconductor device in which the CPU registers and peripheral circuit setting registers are configured as nonvolatile registers (registers having memory circuits that continue to store data even in a power gating state), and a function for individually power gating each block (CPU, peripheral circuit). Each block continues to store data in the nonvolatile register even during power gating, so that processing can resume from the state in which the data in the register was set after returning from power gating. The present invention provides a function for power gating blocks that do not contribute to processing in accordance with the processing of the semiconductor device. With this configuration, it is possible to reduce power consumption of blocks other than those that contribute to the actual processing of the semiconductor device, and to provide a semiconductor device that can reduce power consumption during operation.

[0010] (1) One aspect of the present invention is a device including a first component, a second component, and a command unit, wherein the first component includes a first storage circuit having a function of storing first setting information when power is supplied, and a second storage circuit having a function of storing the first setting information when power is not supplied, the second component includes a third storage circuit having a function of storing second setting information when power is supplied, and a fourth storage circuit having a function of storing the second setting information when power is not supplied, and the command unit has a function of controlling whether or not power is supplied to each of the first component and the second component, and the first component includes a first storage circuit having a function of storing the first setting information when power is not supplied, and a fourth storage circuit having a function of storing the second setting information when power is not supplied, and the command unit has a function of controlling whether or not power is supplied to each of the first component and the second component. The semiconductor device has a function of writing first setting information stored in a memory circuit to a second memory circuit to put the device in a state where power is not supplied, and a function of storing first setting information read from the second memory circuit in the first memory circuit to put the device in a state where power is supplied, and the second component has a function of writing second setting information stored in a third memory circuit to a fourth memory circuit to put the device in a state where power is not supplied, and a function of storing second setting information read from the fourth memory circuit in the third memory circuit to put the device in a state where power is supplied, and each of the second memory circuit and the fourth memory circuit has a transistor including a metal oxide in a semiconductor layer in which a channel is formed.

[0011] (2) In the above (1), each of the second memory circuit and the fourth memory circuit includes a first transistor and a capacitor, one of a source or a drain of the first transistor is electrically connected to one electrode of the capacitor, the first transistor has a function of becoming non-conductive when no power is supplied, the capacitor has a function of retaining charge of the one electrode of the capacitor when the first transistor is non-conductive, and the first transistor can include a metal oxide in a semiconductor layer in which a channel is formed.

[0012] (3) In the above (1), each of the second memory circuit and the fourth memory circuit includes a first transistor and a second transistor, one of a source or a drain of the first transistor is electrically connected to a gate of the second transistor, the first transistor has a function of becoming non-conductive when no power is supplied, the second transistor has a function of retaining charge of the gate of the second transistor when the first transistor is non-conductive, and the first transistor can include a metal oxide in a semiconductor layer in which a channel is formed.

[0013] (4) One aspect of the present invention is a device comprising a processor core, an interface, and a command unit, wherein the processor core comprises a first register having a function of storing first setting information when power is supplied, and a first memory having a function of storing the first setting information when power is not supplied, the interface comprises a second register having a function of storing second setting information when power is supplied, and a second memory having a function of storing the second setting information when power is not supplied, the command unit has a function of controlling whether or not power is supplied to the processor core and the interface, the interface has a function of writing second setting information stored in a second register to the second memory, causing a state in which power is not supplied, and a function of storing the second setting information read from the second memory in the second register, causing a state in which power is supplied, and the first memory and the second memory each include a transistor containing a metal oxide in a semiconductor layer in which a channel is formed.

[0014] (5) In the above (4), each of the first memory and the second memory includes a first transistor and a capacitor, one of a source or a drain of the first transistor is electrically connected to one electrode of the capacitor, the first transistor has a function of becoming non-conductive when no power is supplied, the capacitor has a function of retaining charge of one electrode of the capacitor when the first transistor is non-conductive, and the first transistor can include a metal oxide in a semiconductor layer in which a channel is formed.

[0015] (6) In the above (4), each of the first memory and the second memory includes a first transistor and a second transistor, one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, the first transistor has a function of becoming non-conductive when no power is supplied, the second transistor has a function of retaining charge of the gate of the second transistor when the first transistor becomes non-conductive, and the first transistor can include a metal oxide in a semiconductor layer in which a channel is formed.

[0016] One embodiment of the present invention can provide a semiconductor device with low power consumption. Another embodiment of the present invention can provide a semiconductor device with increased operating speed. Another embodiment of the present invention can provide a miniaturized semiconductor device. Another embodiment of the present invention can provide a highly reliable semiconductor device. Another embodiment of the present invention can provide a novel semiconductor device.

[0017] FIG. 1 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 2A to 2F are diagrams illustrating a configuration example of a semiconductor device. FIG. 3 is a diagram illustrating a configuration example of a semiconductor device. FIGS. 4A to 4F are diagrams illustrating an operation example of a semiconductor device. FIGS. 5A and 5B are flowcharts illustrating an operation example of a semiconductor device. FIGS. 6A and 6B are diagrams illustrating a configuration example of a display device. FIG. 7 is a diagram illustrating a configuration example of a display device. FIGS. 8A and 8B are diagrams illustrating a configuration example of a display device. FIG. 9 is a diagram illustrating a configuration example of a display device. FIGS. 10A to 10F are diagrams illustrating an example of an electronic device. FIGS. 11A to 11F are diagrams illustrating an example of an electronic device. FIGS. 12A and 12B are diagrams illustrating an example of an electronic device. FIG. 13 is a diagram illustrating an example of an electronic device.

[0018] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to, for example, a circuit including a semiconductor element (e.g., a transistor, a diode, or a photodiode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, for example, a memory device, a display device, a light-emitting device, a lighting device, or an electronic device may be a semiconductor device and may also include a semiconductor device.

[0019] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are each an object (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0020] As an example of the case where X and Y are electrically connected, one or more elements (e.g., a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, or a load) that enable the electrical connection between X and Y can be connected between X and Y.

[0021] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit), or a level shifter circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit that can increase the signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a memory circuit, or a control circuit) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, X and Y are considered to be functionally connected if a signal output from X is transmitted to Y.

[0022] It should be noted that when it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit sandwiched between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit sandwiched between them).

[0023] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer, etc.).

[0024] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0025] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0026] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0027] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. The term "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance." Conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with, for example, a "pair of conductors," a "pair of conductive regions," or a "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Alternatively, it may be set to, for example, 1 pF or more and 10 μF or less.

[0028] Furthermore, in this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the amount of current flowing between the source and the drain. The two terminals that function as a source or a drain are the input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the transistor's conductivity type (n-channel or p-channel) and the level of the potential applied to the three terminals. Therefore, in this specification, the terms "source" and "drain" are interchangeable. Furthermore, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure, a transistor may have a backgate in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as the first gate, and the other of the gate or backgate of the transistor may be referred to as the second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, the respective gates may be referred to as, for example, a first gate, a second gate, a third gate, or the like.

[0029] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0030] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential, then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0031] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0032] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified regarding the positive or negative sign (or direction of the current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, a statement such as "current is input to element A" can be rephrased as "current is output from element A," etc.

[0033] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0034] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0035] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] Furthermore, in this specification and the like, the term "overlap" does not limit the state of, for example, the stacking order of components. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0037] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable depending on the situation. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms depending on the situation without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0039] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0040] Furthermore, in this specification and the like, terms such as "wiring," "signal line," or "power line" may be interchangeable depending on the situation. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." The reverse is also true, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." The term "power line" may be changed to the term "signal line." The reverse is also true, for example, terms such as "signal line" may be changed to the term "power line." The term "potential" applied to wiring may be changed to the term "signal" depending on the situation. The reverse is also true, for example, terms such as "signal" may be changed to the term "potential."

[0041] In addition, in this specification, a "switch" has multiple terminals and has the function of switching (selecting) conduction or non-conduction between the terminals. For example, if a switch has two terminals and both terminals are conductive, the switch is said to be in a "conductive state" or "on state." Also, if both terminals are non-conductive, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch to either the conductive state or the non-conductive state, or maintaining either the conductive state or the non-conductive state, may be referred to as "controlling the conduction state."

[0042] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching the path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific one as long as it can control a current.

[0043] There are types of switches that are normally non-conductive but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally conductive but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0044] Examples of switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. Furthermore, the "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0045] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0046] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0047] In this specification, when referring to counting values ​​and measurement values, or to objects, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," or "uniform" (including synonyms thereof) are used, these terms are considered to include an error of plus or minus 20%, unless otherwise specified.

[0048] In this specification and the like, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities in a semiconductor may result in, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main component of the oxide semiconductor. In particular, examples of impurities include hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Furthermore, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, or Group 15 elements.

[0049] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0050] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0051] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, these configuration examples can be combined as appropriate.

[0052] The embodiments described herein will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, those skilled in the art will readily understand that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In the drawings illustrating the embodiments, the same reference numerals may be used in different drawings to designate identical or similarly functional parts in the configuration of the invention, thereby avoiding repetitive description. Furthermore, in the drawings, the same hatching patterns may be used and no particular reference numerals may be used to indicate similar functions. Furthermore, for ease of understanding, the drawings may omit the illustration of some components, for example, in perspective views or top views. Furthermore, the drawings may omit notations such as hatching patterns.

[0053] In addition, in the drawings and the like relating to this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to, for example, their size or aspect ratio. Note that the drawings are schematic illustrations of ideal examples and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations, etc. may be included.

[0054] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification and the like, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0055] In this specification, when the same symbol is used for multiple elements, particularly when it is necessary to distinguish between them, an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the symbol.

[0056] Embodiment 1 A semiconductor device according to one embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be applied to, for example, a part of a CPU, an MPU, an MCU, or the like. It can also be applied to, for example, a part of a display device or an electronic device.

[0057] 1 illustrates an example of the configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device 100 includes components 101-1 to 101-L (where L is an integer greater than or equal to 2) and a command unit 102 that controls whether or not power is supplied to each of the components 101-1 to 101-L.

[0058] Each of the components 101 - 1 to 101 -L includes a power supply line 103 and a switch 105 that has a function of switching electrical connection (conduction or non-conduction) with the functional circuit 104 .

[0059] Note that the components 101-1 to 101-L may share the power line 103. Alternatively, at least one of the components 101-1 to 101-L may have a power line 103 of a different system from the other components.

[0060] The functional circuit 104 has a function of exchanging data with the functional circuits 104 of other components and performing predetermined processing based on the data. Examples of the predetermined processing include operations (such as arithmetic operations or logical operations), writing to a memory circuit, or reading from a memory circuit.

[0061] The functional circuit 104 may also have a function of exchanging data with a functional device (not shown) provided outside the semiconductor device 100. In this case, the functional circuit 104 can function as an interface between the semiconductor device 100 and the functional device. Examples of the functional device include an input device, an output device, and a storage device.

[0062] When the switch 105 is in an on state (conducting state), the functional circuit 104 is brought into an active state (operating state) by power being supplied to the functional circuit 104 from the power supply line 103 via the switch 105. When the switch 105 is in an off state (non-conducting state), power is not supplied to the functional circuit 104 from the power supply line 103, by which the functional circuit 104 is brought into a power gating state (non-operating state).

[0063] The switch 105 can be configured using, for example, an OS transistor (a transistor containing metal oxide in a semiconductor layer in which a channel is formed). An OS transistor has a feature of extremely small leakage current in an off state. Therefore, in a power gating state, leakage current flowing through the switch 105 can prevent power from being supplied from the power line 103 to the functional circuit 104. This can reduce power consumption.

[0064] The functional circuit 104 includes a storage unit 106 that stores setting information for the functional circuit 104. The setting information is, for example, an instruction to execute a predetermined process, or an instruction to execute data exchange with the functional circuit 104 included in another component. Alternatively, the setting information is, for example, information on the presence or absence of a functional device, the type of the functional device, the specifications of the functional device, and a driving method for the functional device when exchanging data with a functional device provided outside the semiconductor device 100.

[0065] The storage unit 106 includes a storage circuit 107 having a function of storing setting information in an active state, and a storage circuit 108 having a function of storing setting information in a power gating state. The functional circuit 104 has a function of performing predetermined processing based on the setting information recorded in the storage circuit 107 in the active state.

[0066] The memory circuit 108 is preferably configured using, for example, an OS transistor. A memory circuit using an OS transistor has, for example, a structure in which one of the source and drain of an OS transistor is connected to the gate of a Si transistor (a transistor containing silicon in a semiconductor layer in which a channel is formed). An OS transistor has a feature of having an extremely small leakage current in an off state. Therefore, in a power-gating state, by turning off the OS transistor of the memory circuit, charge at the gate of the Si transistor can be retained. Therefore, charge according to setting information can be retained even in the power-gating state.

[0067] Note that components other than the memory circuit 108 of the functional circuit 104 may be configured using, for example, Si transistors. Si transistors have a higher operating speed than OS transistors. Furthermore, by electrically connecting the gate of an n-channel Si transistor to the gate of a p-channel Si transistor, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured. This can increase the operating speed of the functional circuit 104 and reduce power consumption in a steady state.

[0068] The semiconductor layer of the OS transistor preferably contains at least one of indium and zinc. Furthermore, the semiconductor layer of the OS transistor preferably contains, for example, indium, M (M is one or more elements selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin.

[0069] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0070] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn=1:1:1 or thereabouts, a composition in which In:M:Zn=1:1:1.2 or thereabouts, a composition in which In:M:Zn=2:1:3 or thereabouts, a composition in which In:M:Zn=3:1:2 or thereabouts, a composition in which In:M:Zn=4:2:3 or thereabouts, a composition in which In:M:Zn=4:2:4.1 or thereabouts, a composition in which In:M:Zn=5:1:3 or thereabouts, a composition in which In:M:Zn=5:1:6 or thereabouts, a composition in which In:M:Zn=5:1:7 or thereabouts, a composition in which In:M:Zn=5:1:8 or thereabouts, a composition in which In:M:Zn=6:1:6 or thereabouts, and a composition in which In:M:Zn=5:2:5 or thereabouts. In addition, the atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include compositions of In:M:Zn=1:3:2 or thereabouts, or In:M:Zn=1:3:4 or thereabouts. Note that the term "nearby compositions" includes a range of plus or minus 30% of the desired atomic ratio.

[0071] For example, when describing a composition having an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when In is taken as 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when In is taken as 5, Ga is more than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when In is taken as 1, Ga is more than 0.1 and 2 or less, and Zn is more than 0.1 and 2 or less.

[0072] Note that in the semiconductor device 100, for example, a layer including an OS transistor may be provided overlapping a layer including a Si transistor. With such a structure, it is possible to reduce area overhead caused by providing the switch 105 and the memory circuit 108.

[0073] The functional circuit 104 can perform first to third operations. In the first operation, an initialization process is performed to store setting information in the memory circuit 107, and the functional circuit 104 is set to an active state. In the second operation, the setting information stored in the memory circuit 107 is written to the memory circuit 108, and the functional circuit 104 is set to a power gating state. In the third operation, the setting information read from the memory circuit 108 is stored in the memory circuit 107, and the functional circuit 104 is set to an active state.

[0074] Therefore, by performing the second operation, the functional circuit 104 can prevent the setting information from being lost from the storage unit 106 when transitioning to the power gating state. Furthermore, by performing the third operation, the initialization process can be omitted when returning to the active state. In other words, since there is no need to perform the first operation again, the time required for the first operation can be reduced, and the operating speed can be increased. Furthermore, the power consumption required for the first operation can be reduced, and low power consumption can be achieved.

[0075] The storage unit 106 included in the functional circuit 104 may be configured to include only the storage circuit 108. In this case, the functional circuit 104 may be configured to have a function of performing predetermined processing based on the setting information recorded in the storage circuit 108 in the active state. With this configuration, the time required for exchanging setting information between the storage circuit 108 and the storage circuit 107 in the second and third operations can be reduced, thereby increasing the operating speed. Furthermore, the power consumption required for exchanging setting information between the storage circuit 108 and the storage circuit 107 can be reduced, thereby achieving low power consumption.

[0076] The command unit 102 has a function of individually controlling the active state or the power gating state of each of the components 101-1 to 101-L. Furthermore, the command unit 102 has a function of, depending on the processing performed by the semiconductor device 100, putting only the components of the components 101-1 to 101-L that contribute to the processing into the active state and putting the components that do not contribute to the processing into the power gating state.

[0077] The command unit 102 can control a component to be shifted to the power gating state among the components 101-1 to 101-L to turn the switch 105 to the off state after causing the functional circuit 104 to perform a second operation, and can also control a component to be returned to the active state to turn the switch 105 to the on state after causing the functional circuit 104 to perform a third operation.

[0078] Although not shown, the command unit 102 may be configured to include, for example, a storage circuit, and to store control information for selecting the active state or the power gating state of each of the components 101-1 to 101-L in the storage circuit. The control information stored in the storage circuit may be rewritten in accordance with the processing performed by the semiconductor device 100, thereby switching the active state or the power gating state of each of the components 101-1 to 101-L.

[0079] The semiconductor device 100 according to one embodiment of the present invention can perform fine-grained power gating in accordance with processing performed by the semiconductor device 100. That is, the command unit 102 places, in a power-gating state, components among the components 101-1 to 101-L that do not contribute to the processing, thereby reducing the power consumption of the components, thereby achieving low power consumption.

[0080] For example, an MCU to which a semiconductor device according to one embodiment of the present invention is applied can achieve low power consumption by performing fine-grained power gating for each component of the MCU, such as a processor core, memory, and interface.

[0081] 2A to 2F are block diagrams for explaining examples of circuit configurations applicable to the memory circuit 108. The block diagram shown in Fig. 2A illustrates a memory cell array 90, a word line driver circuit 91, and a bit line driver circuit 92.

[0082] The memory cell array 90 has memory cells MC arranged in a matrix of m rows and n columns (m and n are positive integers). The memory cells MC are connected to word lines WL_1 to WL_m and bit lines BL_1 to BL_n. In addition to the bit lines and word lines, the memory cells MC may also be connected to, for example, a source line for passing a current, a wiring for applying a potential to a back gate of a transistor, or a capacitance line for setting one electrode of a capacitor at a fixed potential.

[0083] The word line driver circuit 91 is a circuit that outputs a signal for selecting a memory cell MC in each row. The word lines WL_1 to WL_m may be separate word lines for writing and reading.

[0084] The bit line driver circuit 92 is a circuit for writing data to the memory cells MC in each column or reading data from the memory cells MC. The bit lines BL_1 to BL_n may be separate bit lines for writing and reading.

[0085] 2B to 2F show examples of circuit configurations that the memory cell MC described in FIG. 2A can have.

[0086] The memory cell MC_A shown in FIG. 2B includes a transistor OS1 and a capacitor 93. The transistor OS1 is an OS transistor. OS transistors have extremely low off-state current. Therefore, by turning off the transistor OS1, a charge corresponding to data can be held in the charge holding node SN. Therefore, the refresh rate of data corresponding to the charge held in the charge holding node SN can be reduced.

[0087] The memory cell MC_B shown in FIG. 2C includes a transistor OS2 and a capacitor 93. The transistor OS2 is an OS transistor. The transistor OS2 differs from the transistor OS1 shown in FIG. 2B in that the transistor OS2 has a back gate, and the back gate and gate are electrically connected to each other so that the potential of the word line WL is applied from both the back gate and the gate. This configuration can increase the amount of current flowing between the source and drain of the transistor OS2 when it is turned on.

[0088] The memory cell MC_C shown in FIG. 2D includes a transistor OS3 and a capacitor 93. The transistor OS3 is an OS transistor. The transistor OS3 differs from the transistor OS1 shown in FIG. 2B in that the transistor OS3 has a back gate, and the back gate is electrically connected to a back gate line BGL so that a potential different from that of the gate is applied to the back gate. This configuration allows the threshold voltage of the transistor OS3 to be controlled, thereby controlling the amount of current flowing between the source and drain.

[0089] The memory cell MC_D shown in FIG. 2E includes a transistor OS1, a transistor M1, and a capacitor 93. One of the source or drain of the transistor OS1 is connected to a write bit line WBL. The other of the source or drain of the transistor OS1 is connected to the gate of the transistor M1 and one electrode of the capacitor 93. The gate of the transistor OS1 is connected to a write word line WWL. The other electrode of the capacitor 93 is connected to a read word line RWL. One of the source or drain of the transistor M1 is connected to a read bit line RBL. The other of the source or drain of the transistor M1 is connected to a source line SL. While the transistor M1 is illustrated as a p-channel transistor, it may also be an n-channel transistor. By turning off the transistor OS1, charge corresponding to data can be held in the charge holding node SN. The transistor M1 is a Si transistor. Note that the transistor OS1 may have a configuration similar to that of the transistor OS2 or the transistor OS3 described above.

[0090] The memory cell MC_E shown in FIG. 2F includes a transistor OS1, a transistor M1, a transistor M2, and a capacitor 93. One of the source or drain of the transistor OS1 is connected to a write bit line WBL. The other of the source or drain of the transistor OS1 is connected to the gate of the transistor M1 and one electrode of the capacitor 93. The gate of the transistor OS1 is connected to a write word line WWL. The other electrode of the capacitor 93 is connected to a capacitor line CL. One of the source or drain of the transistor M1 is connected to one of the source or drain of the transistor M2. The other of the source or drain of the transistor M1 is connected to a source line SL. The gate of the transistor M2 is connected to a read word line RWL. The other of the source or drain of the transistor M2 is connected to a read bit line RBL. Although a p-channel transistor is illustrated as the transistor M2, it may also be an n-channel transistor. By turning off the transistor OS1, charge corresponding to data can be held in the charge holding node SN. The transistor M2 is a Si transistor. Note that the transistor OS1 can have the same structure as the transistor OS2 or the transistor OS3 described above.

[0091] The memory cell configurations shown in FIGS. 2B to 2D are called DOSRAM (registered trademark). DOSRAM is an abbreviation for Dynamic Oxide Semiconductor RAM (Random Access Memory). A configuration using DOSRAM electrically connects one of the source or drain of an OS transistor to one electrode of a capacitor, so that when the OS transistor is turned off, the charge of one electrode of the capacitor can be retained. A configuration using DOSRAM is particularly effective when the amount of data to be stored increases. For example, compared to when the memory cell of a memory circuit is configured using SRAM (Static RAM), an increase in circuit area can be suppressed. The memory cell configurations shown in FIGS. 2B to 2D are particularly effective in suppressing an increase in circuit area.

[0092] 2E and 2F are referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. In a configuration using NOSRAM, one of the source or drain of an OS transistor is electrically connected to the gate of a Si transistor, so that when the OS transistor is turned off, the charge of the gate of the Si transistor can be retained. Therefore, the NOSRAM can be used as a nonvolatile memory. That is, when the OS transistor is turned off, data can be continuously stored even in a power-gating state, making the NOSRAM suitable for use in the memory circuit 108.

[0093] Note that the circuit configurations illustrated in FIGS. 2B to 2F are merely examples, and any configuration can be used as long as it can realize one embodiment of the present invention.

[0094] 3 is a block diagram illustrating a configuration example of a circuit that includes a memory circuit 107 and a memory circuit 108 and that can be applied to the memory unit 106. The circuit shown in FIG. 3 has a scan flip-flop 70 and a data memory circuit 80.

[0095] The scan flip-flop 70 has a selector 71 and a flip-flop 72. The selector 71 has a function of transmitting data input to terminal D or terminal SD to terminal DF of the scan flip-flop 70 in response to a selection signal input from terminal SE. Terminal D is a terminal that receives data input from the outside. Terminal SD is a terminal that receives data input from the data storage circuit 80. The flip-flop 72 has a function of storing data at terminal DF in response to a clock signal input from terminal CLK, and outputting the stored data from terminal QF to terminal Q. An example of the flip-flop 72 is a D flip-flop. The selector 71 and flip-flop 72 can be configured using, for example, Si transistors.

[0096] The data storage circuit 80 includes transistors OS11, OS12, and OS13, and a capacitor 81. One of the source or drain of the transistor OS12 and one of the source or drain of the transistor OS13 are electrically connected to one electrode of the capacitor 81. The other of the source or drain of the transistor OS12 is electrically connected to a terminal Q. One of the source or drain of the transistor OS11 and the other of the source or drain of the transistor OS13 are electrically connected to a terminal SD. The other of the source or drain of the transistor OS11 is electrically connected to a terminal SD_IN. The other electrode of the capacitor 81 is electrically connected to a terminal PL.

[0097] The transistor OS11 has a function of determining whether to transmit data input from the terminal SD_IN to the terminal SD, depending on a signal input from the terminal BK. The terminal SD_IN is a terminal that provides data for a scan test. The transistor OS12 has a function of determining whether to transmit data at the terminal Q to the node FN11, depending on a signal input from the terminal BK. The transistor OS13 has a function of determining whether to transmit data at the node FN11 to the terminal SD, depending on a signal input from the terminal RE. The capacitor 81 stores data by holding charge at the node FN11 when the transistors OS12 and OS13 are off.

[0098] The transistors OS11 to OS13 are OS transistors. OS transistors have extremely low off-state current. Therefore, by turning off the transistors OS12 and OS13, the charge at the node FN11 can be held in the capacitor 81. Therefore, the data storage circuit 80 can be used as a nonvolatile memory.

[0099] In the data storage circuit 80, the data at the terminal Q can be written to the node FN11 by turning on the transistor OS12. Furthermore, the data at the node FN11 can be continuously stored by turning off the transistors OS12 and OS13. Furthermore, the data at the node FN11 can be read to the terminal SD by turning on the transistor OS13.

[0100] 3 can be suitably used as the memory unit 106 by associating the scan flip-flop 70 with the memory circuit 107 and the data memory circuit 80 with the memory circuit 108. That is, by applying a predetermined signal to the terminal BK and the terminal RE, it is possible to write data from the scan flip-flop 70 to the data memory circuit 80 (corresponding to the second operation), store the data in the data memory circuit 80 (corresponding to the power gating state), and read the data from the data memory circuit 80 to the scan flip-flop 70 (corresponding to the third operation).

[0101] Note that the circuit configuration illustrated in FIG. 3 is merely an example, and any configuration can be used as long as it can realize one embodiment of the present invention.

[0102] 4A to 4F are diagrams illustrating an example of operation of a semiconductor device according to one embodiment of the present invention. The semiconductor device 110 includes a processor core CORE, a memory MEM, an interface IF1, and an interface IF2. The processor core CORE includes a register CORE_REG and a memory CORE_MEM. The interface IF1 includes a register IF1_REG and a memory IF1_MEM. The interface IF2 includes a register IF2_REG and a memory IF2_MEM.

[0103] Although not shown for simplicity, the processor core CORE includes a general-purpose register consisting of multiple nonvolatile registers, which are comprised of a register CORE_REG and a memory CORE_MEM. The register CORE_REG corresponds to the above-mentioned memory circuit 107 (see FIG. 1), and the memory CORE_MEM corresponds to the above-mentioned memory circuit 108 (see FIG. 1). The interface IF1 includes a setting register consisting of multiple nonvolatile registers, which are comprised of a register IF1_REG and a memory IF1_MEM. The register IF1_REG corresponds to the memory circuit 107, and the memory IF1_MEM corresponds to the memory circuit 108. The interface IF2 includes a setting register consisting of multiple nonvolatile registers, which are comprised of a register IF2_REG and a memory IF2_MEM. The register IF2_REG corresponds to the storage circuit 107, and the memory IF2_MEM corresponds to the storage circuit .

[0104] In the active state, the processor core CORE has a function of performing calculations based on the setting information and data stored in the register CORE_REG. Also, in the power gating state, the processor core CORE has a function of storing setting information in the memory CORE_MEM. The memory MEM has a function of storing data. In the active state, the interface IF1 has a function of exchanging data with a functional device (not shown) provided outside the semiconductor device 110 based on the setting information stored in the register IF1_REG. Also, in the power gating state, the interface IF2 has a function of storing setting information in the memory IF1_MEM. In the active state, the interface IF2 has a function of exchanging data with a functional device provided outside the semiconductor device 110 based on the setting information stored in the register IF2_REG.

[0105] The functional device provided outside the semiconductor device 110 can exchange data with the processor core CORE or the memory MEM via the interface IF1 or the interface IF2. Examples of the functional device include an input device, an output device, and a storage device.

[0106] The processor core CORE, the memory MEM, the interface IF1, and the interface IF2 may each include a power supply control switch (not shown) that has a function of selecting whether or not to supply power to each of them. The power supply control switch can be configured using, for example, an OS transistor.

[0107] The semiconductor device 110 also includes a power management unit (not shown) that has the function of controlling whether or not power is supplied to each of the processor core CORE, the memory MEM, the interface IF1, and the interface IF2.

[0108] The semiconductor device 110 may correspond to the semiconductor device 100 shown in FIG. 1 as appropriate. That is, the processor core CORE, the memory MEM, the interface IF1, and the interface IF2 may correspond to the components 101-1 to 101-4 included in the semiconductor device 100, respectively. The registers CORE_REG, IF1_REG, and IF2_REG may correspond to the memory circuit 107, respectively. The memories CORE_MEM, IF1_MEM, and IF2_MEM may correspond to the memory circuit 108, respectively. The power supply control switch may correspond to the switch 105, and the power management unit may correspond to the command unit 102. Therefore, the above-described description of the semiconductor device 100 may be referred to as appropriate, and the description of the semiconductor device 110 may be omitted as appropriate.

[0109] 3 can be suitably used as the nonvolatile registers included in each of the processor core CORE, interface IF1, and interface IF2 in the semiconductor device 110. That is, the register CORE_REG, register IF1_REG, and register IF2_REG can each correspond to a scan flip-flop 70, and the memory CORE_MEM, memory IF1_MEM, and memory IF2_MEM can each correspond to a data storage circuit 80. Furthermore, by individually controlling predetermined signals provided to the terminals BK and RE included in each data storage circuit 80, it is possible to write, store, and read setting information for each data storage circuit 80.

[0110] The semiconductor device 110 can perform fine-grained power gating, i.e., the active state or power gating state of each of the components (processor core CORE, memory MEM, interface IF1, and interface IF2) constituting the semiconductor device 110 can be individually controlled in accordance with the processing performed by the semiconductor device 110.

[0111] 4A to 4F, components without hatching indicate an active state, and components with hatching indicate a power-gating state. That is, FIG. 4A shows that the processor core CORE, memory MEM, interface IF1, and interface IF2 are all in an active state. Also, FIG. 4B shows that the processor core CORE, memory MEM, interface IF1, and interface IF2 are all in a power-gating state.

[0112] FIG. 4C shows the active state or power-gating state of each component constituting the semiconductor device 110 when, for example, a data load instruction or a data store instruction is executed for a general-purpose register included in the processor core CORE. When a data load instruction is executed, data read from the memory MEM is stored in the register CORE_REG. When a data store instruction is executed, data stored in the register CORE_REG is written to the memory MEM. In other words, the only components that contribute to the processing of a data load instruction or a data store instruction are the processor core CORE and the memory MEM. In other words, the interfaces IF1 and IF2 do not directly contribute to the processing of a data load instruction or a data store instruction. Therefore, the semiconductor device 110 can activate only the processor core CORE and the memory MEM and power-gate the interfaces IF1 and IF2. This configuration reduces the power consumption of the interfaces IF1 and IF2, thereby achieving low power consumption.

[0113] FIG. 4D shows the active state or power-gating state of each component constituting the semiconductor device 110 when, for example, a data transfer process is performed using Direct Memory Access (DMA). In the DMA data transfer process, for example, data is transferred between the memory MEM and a functional device via the interface IF2 without going through the processor core CORE. In other words, the only components contributing to the DMA data transfer process are the memory MEM and the interface IF2. In other words, the processor core CORE and the interface IF1 do not directly contribute to the DMA data transfer process. Therefore, the semiconductor device 110 can activate only the memory MEM and the interface IF2 and power-gate the processor core CORE and the interface IF1. This configuration reduces the power consumption of the processor core CORE and the interface IF1, thereby achieving low power consumption.

[0114] 4E and 5A are, as an example, a diagram and a flowchart illustrating the operation of the semiconductor device 110 when transitioning from a state in which a data load instruction or a store instruction is executed for a general-purpose register provided in the processor core CORE (the state of FIG. 4C) to a state in which a data transfer is executed by DMA (the state of FIG. 4D).

[0115] As shown in FIG. 5A , first, in step S11, the configuration information for the processor core CORE stored in the register CORE_REG is written to the memory CORE_MEM (corresponding to the second operation). Next, in step S12, the processor core CORE is transitioned to a power gating state. At this time, the configuration information stored in the register CORE_REG is lost, but the configuration information written to the memory CORE_MEM continues to be stored. Next, in step S13, the configuration information for the interface IF2 read from the memory IF2_MEM is stored in the register IF2_REG (corresponding to the third operation). Next, in step S14, the interface IF2 is returned to the active state. At this time, DMA data transfer processing can be immediately executed without performing the initialization processing (corresponding to the first operation) of the configuration information again, thereby increasing the operating speed. Furthermore, power consumption associated with the initialization processing can be reduced, thereby achieving low power consumption.

[0116] 4F and 5B are, as an example, a diagram and a flowchart illustrating the operation of the semiconductor device 110 when transitioning from a state in which data transfer processing by DMA is being executed (the state of FIG. 4D) to a state in which data load instructions or store instructions are being executed for general-purpose registers provided in the processor core CORE (the state of FIG. 4C).

[0117] As shown in FIG. 5B , first, in step S21, the setting information for the interface IF2 stored in the register IF2_REG is written to the memory IF2_MEM (corresponding to the second operation). Next, in step S22, the interface IF2 is transitioned to a power gating state. At this time, the setting information stored in the register IF2_REG is lost, but the setting information written to the memory IF2_MEM continues to be stored. Next, in step S23, the setting information for the processor core CORE read from the memory CORE_MEM is stored in the register CORE_REG (corresponding to the third operation). Next, in step S24, the processor core CORE is returned to the active state. At this time, it is possible to immediately execute a load command or store command for data in the register CORE_REG without performing the initialization process (corresponding to the first operation) again, thereby increasing the operating speed. Furthermore, power consumption associated with the initialization process is reduced, thereby achieving low power consumption.

[0118] In the semiconductor device 110 according to one embodiment of the present invention, only components that actually contribute to processing among the components constituting the semiconductor device 110 can be set to an active state, and components that do not contribute to processing can be set to a power-gating state. This reduces the power consumption of the components that do not contribute to processing, thereby achieving low power consumption. In other words, power consumption can be reduced even during operation of the semiconductor device.

[0119] Although the semiconductor device 110 according to one embodiment of the present invention has been described as including two interfaces (interface IF1 and interface IF2) as an example, it may include three or more interfaces. Even in a semiconductor device with a wide variety of interfaces and a large circuit scale, the power consumption can be reduced by suitably using the configuration of the present invention.

[0120] Note that a semiconductor device according to one embodiment of the present invention is not limited to the above-described semiconductor device 100 and the semiconductor device 110. At least part of the configuration examples and operation examples illustrated in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples, operation examples, other drawings, and other embodiments described in this specification.

[0121] Embodiment 2 In this embodiment, a structural example of a display device including a semiconductor device according to one embodiment of the present invention will be described.

[0122] <Configuration Example 1> FIGS. 6A and 7 are perspective views of a display device 300A according to one embodiment of the present invention. FIG. 6B is a block diagram illustrating the configuration of the display device 300A. The display device 300A includes a layer 30 on the layer 20 and a sealing substrate 40 on the layer 30. Note that in FIG. 7, for example, the layer 20, the layer 30, the layer 60, and the sealing substrate 40 are shown separated from one another to make the configuration of the display device 300A easier to understand. As shown in FIG. 7, the layer 30 includes a memory unit 11 and a display unit 31. Furthermore, a layer 60 is provided between the sealing substrate 40 and the display unit 31. Furthermore, FIG. 7 illustrates, as an example, a configuration in which the memory unit 11 is provided on the outer periphery of the region in which the display unit 31 is provided in the layer 30.

[0123] The layer 20 includes a functional circuit 21 and a terminal section 29. The functional circuit 21 includes a control circuit 22, a display section drive circuit 23, an image processing circuit 25, a sensor circuit 26, a communication circuit 27, and an input / output circuit 28.

[0124] The display unit driving circuit 23, the image processing circuit 25, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28 each include a memory circuit 23M, a memory circuit 25M, a memory circuit 26M, a memory circuit 27M, and a memory circuit 28M, respectively, which have the function of storing data even in a power gating state.

[0125] In addition, each of the display unit drive circuit 23, image processing circuit 25, sensor circuit 26, communication circuit 27, and input / output circuit 28 may be provided with a power supply control switch (not shown) that has the function of selecting whether or not to supply power to each of them.

[0126] A display device 300A using a semiconductor device according to one embodiment of the present invention can correspond to the semiconductor device 100 illustrated in FIG. 1 as appropriate. That is, the functional circuit 21 can correspond to the semiconductor device 100. Thus, the control circuit 22 can correspond to the command unit 102, and the display unit driver circuit 23, the image processing circuit 25, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28 can correspond to the components 101-1 to 101-5 included in the semiconductor device 100, respectively. Furthermore, the memory circuit 23M, the memory circuit 25M, the memory circuit 26M, the memory circuit 27M, and the memory circuit 28M can correspond to the memory circuit 108, respectively. Furthermore, the power supply control switch can correspond to the switch 105. Thus, the description of the semiconductor device 100 described in Embodiment 1 can be referred to as appropriate, and therefore, the description may be omitted in this embodiment as appropriate.

[0127] The functional circuit 21 does not need to include all of these components, or may include other components. For example, the functional circuit 21 may include at least one of a power supply circuit and a power management circuit that controls the supply of power. The functional circuit 21 may also include at least one of a DSP (Digital Signal Processor) or an FPGA (Field Programmable Gate Array). The functional circuit 21 may also include at least one of a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). The functional circuit 21 may also include a super-resolution circuit. The super-resolution circuit has a function of up-converting image data with a resolution lower than that of the display unit. The super-resolution circuit has a function of down-converting image data with a resolution higher than that of the display unit.

[0128] The functional circuit 21 is preferably configured with a Si CMOS, i.e., a transistor having silicon in a channel formation region (Si transistor). That is, the layer 20 having the functional circuit 21 is a layer having Si transistors. By configuring the functional circuit 21 with Si transistors, circuits having functions such as a control circuit 22, a display unit drive circuit 23, an image processing circuit 25, a sensor circuit 26, a communication circuit 27, and an input / output circuit 28 can be provided in the functional circuit 21.

[0129] For the Si transistor, it is preferable to use silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon, because high field effect mobility can be achieved and higher speed operation is possible.

[0130] The layer 30 is a layer including an OS transistor, that is, a transistor including an oxide semiconductor in a channel formation region. With this structure, the memory unit 11 and the display unit 31 including the OS transistor can be stacked with the layer 20.

[0131] An OS transistor has a characteristic of having a very low off-state current. Therefore, for example, when an OS transistor is used as a transistor in a pixel circuit, analog data written to the pixel circuit can be stored for a long period of time. For example, when an OS transistor is used as a transistor in a memory circuit, data written to the memory circuit can be stored for a long period of time.

[0132] The memory circuits 23M, 25M, 26M, 27M, and 28M can each be partially formed using OS transistors (see FIG. 2E or FIG. 2F). Thus, the memory circuits 23M, 25M, 26M, 27M, and 28M can each be partially provided in the memory portion 11 of the layer 30.

[0133] The power supply control switches included in the display unit driver circuit 23, the image processing circuit 25, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28 can be configured using, for example, OS transistors. Therefore, the power supply control switches can be provided in the layer 30.

[0134] The image processing circuit 25 has a function of processing image data. For example, the image processing circuit 25 may have a super-resolution circuit and a function of up-converting or down-converting image data.

[0135] The control circuit 22 has a function of controlling the operation of the functional circuit 21 provided in the layer 20 based on a signal from the image processing circuit 25. For example, the control circuit 22 may have a function of controlling whether or not power is supplied to each of the display unit drive circuit 23, the image processing circuit 25, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28 included in the functional circuit 21.

[0136] The display unit driving circuit 23 is electrically connected to the display unit 31 included in the layer 30, and has a function of supplying image data to the display unit 31. The display unit driving circuit 23 can be any of various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit.

[0137] Furthermore, a layer 60 is provided over the display section 31 included in the layer 30. The layer 60 includes a plurality of light-emitting elements, and the light emission brightness is controlled by a pixel circuit 51 provided in the display section 31. Therefore, the layer 60 can also be considered as part of the display section 31.

[0138] The display unit 31 includes pixels 50. The pixels 50 include a plurality of pixel circuits 51 and light-emitting elements (not shown) provided in a layer 60 above the pixel circuits 51. The pixel circuits 51 correspond to pixel circuits included in sub-pixels for color display.

[0139] Each of the three subpixels controls, for example, the amount of light emitted by red, green, or blue light. The color of light controlled by each of the three subpixels is not limited to a combination of red (R), green (G), and blue (B), but may also be a combination of cyan (C), magenta (M), and yellow (Y). The areas of the three subpixels do not need to be the same. If, for example, the luminous efficiency and reliability differ depending on the luminous color, the area of ​​the subpixel may be varied for each luminous color. Four subpixels may be combined to function as a single pixel. For example, a subpixel controlling the amount of white light may be added to the three subpixels controlling the amount of red, green, and blue light. Adding a subpixel controlling the amount of white light can increase the luminance of the display area. A subpixel controlling the amount of yellow light may be added to the three subpixels controlling the amount of red, green, and blue light. A subpixel controlling the amount of white light may be added to the three subpixels controlling the amount of cyan, magenta, and yellow light.

[0140] By increasing the number of sub-pixels that function as one pixel and appropriately combining sub-pixels that control the amount of light emitted, for example, red, green, blue, cyan, magenta, or yellow, it is possible to improve the reproducibility of intermediate tones, and therefore color reproducibility.

[0141] The sensor circuit 26 has a function of acquiring information from one or more of human vision, hearing, touch, taste, and smell. More specifically, the sensor circuit 26 has a function of detecting or measuring one or more of force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared light. The sensor circuit 26 may also have other functions.

[0142] The communication circuit 27 has a function of communicating with other terminals wirelessly or via a wire, for example. In particular, if the communication circuit 27 has a function of communicating wirelessly, it is preferable because it can reduce the number of components such as cables for connection.

[0143] The input / output circuit 28 has a function of distributing a signal supplied to the display device 300A via the terminal unit 29 to each circuit, such as the control circuit 22. The input / output circuit 28 also has a function of distributing a signal supplied to the display device 300A via the communication circuit 27 to each circuit, such as the control circuit 22. The input / output circuit 28 also has a function of outputting a signal to the outside via the terminal unit 29. The input / output circuit 28 also has a function of outputting a signal to the outside via the communication circuit 27.

[0144] For example, an FPC (Flexible Printed Circuit) is electrically connected to the terminal portion 29. Therefore, the layer 30 and the sealing substrate 40 are not formed in the region overlapping with the terminal portion 29.

[0145] The functional circuit 21 can perform fine-grained power gating, that is, the control circuit 22 can individually control the active state or power gating state of each of the circuits constituting the functional circuit 21 (the display unit drive circuit 23, the image processing circuit 25, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28) in accordance with the processing performed by the functional circuit 21.

[0146] For example, when image data processing is to be performed, the setting information of the image processing circuit 25 is read from the storage circuit 25M and the image processing circuit 25 is set to an active state, thereby enabling the image data processing to be performed immediately without performing initialization processing. Furthermore, power consumption can be reduced by setting the display unit drive circuit 23, the sensor circuit 26, the communication circuit 27, and the input / output circuit 28, which do not directly contribute to the processing of image data, to a power gating state.

[0147] <Configuration Example 2> Another configuration example of a display device according to one embodiment of the present invention will be described. FIGS. 8A and 9 are perspective views of a display device 300B according to one embodiment of the present invention. FIG. 8B is a block diagram illustrating the configuration of display device 300B. Display device 300B includes a layer 10 on layer 20, a layer 30 on layer 10, and a sealing substrate 40 on layer 30. Layer 30 includes a display unit 31, and a layer 60 is provided between the sealing substrate 40 and the display unit 31. Layer 10 also includes a memory unit 11. In FIG. 9, to make the configuration of display device 300B easier to understand, for example, layers 20, 30, 60, and the sealing substrate 40 are shown separated from one another.

[0148] Note that repeated description of components denoted by the same reference numerals as those in the display device 300A shown in FIGS. 6 and 7 may be omitted.

[0149] The layer 20 is the same as the layer 20 included in the display device 300A, and therefore the description of the above-mentioned configuration example 1 can be appropriately taken into consideration.

[0150] The memory unit 11 provided in the layer 10 includes at least a part of each of the memory circuits 23M, 25M, 26M, 27M, and 28M. The layer 10 may also include a power supply control switch (not shown). In the configuration of the display device 300B, the memory unit 11 and the power supply control switch are provided in the layer 10, and the display unit 31 is provided in a layer 30, which is a different layer from the layer 10. Therefore, the area of ​​the display unit 31 can be made larger than that of the display device 300A. Both the layer 10 and the layer 30 may include OS transistors.

[0151] As described above, the display device 300B of one embodiment of the present invention has a stacked structure including a layer including the display unit 31, a layer including the memory unit 11 and the power supply control switch, and a layer including the functional circuit 21. Stacking the layers including the circuits can reduce the size of the display device 300B. Furthermore, the display unit driver circuit 23 can be provided overlapping the display unit 31, thereby increasing the area of ​​the display unit 31. Therefore, the resolution of the display unit 31 can be increased, and the display quality of the display device 300B can be improved.

[0152] Furthermore, by stacking a layer having the display unit 31, a layer having the memory unit 11 and the power supply control switch, and a layer having the functional circuit 21, it is possible to shorten the wiring electrically connecting each of them. This reduces wiring resistance and parasitic capacitance, making it possible to increase the operating speed of the display device 300B. Furthermore, the power consumption of the display device 300B is reduced.

[0153] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0154] Embodiment 3 In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0155] The metal oxide used in the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin, and more preferably gallium.

[0156] The metal oxide can be formed by, for example, a sputtering method, a chemical vapor deposition (CVD) method such as a metal organic chemical vapor deposition (MOCVD) method, or an atomic layer deposition (ALD) method.

[0157] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0158] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0159] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0160] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0161] Furthermore, the crystalline structure of a film or substrate can be evaluated using a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. Therefore, an In—Ga—Zn oxide film formed at room temperature is neither single-crystal nor polycrystalline, nor in an amorphous state, but in an intermediate state. Therefore, it is difficult to conclude that it is in an amorphous state.

[0162] [Structure of Oxide Semiconductor] Note that oxide semiconductors may be classified differently from the above when focusing on their structure. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, examples of non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), and amorphous oxide semiconductors.

[0163] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0164] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0165] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of multiple minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0166] In addition, in an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0167] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on, for example, the type or composition of metal elements constituting the CAAC-OS.

[0168] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0169] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal or heptagonal lattice arrangement, for example. It is difficult to identify clear grain boundaries in the CAAC-OS even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This may be because the CAAC-OS can tolerate distortion due to, for example, the lack of a dense arrangement of oxygen atoms in the a-b plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0170] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and carriers are likely to be captured, resulting in, for example, a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0171] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by, for example, the inclusion of impurities or the generation of defects, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (e.g., oxygen vacancies). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0172] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0173] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0174] [Structure of Oxide Semiconductor] Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0175] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0176] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0177] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0178] Specifically, the first region is a region whose main component is, for example, indium oxide or indium zinc oxide. The second region is a region whose main component is, for example, gallium oxide or gallium zinc oxide. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0179] It may be difficult to observe a clear boundary between the first region and the second region.

[0180] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0181] The CAC-OS can be formed by sputtering, for example, without intentionally heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0182] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0183] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0184] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0185] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, so that the CAC-OS can be given a switching function (a function of turning on or off a transistor). In other words, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the entire material functions as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0186] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0187] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0188] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0189] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0190] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer in which the channel is formed. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO") may be used as the semiconductor layer.

[0191] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10 １０ cm −３is less than 1×10 −９ cm −３ That is all. Note that in order to reduce the carrier concentration in an oxide semiconductor, the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0192] A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states, and therefore may also have a low density of trap states.

[0193] Charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0194] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the term "impurity" in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0195] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0196] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably１７ atoms / cm ３ The following applies.

[0197] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0198] When nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0199] Hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0200] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0201] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments mode.

[0202] Embodiment 4 In this embodiment, electronic devices to which a semiconductor device according to one embodiment of the present invention can be applied will be described.

[0203] A semiconductor device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, one embodiment of the present invention can realize an electronic device with high display quality. Alternatively, one embodiment of the present invention can realize an electronic device with extremely high resolution. Alternatively, one embodiment of the present invention can realize an electronic device with high reliability.

[0204] Examples of electronic devices using a semiconductor device or the like according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of the equipment include image playback devices that play back still images or videos stored on recording media such as a portable CD player, a radio, a tape recorder, a headphone stereo, a stereo, a table clock, a wall clock, a cordless telephone handset, a transceiver, a car telephone, a mobile phone, a personal digital assistant, a tablet terminal, a portable game machine, a fixed game machine such as a pachinko machine, a calculator, an electronic organizer, an electronic book terminal, an electronic translator, a voice input device, a video camera, a digital still camera, an electric shaver, a high-frequency heating device such as a microwave oven, an electric rice cooker, an electric washing machine, an electric vacuum cleaner, a water heater, an electric fan, a hair dryer, an air conditioning equipment such as an air conditioner, a humidifier, a dehumidifier, a dishwasher, a dish dryer, a clothes dryer, a futon dryer, an electric refrigerator, an electric freezer, an electric refrigerator-freezer, a DNA storage freezer, a flashlight, a tool such as a chainsaw, a smoke detector, and a medical device such as a dialysis machine. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Furthermore, mobile objects propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile objects include electric vehicles (EVs), hybrid vehicles (HVs) equipped with both internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0205] An electronic device according to one embodiment of the present invention may include a secondary battery. Preferably, the secondary battery can be charged using contactless power transmission.

[0206] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0207] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0208] An electronic device according to one embodiment of the present invention may have a sensor (e.g., a sensor having the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light, etc.).

[0209] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (e.g., still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, or a function to read out programs or data recorded on a recording medium.

[0210] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on some of the display units and mainly displaying text information on other display units, or a function of displaying a stereoscopic image by displaying images taking parallax into account on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing still images or videos, a function of automatically or manually correcting the captured images, a function of saving the captured images in a recording medium (external or built into the electronic device), or a function of displaying the captured images on the display unit. Note that the functions of the electronic device according to one embodiment of the present invention are not limited to these. The electronic device according to one embodiment of the present invention can have various functions.

[0211] The semiconductor device according to one embodiment of the present invention can display high-resolution images. Therefore, the semiconductor device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, and the like. For example, the semiconductor device can be suitably used in xR devices such as VR devices and AR devices.

[0212] FIG. 10A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0213] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000. Note that the lens 8006 and the housing of the camera 8000 may be integrated together.

[0214] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 that functions as a touch panel.

[0215] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as, for example, a strobe device.

[0216] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0217] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display, for example, an image received from the camera 8000 on a display portion 8102.

[0218] The button 8103 has a function as, for example, a power button.

[0219] A semiconductor device according to one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the finder 8100 may be built in the camera 8000.

[0220] FIG. 10B is a diagram showing the appearance of the head-mounted display 8200.

[0221] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0222] The cable 8205 has a function of supplying power from a battery 8206 to the main body 8203. The main body 8203 includes, for example, a wireless receiver or the like and can display received video information on a display portion 8204. The main body 8203 also includes, for example, a camera and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0223] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user, the electrodes being capable of detecting a current that flows in association with the movement of the user's eyeballs. The wearing unit 8201 may also have a function of monitoring the user's pulse based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors, such as a temperature sensor, a pressure sensor, or an acceleration sensor. The head-mounted display 8200 may have a function of displaying biometric information of the user on the display unit 8204 or a function of changing an image displayed on the display unit 8204 in accordance with the movement of the user's head.

[0224] The semiconductor device according to one embodiment of the present invention can be applied to the display portion 8204.

[0225] 10C to 10E are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0226] The user can view the display on the display portion 8302 through the lens 8305. Note that the head-mounted display 8300 is preferably configured such that the display portion 8302 is curved, for example, because the user can feel a high sense of presence. Furthermore, for example, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform, for example, three-dimensional display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and for example, two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0227] The semiconductor device according to one embodiment of the present invention can be applied to the display portion 8302. The semiconductor device according to one embodiment of the present invention can also achieve extremely high definition. For example, even when the display is enlarged and viewed using the lens 8305 as shown in FIG. 10E , the pixels are difficult for the user to view. That is, the display portion 8302 can be used to allow the user to view a highly realistic image.

[0228] 10F is a diagram showing the appearance of a goggle-type head-mounted display 8400. The head-mounted display 8400 includes a pair of housings 8401, an attachment portion 8402, and a buffer member 8403. A display portion 8404 and a lens 8405 are provided in each of the pair of housings 8401. The pair of display portions 8404 can display different images from each other, thereby enabling three-dimensional display using parallax.

[0229] A user can view the display on the display portion 8404 through the lens 8405. The lens 8405 has a focus adjustment mechanism, and the position of the lens 8405 can be adjusted according to the user's eyesight. The display portion 8404 is preferably a square or a horizontally long rectangle. This can enhance the sense of realism.

[0230] The wearing portion 8402 preferably has plasticity and elasticity so that it can be adjusted according to the size of the user's face and does not slip off. Furthermore, a portion of the wearing portion 8402 preferably has a vibration mechanism that functions as a bone conduction earphone, for example. This allows the user to enjoy video and audio simply by wearing the device, without the need for separate earphones or audio equipment such as a speaker. The housing 8401 may also have a function for outputting audio data via wireless communication, for example.

[0231] The mounting portion 8402 and the buffer member 8403 are portions that come into contact with the user's face (forehead, cheek, etc.). The close contact of the buffer member 8403 with the user's face can prevent light leakage and enhance the sense of immersion. The buffer member 8403 is preferably made of a soft material so that it can be in close contact with the user's face when the user wears the head-mounted display 8400. For example, materials such as rubber, silicone rubber, urethane, or sponge can be used. Furthermore, for example, using a sponge or the like with a surface covered with cloth or leather (natural leather or synthetic leather) can prevent gaps from forming between the user's face and the buffer member 8403, thereby effectively preventing light leakage. Furthermore, using such materials is preferable because they are pleasant to the touch and do not cause the user to feel cold when worn, for example, in cold seasons. It is preferable that components that come into contact with the user's skin, such as the buffer member 8403 or the mounting portion 8402, be removable for easy cleaning or replacement.

[0232] The semiconductor device according to one embodiment of the present invention can be applied to the display portion 8404.

[0233] 11A is a diagram showing an example of a television device. A television device 7100 has a display unit 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0234] In FIG. 11A , the semiconductor device according to one embodiment of the present invention can be applied to the display portion 7000 .

[0235] 11A can be operated using an operation switch provided on the housing 7101 or a separate remote control 7111. Alternatively, a touch sensor may be provided on the display portion 7000, so that the television set 7100 can be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. The television set 7100 can be operated to change channels or volume using operation keys or a touch panel provided on the remote control 7111. Furthermore, an image displayed on the display portion 7000 can be operated.

[0236] The television device 7100 may be configured to include, for example, a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (for example, between a sender and a receiver, or between receivers themselves) information communication.

[0237] 11B is a diagram showing an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0238] In FIG. 11B , the semiconductor device according to one embodiment of the present invention can be applied to the display portion 7000 .

[0239] 11C and 11D are diagrams showing an example of digital signage.

[0240] 11C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0241] 11D is a diagram showing a digital signage device attached to a cylindrical pole. The digital signage device 7400 has a display unit 7000 provided along the curved surface of a pole 7401.

[0242] 11C and 11D, the semiconductor device according to one embodiment of the present invention can be applied to the display portion 7000.

[0243] The larger the display unit 7000 of the digital signage 7300 or the digital signage 7400, the more information can be provided at one time. Furthermore, the larger the display unit 7000, the more easily it attracts people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0244] Furthermore, it is preferable that the digital signage 7300 or the digital signage 7400 has a touch panel applied to the display unit 7000. This not only allows images or videos to be displayed on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0245] 11C and 11D , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with, for example, an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, by operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0246] Furthermore, the digital signage 7300 or the digital signage 7400 can also run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0247] 11E illustrates an example of an information terminal. The information terminal 7550 includes a housing 7551, a display portion 7552, a microphone 7557, a speaker portion 7554, a camera 7553, an operation switch 7555, and the like. A semiconductor device according to one embodiment of the present invention can be applied to the display portion 7552. The display portion 7552 can function as a touch panel. The information terminal 7550 can include an antenna, a battery, and the like inside the housing 7551. The information terminal 7550 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

[0248] 11F is a diagram illustrating an example of a wristwatch-type information terminal. The information terminal 7660 includes a housing 7661, a display portion 7662, a band 7663, a buckle 7664, operation switches 7665, and an input / output terminal 7666. A semiconductor device according to one embodiment of the present invention can be applied to the display portion 7662. The information terminal 7660 can include, for example, an antenna and a battery inside the housing 7661. The information terminal 7660 can run various applications, such as mobile phone calls, emails, text browsing and creation, music playback, Internet communication, and computer games.

[0249] The information terminal 7660 also includes a touch sensor on the display portion 7662, allowing it to be operated by touching the screen with a finger or a stylus, for example. For example, an application can be started by touching an icon 7667 displayed on the display portion 7662. The operation switch 7665 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, or power saving mode activation / deactivation. For example, the functions of the operation switch 7665 can be set by an operating system incorporated in the information terminal 7660.

[0250] The information terminal 7660 can also perform short-range wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wireless headset. The information terminal 7660 can also transmit and receive data to and from other information terminals via the input / output terminal 7666. Charging can also be performed via the input / output terminal 7666. Note that charging may also be performed by wireless power supply without using the input / output terminal 7666.

[0251] 12A is a diagram illustrating the appearance of an automobile 9700. FIG. 12B is a diagram illustrating a driver's seat of the automobile 9700. The automobile 9700 includes a body 9701, wheels 9702, a dashboard 9703, and lights 9704. A display device according to one embodiment of the present invention can be used for, for example, a display portion of the automobile 9700. For example, the display device according to one embodiment of the present invention can be applied to each of display portions 9710 to 9715 illustrated in FIG. 12B.

[0252] The display portion 9710 and the display portion 9711 are display devices provided on a windshield of an automobile. The display device according to one embodiment of the present invention can be a so-called see-through display device, in which the other side can be seen through, by forming electrodes of the display device using a light-transmitting conductive material. A see-through display device does not obstruct visibility even when driving the automobile 9700. Therefore, the display device according to one embodiment of the present invention can be installed on the windshield of the automobile 9700. Note that when the display device includes a transistor for driving the display device, for example, the transistor may be a light-transmitting transistor, such as an organic transistor using an organic semiconductor material or a transistor using an oxide semiconductor.

[0253] The display portion 9712 is a display device provided at a pillar portion. For example, by displaying an image from an imaging means provided in the vehicle body 9701 on the display portion 9712, the view blocked by the pillar can be complemented. The display portion 9713 is a display device provided at the dashboard 9703. For example, by displaying an image from an imaging means provided in the vehicle body 9701 on the display portion 9713, the view blocked by the dashboard 9703 can be complemented. That is, the automobile 9700 can complement blind spots and improve safety by displaying images from an imaging means provided in the vehicle body 9701 on the display portions 9712 and 9713. Furthermore, by displaying an image that complements the invisible parts, safety can be confirmed more naturally and without discomfort.

[0254] 13 is a diagram showing the interior of an automobile 9700 that employs bench seats for the driver's seat and the passenger seat. The display portion 9721 is a display device provided in a door portion. For example, by displaying an image from an imaging unit provided in the vehicle body 9701 on the display portion 9721, it is possible to complement the view blocked by the door. The display portion 9722 is a display device provided in a steering wheel. The display portion 9723 is a display device provided in the center of the seat surface of the bench seat. A display device according to one embodiment of the present invention can be applied to each of the display portions 9721 to 9723.

[0255] The display unit 9714, the display unit 9715, or the display unit 9722 can provide the user with various information by displaying, for example, navigation information, driving speed, engine RPM, mileage, remaining fuel, gear status, or air conditioning settings. The display items and layout displayed on the display unit can be changed as appropriate to suit the user's preferences. The information can also be displayed on one or more of the display units 9710 to 9713, the display unit 9721, and the display unit 9723. One or more of the display units 9710 to 9715 and the display units 9721 to 9723 can also be used as lighting devices.

[0256] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments mode.

[0257] In this example, an actually designed MCU will be described. The MCU can be suitably used as a part of an xR device such as a VR device or an AR device. A semiconductor device according to one embodiment of the present invention can be suitably used for the MCU shown in this example.

[0258] Table 1 shows some of the modules and functions of the designed MCU.

[0259]

[0260] The designed MCU uses the Arm® Cortex®-M0 CPU core. It also uses the Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) of the Advanced Microcontroller Bus Architecture (AMBA), as well as the Peripheral Component Interconnect (PCI) system bus. It also includes functions for clock control (RCC: Reset and Clock Control) and power management (PMU: Power Management Unit). The board also includes interfaces such as a system controller, default slave, proprietary interface, GPIO (General Purpose Input / Output), DMA (Direct Memory Access), timer, UART (Universal Asynchronous Receiver Transmitter), PCI (Peripheral Component Interconnect), I2C (Inter-Integrated Circuit), and SPI (Serial Peripheral Interface). The chip also includes clock generation using a multiplier circuit and a divider circuit, a power supply circuit with a power switch, and a 12-bit analog-to-digital converter (ADC). It also includes static random access memory (SRAM) with error check and correction (ECC) and NOSRAM (registered trademark). DRAM (dynamic random access memory) may also be included. It also includes a scan chain-based debug circuit for the CPU core and peripheral circuits, and a triple modular redundancy (TMR) flip-flop function to protect against soft errors. It may also include a bit interleaving function and a memory scrubbing function.It also has the functionality to perform power gating for the entire MCU and power gating for each module (fine-grained power gating).

[0261] The designed MCU can suitably use the configuration of the semiconductor device 100 according to one aspect of the present invention. That is, for example, the PMU included in the designed MCU can be made to correspond to the command unit 102 included in the semiconductor device 100, and each module such as a CPU core, memory, and interface can be made to correspond to each component included in the semiconductor device 100.

[0262] For example, when performing arithmetic processing with the CPU core, each interface module can be placed in a power gating state, thereby reducing the power consumption of the interface. Furthermore, for example, when performing data transfer processing using DMA, each interface module other than the CPU core and DMA can be placed in a power gating state, thereby reducing the power consumption of the interface module. This allows for reduced power consumption in the designed MCU.

[0263] Furthermore, for example, when transitioning from a state in which a CPU core performs arithmetic processing to a state in which data transfer processing is performed by DMA, the DMA data transfer processing can be immediately executed. Also, for example, when transitioning from a state in which a DMA data transfer processing is performed to a state in which a CPU core performs arithmetic processing, the arithmetic processing can be immediately executed. Therefore, the operating speed of the designed MCU can be increased.

[0264] 100: semiconductor device, 101-1: component, 101-2: component, 101-L: component, 102: command unit, 103: power supply line, 104: functional circuit, 105: switch, 106: memory unit, 107: memory circuit, 108: memory circuit, 90: memory cell array, 91: word line driver circuit, 92: bit line driver circuit, 93: capacitor, OS1: transistor, OS2: transistor, OS3: transistor, M1: transistor, M2: transistor, MC: memory cell, MC_A: memory cell, MC_B: memory cell, MC_C: Memory cell, MC_D: memory cell, MC_E: memory cell, SN: charge retention node, BL: bit line, BL_1: bit line, BL_n: bit line, WL: word line, WL_1: word line, WL_m: word line, BGL: back gate line, RBL: read bit line, RWL: read word line, WBL: write bit line, WWL: write word line, CL: capacitance line, SL: source line, 70: scan flip-flop, 71: selector, 72: flip-flop, 80: data storage circuit, 81: capacitance element, OS11: transistor, OS12: Transistor, OS13: Transistor, FN11: Node, PL: Terminal, SE: Terminal, D: Terminal, SD: Terminal, CLK: Terminal, DF: Terminal, QF: Terminal, Q: Terminal, BK: Terminal, RE: Terminal, SD_IN: Terminal, 110: Semiconductor device, CORE: Processor core, CORE_REG: Register, CORE_MEM: Memory, IF1: Interface, IF1_REG: Register, IF1_MEM: Memory, IF2: Interface, IF2_REG: Register, IF2_MEM: Memory, MEM: Memory, S11: Step, S12: Step step, S13: step, S14: step, S21: step, S22: step, S23: step, S24: step, 300A: display device, 300B: display device, 10: layer, 20: layer, 30: layer, 60: layer, 11: memory unit, 21: functional circuit, 22: control circuit, 23: display unit drive circuit, 23M: memory circuit, 25: image processing circuit, 25M: memory circuit, 26: sensor circuit, 26M: memory circuit, 27: communication circuit, 27M: memory circuit, 28: input / output circuit, 28M: memory circuit, 29: terminal unit, 31: display unit, 40: sealing substrate, 50: pixel, 51: pixel circuit

Claims

1. A display device comprising a display unit, a display unit drive circuit, and a command unit, the display unit drive circuit includes a first storage circuit having a function of storing first setting information in a state where power is supplied, and a second storage circuit having a function of storing the first setting information in a state where power is not supplied, the command unit has a function of controlling whether or not power is supplied to the display unit drive circuit, the display unit drive circuit has a function of writing the first setting information stored in the first storage circuit to the second storage circuit and bringing the display unit into a power-off state, and a function of storing the first setting information read from the second storage circuit in the first storage circuit and bringing the display unit into a power-on state; a display device, wherein the second memory circuit includes a transistor including a metal oxide in a semiconductor layer in which a channel is formed, the first memory circuit and the command unit are provided in a first layer, the second memory circuit and the display unit are provided on a second layer above the first layer; Display device.

2. In claim 1, the second memory circuit includes a first transistor and a capacitance element; one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitance element; the first transistor has a function of being in a non-conductive state when no power is supplied, the capacitance element has a function of retaining charge on one electrode of the capacitance element when the first transistor is in a non-conductive state; the first transistor includes a metal oxide in a semiconductor layer in which a channel is formed; Display device.

3. In claim 1, the second memory circuit includes a first transistor and a second transistor; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; the first transistor has a function of being in a non-conductive state when no power is supplied, the second transistor has a function of retaining charge at a gate of the second transistor when the first transistor is in a non-conductive state; the first transistor includes a metal oxide in a semiconductor layer in which a channel is formed; Display device.