Semiconductor device, storage device, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that enables miniaturization and high integration. A semiconductor device having a transistor and a capacitance element, wherein: the transistor has an oxide, a first conductor and a second conductor on the oxide, a first insulator disposed on the first conductor and the second conductor and having a first opening and a second opening, a second insulator inside the first opening of the first insulator, and a third conductor on the second insulator; the first opening of the first insulator has a region that overlaps the oxide; the third conductor has a region that overlaps the oxide with the second insulator therebetween; the capacitance element has the second conductor, the third conductor inside the second opening of the first insulator, and a fourth conductor on the third insulator; and the distance between the first conductor and the second conductor is less than the width of the first opening when viewing a cross-section in the channel length direction of the transistor.

Description

Semiconductor device, memory device, and method for manufacturing semiconductor device

[0001] One embodiment of the present invention relates to a method for manufacturing a metal oxide, a transistor, a semiconductor device, and an electronic device, a method for manufacturing a semiconductor device, or a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Another embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits.

[0009] JP 2012-257187 A JP 2011-151383 A

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a reduced number of steps.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a transistor and a capacitor. The transistor includes an oxide, a first conductor and a second conductor over the oxide, a first insulator disposed over the first conductor and the second conductor and having a first opening and a second opening, a second insulator in the first opening of the first insulator, and a third conductor over the second insulator. The first opening of the first insulator has a region overlapping with the oxide, and the third conductor overlaps with the second insulator. the second insulator has regions that are in contact with an upper surface of the oxide and a sidewall of a first opening in the first insulator, the capacitive element has a second conductor, a third insulator on the second conductor, and a fourth conductor on the third insulator, the third insulator and the fourth conductor being disposed within the second opening, and in a cross-sectional view in the channel length direction of the transistor, the distance between the first conductor and the second conductor is smaller than the width of the first opening.

[0013] In the above semiconductor device, it is preferable that the second opening of the first insulator has a region overlapping with the second conductor, the fourth conductor has a region overlapping with the second conductor via the third insulator, and the third insulator has regions in contact with the top surface of the second conductor and the sidewall of the first opening of the first insulator, respectively.

[0014] Furthermore, in the above-described semiconductor device, it is preferable that the second insulator has a fourth insulator, a fifth insulator on the fourth insulator, and a sixth insulator on the fifth insulator, the third insulator has a seventh insulator, an eighth insulator on the seventh insulator, and a ninth insulator on the eighth insulator, the film thickness of the fourth insulator has a region smaller than the film thickness of the fifth insulator, the sixth insulator is less permeable to oxygen than the fifth insulator, the film thickness of the seventh insulator has a region smaller than the film thickness of the eighth insulator, and the ninth insulator is less permeable to oxygen than the eighth insulator.

[0015] Furthermore, in the above semiconductor device, it is preferable that the fourth insulator has the same insulating material as the seventh insulator, the fifth insulator has the same insulating material as the eighth insulator, the sixth insulator has the same insulating material as the ninth insulator, and the third conductor has the same conductive material as the fourth conductor.

[0016] Furthermore, in the above semiconductor device, it is preferable that a tenth insulator is provided between the first conductor and the second conductor and the first insulator, the tenth insulator has a third opening overlapping with the first opening and a fourth opening overlapping with the second opening, the tenth insulator is less permeable to oxygen than the fourth insulator and the seventh insulator, the tenth insulator has regions in contact with a side surface of the oxide, a side surface of the first conductor, and a side surface of the second conductor, respectively, and the distance between the first conductor and the second conductor in a cross-sectional view in the channel length direction of the transistor is smaller than the width of the third opening.

[0017] Furthermore, in the above semiconductor device, it is preferable that the first conductor has a fifth conductor and a sixth conductor on the fifth conductor, the second conductor has a seventh conductor and an eighth conductor on the seventh conductor, and in a cross-sectional view of the transistor in the channel length direction, the distance between the fifth conductor and the seventh conductor is smaller than the distance between the sixth conductor and the eighth conductor.

[0018] In the semiconductor device, it is preferable that the opposing side surfaces of the first conductor and the second conductor are substantially perpendicular to the upper surface of the oxide.

[0019] In the semiconductor device, the oxide preferably contains indium, zinc, and one or more selected from the group consisting of gallium, aluminum, and tin.

[0020] In the semiconductor device, the oxide preferably has crystals, and the c-axes of the crystals are preferably approximately perpendicular to the surface of the oxide or a surface on which the oxide is formed.

[0021] In the above semiconductor device, it is preferable that a ninth conductor be provided under the oxide, and that the ninth conductor overlap with the oxide and the third conductor.

[0022] Another aspect of the present invention is a memory device having a plurality of layers each having a memory array in which the above-mentioned semiconductor device is provided, each layer having a first wiring electrically connected to a first conductor, a second wiring electrically connected to a third conductor, and a third wiring electrically connected to a fourth conductor, and in successive layers, a ninth conductor in an upper layer is electrically connected to the third wiring in a lower layer, and in successive layers, the second wiring in a lower layer is positioned so as to overlap with the third wiring in an upper layer.

[0023] In the memory device, it is preferable that the first wirings in the odd-numbered layers are electrically connected to each other, and the first wirings in the even-numbered layers are electrically connected to each other.

[0024] Preferably, the storage device further includes a driver circuit, and the plurality of layers are provided over the driver circuit.

[0025] Another embodiment of the present invention provides a method for manufacturing a semiconductor device including a transistor and a capacitor, the transistor including an oxide, first to third conductors, a first insulator, and a second insulator, and the capacitor including a second conductor, a third insulator, and a fourth conductor. The method includes forming a first insulator to cover the oxide and a conductive layer over the oxide, forming a first opening and a second opening in the first insulator, which expose a top surface and side surfaces of the conductive layer and a side surface of the oxide, and forming a mask layer that covers the first insulator and the second opening. a third opening overlapping with a first opening, the width of the third opening being smaller than the width of the first opening in a cross-sectional view in a channel length direction of the transistor; a conductive layer being etched using a mask layer to form a first conductor and a second conductor; an insulating film being formed to cover the first insulator, the first opening, and the second opening; a conductive film being formed over the insulating film; portions of the insulating film and the conductive film that are exposed through the first opening and the second opening being removed; a second insulator and a third conductor being formed in the first opening; and a third insulator and a fourth conductor being formed in the second opening.

[0026] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with a reduced number of steps can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc.

[0028] FIG. 1A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 1B to 1D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIGS. 3A and 3B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 4A is a top view of a semiconductor device according to one embodiment of the present invention. FIGS. 4B to 4D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 9B to 9D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 11A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 11B to 11D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 13A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 14A is a top view illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.15B to 15D are cross-sectional views illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention. FIG. 16A is a top view illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention. FIGS. 16B to 16D are cross-sectional views illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention. FIG. 17A is a top view illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention. FIGS. 17B to 17D are cross-sectional views illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention. FIG. 18 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 19 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 20 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 21 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 22A is a plan view of a semiconductor device according to one embodiment of the present invention. FIGS. 22B and 22C are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 23A is a plan view of a semiconductor device according to one embodiment of the present invention. FIG. 23B is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 24 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIGS. 25A to 25C are a block diagram, a schematic diagram, and a circuit diagram illustrating a configuration of a memory device according to one embodiment of the present invention. FIGS. 26A and 26B are schematic diagrams illustrating a configuration of a memory device according to one embodiment of the present invention. FIGS. 27A and 27B are schematic diagrams and circuit diagrams illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 28 is a schematic diagram illustrating a configuration of a memory device according to one embodiment of the present invention. FIGS. 29A and 29B are layout diagrams illustrating a configuration of a memory device according to one embodiment of the present invention. FIGS. 30A and 30B are layout diagrams and schematic cross-sectional diagrams illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 31 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 32 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 33 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIGS. 34A and 34B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. FIGS. 35A and 35B are diagrams illustrating an example of an electronic component. FIGS. 36A to 36E are schematic diagrams of memory devices according to one embodiment of the present invention.37A to 37H are diagrams showing an electronic device according to one aspect of the present invention, and Fig. 38 is a diagram showing an example of a space device.

[0029] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0030] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0031] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0032] In addition, in this specification and the like, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc., for explanation. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification and the like.

[0033] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0034] For example, in this specification, "X and Y are connected" refers to an electrical connection between X and Y. Here, "X and Y are electrically connected" refers to a connection in which an electrical signal can be transmitted between X and Y when an object (such as a switch, transistor element, or diode, or a circuit including such an object and wiring) is present between X and Y. Note that "X and Y are electrically connected" also includes a case in which X and Y are directly connected. Here, "X and Y are directly connected" refers to a connection in which an electrical signal can be transmitted between X and Y via wiring (or electrodes) or the like, without passing through the object. In other words, a direct connection refers to a connection that can be regarded as the same circuit diagram when represented by an equivalent circuit.

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0036] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0037] Note that the channel length refers to, for example, the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0038] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0039] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may become unnegligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0040] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0041] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, for example.

[0042] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor, reduce the crystallinity, and so on. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, oxygen vacancies (also called oxygen vacancies) may be formed.

[0043] In this specification and the like, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. Silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen. Aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen. Hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0044] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0045] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0047] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ This means that it is A or below.

[0048] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0049] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m, n]” may be added to the symbol.

[0050] In this specification, the term "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also considered to be "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height."

[0051] In this specification, "edges that coincide or approximately coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges that coincide or approximately coincide" is also used.

[0052] 1A to 23B , an example of a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. The semiconductor device according to one embodiment of the present invention includes a transistor and a capacitor.

[0053] <Configuration Example of Semiconductor Device> The configuration of a semiconductor device including a transistor 200 and a capacitor 100 will be described with reference to FIG. 1. FIGS. 1A to 1D are a top view and a cross-sectional view of a semiconductor device including the transistor 200 and the capacitor 100. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 200 and the capacitor 100 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A and is also a cross-sectional view of the capacitor 100 in the channel width direction. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0054] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 and a capacitor 100 on the insulator 214, an insulator 280 over the insulator 275 and the insulator 271 (insulators 271a and 271b) provided in the transistor 200, an insulator 282 over the insulator 280, an insulator 283 over the insulator 282, an insulator 274 over the insulator 283, and an insulator 285 over the insulator 283 and the insulator 274. The insulators 212, 214, 280, 282, 283, 285, 274, and 285 function as interlayer films. The insulator 283 is in contact with part of the top surface of the insulator 214, the side surface of the insulator 280, and the side surface and top surface of the insulator 282. As shown in FIG. 1 , the transistor 200 and the capacitor 100 are arranged so that at least a portion of them is embedded in the insulator 280.

[0055] Here, the transistor 200 includes an oxide 230 that functions as a semiconductor layer, a conductor 260 that functions as a first gate, a conductor 205 that functions as a second gate, a conductor 242a that functions as one of a source and a drain, and a conductor 242b that functions as the other of the source and the drain. The transistor 200 also includes an insulator 252, an insulator 250, and an insulator 254 that function as a first gate insulating film. The transistor 200 also includes an insulator 222 and an insulator 224 that function as a second gate insulating film.

[0056] The first gate and the first gate insulating film of the transistor 200 are disposed in an opening 258 formed in the insulators 280, 275, and 271. That is, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are disposed in the opening 258.

[0057] The capacitor 100 includes a conductor 242b that functions as a lower electrode, insulators 152, 150, and 154 that function as dielectrics, and a conductor 160 that functions as an upper electrode. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. The conductor 242b can serve as both the lower electrode of the capacitor 100 and the other of the source and drain of the transistor 200. Therefore, part of the manufacturing process of the transistor 200 can be used in the manufacturing process of the capacitor 100, thereby providing a semiconductor device with high productivity.

[0058] The upper electrode and dielectric of the capacitor element 100 are disposed in the opening 158 formed in the insulators 280, 275, and 271. That is, the conductor 160, the insulator 152, the insulator 150, and the insulator 154 are disposed in the opening 158.

[0059] The semiconductor device of one embodiment of the present invention also includes a conductor 240 that is electrically connected to the transistor 200 and functions as a plug. An insulator 241 is provided in contact with a side surface of the conductor 240. The conductor 240 is electrically connected to a conductor 242a. A conductor 246 that is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 285 and the conductor 240.

[0060] The conductors 240 and 246 function as plugs or wirings for electrically connecting the transistor 200 to circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes.

[0061] The semiconductor device including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. In this case, the conductor 246 may be electrically connected to a sense amplifier. Here, as shown in FIG. 1A , both the transistor 200 and the capacitor 100 are formed over the oxide 230. Therefore, the capacitor 100 can be provided without significantly increasing the occupied area in a plan view, which allows miniaturization or high integration of the semiconductor device according to this embodiment.

[0062] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a and 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, an insulator 271a on the conductor 242a, and an oxide 271b on the oxide 230b. The semiconductor device has conductor 242b, insulator 271b on conductor 242b, insulator 252 on oxide 230b, insulator 250 on insulator 252, insulator 254 on insulator 250, conductor 260 (conductor 260a and conductor 260b) located on insulator 254 and overlapping with part of oxide 230b, and insulator 275 arranged on insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 271a, and insulator 271b. 1B and 1C , insulator 252 contacts at least a portion of the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface and top surface of oxide 230b, the side surfaces of conductors 242a and 242b, the side surfaces of insulators 271a and 271b, the side surface of insulator 275, the side surface of insulator 280, and the bottom surface of insulator 250. Furthermore, the top surface of conductor 260 is positioned so as to be roughly flush with the top of insulator 254, the top of insulator 250, the top of insulator 252, and the top surface of insulator 280. Furthermore, insulator 282 contacts at least a portion of the top surfaces of conductor 260, insulator 252, insulator 250, insulator 254, and insulator 280.

[0063] In this specification and the like, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0064] The insulators 280, 271, and 275 have openings 258 that reach the oxide 230b. That is, the openings 258 can be said to have a region overlapping with the oxide 230b. The insulator 275 can be said to have an opening that overlaps with the opening 258 of the insulator 280. The insulators 252, 250, 254, and conductor 260 are arranged in the opening 258. That is, the conductor 260 has a region overlapping with the oxide 230b with the insulators 252, 250, and 254 interposed therebetween. In the channel length direction of the transistor 200, the conductor 260, the insulator 252, the insulator 250, and the insulator 254 are provided between the insulator 271a and the conductor 242a and the insulator 271b and the conductor 242b. The insulator 254 has a region in contact with the side surface of the conductor 260 and a region in contact with the bottom surface of the conductor 260. Note that, as shown in FIG. 1C , the opening 258 reaches the insulator 222 in the region where it does not overlap with the oxide 230.

[0065] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0066] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0067] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulators 252, 250, and 254 function as first gate insulators, and the insulators 222 and 224 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0068] Here, FIG. 2A shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 2A, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a and the conductor 242b is preferably smaller than the width of the opening 258. Here, the width of the opening 258 corresponds to the distance L1 between the interface between the insulator 280 and the insulator 252 on the conductor 242a side and the interface between the insulator 280 and the insulator 252 on the conductor 242b side, as shown in FIG. 2A. As will be described in detail later, in this embodiment, channel etching of the conductors 242a and 242b is performed after the formation of the opening 258. With this configuration, the distance L2 between the conductors 242a and 242b can be made relatively easily into a very fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more).

[0069] 2A and 1C , the opening 258 can also be considered to have a shape in which a part of the structure consisting of the insulator 224, the oxide 230, and the conductor 242 protrudes into an opening having the insulator 222 as a bottom surface and the insulators 280, 275, and 271 as side surfaces. Furthermore, in the structure consisting of the insulator 224, the oxide 230, and the conductor 242, the region of the oxide 230 sandwiched between the conductors 242a and 242b can be considered to be exposed.

[0070] 2A and 1C , an insulator 252 is provided in contact with the bottom surface and inner wall of the opening 258. Thus, the insulator 252 is in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the top surface and side surface of the oxide 230b, a portion of the top surface and side surface of the conductor 242a, a portion of the top surface and side surface of the conductor 242b, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the insulator 275, and the side surface of the insulator 280. Furthermore, the insulator 250, the insulator 254, and the conductor 260 are stacked on the insulator 252. Therefore, the insulator 252, the insulator 250, the insulator 254, and the conductor 260 are provided to cover the conductors 242a and 242b that partially protrude into the opening 258.

[0071] By supplying oxygen to the oxide 230b, a channel formation region is formed in the region of the distance L2 between the conductor 242a and the conductor 242b. Therefore, the channel formation region of the transistor 200 has a very fine structure. As a result, the on-state current of the transistor 200 increases, and the frequency characteristics can be improved.

[0072] 2A , the oxide 230b includes a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0073] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. Therefore, the region 230bc can be said to be i-type (intrinsic) or substantially i-type.

[0074] Furthermore, the regions 230ba and 230bb, which function as source and drain regions, have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces resistance. That is, the regions 230ba and 230bb are n-type regions with a higher carrier concentration and lower resistance than the region 230bc.

[0075] 2A, the opposing side surfaces of the conductor 242a and the conductor 242b are preferably approximately perpendicular to the top surface of the oxide 230b. This configuration can prevent the side edge of the region 230ba formed under the conductor 242a, facing the region 230bc, from being excessively recessed from the side edge of the conductor 242a facing the region 230bc. Similarly, the side edge of the region 230bb formed under the conductor 242b, facing the region 230bc, can be prevented from being excessively recessed from the side edge of the conductor 242b facing the region 230bc. This can reduce the formation of offset regions (so-called Loff regions) between the regions 230ba and 230bc and between the regions 230bb and 230bc.

[0076] As a result, the frequency characteristics of the transistor 200 can be improved, and the operation speed of the semiconductor device according to one embodiment of the present invention can be increased. For example, when the semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, the writing speed and reading speed can be improved.

[0077] The carrier concentration of the region 230bc functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0078] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, whose carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0079] 2A shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0080] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in a region closer to the channel formation region.

[0081] In the transistor 200, a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a and the oxide 230b) including the channel formation region.

[0082] The band gap of the metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of a transistor.

[0083] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In—Ga oxide, In—Zn oxide, or indium oxide may be used as oxide 230.

[0084] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0085] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have a large on-state current and high frequency characteristics.

[0086] Furthermore, since the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230a and the oxide 230b can be reduced. This reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0087] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of the oxide 230b is provided as the oxide 230, a metal oxide that can be used for the oxide 230a may be applied as the oxide 230b.

[0088] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0089] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0090] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide is not polycrystallized after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0091] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0092] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0093] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in a region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0094] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0095] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb. It is also preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, etc.

[0096] Therefore, in this embodiment, the semiconductor device is configured to efficiently supply oxygen to the region 230bc and to suppress oxidation of the conductors 242a, 242b, and 260.

[0097] To supply oxygen to the region 230bc, it is preferable to use an insulator that is easily permeable to oxygen as the insulator 250. It is also preferable to use an insulator containing excess oxygen as the insulator 280. With this configuration, the oxygen contained in the insulator 280 can be supplied to the region 230bc via the insulator 250.

[0098] Furthermore, in order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide an insulator having a function of suppressing the diffusion of oxygen near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 252, the insulator 254, and the insulator 275.

[0099] The insulator 252 preferably has a barrier property against oxygen. The insulator 252 is provided between the insulator 250 and the conductor 242a and between the insulator 250 and the conductor 242b. This prevents oxygen contained in the insulator 250 from diffusing to the conductor 242a and the conductor 242b, thereby suppressing oxidation of the conductor 242a and the conductor 242b. Alternatively, the amount of oxygen contained in the insulator 250 that diffuses to the conductor 242a and the conductor 242b is reduced, thereby thinning the oxide layer formed on the side surfaces of the conductor 242a and the conductor 242b. The insulator 252 is also provided between the insulator 250 and the oxide 230b. This prevents oxygen from being released from the region 230bc of the oxide 230b during heat treatment or the like.

[0100] Note that the insulator 252 is preferably thin. For example, the insulator 252 preferably has a region where its thickness is smaller than that of the insulator 250. The insulator 250 has a region in contact with the top surface of the oxide 230b. By thinning the insulator 252, oxygen contained in the insulator 250 can be supplied to the region 230bc of the oxide 230b, thereby preventing excessive supply of oxygen contained in the insulator 250. Furthermore, the insulator 252 is provided between the insulators 280 and 250, and has a region in contact with the sidewall of the opening of the insulator 280. By thinning the insulator 252, oxygen contained in the insulator 280 can be supplied to the insulator 250, thereby preventing excessive supply of oxygen contained in the insulator 280.

[0101] The insulator 254 preferably has a barrier property against oxygen. The insulator 254 is provided between the insulator 250 and the conductor 260. Therefore, oxygen contained in the insulator 250 can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. Note that the insulator 254 only needs to be at least less permeable to oxygen than the insulator 250.

[0102] It is preferable to use an insulator having a function of suppressing oxygen permeation as the insulator 275. The insulator 275 is provided between the insulator 280 and the conductors 242a and 242b. This configuration can suppress the oxygen contained in the insulator 280 from diffusing into the conductors 242a and 242b. Therefore, it is possible to suppress the conductors 242a and 242b from being oxidized by the oxygen contained in the insulator 280, which increases their resistivity and reduces the on-current. Note that the insulator 275 only needs to be at least less permeable to oxygen than the insulator 250.

[0103] By adopting the above-described structure, the region 230bc functioning as a channel formation region can be made i-type or substantially i-type, and the regions 230ba and 230bb functioning as source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the semiconductor device can maintain excellent electrical characteristics even when miniaturized or highly integrated. For example, even when the distance L2 shown in FIG. 2A is 20 nm or less, 15 nm or less, 10 nm or less, or 7 nm or less, or 2 nm or more, 3 nm or more, or 5 nm or more, excellent electrical characteristics can be obtained.

[0104] Furthermore, miniaturization of the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved. When the gate length is within any of the above ranges, the cutoff frequency of the transistor can be set to 50 GHz or higher, or 100 GHz or higher, for example, in a room temperature environment.

[0105] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0106] One or more of the conductors 242a, 242b, and 260 may have a layered structure. For example, when the conductors 242a and 242b have a layered structure, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion may be used as a layer in contact with the oxide 230b. Furthermore, for example, when the conductor 260 has a layered structure of the conductors 260a and 260b as shown in FIG. 1B, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion may be used as the conductor 260a.

[0107] It is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. It is preferable to use a metal oxide applicable to the oxide 230 described above as the oxide. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. CAAC-OS is a crystalline oxide, and the c-axis of the crystal is approximately perpendicular to the surface of the oxide or the surface on which it is formed. This can prevent oxygen from being extracted from the oxide 230b by the conductor 242a or the conductor 242b. It can also prevent a decrease in the conductivity of the conductor 242a and the conductor 242b.

[0108] Furthermore, the insulator 282 provided over the insulator 280 is preferably formed by a method that can add oxygen to the insulator 280. This allows the insulator 280 to contain excess oxygen.

[0109] In addition to the above structure, the semiconductor device in this embodiment has a structure that prevents hydrogen from entering the transistor 200. For example, an insulator that has a function of suppressing hydrogen diffusion is provided to cover the transistor 200. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 212 and the insulator 283.

[0110] An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 212. This can suppress diffusion of hydrogen from below the insulator 212 to the transistor 200.

[0111] An insulator having a function of suppressing diffusion of hydrogen is preferably used as the insulator 283. This can suppress diffusion of hydrogen from above the insulator 283 to the transistor 200. Furthermore, diffusion of hydrogen contained in the insulator 274 to the transistor 200 can be suppressed.

[0112] In this embodiment, in a state where the conductors 242a and 242b are provided on the oxide 230b, microwave treatment is performed in an atmosphere containing oxygen, and oxygen vacancies in the region 230bc and V Ｏ The microwave treatment here refers to a treatment using an apparatus having a power source that generates high density plasma using microwaves, for example.

[0113] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can be irradiated onto the region 230bc. The action of the plasma, microwaves, etc. can be used to irradiate the V of the region 230bc. Ｏ The H is split into oxygen vacancies and hydrogen, the hydrogen is removed from the region 230bc, and the oxygen vacancies are compensated for with oxygen. Ｏ H can be reduced to lower the carrier concentration.

[0114] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 271 and 280 that cover the oxide 230b and the conductor 242. As a result, during microwave processing, V Ｏ Since the reduction of H and the supply of an excessive amount of oxygen do not occur, a decrease in the carrier concentration can be prevented.

[0115] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 252 or after forming the insulating film that becomes the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 252 or the insulator 250 in this manner, oxygen can be efficiently injected into the region 230bc. Furthermore, by arranging the insulator 252 so that it is in contact with the side surface of the conductor 242 and the surface of the region 230bc, it is possible to prevent more oxygen than necessary from being injected into the region 230bc and to prevent oxidation of the side surface of the conductor 242. Furthermore, it is possible to prevent oxidation of the side surface of the conductor 242 during the formation of the insulating film that becomes the insulator 250.

[0116] The oxygen implanted into the region 230bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 230bc may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 252 and the insulator 250 can be improved, thereby improving the reliability of the transistor 200.

[0117] In this manner, oxygen vacancies and V Ｏ By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, and the n-type state of the regions before the microwave treatment can be maintained. This prevents fluctuations in the electrical characteristics of the transistor 200 and prevents variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0118] By adopting the above-described configuration, it is possible to provide a semiconductor device with little variation in transistor characteristics. It is also possible to provide a semiconductor device with good frequency characteristics. It is also possible to provide a semiconductor device with high operating speed. It is also possible to provide a semiconductor device with good reliability. It is also possible to provide a semiconductor device with good electrical characteristics. It is also possible to provide a semiconductor device that allows for miniaturization or high integration.

[0119] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0120] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. By using such a shape, the coverage of the insulator 252, the insulator 250, the insulator 254, and the conductor 260 with the oxide 230b can be improved.

[0121] 1C and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide or In—Zn oxide. The increase in the atomic ratio of indium near the surface of the oxide 230, particularly the oxide 230b, can improve the field-effect mobility of the transistor 200.

[0122] At least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side or from above the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 275, 282, 283, and 285 preferably suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0123] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0124] For the insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 212, 275, and 283. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 214, 271, 282, and 285. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress diffusion of impurities such as water and hydrogen toward the transistor 200 from an interlayer insulating film disposed outside the insulator 285. Alternatively, it is possible to suppress diffusion of oxygen contained in the insulator 224 or the like toward the substrate through the insulators 212 and 214. Alternatively, it is possible to suppress diffusion of oxygen contained in the insulator 280 or the like toward a position above the transistor 200 through the insulator 282 or the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing diffusion of impurities such as water and hydrogen, and oxygen.

[0125] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO ｘ (x is any number greater than 0), or MgO ｙ(y is an arbitrary number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured.

[0126] Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 preferably have an amorphous structure, but may have a polycrystalline structure region formed in a portion thereof. Furthermore, the insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0127] The insulators 212, 214, 271, 275, 282, 283, and 285 can be formed by, for example, a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the film formation gas, and therefore the hydrogen concentrations of the insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. The film formation method is not limited to sputtering, and may be chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like, as appropriate.

[0128] It may also be preferable to reduce the resistivity of the insulators 212, 275, and 283. For example, it may be preferable to reduce the resistivity of the insulators 212, 275, and 283 to approximately 1×10 １３ By setting the resistivity to Ωcm, the insulators 212, 275, and 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulators 212, 275, and 283 is preferably 1×10 １０ Ωcm or more 1×10 １５ Ωcm or less.

[0129] The insulators 216, 274, 280, and 285 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 216, 274, 280, and 285.

[0130] The conductor 205 is arranged to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. In addition, a part of the conductor 205 may be embedded in the insulator 214.

[0131] The conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0132] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0133] By using a conductive material for the conductor 205a that has the function of reducing hydrogen diffusion, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulators 216 and 224, etc. Furthermore, by using a conductive material for the conductor 205a that has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be formed as a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0134] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0135] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0136] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0137] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to an area outside the channel width direction ends of the oxide 230a and the oxide 230b. That is, outside the side surfaces of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0138] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a type of Fin structure. In this specification and the like, the Fin structure refers to a structure in which the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to obtain a transistor in which the short channel effect is less likely to occur.

[0139] By configuring the transistor 200 as a normally-off transistor and having the above-described S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By configuring the transistor 200 as an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to result in an improvement in the on-state current of the transistor or an improvement in the field-effect mobility of the transistor.

[0140] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0141] Note that although the conductor 205 in the transistor 200 has a stacked structure of the conductor 205a and the conductor 205b, the present invention is not limited to this. For example, the conductor 205 may have a single layer structure or a stacked structure of three or more layers.

[0142] The insulators 222 and 224 function as gate insulators.

[0143] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0144] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress diffusion of impurities such as hydrogen into the inside of the transistor 200 and suppress the generation of oxygen vacancies in the oxide 230. Furthermore, reaction of the conductor 205 with oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0145] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0146] The insulator 222 may be a single layer or a multilayer insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0147] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0148] During the manufacturing process of the transistor 200, heat treatment is preferably performed while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 550° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen vacancies. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to replenish desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher, followed by another heat treatment in a nitrogen gas or inert gas atmosphere.

[0149] By performing oxygen addition treatment on the oxide 230, oxygen vacancies in the oxide 230 can be repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230 to convert the hydrogen into H ２ As a result, the hydrogen remaining in the oxide 230 is recombined with the oxygen vacancies to form V. Ｏ The formation of H can be suppressed.

[0150] Note that the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape overlapping the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222. Note that in this specification, the term "island shape" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0151] The conductor 242a and the conductor 242b are provided in contact with the top surface of the oxide 230b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0152] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen.

[0153] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0154] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction, as shown in FIG. 1D . This can increase the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0155] Furthermore, when heat treatment is performed while the conductor 242a (conductor 242b) and the oxide 230b are in contact with each other, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) can be reduced in a self-aligned manner.

[0156] The conductors 242a and 242b are preferably formed using a conductive film having compressive stress. This allows strain (hereinafter sometimes referred to as tensile strain) that expands in the tensile direction to be formed in the regions 230ba and 230bb. The tensile strain causes V Ｏ By stably forming H, regions 230ba and 230bb can become stable n-type regions. The compressive stress of conductor 242a is a stress that attempts to relax the compressed shape of conductor 242a, and is a stress with a vector in the direction from the center to the end of conductor 242a. The same applies to the compressive stress of conductor 242b.

[0157] The magnitude of the compressive stress of the conductor 242a may be, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and even more preferably 2000 MPa or more. The magnitude of the stress of the conductor 242a may be determined by preparing a sample in which the conductive film used for the conductor 242a is formed on a substrate and measuring the stress of the sample. The same applies to the magnitude of the compressive stress of the conductor 242b.

[0158] Strain is formed in each of the regions 230ba and 230bb due to the action of compressive stresses of the conductors 242a and 242b. The strain is a strain (tensile strain) that is expanded in the tensile direction due to the action of compressive stresses of the conductors 242a and 242b. When the regions 230ba and 230bb have a CAAC structure, the strain corresponds to elongation in a direction perpendicular to the c-axis of the CAAC structure. When the CAAC structure elongates in a direction perpendicular to the c-axis of the CAAC structure, oxygen vacancies are likely to be formed in the strain. In addition, hydrogen is likely to be taken up in the strain, so V Ｏ Therefore, in this strain, oxygen vacancies and V Ｏ H is easily formed and these easily take a stable structure. As a result, the regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0159] Although the above description has been made on the distortion formed in the oxide 230b, the present invention is not limited to this. Similar distortion may be formed in the oxide 230a.

[0160] In one embodiment of the present invention, it is particularly preferable to use a nitride containing tantalum or a nitride containing titanium as the conductors 242 a and 242 b. In this case, the conductors 242 a and 242 b are conductors containing tantalum or titanium and nitrogen.

[0161] 1A to 1D, the conductor 242 is shown as a single layer, but the present invention is not limited to this and may have a stacked structure of two or more layers. For example, as shown in FIG. 3A, the conductor 242a may have a two-layer stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b may have a two-layer stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, the conductors 242a1 and 242b1 are arranged on the side in contact with the oxide 230b.

[0162] In the following, the conductors 242a1 and 242b1 may be collectively referred to as the lower layer of the conductor 242. The conductors 242a2 and 242b2 may be collectively referred to as the upper layer of the conductor 242.

[0163] The lower layer of the conductor 242 (conductor 242a1 and conductor 242b1) is preferably made of a conductive material that is resistant to oxidation. This prevents the lower layer of the conductor 242 from oxidizing and reducing the conductivity of the conductor 242. The lower layer of the conductor 242 may also have the property of easily absorbing (extracting) hydrogen. This allows hydrogen from the oxide 230 to diffuse into the lower layer of the conductor 242, reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics. Furthermore, the lower layer of the conductor 242 preferably has a large compressive stress, as described above, and preferably has a compressive stress greater than that of the upper layer of the conductor 242. This allows the regions 230ba and 230bb, which are in contact with the lower layer of the conductor 242, to be stable n-type regions with high carrier concentrations, as described above.

[0164] Furthermore, it is preferable that the upper layer of the conductor 242 (conductor 242a2 and conductor 242b2) has higher conductivity than the lower layer of the conductor 242 (conductor 242a1 and conductor 242b1). For example, the film thickness of the upper layer of the conductor 242 may be greater than the film thickness of the lower layer of the conductor 242. Note that the upper layer of the conductor 242 may have at least a portion that is more conductive than the lower layer of the conductor 242. Alternatively, it is preferable that the upper layer of the conductor 242 is made of a conductive material with lower resistivity than the lower layer of the conductor 242. This makes it possible to manufacture a semiconductor device in which wiring delay is suppressed.

[0165] The upper layer of the conductor 242 may have a property of easily absorbing hydrogen. This allows hydrogen absorbed into the lower layer of the conductor 242 to diffuse into the upper layer of the conductor 242, further reducing the hydrogen concentration in the oxide 230. This allows the transistor 200 to have stable electrical characteristics.

[0166] Here, it is preferable that the lower layer and the upper layer of the conductor 242 are made of conductive materials that have the same constituent elements but different chemical compositions. In this case, the lower layer and the upper layer of the conductor 242 can be formed successively without being exposed to the atmospheric environment. By forming the layers without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the surface of the lower layer of the conductor 242, and it is possible to keep the vicinity of the interface between the lower layer of the conductor 242 and the upper layer of the conductor 242 clean.

[0167] It is also preferable to use a tantalum-containing nitride having a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242, and a tantalum-containing nitride having a low atomic ratio of nitrogen to tantalum for the upper layer of the conductor 242. For example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 1.0 to 2.0, preferably 1.1 to 1.8, and more preferably 1.2 to 1.5, is used for the lower layer of the conductor 242. Furthermore, for example, a tantalum-containing nitride having a nitrogen-to-tantalum atomic ratio of 0.3 to 1.5, preferably 0.5 to 1.3, and more preferably 0.6 to 1.0, is used for the upper layer of the conductor 242.

[0168] In a tantalum-containing nitride, increasing the atomic ratio of nitrogen to tantalum can suppress oxidation of the tantalum-containing nitride. Furthermore, the oxidation resistance of the tantalum-containing nitride can be improved. Furthermore, the diffusion of oxygen into the tantalum-containing nitride can be suppressed. Therefore, it is preferable to use a tantalum-containing nitride with a high atomic ratio of nitrogen to tantalum for the lower layer of the conductor 242. This can prevent the formation of an oxide layer between the lower layer of the conductor 242 and the oxide 230, or can reduce the thickness of the oxide layer.

[0169] Furthermore, in a nitride containing tantalum, the resistivity of the nitride can be reduced by lowering the atomic ratio of nitrogen to tantalum. Therefore, it is preferable to use a nitride containing tantalum with a low atomic ratio of nitrogen to tantalum as the upper layer of the conductor 242. This makes it possible to manufacture a semiconductor device with reduced wiring delay.

[0170] It should be noted that it may be difficult to clearly detect the boundary between the upper and lower layers of the conductor 242. When a nitride containing tantalum is used for the conductor 242, the tantalum and nitrogen concentrations detected in each layer are not limited to a stepwise change in each layer, but may also change continuously (also called a gradation) in the region between the upper and lower layers. In other words, the closer to the oxide 230 in the region of the conductor 242, the higher the atomic ratio of nitrogen to tantalum should be. Therefore, it is preferable that the atomic ratio of nitrogen to tantalum in the region located below the conductor 242 be higher than the atomic ratio of nitrogen to tantalum in the region located above the conductor 242.

[0171] The film thickness of the lower layer of the conductor 242 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that at least a portion of the lower layer of the conductor 242 has a region with the above-mentioned film thickness. It is also preferable that the film thickness of the lower layer of the conductor 242 is thinner than the film thickness of the upper layer of the conductor 242. In this case, it is sufficient that at least a portion of the lower layer of the conductor 242 has a region with a film thickness thinner than the upper layer of the conductor 242.

[0172] In addition, an example has been shown in which the lower layer of conductor 242 and the upper layer of conductor 242 are made of conductive materials that are the same in constituent elements but have different chemical compositions, but this is not limited to this, and the lower layer of conductor 242 and the upper layer of conductor 242 may be made of different conductive materials.

[0173] For example, the lower layer of the conductor 242 and the upper layer of the conductor 242 may differ in one or more of the constituent elements, chemical composition, and film formation conditions. For example, a nitride containing tantalum (e.g., tantalum nitride) may be used as the lower layer of the conductor 242, and a nitride containing titanium (e.g., titanium nitride) may be used as the upper layer of the conductor 242. Titanium nitride can have higher conductivity than tantalum nitride, so the conductivity of the upper layer of the conductor 242 can be made higher than that of the lower layer of the conductor 242. Therefore, the contact resistance with the conductor 240 provided in contact with the upper surface of the conductor 242 can be reduced, making it possible to manufacture a semiconductor device with reduced wiring delay.

[0174] Here, the distance between the conductor 242a2 and the conductor 242b2 is approximately equal to the distance L1 of the width of the opening 258 in the channel length direction. As shown in FIG. 3A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is preferably smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. This configuration reduces the film thickness of the portion of the conductor 242 (the conductor 242a1 and the conductor 242b1) sandwiched between a portion of the conductor 260 and the oxide 230b, thereby reducing the distance between the portion of the conductor 260 and the oxide 230b. This increases the effect of the electric field of the conductor 260 on the oxide 230b.

[0175] At this time, the insulator 252 contacts the side surfaces and part of the upper surface of the conductor 242a1, the side surfaces and part of the upper surface of the conductor 242b1, the side surfaces of the conductor 242a2, and the side surfaces of the conductor 242b2.

[0176] 3A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are flat from top to bottom, and these flat surfaces are approximately perpendicular to the top surface of the oxide 230b. However, the present invention is not limited to this. For example, as shown in FIG. 3B, the upper ends of the opposing side surfaces of the conductor 242a1 and the conductor 242b1 may have curved shapes. However, even in this case, it is preferable that the lower ends of the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are approximately perpendicular to the top surface of the oxide 230b.

[0177] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film at least against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. As the insulator 271, for example, an insulator such as silicon nitride, aluminum oxide, or magnesium oxide may be used.

[0178] The insulator 275 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and the insulator 271. Specifically, the insulator 275 has regions in contact with the side surface of the oxide 230b, the side surface of the conductor 242a, and the side surface of the conductor 242b. The insulator 275 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 275 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 275 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0179] By providing the insulators 271 and 275 as described above, the conductor 242 can be wrapped in an insulator that has a barrier property against oxygen. In other words, it is possible to prevent the oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by the oxygen contained in the insulators 224 and 280, which would increase the resistivity and reduce the on-current.

[0180] The insulator 252 functions as part of the gate insulator. A barrier insulating film against oxygen is preferably used as the insulator 252. Any of the insulators that can be used for the insulator 282 described above may be used as the insulator 252. An insulator containing an oxide of one or both of aluminum and hafnium may be used as the insulator 252. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 contains at least oxygen and aluminum.

[0181] As shown in FIG. 1C , the insulator 252 is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. That is, the regions of the oxide 230a, the oxide 230b, and the insulator 224 that overlap with the conductor 260 are covered with the insulator 252 in the cross section in the channel width direction. This allows the insulator 252, which has oxygen barrier properties, to block oxygen from being released from the oxide 230a and the oxide 230b when heat treatment or the like is performed. This reduces the formation of oxygen vacancies in the oxide 230a and the oxide 230b. This reduces the oxygen vacancies and V formed in the region 230bc. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0182] Conversely, even if the insulators 280 and 250 contain excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxides 230a and 230b. Therefore, the regions 230ba and 230bb can be prevented from being excessively oxidized through the region 230bc, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0183] 1B , the insulator 252 is provided in contact with the side surfaces of the conductor 242, the insulator 271, the insulator 275, and the insulator 280. The insulator 252 is also in contact with a portion of the top surface of the conductor 242. This reduces the oxidation of a portion of the top surface and the side surface of the conductor 242, thereby reducing the formation of an oxide film on the portion of the top surface and the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0184] Furthermore, the insulator 252, together with the insulator 254, the insulator 250, and the conductor 260, needs to be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 252 have a thin film thickness. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, the insulator 252 only needs to have a region with the above-described film thickness in at least a portion thereof. Furthermore, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is preferable that the insulator 252 only needs to have a region with a film thickness thinner than the insulator 250 in at least a portion thereof.

[0185] To thin the insulator 252 as described above, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. The PEALD method may be preferable because it uses plasma, which allows film formation at a lower temperature.

[0186] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with fewer defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 252 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280, etc., and on the side edges of the conductor 242, etc., with a thin film thickness as described above.

[0187] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0188] By appropriately adjusting the film formation conditions of the insulating film that becomes the insulator 250, the conditions of the microwave treatment in an oxygen-containing atmosphere, and the addition of oxygen to the insulator 280 by forming the insulator 282, the oxygen vacancies and V Ｏ In some cases, it may be possible to reduce H and prevent the regions 230ba and 230bb from being excessively oxidized. In such a case, by not providing the insulator 252, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0189] The insulator 250 functions as part of the gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the insulator 252. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 250 is an insulator containing at least oxygen and silicon.

[0190] Like the insulator 224, the insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 250 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 15 nm. In particular, to fabricate a fine transistor (e.g., a transistor with a distance L2 of 20 nm or less), the thickness of the insulator 250 is preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 5 nm. In the above case, it is sufficient that at least a portion of the insulator 250 has a region with the above-described thickness.

[0191] 1A to 1D, the insulator 250 is shown as a single layer, but the present invention is not limited to this and may have a stacked structure of two or more layers. For example, as shown in FIG. 2B, the insulator 250 may have a two-layer stacked structure of an insulator 250a and an insulator 250b on the insulator 250a.

[0192] As shown in FIG. 2B , when the insulator 250 has a two-layer stacked structure, the lower insulator 250a is preferably formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b is preferably formed using an insulator that has a function of suppressing oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a may be formed using a material that can be used for the insulator 250 described above, and the insulator 250b may be an insulator containing oxides of one or both of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b contains at least oxygen and hafnium. The thickness of the insulator 250b is 0.5 nm to 5.0 nm, preferably 1.0 nm to 5.0 nm, and more preferably 1.0 nm to 3.0 nm. In this case, the insulator 250b only needs to have a region with the above thickness in at least a portion thereof.

[0193] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a layered structure of the insulators 250a and 250b, a thermally stable layered structure with a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 250 to be increased.

[0194] The insulator 254 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 254. This can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and the oxide 230b. The insulator 254 may be any of the insulators that can be used for the insulator 283 described above. For example, silicon nitride formed by the PEALD method may be used as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0195] The insulator 254 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 250 from diffusing into the conductor 260.

[0196] Furthermore, the insulator 254, together with the insulator 252, the insulator 250, and the conductor 260, needs to be provided in an opening formed in the insulator 280 or the like. To miniaturize the transistor 200, it is preferable that the insulator 254 be thin. The thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, the insulator 254 only needs to have a region with the above-described thickness in at least a portion thereof. Furthermore, it is preferable that the thickness of the insulator 254 is thinner than the thickness of the insulator 250. In this case, it is preferable that the insulator 254 only needs to have a region with a thickness thinner than the insulator 250 in at least a portion thereof.

[0197] 2B , when the insulator 250 has a two-layer stacked structure, by using an insulator such as hafnium oxide that has a function of suppressing the permeation of impurities such as hydrogen and oxygen as the insulator 250b, the insulator 250b can also function as the insulator 254. In such a case, by not providing the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0198] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 1C, the top surface of the conductor 260 is generally flush with the top surface of the insulator 250. Note that although the conductor 260 is shown as having a two-layer structure of the conductor 260a and the conductor 260b in FIGS. 1B and 1C, it may have a single-layer structure or a stacked structure of three or more layers.

[0199] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0200] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0201] The conductor 260 is formed to fill the opening 258 extending in the channel width direction, and the conductor 260 is also provided extending in the channel width direction. This allows the conductor 260 to function as wiring when multiple transistors 200 are provided. In this case, the insulators 252, 250, and 254 are also provided extending along with the conductor 260.

[0202] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0203] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill the opening 258 formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242 a and the conductor 242 b without alignment.

[0204] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. When the conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0205] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The top surface of the insulator 280 may be flattened.

[0206] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0207] The insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 280. For example, the insulator 280 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0208] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 282 contains at least oxygen and aluminum. By providing the insulator 282 in contact with the insulator 280 in the region sandwiched between the insulators 212 and 283 and having a function of capturing impurities such as hydrogen, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0209] The insulator 282 is preferably formed by sputtering an aluminum oxide film, and more preferably by pulsed DC sputtering using an aluminum target in an oxygen-containing atmosphere. Using pulsed DC sputtering can achieve a more uniform film thickness distribution and improve the sputtering rate and film quality. Here, RF (radio frequency) power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the more likely the oxygen amount is saturated even if the insulator 282 is thin. Furthermore, the greater the RF power, the greater the amount of oxygen implanted into the layer below the insulator 282.

[0210] The RF power is, for example, 0 W / cm ２ Over 1.86 W / cm ２ That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 282. Therefore, the amount of oxygen suitable for improving the reliability of the transistor can be injected.

[0211] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0212] 1A to 1D and the like, the insulator 282 is shown as a single layer, but the present invention is not limited to this and may have a stacked structure of two or more layers. For example, the insulator 282 may have a stacked structure of two layers.

[0213] The upper and lower layers of the insulator 282 may be formed using the same material but by different methods. For example, when aluminum oxide is formed as the insulator 282 by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas, it is preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is different from the RF power applied to the substrate when forming the upper layer of the insulator 282, and it is more preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is lower than the RF power applied to the substrate when forming the upper layer of the insulator 282. Specifically, it is preferable that the RF power applied to the substrate when forming the lower layer of the insulator 282 is 0 W / cm ２ 0.62W / cm or more ２ The upper layer of the insulator 282 is formed as follows: ２ More specifically, the lower layer of the insulator 282 is formed under the following conditions: RF power applied to the substrate is 0 W / cm ２ The upper layer of the insulator 282 was formed as a film with an RF power of 0.31 W / cm ２ With this structure, the insulator 282 can have an amorphous structure and the amount of oxygen supplied to the insulator 280 can be adjusted.

[0214] The RF power applied to the substrate when forming the lower layer of the insulator 282 may be higher than the RF power applied to the substrate when forming the upper layer of the insulator 282. Specifically, the RF power applied to the substrate when forming the lower layer of the insulator 282 may be 1.86 W / cm ２ The upper layer of the insulator 282 is formed as follows: ２ 0.62W / cm or more ２ More specifically, the lower layer of the insulator 282 is formed at an RF power of 1.86 W / cm ２ The upper layer of the insulator 282 was formed as a film with an RF power of 0.62 W / cm ２ With this structure, the amount of oxygen supplied to the insulator 280 can be increased.

[0215] Furthermore, the film thickness of the lower layer of the insulator 282 is 1 nm or more and 20 nm or less, preferably 1.5 nm or more and 15 nm or less, more preferably 2 nm or more and 10 nm or less, and even more preferably 3 nm or more and 8 nm or less. With this configuration, the lower layer of the insulator 282 can be made to have an amorphous structure regardless of RF power. Furthermore, by making the lower layer of the insulator 282 have an amorphous structure, the upper layer of the insulator 282 is more likely to have an amorphous structure, and the insulator 282 can be made to have an amorphous structure.

[0216] The lower layer and the upper layer of the insulator 282 described above have a laminated structure made of the same material, but the present invention is not limited to this. The lower layer and the upper layer of the insulator 282 may have a laminated structure made of different materials.

[0217] Insulator 283 contacts a portion of the top surface of insulator 214 , the side of insulator 216 , the side of insulator 222 , the side of insulator 275 , the side of insulator 280 , and the side and top surface of insulator 282 .

[0218] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed over the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method may be used as the insulator 283. By forming the insulator 283 by a sputtering method, a high-density silicon nitride film can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a PEALD method or a CVD method on a silicon nitride film formed by a sputtering method.

[0219] An insulator 241 is provided in contact with the inner walls of the openings of the insulators 280, 282, 283, and 285, and a conductor 240 is provided in contact with the side surface of the insulator 241. The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure. For example, as shown in FIG. 1B, the conductor 240 may have a structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside.

[0220] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from mixing into the oxide 230 through the conductor 240.

[0221] Although the transistor 200 shows a structure in which the conductor 240 is formed by stacking a first conductor and a second conductor, the present invention is not limited to this. For example, the conductor 240 may be formed as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the layers may be distinguished by assigning an ordinal number to indicate the order of formation. Furthermore, although not shown in FIG. 1B , the height of the top surface of the conductor 240 may be higher than the height of the top surface of the insulator 285 in the region overlapping with the conductor 246.

[0222] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241 is provided in contact with the insulators 283, 282, and 271, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280, etc., from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0223] When the insulator 241 has a layered structure as shown in Figure 1B, it is preferable that the first insulator in contact with the inner wall of the opening, such as insulator 280, and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0224] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. This configuration can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0225] Note that, although the transistor 200 illustrates a structure in which the insulator 241 is formed by stacking a first insulator and a second insulator, the present invention is not limited to this. For example, the insulator 241 may be formed as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0226] A conductor 246 that functions as wiring may be disposed in contact with the upper surface of the conductor 240. The conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 246 may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor 246 may be formed so as to be embedded in an opening provided in the insulator.

[0227] [Capacitor 100] In the capacitor 100, the insulators 152, 150, 154, conductors 160a, and 160b are arranged in openings 158 formed in the insulators 280, 275, and 271. The insulator 150 is provided over the insulator 152, the insulator 154 is provided over the insulator 150, the conductor 160a is provided over the insulator 154, and the conductor 160b is provided over the conductor 160a. Note that in this specification and the like, the conductors 160a and 160b may be collectively referred to as conductors 160.

[0228] As will be described in detail later, the insulators 152, 150, 154, conductor 160a, and conductor 160b that constitute the capacitor 100 can be formed using the same materials and in the same process as the insulators 252, 250, 254, conductor 260a, and conductor 260b that constitute the transistor 200. Therefore, the insulator 152 preferably has the same insulating material as the insulator 252, and the description of the insulator 252 can be referred to for details. The insulator 150 preferably has the same insulating material as the insulator 250, and the description of the insulator 250 can be referred to for details. The insulator 154 preferably has the same insulating material as the insulator 254, and the description of the insulator 254 can be referred to for details. The conductor 160a preferably has the same conductive material as the conductor 260a, and the description of the conductor 260a can be referred to for details. The conductor 160b preferably has the same conductive material as the conductor 260b, and for details, the description of the conductor 260b can be referred to.

[0229] By forming insulator 152, insulator 150, insulator 154, conductor 160a, and conductor 160b using the same material and in the same process as insulator 252, insulator 250, insulator 254, conductor 260a, and conductor 260b, the number of steps in the manufacturing process of a semiconductor device can be reduced.

[0230] 2B, when the insulator 250 has a layered structure, the insulator 150 can also have a layered structure. An insulator containing an oxide of one or both of aluminum and hafnium, which can be used for the insulator 250b, functions as a high-dielectric-constant (high-k) material. By using such a high-k material, the capacitance of the capacitor 100 can be sufficiently ensured even if the insulators 152, 150, and 154 are made thick. By making the insulators 152, 150, and 154 thick, the leakage current occurring between the conductor 242b and the conductor 160 can be suppressed.

[0231] The opening 158 is provided in the insulators 280, 271, and 275 so as to reach the conductor 242b and the insulator 222. In other words, it can be said that the opening 158 has a region overlapping with the conductor 242b. Furthermore, it can be said that the insulator 275 has an opening that overlaps with the opening 158 of the insulator 280.

[0232] 1A , in a plan view, a region where the conductor 160 in the opening 158 intersects with the conductor 242b functions as the capacitor 100. This region overlaps with the oxide 230b that functions as the transistor 200. That is, the capacitor 100 can be provided without excessively increasing the occupied area compared to the occupied area of ​​the transistor 200. This enables miniaturization or high integration of the semiconductor device. For example, when a semiconductor device according to one embodiment of the present invention is used as a memory cell of a memory device, the storage capacity per unit area can be increased.

[0233] 1B and 1D , opening 158 can also be considered to have a shape in which a part of a structure made up of insulator 224, oxide 230, and conductor 242 protrudes into an opening having insulator 222 as a bottom surface and insulators 280, 275, and 271 as side surfaces. Note that in opening 158, unlike opening 258, the top surface of oxide 230b is covered with conductor 242b, and therefore the top surface of oxide 230b is not exposed within opening 158.

[0234] 1B and 1D , the insulator 152 is provided in contact with the bottom surface and inner wall of the opening 158. Thus, the insulator 152 is in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, part of the top surface and side surface of the conductor 242b, the side surface of the insulator 271b, the side surface of the insulator 275, and the side surface of the insulator 280. Furthermore, on the insulator 152, the insulator 150 is provided in contact with the top surface of the insulator 152, the insulator 154 is provided in contact with the top surface of the insulator 150, and the conductor 160 is provided in contact with the top surface of the insulator 154. Therefore, the insulator 152, the insulator 150, the insulator 154, and the conductor 160 are provided to cover the conductor 242b that partially protrudes into the opening 158.

[0235] 1D , the capacitor 100 is provided with the above-described structure, so that the conductor 160 faces the top surface of the conductor 242b, the side surface of the conductor 242b on the A5 side, and the side surface of the conductor 242b on the A6 side, with the insulators 152, 150, and 154 interposed therebetween. This allows the capacitor 100 to be formed on the above-described three surfaces of the conductor 242b, thereby increasing the capacitance per unit area of ​​the capacitor 100. This allows for miniaturization or high integration of semiconductor devices.

[0236] The conductor 160 is formed to fill the opening 158 extending in the channel width direction of the transistor 200, and the conductor 160 is also provided extending in the channel width direction of the transistor 200. This allows the conductor 160 to function as wiring when a plurality of transistors 200 and capacitors 100 are provided. In this case, the insulators 152, 150, and 154 are also provided extending along with the conductor 160.

[0237] <Constituent Materials of Semiconductor Device> Constituent materials that can be used in the semiconductor device will be described below.

[0238] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0239] <<Insulator>> Examples of insulators include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0240] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0241] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0242] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0243] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0244] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0245] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0246] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0247] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0248] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0249] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 according to the present invention will be described below.

[0250] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0251] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, the element M may be a combination of two or more of the above-mentioned elements. In particular, the element M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0252] In particular, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferably used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer.

[0253] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0254] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In—Ga—Zn oxide.

[0255] <Classification of Crystal Structure> Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0256] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by GIXD (Grazing-Incident XRD) measurement. The GIXD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXD measurement may be simply referred to as the XRD spectrum.

[0257] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is almost symmetrical. On the other hand, in the case of an In-Ga-Zn oxide film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0258] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an In—Ga—Zn oxide film formed at room temperature, rather than a halo. For this reason, it is estimated that the In—Ga—Zn oxide formed at room temperature is neither single crystal nor polycrystalline, nor in an amorphous state, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0259] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0260] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0261] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0262] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0263] In an In—Ga—Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter referred to as a (Ga, Zn) layer) are stacked. Note that indium and gallium are mutually substituted. Therefore, the (Ga, Zn) layer may contain indium. The In layer may contain gallium. The In layer may contain zinc. The layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

[0264] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0265] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the spots are observed at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0266] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed arrangement of oxygen atoms in the a-b plane and the change in interatomic bond distance caused by metal atom substitution.

[0267] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0268] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having the CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having the CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using the CAAC-OS in a transistor having a metal oxide in a channel formation region (sometimes referred to as an OS transistor) can increase the flexibility of the manufacturing process.

[0269] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0270] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0271] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0272] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0273] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0274] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0275] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be referred to as a region whose main component is In. The second region can be referred to as a region whose main component is Ga.

[0276] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0277] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0278] The CAC-OS can be formed by sputtering without heating the substrate. When forming the CAC-OS by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0279] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0280] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0281] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0282] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0283] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0284] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0285] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0286] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0287] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ Less than 1×10, more preferably 1×10 １１ cm −３ More preferably, 1×10１０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0288] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0289] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0290] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0291] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0292] When an oxide semiconductor contains silicon or carbon, which is one of Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 １８ atoms / cm３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0293] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0294] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0295] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is measured to be 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0296] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0297] <<Other Semiconductor Materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, two-dimensional material, etc.) is preferably used as the semiconductor material. In particular, a layered material that functions as a semiconductor is preferably used as the semiconductor material.

[0298] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0299] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0300] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0301] <Manufacturing Method of Semiconductor Device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention illustrated in FIGS. 1A to 1D will be described with reference to FIGS. 5A to 17D.

[0302] A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A of each figure, and is also a cross-sectional view in the channel width direction of the capacitor element 100. Note that in the top view A in each figure, some elements are omitted for clarity.

[0303] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0304] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0305] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0306] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0307] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0308] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0309] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0310] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0311] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate (see FIGS. 5A to 5D ). The insulator 212 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0312] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. The use of pulsed DC sputtering can suppress particle generation due to arcing on the target surface, resulting in a more uniform film thickness distribution. Furthermore, the use of pulsed voltage can make the rise and fall of discharge steeper than with high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0313] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0314] Next, the insulator 214 is deposited over the insulator 212 (see FIGS. 5A to 5D ). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0315] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF power may be applied to the substrate. The amount of oxygen implanted into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. ２ More than 1.86 W / cm ２ The following is true. That is, the amount of oxygen suitable for the characteristics of the transistor can be changed and injected by changing the RF power when forming the insulator 214. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected. The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0316] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of capturing and fixing hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 or the like to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0317] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0318] In this embodiment, a silicon oxide film is formed as the insulator 216 by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0319] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and further reduces hydrogen contamination between deposition steps.

[0320] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region in which the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0321] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used.

[0322] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0323] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0324] Next, a conductive film to be the conductor 205b is formed. For the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0325] Next, CMP treatment is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 5A to 5D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP treatment may remove a portion of the insulator 216.

[0326] Next, the insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 6A to 6D ). The insulator 222 may contain one or both of aluminum and hafnium oxides. Note that aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water can prevent hydrogen and water contained in structures provided around the transistor 200 from diffusing into the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0327] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. In particular, it is preferable to use a method for forming hafnium oxide with a reduced hydrogen concentration, which is one embodiment of the present invention.

[0328] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0329] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the insulator 222 as much as possible.

[0330] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0331] Next, an insulating film 224A is formed over the insulator 222 (see FIGS. 6A to 6D ). The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulating film 224A by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the film formation gas, the hydrogen concentration in the insulating film 224A can be reduced. Because the insulating film 224A will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0332] Next, oxide films 230A and 230B are sequentially formed on the insulating film 224A (see FIGS. 6A to 6D). It is preferable to form the oxide films 230A and 230B consecutively without exposing them to the atmospheric environment. By forming the films without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B, and to keep the vicinity of the interface between the oxide films 230A and 230B clean.

[0333] The oxide films 230A and 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide films 230A and 230B are preferably formed by the ALD method, since they can be formed with a uniform thickness even in trenches or openings with a large aspect ratio. The PEALD method is also preferable, since it allows the oxide films 230A and 230B to be formed at a lower temperature than the thermal ALD method. In this embodiment, the oxide films 230A and 230B are formed by the sputtering method.

[0334] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target or the like can be used.

[0335] In particular, during the formation of oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0336] When the oxide film 230B is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0337] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films 230a and 230b can be formed according to the desired characteristics by appropriately selecting the film formation conditions and atomic ratios.

[0338] Note that the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This can reduce the incorporation of hydrogen into the insulating film 224A, the oxide film 230A, and the oxide film 230B between film formation steps.

[0339] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A and the oxide film 230B do not become polycrystallized, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0340] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the oxide film 230A, the oxide film 230B, and the like as much as possible.

[0341] In this embodiment, the heat treatment is performed at 400° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230A and the oxide film 230B. Reducing the impurities in the film can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230A and the oxide film 230B, reducing the in-plane variation of the crystalline regions in the oxide film 230A and the oxide film 230B. Therefore, the in-plane variation of the electrical characteristics of the transistor 200 can be reduced.

[0342] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224A, the oxide film 230A, and the oxide film 230B decrease.

[0343] In particular, the insulating film 224A functions as a gate insulator of the transistor 200, and the oxide film 230A and the oxide film 230B function as a channel formation region of the transistor 200. Therefore, the transistor 200 including the insulating film 224A, the oxide film 230A, and the oxide film 230B in which the hydrogen concentrations are reduced is preferable because it has good reliability.

[0344] Next, a conductive film 242A is formed on the oxide film 230B (see FIGS. 6A to 6D ). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be formed as the conductive film 242A by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230B can be removed, and the moisture and hydrogen concentrations in the oxide film 230A and the oxide film 230B can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0345] Next, an insulating film 271A is formed over the conductive film 242A (see FIGS. 6A to 6D ). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, an aluminum oxide film or a silicon nitride film may be formed by a sputtering method as the insulating film 271A. Alternatively, for example, a silicon nitride film and a silicon oxide film on the silicon nitride film may be formed by a sputtering method as the insulating film 271A.

[0346] Note that the conductive film 242A and the insulating film 271A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A and the insulating film 271A to be formed with reduced hydrogen content and further reduces the amount of hydrogen mixed into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 271A, the film that becomes the hard mask may also be formed continuously without exposure to the atmosphere.

[0347] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A are processed into island shapes by lithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 7A to 7D ). The insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B are formed so that at least a portion of each overlaps with the conductor 205. This processing can be performed by dry etching or wet etching. Dry etching is suitable for microfabrication. The insulating film 224A, the oxide film 230A, the oxide film 230B, the conductive film 242A, and the insulating film 271A may be processed under different conditions.

[0348] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Then, etching is performed through the resist mask to process a conductor, semiconductor, or insulator into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or ion beam may also be used instead of the light described above. When an electron beam or ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0349] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask. In this embodiment, the insulating layer 271B is used as the hard mask.

[0350] Here, since the insulating layer 271B functions as a mask for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 7B to 7D . As a result, the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-state current of the transistor 200.

[0351] 7B to 7D , the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be tapered. In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface. For example, the angle between the inclined side surface and the substrate surface (hereinafter, sometimes referred to as the taper angle) is preferably less than 90°. The insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may have a taper angle of, for example, 60° or more and less than 90°. Tapering the side surfaces in this manner improves the coverage of the insulator 275 and the like in subsequent processes, thereby reducing defects such as voids.

[0352] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B may be configured to be approximately perpendicular to the top surface of the insulator 222. With such a configuration, it is possible to reduce the area and increase the density when providing multiple transistors 200.

[0353] Furthermore, by-products generated in the etching process may form layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B. In this case, the layer-like by-products are formed between the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B and the insulator 275. Therefore, it is preferable to remove the layer-like by-products formed in contact with the upper surface of the insulator 222.

[0354] Next, an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductive layer 242B, and the insulating layer 271B (see FIGS. 8A to 8D ). The insulator 275 is preferably in close contact with the top surface of the insulator 222 and the side surface of the insulator 224. The insulator 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 is preferably an insulating film that has a function of suppressing oxygen permeation. For example, a silicon nitride film may be formed as the insulator 275 by an ALD method. Alternatively, an aluminum oxide film may be formed as the insulator 275 by a sputtering method, and then a silicon nitride film may be formed thereon by a PEALD method. The insulator 275 having such a layered structure may have an improved function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0355] In this way, the oxide 230 a, the oxide 230 b, and the conductive layer 242 B can be covered with the insulator 275 and the insulating layer 271 B, which have the function of suppressing the diffusion of oxygen, thereby reducing the direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230 a, the oxide 230 b, and the conductive layer 242 B in a later process.

[0356] Next, an insulating film to be the insulator 280 is formed over the insulator 275. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film can be formed as the insulating film by a sputtering method. The insulating film can be formed by sputtering in an oxygen-containing atmosphere to form the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Note that heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0357] Next, CMP treatment is performed on the insulating film that will become the insulator 280 to form the insulator 280 with a flat upper surface (see FIGS. 8A to 8D). Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and CMP treatment may be performed on the silicon nitride until it reaches the insulator 280.

[0358] Next, a portion of the insulator 280, a portion of the insulator 275, and a portion of the insulating layer 271B are processed to form openings 258 and 158 that reach the conductive layer 242B and the insulator 222 (see FIGS. 9A to 9D ). As shown in FIGS. 9C and 9D , the side surfaces of the insulator 224, the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, and the top and side surfaces of the conductive layer 242B are exposed in the openings 258 and 158, respectively. Furthermore, the formation of the openings 258 forms the insulators 271a and 271b.

[0359] Here, as shown in FIG. 9B, the width of the opening 258 in a cross-sectional view in the channel length direction of the transistor is defined as a distance L1.

[0360] 9A , the openings 258 and 158 are preferably configured to extend in a direction parallel to the line A3-A4 (the channel width direction of the transistor). By forming the openings 258 and 158 in this manner, the conductors 260 and 160, which will be formed later, can be extended and function as wiring. Furthermore, the opening 258 is preferably formed so as to overlap the conductor 205.

[0361] As shown in FIGS. 9B to 9D, the side surfaces of the insulators 280, 275, and 271 that form the inner walls of the openings 258 and 158 are preferably substantially vertical and not tapered.

[0362] Furthermore, a portion of the insulator 280, a portion of the insulator 275, and a portion of the insulating layer 271B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Furthermore, the processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, and a portion of the insulator 275 and a portion of the insulating layer 271B may be processed by wet etching.

[0363] Next, a mask layer 259 is formed to cover the insulator 280 and the opening 158 (see FIGS. 10A to 10D ). The mask layer 259 has an opening 263 that overlaps a portion of the opening 258. The mask layer 259 may be made of, for example, a resist. In this case, to improve the adhesion of the resist, it is preferable to provide an organic coating film such as an SOG (spin on glass) film or an SOC (spin on carbon) film under the resist. Alternatively, a hard mask made of an insulator or conductor may be used under the resist.

[0364] 10B, the width of opening 263 in a cross-sectional view in the channel length direction of the transistor is defined as distance L2. As shown in FIG. 10B, in a cross-sectional view in the channel length direction of the transistor, distance L2 is shorter than distance L1, and opening 263 is formed inside opening 258. Therefore, a portion of the lower surface of mask layer 259 contacts the upper surface of conductive layer 242B inside opening 258.

[0365] Since the width of the opening 263 is reflected in the distance between the conductors 242 a and 242 b, it is preferable that the distance L2 be very small. For example, it is preferable that the distance L2 be 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more.

[0366] In order to process the opening 263 finely in this way, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0367] As described above, by providing mask layer 259 having opening 263 with a width of distance L2 inside opening 258 with a width of distance L1, opening 263 can be provided with a margin. This makes it possible to form a channel with a fine structure relatively easily.

[0368] Next, the mask layer 259 is used to remove the portion of the conductive layer 242B that is not covered by the mask layer 259, thereby exposing the oxide 230b, thereby forming the conductors 242a and 242b (see FIGS. 11A to 11D).

[0369] Part of the conductive layer 242B is preferably processed by anisotropic etching. Dry etching is particularly preferable because it is suitable for fine processing. By processing the conductive layer 242B using anisotropic etching, the opposing side surfaces of the conductor 242a and the conductor 242b can be formed to be approximately perpendicular to the top surface of the oxide 230b. This structure can reduce the formation of so-called Loff regions between the regions 230ba and 230bc and between the regions 230bb and 230bc. Therefore, the frequency characteristics of the transistor 200 can be improved, and the operating speed of the semiconductor device according to one embodiment of the present invention can be increased.

[0370] After the conductors 242 a and 242 b are formed, the mask layer 259 may be removed. When a resist mask is used as the mask layer 259, the mask layer 259 can be removed by performing dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0371] The etching process may result in impurities adhering to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, the side surfaces of the conductor 242, and the side surfaces of the insulator 280, or diffusing into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulator 280, the insulator 275, part of the insulating layer 271B, and the conductive layer 242B, components contained in the materials used in the device used to form the opening, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0372] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 230b and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0373] In addition, in the region where the crystallinity of the oxide 230b is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 230b be reduced or removed.

[0374] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom end of the conductor 242a (conductor 242b) has a CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0375] A cleaning process is performed to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0376] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0377] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0378] In addition, ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably uses a frequency of 900 kHz or more, since use of such a frequency can reduce damage to the oxide 230b and the like.

[0379] The cleaning process may be repeated multiple times, and different cleaning solutions may be used for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0380] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0381] Heat treatment may be performed after the etching or cleaning. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide 230b. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0382] Next, an insulating film 252A is formed (see FIGS. 12A to 12D ). The insulating film 252A will become the insulator 252 and the insulator 152 in later processes. The insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 252A is preferably formed using the ALD method. As described above, the insulating film 252A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, as shown in FIGS. 12B and 12C , the insulating film 252A must be formed with good coverage on the bottom and side surfaces of the openings 258 and 158. In particular, in opening 258, it is preferable that the film be formed with good coverage on the top and side surfaces of oxide 230 and the side surfaces of conductor 242. It is also preferable that the film be formed with good coverage on the side and top surfaces of conductor 242b in opening 158. Since atomic layers can be deposited one by one on the bottom and side surfaces of the opening, insulating film 252A can be formed with good coverage on the opening.

[0383] When the insulating film 252A is formed by the ALD method, ozone (O ３ ), oxygen (O２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using an oxidizing agent such as HCl, hydrogen diffusing into the oxide 230b can be reduced.

[0384] In this embodiment, the insulating film 252A is formed by depositing aluminum oxide using a thermal ALD method.

[0385] Next, the insulating film 250A is formed (see FIGS. 12A to 12D). The insulating film 250A will become the insulator 250 and the insulator 150 in later steps. Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately without exposure to the air. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulating film 252A can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0386] The insulating film 250A can be formed by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. Furthermore, the insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A will become the insulator 250 facing the oxide 230b via the thin insulator 252 in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0387] In this embodiment, the insulating film 250A is formed of silicon oxynitride by PECVD.

[0388] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere (see FIGS. 12A to 12D). Here, microwave treatment refers to treatment using, for example, a device with a power source that generates high-density plasma using microwaves. In this specification and elsewhere, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0389] The dotted lines in Figures 12B to 12D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For microwave processing, it is preferable to use a microwave processing device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device may be 300 MHz to 300 GHz, preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. The use of high-density plasma can generate high-density oxygen radicals. Furthermore, the power of the power supply that applies microwaves to the microwave processing device may be 1000 W to 10,000 W, preferably 2000 W to 5,000 W. The microwave processing device may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side can efficiently guide oxygen ions generated by high-density plasma into the oxide 230b.

[0390] The microwave treatment is preferably carried out under reduced pressure, with the pressure being 10 Pa to 1000 Pa, preferably 300 Pa to 700 Pa. The treatment temperature is 750°C or less, preferably 500°C or less, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. For example, the temperature may be 100°C to 750°C, preferably 300°C to 500°C.

[0391] Furthermore, for example, the microwave treatment may be performed using oxygen gas and argon gas. ２ / (O ２ The oxygen flow rate ratio (O + Ar)) should be greater than 0% and not more than 100%. ２ / (O ２The oxygen flow rate ratio (O + Ar) should be greater than 0% and less than or equal to 50%. ２ / (O ２ The oxygen flow rate ratio (O + Ar)) should be 10% or more and 40% or less. ２ / (O ２ +Ar)) should be 10% or more and 30% or less. Thus, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in region 230bc can be reduced. Furthermore, by preventing excessive oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in regions 230ba and 230bb can be prevented.

[0392] 12B to 12D, by performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 230bc. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in FIG. 2A. The action of plasma, microwaves, etc. can increase the V of the region 230bc. Ｏ H can be split and hydrogen can be removed from the region 230bc. Ｏ Therefore, oxygen vacancies in the region 230bc and V Ｏ By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be lowered.

[0393] 2A , conductors 242a and 242b are provided on regions 230ba and 230bb. Here, conductor 242 preferably functions as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when microwave processing is performed in an oxygen-containing atmosphere. Therefore, conductor 242 preferably has the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0394] 12B to 12D, the conductors 242a and 242b shield the regions 230ba and 230bb from the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. As a result, the microwave treatment can reduce the V Ｏ Since the reduction of H and the supply of an excessive amount of oxygen do not occur, a decrease in the carrier concentration can be prevented.

[0395] Furthermore, an insulator 252 having a barrier property against oxygen is provided in contact with the side surfaces of the conductor 242 a and the conductor 242 b, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductor 242 a and the conductor 242 b by microwave processing.

[0396] Furthermore, the film quality of the insulator 252 and the insulator 250a can be improved, thereby improving the reliability of the transistor 200.

[0397] In this manner, oxygen vacancies and V Ｏ By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0398] In microwave treatment, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interaction between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave treatment in an oxygen-containing atmosphere may produce an effect equivalent to oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, thereby activating and releasing the hydrogen from the oxide 230b.

[0399] The microwave treatment may be performed after the formation of the insulating film 252A. Alternatively, the microwave treatment may be performed after the formation of the insulating film 252A without performing the microwave treatment after the formation of the insulating film 250A.

[0400] When the insulator 250 has the two-layer stacked structure shown in FIG. 2B , an insulating film that becomes the insulator 250b can be formed after the insulating film 250A is formed. In this case, the insulating film that becomes the insulator 250b is formed in the openings 258 and 258. The insulating film that becomes the insulator 250b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that becomes the insulator 250b is preferably formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the insulator 250a into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. Furthermore, it can suppress oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. The insulating film that becomes the insulator 250b can be formed using the same material as the insulator 222. For example, the insulating film that becomes the insulator 250b can be formed using hafnium oxide by a thermal ALD method.

[0401] 2B , the microwave treatment may be performed after the formation of the insulating film 250 A. Alternatively, the microwave treatment may be performed after the formation of the insulating film that will become the insulator 250 b, without performing the microwave treatment after the formation of the insulating film 250 A.

[0402] Furthermore, after the formation of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, a heat treatment may be performed while maintaining a reduced pressure after each microwave treatment. By performing such a treatment, hydrogen can be efficiently removed from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be repeated multiple times while maintaining a reduced pressure after the microwave treatment. Repeated heat treatment can more efficiently remove hydrogen from the insulating film 252A, the insulating film 250A, the insulating film that will become the insulator 250b, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be necessary.

[0403] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 252A, the insulating film 250A, and the insulating film that will become the insulator 250b, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 252 in a post-process such as film formation of the conductive film that will become the conductor 260 or a post-treatment such as heat treatment.

[0404] Next, an insulating film 254A is formed (see FIGS. 13A to 13D). The insulating film 254A is an insulating film that will become the insulator 254 and the insulator 154 in later steps. The insulating film 254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 254A is preferably formed by an ALD method, similar to the insulating film 252A. By using the ALD method, the insulating film 254A can be formed to a thin film thickness with good coverage. In this embodiment, silicon nitride is formed as the insulating film 254A by a PEALD method.

[0405] Next, a conductive film that will become the conductor 260a and the conductor 160a, and a conductive film that will become the conductor 260b and the conductor 160b are formed in this order. The conductive films that will become the conductors 260a and the conductor 160a, and the conductive films that will become the conductors 260b and the conductor 160b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a titanium nitride film is formed as the conductive film that will become the conductor 260a and the conductor 160a using the ALD method, and a tungsten film is formed as the conductive film that will become the conductor 260b and the conductor 160b using the CVD method.

[0406] Next, the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that will become the conductor 260a and the conductor 160a, and the conductive film that will become the conductor 260b and the conductor 160b are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulating film 252A, the insulating film 250A, the insulating film 254A, the conductive film that will become the conductor 260a and the conductor 160a, and the conductive film that will become the conductor 260b and the conductor 160b that are exposed from the opening 258 and the opening 158 are removed. This forms insulators 252, 250, 254, and conductor 260 (conductor 260a and conductor 260b) in opening 258, and insulators 152, 150, 154, and conductor 160 (conductor 160a and conductor 160b) in opening 158 (see Figures 14A to 14D).

[0407] As a result, the insulator 252 is provided in contact with the inner wall and side surface of the opening 258 that overlaps with the oxide 230b. The conductor 260 is also arranged to fill the opening 258 via the insulators 252, 250, and 254. In this manner, the transistor 200 is formed.

[0408] The insulator 152 is provided in contact with the inner wall and side surface of the opening 158 that overlaps with the conductor 242b. The conductor 160 is arranged to fill the opening 158 with the insulators 152, 150, and 154 interposed therebetween. In this manner, the capacitor 100 is formed.

[0409] As described above, the transistor 200 and the capacitor 100 can be fabricated in parallel using the same process. As described above, the insulators 252 and 152, the insulators 250 and 150, the insulators 254 and 154, the conductors 260a and 160a, and the conductors 260b and 160b can be formed using the same material. This allows the number of steps in the manufacturing process of a semiconductor device including the transistor 200 and the capacitor 100 to be reduced.

[0410] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0411] Next, the insulator 282 is formed over the insulator 252, the insulator 250, the conductor 260, the insulator 152, the insulator 150, the conductor 160, and the insulator 280 (see FIGS. 14A to 14D ). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0412] In this embodiment, an aluminum oxide film is formed as the insulator 282 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 1.86 W / cm. ２ Preferably, 0 W / cm ２ 0.62W / cm or more ２The amount of oxygen injected into the insulator 280 can be suppressed by reducing the RF power. Alternatively, the insulator 282 may be formed to have a two-layer laminate structure. In this case, the lower layer of the insulator 282 is formed by applying an RF power of 0 W / cm to the substrate. ２ The upper layer of the insulator 282 was formed as follows: the RF power applied to the substrate was 0.62 W / cm ２ The film is formed as follows.

[0413] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0414] Next, an etching mask is formed on the insulator 282 by lithography, and a part of the insulator 282, a part of the insulator 280, a part of the insulator 275, a part of the insulator 222, and a part of the insulator 216 are processed until the top surface of the insulator 214 is exposed (see FIGS. 15A to 15D). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0415] Next, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 350° C. or higher and 600° C. or lower. The temperature of this heat treatment is preferably lower than the temperature of the heat treatment performed after the formation of the oxide film 230B. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing this heat treatment, part of the oxygen added to the insulator 280 diffuses into the oxide 230 via the insulator 250 or the like.

[0416] Furthermore, by performing this heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by processing the insulators 282, 280, 275, 222, and 216. Note that the hydrogen bonded to the oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

[0417] Furthermore, in the region of the oxide 230 overlapping with the conductor 260, an insulator 252 is provided in contact with the top surface and side surface of the oxide 230. The insulator 252 has a barrier property against oxygen, and can reduce the diffusion of an excessive amount of oxygen into the oxide 230. This allows oxygen to be supplied to the region 230bc and its vicinity without excessive oxygen being supplied. This prevents the side surface of the conductor 242 from being oxidized by excess oxygen, and reduces oxygen vacancies and V formed in the region 230bc. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0418] On the other hand, when the transistors 200 are highly integrated, the volume of the insulator 280 for each transistor 200 may become excessively small. In this case, the amount of oxygen diffusing into the oxide 230 during the heat treatment is significantly reduced. Heating the oxide 230 in contact with an oxide insulator (such as the insulator 250) that does not contain sufficient oxygen may cause oxygen to be released from the oxide 230. However, in the transistor 200 described in this embodiment, the insulator 252 is provided in contact with the top and side surfaces of the oxide 230 in a region of the oxide 230 that overlaps with the conductor 260. The insulator 252 has a barrier property against oxygen, and therefore can reduce oxygen release from the oxide 230 during the heat treatment. This reduces oxygen vacancies and V formed in the region 230bc. Ｏ H can be reduced. Therefore, the electrical characteristics of the transistor 200 can be improved, and the reliability can be improved.

[0419] As described above, in the semiconductor device according to this embodiment, a transistor having good electrical characteristics and good reliability can be formed regardless of whether the amount of oxygen supplied from the insulator 280 is large or small. Therefore, a semiconductor device in which variations in the electrical characteristics of the transistor 200 within the substrate surface are suppressed can be provided.

[0420] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 16A to 16D ). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas. The insulator 283 may also have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and then a silicon nitride film may be formed on the silicon nitride by an ALD method. The insulator 283 and the insulator 214, which have high barrier properties, surround the transistor 200, thereby preventing moisture and hydrogen from entering from the outside.

[0421] Next, an insulating film to be the insulator 274 is formed over the insulator 283. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed as the insulating film by a CVD method.

[0422] Next, the insulating film to be the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby planarizing the upper surface of the insulating film and forming the insulator 274 (see FIGS. 16A to 16D). The CMP treatment may remove a part of the upper surface of the insulator 283.

[0423] Next, the insulator 285 is formed over the insulator 274 and the insulator 283 (see FIGS. 17A to 17D ). The insulator 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 285 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced.

[0424] In this embodiment, a silicon oxide film is formed as the insulator 285 by a sputtering method.

[0425] Next, openings are formed in the insulators 271, 275, 280, 282, 283, and 285, reaching the conductor 242a (see FIGS. 17A and 17B). The openings may be formed using lithography. Note that, although the shape of the openings is circular in top view in FIG. 17A, the shape is not limited to this. For example, the openings may have a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners in top view.

[0426] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 17B). The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by an ALD method, and then form a silicon nitride film thereon by a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0427] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 240 that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductor 240.

[0428] Next, a conductive film that will become the conductor 240 is formed. The conductive film preferably has a layered structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, the conductive film may be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0429] Next, CMP treatment is performed to remove a portion of the conductive film that will become the conductor 240, thereby exposing the upper surface of the insulator 285. As a result, the conductive film remains only in the opening, and the conductor 240 can be formed with a flat upper surface (see FIGS. 17A to 17D). Note that the CMP treatment may remove a portion of the upper surface of the insulator 285.

[0430] Next, a conductive film is formed to become the conductor 246. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0431] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246 that is in contact with the top surface of the conductor 240. At this time, a part of the insulator 285 in the region where the conductor 246 and the insulator 285 do not overlap may be removed.

[0432] 1A to 1D can be manufactured. By using the manufacturing method of a semiconductor device described in this embodiment, the capacitor 100 and the transistor 200 can be manufactured in the same process, as shown in FIGS. 5A to 17D. This allows the number of manufacturing steps for a semiconductor device including the capacitor 100 and the transistor 200 to be reduced.

[0433] <Microwave Processing Apparatus> Hereinafter, a microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described.

[0434] First, the configuration of a manufacturing apparatus that minimizes the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0435] 18 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, and chambers 2706a, 2706b, 2706c, and 2706d.

[0436] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c, and 2706d.

[0437] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0438] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 −４ Pa or less, preferably 3×10 −５ Pa or less, more preferably 1×10 −５ The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５Pa or less, more preferably 3×10 −６ The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５ Pa or less, more preferably 3×10 −６ The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 −５ Pa or less, preferably 1×10 −５ Pa or less, more preferably 3×10 −６ Pa or less.

[0439] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using an ionization vacuum gauge, a mass spectrometer, or the like.

[0440] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 is 1×10 ０ Pa / min or less, preferably 5 x 10 −１ The leak rate of each chamber is 1 x 10 −１ Pa / min or less, preferably 5 x 10 −２ Pa / min or less.

[0441] The leak rate may be derived from the total pressure and partial pressure measured using an ionization vacuum gauge, mass spectrometer, or the like. For example, it may be derived from the total pressure 10 minutes after starting evacuation using a vacuum pump such as a turbomolecular pump, and the total pressure 10 minutes after closing the valve. The total pressure 10 minutes after starting evacuation may be the average value of multiple measurements of the total pressure.

[0442] The leak rate depends on external and internal leaks. External leaks are gases that enter from outside the vacuum system due to tiny holes, poor seals, etc. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. To keep the leak rate below the above figures, measures must be taken to prevent both external and internal leaks.

[0443] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0444] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emit little impurity-containing gases, are used as components constituting the manufacturing apparatus 2700. Furthermore, the aforementioned metals that emit little impurity-containing gases may be coated on alloys containing iron, chromium, nickel, and the like. Alloys containing iron, chromium, nickel, and the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gases.

[0445] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0446] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide or the like to suppress gas emissions.

[0447] The adsorbed matter present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 or each chamber because it is adsorbed to the inner walls, but it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at a temperature of 100°C or higher and 450°C or lower. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing the adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by exhaust alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. It is preferable to use a noble gas as the inert gas.

[0448] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated noble gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbates from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be increased to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0449] Next, the chamber 2706b and the chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0450] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave treatment on a workpiece. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave treatment. Since the other configurations are common, they will be described together below.

[0451] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also, outside chamber 2706b and chamber 2706c, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0452] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has the function of evacuating gases and the like from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0453] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0454] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because water can be efficiently evacuated.

[0455] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas may be used for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

[0456] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of −80° C. or lower, preferably −100° C. or lower. For example, oxygen gas, nitrogen gas, or a noble gas (such as argon gas) may be used.

[0457] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0458] The high-frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals according to the gas species supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0459] At this time, ions and radicals generated in the high-density plasma 2810 can modify a film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF (Radio Frequency) power supply with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used as the high-frequency power supply 2816. Applying a bias to the substrate side allows ions in the high-density plasma 2810 to efficiently reach the depths of openings in a film or the like on the substrate 2811.

[0460] For example, oxygen radical treatment can be performed using high density plasma 2810 by introducing oxygen from a gas supply source 2801 into the chamber 2706b or the chamber 2706c.

[0461] Next, the chamber 2706a and the chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0462] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. The only difference between chamber 2706a and chamber 2706d is the type of electromagnetic wave. Since the other configurations are largely common, they will be described together below.

[0463] The chamber 2706a and the chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0464] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0465] A light source capable of emitting electromagnetic waves such as visible light, ultraviolet light, or infrared light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0466] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0467] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0468] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0469] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0470] The microwave processing apparatus that can be used in this embodiment is not limited to the above. A microwave processing apparatus 2900 shown in FIG. 21 can be used. The microwave processing apparatus 2900 includes a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing apparatus 2900 also includes a substrate holder 2902 that holds multiple substrates 2811 (2811_1 to 2811_n, where n is an integer of 2 or more) inside the quartz tube 2901. The microwave processing apparatus 2900 may also include a heating unit 2903 outside the quartz tube 2901.

[0471] Microwaves generated by a high-frequency generator 2803 are irradiated onto a substrate provided in a quartz tube 2901 via a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 via a valve 2818, and the pressure inside the quartz tube 2901 can be adjusted. A gas supply source 2801 is connected to a gas pipe 2806 via a valve 2802, and a desired gas can be introduced into the quartz tube 2901. A heating means 2903 can heat the substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat the gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Alternatively, the microwave treatment can be performed after the substrate 2811 is heated. Alternatively, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0472] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Alternatively, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. Using dummy substrates is preferable because multiple processing substrates can be uniformly processed during microwave processing or heat treatment, reducing variations between processing substrates. For example, placing a dummy substrate on the processing substrate closest to the high-frequency generator 2803 and the waveguide 2804 is preferable because it prevents the processing substrate from being directly exposed to microwaves.

[0473] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0474] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 4A to 4D.

[0475] Fig. 4A shows a top view of a semiconductor device. Fig. 4B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 4A. Fig. 4C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 4A. Fig. 4D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in Fig. 4A. Some elements have been omitted from the top view of Fig. 4A for clarity.

[0476] 4A to 4D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0477] The semiconductor device shown in FIGS. 4A to 4D is a modified example of the semiconductor device shown in FIGS. 1A to 1D . The semiconductor device shown in FIGS. 4A to 4D differs from the semiconductor device shown in FIGS. 1A to 1D in that the insulator 283 is in contact with part of the top surface of the insulator 212. Therefore, the transistor 200 is disposed in a region sealed by the insulator 283 and the insulator 212. This configuration can prevent hydrogen contained outside the sealed region from entering the sealed region. Although the semiconductor device shown in FIGS. 4A to 4D has a configuration in which the insulators 212 and 283 are provided as single layers, the present invention is not limited thereto. For example, the insulators 212 and 283 may each have a stacked structure of two or more layers.

[0478] For example, when the insulator 283 has a two-layer stacked structure, a silicon nitride film may be formed as a lower layer of the insulator 283 by sputtering, and a silicon nitride film may be formed as an upper layer of the insulator 283 by ALD. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the lower layer of the insulator 282 can be reduced. Furthermore, if a pinhole or a step is formed in a film deposited by sputtering, the portion overlapping the pinhole or step can be blocked by using a film deposited by ALD, which has good coverage.

[0479] When the insulator 283 has a two-layer laminated structure, a part of the upper surface of the upper layer of the insulator 283 may be removed. Also, it may be difficult to clearly detect the boundary between the upper and lower layers of the insulator 283.

[0480] 4B and 4C, the conductor 205 may have a three-layer structure of conductor 205a, conductor 205b, and conductor 205c. The conductor 205c is provided in contact with the upper surface of the conductor 205b. The side surface of the conductor 205c may be in contact with the conductor 205a. The upper surface of the conductor 205c may be configured to roughly coincide with the top of the conductor 205a.

[0481] Like the conductor 205a, the conductor 205c is preferably made of a conductive material that has the function of reducing hydrogen diffusion. This allows the conductor 205b to be surrounded by the conductors 205a and 205c, thereby preventing impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulators 216 and 224. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductors 205a and 205c, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity.

[0482] Furthermore, the insulator 271a and the insulator 271b may each have a two-layer stacked structure. It is preferable that the lower layers of the insulators 271a and 271b function as barrier insulating films against oxygen. Therefore, it is preferable that the lower layers of the insulators 271a and 271b have a function of suppressing oxygen diffusion. This can prevent oxygen contained in the insulator 280 from diffusing into the conductors 242a and 242b. Therefore, it is possible to suppress the oxidation of the conductors 242a and 242b by the oxygen contained in the insulator 280, which would increase the resistivity and reduce the on-current.

[0483] The upper layers of the insulators 271a and 271b function as protective layers to allow the lower layers of the insulators 271a and 271b to remain. When removing the hard mask after processing the conductive film that will become the conductors 242a and 242b and the oxide film that will become the oxide 230b into islands, the insulating layer that will become the lower layers of the insulators 271a and 271b may be removed. Therefore, by providing the insulating layer that will become the upper layer of the insulators 271a and 271b between the hard mask and the insulating layer that will become the lower layers of the insulators 271a and 271b, the insulating layer that will become the lower layers of the insulators 271a and 271b can be retained. For example, when tungsten is used as the hard mask, it is preferable to use silicon oxide or the like as the upper layer of the insulators 271a and 271b.

[0484] OS transistors such as the transistor 200 have small changes in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. For example, OS transistors can be suitably used in outer space. Specifically, OS transistors can be used as transistors for semiconductor devices installed in space shuttles, artificial satellites, space probes, and the like. Examples of radiation include X-rays and neutron rays. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0485] Alternatively, for example, the OS transistor can be used as a transistor for a semiconductor device provided in a robot for working at a nuclear power plant or a radioactive waste treatment or disposal site, and particularly as a transistor for a semiconductor device provided in a remote-controlled robot that is remotely operated to dismantle a nuclear reactor facility, remove nuclear fuel or fuel debris, or conduct on-site inspections of spaces containing a lot of radioactive material.

[0486] <Application Example 1 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS.

[0487] FIG. 22A shows a top view of the semiconductor device 500. The x-axis in FIG. 22A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 22B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in FIG. 22A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 22C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in FIG. 22A and is also a cross-sectional view of the opening region 400 and its vicinity. Note that some elements are omitted from the top view in FIG. 22A for clarity.

[0488] 22A to 22C, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Example of Semiconductor Device>. Note that, in this section as well, the materials described in detail in <Configuration Example of Semiconductor Device> can be used as the constituent materials of the semiconductor device.

[0489] 22A to 22C is a modified example of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device 500 shown in FIGS. 22A to 22C differs from the semiconductor device shown in FIGS. 1A to 1D in that an opening region 400 is formed in the insulator 282 and the insulator 280. The semiconductor device 500 also differs from the semiconductor device shown in FIGS. 1A to 1D in that a sealing portion 265 is formed to surround the plurality of transistors 200 and the capacitor 100.

[0490] The semiconductor device 500 includes a plurality of transistors 200, a plurality of capacitors 100, and a plurality of opening regions 400 arranged in a matrix. A plurality of conductors 260 functioning as gate electrodes of the transistors 200 extend in the y-axis direction. A plurality of conductors 160 functioning as upper electrodes of the capacitors 100 extend in the y-axis direction. The opening regions 400 are formed in regions that do not overlap with the oxide 230, the conductors 260, and the conductors 160. A sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, the plurality of capacitors 100, the plurality of conductors 160, and the plurality of opening regions 400. The number, arrangement, and size of the transistors 200, the conductors 260, the capacitors 100, the conductors 160, and the opening regions 400 are not limited to the structure shown in FIG. 22 and may be appropriately set according to the design of the semiconductor device 500.

[0491] 22B and 22C , the sealing portion 265 is provided to surround the plurality of transistors 200, the plurality of capacitor elements 100, the insulators 216, 222, 275, 280, and 282. In other words, the insulator 283 is provided to cover the insulators 216, 222, 275, 280, and 282. Furthermore, in the sealing portion 265, the insulator 283 is in contact with the upper surface of the insulator 214. Furthermore, on the sealing portion 265, the insulator 274 is provided between the insulators 283 and 285. The upper surface of the insulator 274 is approximately flush with the uppermost surface of the insulator 283. Furthermore, the insulator 274 may be made of the same insulator as the insulator 280.

[0492] With this structure, the plurality of transistors 200 and the plurality of capacitors 100 can be enclosed by the insulators 283, 214, and 212. Here, it is preferable that one or more of the insulators 283, 214, and 212 function as a barrier insulating film against hydrogen. This can prevent hydrogen contained outside the region of the sealing portion 265 from mixing into the region of the sealing portion 265.

[0493] 22C , insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove in opening region 400, overlapping the opening of insulator 282. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 275, and may be, for example, approximately ¼ to ½ of the maximum film thickness of insulator 280.

[0494] 22C , insulator 283 contacts the side surface of insulator 282, the side surface of insulator 280, and the top surface of insulator 280 inside opening region 400. In addition, a portion of insulator 274 may be formed within opening region 400 so as to fill a recess formed in insulator 283. In this case, the height of the top surface of insulator 274 formed within opening region 400 may roughly coincide with the height of the top surface of insulator 283.

[0495] By performing heat treatment in a state where the opening region 400 is formed and the insulator 280 is exposed through the opening of the insulator 282, oxygen can be supplied to the oxide 230 while some of the oxygen contained in the insulator 280 diffuses outward from the opening region 400. This allows sufficient oxygen to be supplied from the insulator 280 containing oxygen released by heating to a region in the oxide semiconductor layer that functions as a channel formation region and its vicinity, while preventing excessive oxygen from being supplied.

[0496] At this time, the hydrogen contained in the insulator 280 can be bonded with oxygen and released to the outside through the opening region 400. The hydrogen bonded with oxygen is released as water. Therefore, the hydrogen contained in the insulator 280 can be reduced, and the hydrogen contained in the insulator 280 can be prevented from mixing into the oxide 230.

[0497] 22A , the shape of the opening region 400 in a top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400 in a top view may be rectangular, elliptical, circular, diamond-shaped, or a combination thereof. The area and spacing of the opening regions 400 can be appropriately set in accordance with the design of the semiconductor device including the transistors 200 and the capacitor elements 100. For example, in a region where the density of the transistors 200 is low, the area of ​​the opening regions 400 can be increased or the spacing between the opening regions 400 can be narrowed. For example, in a region where the density of the transistors 200 is high, the area of ​​the opening regions 400 can be narrowed or the spacing between the opening regions can be widened.

[0498] <Application Example 2 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 23A and 23B.

[0499] 23A is a top view of a semiconductor device 600. The semiconductor device 600 includes a transistor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b according to one embodiment of the present invention. FIG. 23B is a cross-sectional view corresponding to a portion indicated by a dashed dotted line A1-A2 in FIG. 23A and is also a cross-sectional view of the transistor 200a and the transistor 200b in the channel length direction. Note that some elements are omitted from the top view in FIG. 23A for clarity.

[0500] In the semiconductor device 600, the transistor 200a and the transistor 200b have the same structure as the transistor 200 except that the insulator 224, the oxide 230a, the oxide 230b, the conductor 242c, the insulator 271c, the conductor 240, the insulator 241, and the conductor 246 are shared between the transistor 200a and the transistor 200b. Therefore, the above description can be referred to for details. The capacitor 100a and the capacitor 100b have the same structure as the capacitor 100. Therefore, the above description can be referred to for details.

[0501] As shown in FIGS. 23A and 23B , the semiconductor device 600 has a linear symmetry structure with the dashed-dotted line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. An insulator 271c is provided on conductor 242c. Furthermore, conductor 246, which functions as a wiring, and conductor 240, which functions as a plug, are also shared between transistors 200a and 200b. By sharing wiring and plugs between two transistors and two capacitors in this manner, the area occupied by each transistor and each capacitor in a top view can be reduced. This allows for a semiconductor device that can be miniaturized or highly integrated.

[0502] According to one embodiment of the present invention, a novel transistor can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with favorable frequency characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to another embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0503] At least part of the structures, methods, and the like described in this embodiment mode can be implemented in appropriate combination with other embodiment modes and examples described in this specification.

[0504] Embodiment Mode 2 In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0505] 24 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. The semiconductor device illustrated in FIG. 24 is a memory device including a transistor using an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor. The memory device includes at least the capacitor and the OS transistor that controls charging and discharging of the capacitor.

[0506] 24 , in the semiconductor device of one embodiment of the present invention, a transistor 200 and a capacitor 100 are provided above a transistor 300. Note that the transistor 200 described in the above embodiment can be used as the transistor 200. The capacitor 100 can be used as the capacitor 100.

[0507] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the transistor 200 can retain stored data for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced. Furthermore, as described in the above embodiment, the transistor 200 has high frequency characteristics; therefore, reading and writing to and from the memory device can be performed at high speed.

[0508] 24 , a wiring 1001 is electrically connected to the source of the transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. The other of the source and drain of the transistor 200 is electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0509] Moreover, the memory device shown in FIG. 24 can be arranged in a matrix to form a memory array.

[0510] The transistor 300 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor.

[0511] Here, in the transistor 300 shown in FIG. 24 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0512] Note that the transistor 300 illustrated in FIG. 24 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0513] <Wiring Layer> A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Here, for conductors that function as plugs or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as the wiring, and cases where a portion of the conductor functions as the plug.

[0514] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0515] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0516] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 24, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0517] Similarly, a conductor 218, a conductor (the conductor 205) that constitutes the transistor 200, and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring that electrically connects to the capacitor 100 or the transistor 300.

[0518] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0519] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0520] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0521] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0522] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0523] For example, the insulators 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, resin, or the like. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0524] Furthermore, when a transistor including an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, 350, and the like can be insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen.

[0525] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0526] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0527] For example, the conductors 328, 330, 356, conductor 218, and 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, they are preferably formed using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

[0528] <Wiring or Plug in Layer Including Oxide Semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0529] 24, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0530] That is, the insulator 241 can prevent excess oxygen contained in the insulators 224 and 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0531] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high blocking property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0532] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the amount of hydrogen contained in the insulator 274 or the like that gets mixed into the insulator 280 or the like.

[0533] Here, the conductor 240 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214 and 212. As described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 212, 214, 282, and 283 via the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, and it is possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274, etc. from the outside.

[0534] A conductor 112 is provided on the conductor 240. The conductor 112 corresponds to the conductor 246 shown in FIG. 1B and other figures. That is, the conductor 112 functions as a wiring. In FIG. 24, the conductor 112 has a single-layer structure, but is not limited to this configuration and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0535] The insulator 130 is provided to cover the conductor 112, and the insulator 146 is provided over the insulator 130. The insulator 130 is preferably an insulator that can be used as the insulator 283 described in the above embodiment. The insulator 146 is preferably an insulator that can be used for the insulator 210, the insulator 352, the insulator 354, and the like.

[0536] <Dicing Lines> The following describes dicing lines (which may also be referred to as scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, there is a case where grooves (dicing lines) for dividing the semiconductor elements are first formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the substrate into multiple semiconductor devices.

[0537] 24, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, and the insulator 216 so that the region where the insulator 283 and the insulator 214 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 224, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0538] That is, the insulator 214 and the insulator 283 are in contact with each other through the openings provided in the insulators 282 , 280 , 275 , 224 , 222 , and 216 .

[0539] Furthermore, for example, openings may be provided in the insulators 282, 280, 275, 224, 222, 216, and 214. With this configuration, the insulators 212 and 283 are in contact with each other through the openings provided in the insulator...

Claims

1. A semiconductor device having a transistor and a capacitor, The transistor is An oxide, a first conductor and a second conductor on the oxide; a first insulator disposed on the first conductor and the second conductor, the first insulator having a first opening and a second opening; a second insulator within the first opening of the first insulator; and a third conductor on the second insulator; and and the first opening of the first insulator has a region overlapping with the oxide, the third conductor has a region overlapping with the oxide via the second insulator, the second insulator has regions in contact with an upper surface of the oxide and a sidewall of the first opening of the first insulator, the capacitive element has the second conductor, a third insulator on the second conductor, and a fourth conductor on the third insulator; the third insulator and the fourth conductor are disposed in the second opening; the second opening has a region overlapping with the second conductor; the fourth conductor has a region overlapping with the second conductor via the third insulator, the third insulator has regions in contact with an upper surface of the second conductor and a sidewall of the first opening of the first insulator, the second insulator includes a fourth insulator, a fifth insulator on the fourth insulator, and a sixth insulator on the fifth insulator; the third insulator includes a seventh insulator, an eighth insulator on the seventh insulator, and a ninth insulator on the eighth insulator; the fourth insulator has a region in which the film thickness is smaller than the film thickness of the fifth insulator; the sixth insulator is less permeable to oxygen than the fifth insulator; the seventh insulator has a region in which the film thickness is smaller than the film thickness of the eighth insulator; the ninth insulator is less permeable to oxygen than the eighth insulator; In a cross-sectional view of the transistor in a channel length direction, a distance between the first conductor and the second conductor is smaller than a width of the first opening. Semiconductor device.

2. In claim 1, the fourth insulator has the same insulating material as the seventh insulator; the fifth insulator has the same insulating material as the eighth insulator; the sixth insulator has the same insulating material as the ninth insulator; the third conductor has the same conductive material as the fourth conductor; Semiconductor device.

3. In claim 2, a tenth insulator is disposed between the first conductor and the second conductor and the first insulator; the tenth insulator has a third opening overlapping the first opening and a fourth opening overlapping the second opening; the tenth insulator is less permeable to oxygen than the fourth insulator and the seventh insulator; the tenth insulator has regions in contact with a side surface of the oxide, a side surface of the first conductor, and a side surface of the second conductor, In a cross-sectional view of the transistor in a channel length direction, a distance between the first conductor and the second conductor is smaller than a width of the third opening. Semiconductor device.

4. In claim 3, the opposing side surfaces of the first conductor and the second conductor are approximately perpendicular to the top surface of the oxide; Semiconductor device.

5. In claim 3, the first conductor has a fifth conductor and a sixth conductor on the fifth conductor; the second conductor has a seventh conductor and an eighth conductor on the seventh conductor; In a cross-sectional view of the transistor in a channel length direction, a distance between the fifth conductor and the seventh conductor is shorter than a distance between the sixth conductor and the eighth conductor. Semiconductor device.

6. In claim 3, The oxide contains indium, zinc, and one or more selected from gallium, aluminum, and tin. Semiconductor device.

7. In claim 3, The oxide has a crystal structure, The c-axis of the crystal is approximately perpendicular to the surface or the surface on which the oxide is formed. Semiconductor device.

8. In any one of claims 1 to 7, a ninth conductor below the oxide; the ninth conductor overlaps the oxide and the third conductor; Semiconductor device.

9. 9. A semiconductor device according to claim 8, comprising a plurality of layers each having a memory array provided thereon; each of the layers includes a first wiring electrically connected to the first conductor, a second wiring electrically connected to the third conductor, and a third wiring electrically connected to the fourth conductor; In the successive layers, the ninth conductor in an upper layer is electrically connected to the third wiring in a lower layer; In the consecutive layers, the second wiring in a lower layer is provided at a position overlapping with the third wiring in an upper layer.

10. In claim 9, the first wirings included in the odd-numbered layers are electrically connected to each other; The first wirings of the even-numbered layers are electrically connected to each other.

11. In claim 10, A drive circuit is provided. The memory device, wherein the plurality of layers are stacked on the drive circuit.

12. a transistor and a capacitor, the transistor includes an oxide, first to third conductors, a first insulator, and a second insulator; the capacitive element includes the second conductor, a third insulator, and a fourth conductor. In a method for manufacturing a semiconductor device, forming the first insulator over the oxide and the conductive layer on the oxide; forming a first opening and a second opening in the first insulator, exposing the top and side surfaces of the conductive layer and the side surface of the oxide; forming a mask layer covering the first insulator and the second opening; the mask layer has a third opening having an area overlapping with the first opening; In a cross-sectional view of the transistor in a channel length direction, a width of the third opening is smaller than a width of the first opening; etching the conductive layer using the mask layer to form the first conductor and the second conductor; forming an insulating film to cover the first insulator, the first opening, and the second opening; forming a conductive film on the insulating film; removing portions of the insulating film and the conductive film exposed from the first opening and the second opening to form the second insulator and the third conductor in the first opening, and to form the third insulator and the fourth conductor in the second opening; A method for manufacturing a semiconductor device.