Interposer, semiconductor package, and methods for manufacturing same

Abstract

The purpose of the present invention is to provide a system in package (SiP) in which the quality of an interposer can be checked before a semiconductor device is mounted thereon, and that has high yield. Accordingly, provided is an interposer comprising: an inner-layer structure which includes at least one inner-layer wiring layer; a first outer-layer structure which is disposed on a first surface of the inner-layer structure and has higher stiffness than the inner-layer structure; and a second outer-layer structure which is disposed on a second surface of the inner-layer structure and has higher stiffness than the inner-layer structure. The inner-layer wiring layer comprises a wire disposed on a surface of a first insulating resin layer and a conductive member which connects to the wire and penetrates through the first insulating resin layer. The first outer-layer structure and the second outer-layer structure each comprises a second insulating resin layer and a conductive member penetrating through the second insulating resin. A terminal that can be connected to a semiconductor device and allows for electric testing is formed on a surface of the first outer-layer structure and / or the second outer-layer structure on the opposite side to the surface thereof connected to the inner-layer structure.

Description

Interposer, semiconductor package, and manufacturing method thereof

[0001] The present invention relates to an interposer for mounting a semiconductor device, a semiconductor package in which a semiconductor device is mounted on an interposer, and a method for manufacturing the same.

[0002] In recent years, SiP (System In Package) has been put to practical use, in which multiple heterogeneous semiconductor devices (semiconductor chips) are mounted on an interposer to form a single highly functional semiconductor package. This method makes it possible to obtain a "semiconductor package," which is a single highly functional semiconductor device, without increasing process costs.

[0003] Furthermore, there is a tendency for stacked DRAM, such as high bandwidth memory (HBM), to be widely used as a semiconductor device mounted on the SiP. HBM generally has narrow connection terminal pitches of about 55 μm, which requires connection terminals of the same pitch to be formed on the interposer.

[0004] Furthermore, the interposer described above will be connected to an FC-BGA, but the CTE (Coefficient of Thermal Expansion) of the FC-BGA is approximately 18 ppm / °C, which is higher than the CTE of a semiconductor chip, which is 3 ppm / °C. For this reason, the interposer is required to have the function of mitigating the CTE mismatch between the semiconductor chip and the FC-BGA. Furthermore, for convenience in assembling the semiconductor package, it is desirable to be able to mount the semiconductor device on the interposer and then mount this on the FC-BGA. For this reason, the interposer needs to be able to exist as a standalone unit separate from the FC-BGA.

[0005] Patent Document 1 discloses a technology for suppressing warpage of an interposer, as a manufacturing method for a semiconductor package (1), including the steps of: preparing a laminate (20) having a plate-shaped first reinforcing member (5A), a laminate (2A) for a first conductor pattern wiring board, and a plate-shaped second reinforcing member (4A) arranged on a second conductor pattern (224); heating the laminate (20) to thermally harden the insulating layer; selectively removing a portion of the first reinforcing member (5A) to form an opening for exposing the first conductor pattern (224); selectively removing a portion of the second reinforcing member (4A) to form an opening 41 for exposing the second conductor pattern (221); and connecting a semiconductor element (3) to the second conductor pattern (221) exposed from the opening of the second reinforcing member (4A).

[0006] WO2013-065287

[0007] However, because the interposer disclosed in Patent Document 1 has a structure in which a fiber substrate is impregnated with a resin composition, the diameter of the vias that can be formed is limited to 50 μm. Also, the via-to-via pitch is limited to 130 μm, making it difficult to mount an HBM, which is a stacked DRAM.

[0008] Furthermore, conventional interposers, such as fan-out packages and silicon interposers, and semiconductor packages using them are not designed to undergo a process of mounting a semiconductor device after inspecting the interposer itself. Therefore, in conventional manufacturing methods, multiple chips are mounted on the interposer without the interposer itself being inspected. As a result, the yield of the semiconductor package is the sum of interposer manufacturing defects and chip mounting defects, and it is not possible to separate them.

[0009] Specifically, the manufacturing yield of SiP can be simply expressed by the following calculation formula (1): "Interposer yield" (Y INTERPOSER ): (value between 0 and 1) Geometric mean yield of semiconductor chip mounting ("mounting yield" (Y ASSEMBRY): (value between 0 and 1) Number of semiconductor devices mounted on the SiP: N (an integer of 1 or more) Manufacturing yield of the SiP (Y TOTAL ): (values ​​between 0 and 1), the manufacturing yield of SiP is as follows: (Y TOTAL )=(Y INTERPOSER ) × (Y ASSEMBRY ) Ｎ ....(1)

[0010] As shown in formula (1), the manufacturing yield of SiP is the interposer yield multiplied by the geometric mean yield of chip packaging raised to the power of the number of chips. INTERPOSER ) and "mounting yield" (Y ASSEMBRY ) are both 90%, and in the case of a SiP with seven chips mounted, (Y INTERPOSER )=(Y ASSEMBRY )=90%, N=7...(2) (Y TOTAL ) = 0.9 7 = 47.8% (3) Even if the yield of each process is 90%, the manufacturing yield of the entire SiP becomes extremely low.

[0011] In a SiP, where multiple semiconductor devices are mounted to form a single semiconductor package, even if each individual semiconductor device passes inspection, if there is a manufacturing defect or mounting defect in just one interposer, the entire SiP (all of the multiple semiconductor devices) will have to be discarded. As a result, as the number of mounted chips increases, the SiP manufacturing yield will exponentially decrease, and the number of discarded good chips will also increase.

[0012] Furthermore, in the conventional manufacturing method, the entire surface of the mounted semiconductor device is hardened with molding resin, which makes it impossible to replace or otherwise repair individual semiconductor devices that have manufacturing defects.

[0013] Therefore, an object of the present invention is to provide an interposer that allows connection terminals for semiconductor devices to be formed at a narrow pitch of 60 μm or less, and that allows electrical testing of the interposer itself before mounting the semiconductor device.

[0014] In order to solve the above problems, one representative interposer of the present invention is an interposer comprising: an inner layer structure including at least one inner layer wiring layer; a first outer layer structure arranged on a first main surface of the inner layer structure and having higher rigidity than the inner layer structure; and a second outer layer structure arranged on a second main surface of the inner layer structure and having higher rigidity than the inner layer structure, wherein the inner layer wiring layer comprises wiring arranged on the surface of a first insulating resin layer and a conductive member connected to the wiring and penetrating the first insulating resin layer; the first outer layer structure and the second outer layer structure comprise a second insulating resin layer and a conductive member penetrating the second insulating resin; and the first outer layer structure and / or the second outer layer structure comprise terminals on the surface opposite to the surface connected to the inner layer structure that can be connected to a semiconductor device and can be electrically tested.

[0015] According to the present invention, it is possible to provide an interposer that can form connection terminals for semiconductor devices with a narrow pitch of 60 μm or less and that can perform electrical testing of the interposer itself before mounting the semiconductor device. Problems, configurations, and effects other than those described above will become clear from the description of the following embodiments.

[0016] FIG. 1 is a cross-sectional view of an interposer and a semiconductor package according to the first embodiment. FIG. 2 is a diagram showing the relationship between the overall CTE and the CTE of an outer wiring layer. FIG. 3 is a diagram showing the relationship between the manufacturing defect rate and thickness. FIG. 4 is a schematic diagram showing a modified example of the interposer according to the first embodiment. FIG. 5 is a schematic diagram showing a modified example of the interposer according to the first embodiment. FIG. 6 is a schematic diagram showing a modified example of the interposer according to the first embodiment. FIG. 7 is a diagram explaining the manufacturing process of the interposer and semiconductor package according to the first embodiment. FIG. 8 is a diagram explaining the manufacturing process of the interposer and semiconductor package according to the first embodiment. FIG. 9 is a diagram explaining the manufacturing process of the interposer and semiconductor package according to the first embodiment. FIG. 10 is a diagram explaining the manufacturing process of the interposer and semiconductor package according to the first embodiment. FIG. 11 is a diagram explaining the manufacturing process of an interposer according to a modified example of the first embodiment. FIG. 12 is a diagram explaining the manufacturing process of the semiconductor package according to the first embodiment. FIG. 13 is a diagram explaining the manufacturing process of the semiconductor package according to the first embodiment. FIG. 14 is a schematic diagram showing an interposer according to a second embodiment. FIG. 15 is a diagram illustrating a method for manufacturing an interposer according to the second embodiment. FIG. 16 is a schematic diagram illustrating an interposer and a semiconductor package according to a third embodiment. FIG. 17 is a diagram illustrating a method for manufacturing an interposer according to the third embodiment. FIG. 18 is a diagram illustrating a method for manufacturing an interposer according to the third embodiment. FIG. 19 is a schematic diagram illustrating an interposer and a semiconductor package according to a fourth embodiment. FIG. 20 is a diagram illustrating a method for manufacturing an interposer and a semiconductor package according to the fourth embodiment. FIG. 21 is a diagram illustrating a method for manufacturing a semiconductor package according to the fourth embodiment. FIG. 22 is a diagram illustrating an outline of a four-point bending test. FIG. 23 is a table showing standard values ​​for deflection rate in a four-point bending test. FIG. 24 is a diagram illustrating the relationship between the thickness of an interposer and the ratio of the load to the deflection amount in a four-point bending test. FIG. 25 is a schematic diagram illustrating an interposer and a semiconductor package according to a fifth embodiment. FIG. 26 is a diagram illustrating a method for manufacturing an interposer and a semiconductor package according to the fifth embodiment. FIG. 27 is a diagram illustrating a method for manufacturing an interposer and a semiconductor package according to a first modified example of the fifth embodiment.28A to 28C are diagrams illustrating a method for manufacturing an interposer and a semiconductor package according to the second modification of the fifth embodiment.

[0017] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the present invention is not limited to this embodiment. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals. The designations "first" and "second" do not particularly limit the order or configuration, but are defined for the convenience of explanation.

[0018] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0019] In this disclosure, the term "surface" may refer not only to the surface of a plate-shaped member, but also to the interface of a layer contained in the plate-shaped member that is approximately parallel to the surface of the plate-shaped member. Furthermore, the terms "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing of a plate-shaped member or a layer contained in the plate-shaped member. The "upper surface" and "lower surface" may also be referred to as the "first surface" and "second surface."

[0020] Furthermore, "side" refers to the surface or thickness of a layer of a plate-like member or a layer contained in a plate-like member. Furthermore, a portion of the surface and the side may be collectively referred to as the "end." Furthermore, "upper" refers to the direction vertically upward when the plate-like member or layer is placed horizontally. Furthermore, "upper" and its opposite, "lower," may be referred to as the "positive Z-axis direction" and the "negative Z-axis direction," and the horizontal direction may be referred to as the "X-axis direction" and the "Y-axis direction."

[0021] Furthermore, "planar shape" and "plan view" refer to the shape of a surface or layer when viewed from above. Furthermore, "cross-sectional shape" and "cross-sectional view" refer to the shape of a plate-like member or layer when cut in a specific direction and viewed from the horizontal direction. Furthermore, "center" refers to the center, not the peripheral part, of a surface or layer. And "central direction" refers to the direction from the peripheral part of a surface or layer toward the center of the planar shape of the surface or layer.

[0022] (First embodiment) <Structure of interposer> Fig. 1(a) is an example of a schematic cross-sectional view of an interposer 100 according to a first embodiment of the present invention. Fig. 1(b) is a schematic cross-sectional view of a semiconductor package 150 in which semiconductor devices 50 and 51 are mounted on the interposer 100 according to the first embodiment. Note that in this disclosure, with respect to the top and bottom surfaces of the interposer 100, the side on which the semiconductor devices 50 and 51 are mounted will be referred to as the "first surface side," and the side on which the interposer 100 is connected to a motherboard or FC-BGA will be referred to as the "second surface side."

[0023] In this embodiment, second connection terminals 17 are disposed on the second surface of the second outer layer structure 11. The second connection terminals 17 serve as connection terminals to an FC-BGA substrate or a motherboard. The interposer 100 in FIG. 1( a) is primarily composed of a first outer layer structure 5, an inner layer structure 7, and a second outer layer structure 11. The first outer layer structure 5 is disposed above the inner layer structure 7, i.e., in the positive direction of the Z-axis. The first outer layer structure 5 is formed of a second insulating resin layer 6, and a conductive member 4 is formed in the second insulating resin layer 6, penetrating the second insulating resin layer 6 in the Z-axis direction. The conductive member 4 penetrating the second insulating resin layer 6 can function as a pad for an external connection terminal of the first outer layer structure 5. A first connection terminal 16 is disposed on the first surface of the first outer layer structure 5.

[0024] The inner layer structure 7 is disposed between the first outer layer structure 5 and the second outer layer structure 11. The inner layer structure 7 includes at least one inner wiring layer, which includes a first insulating resin layer 8, wiring 10 disposed on the surface of the first insulating resin layer, and a conductive member connected to the wiring 10 and penetrating the first insulating resin layer in the Z-axis direction. The conductive member penetrating the first insulating resin layer can function as a via 9 of the inner wiring layer. A first connection terminal (solder) 16 is disposed on the first surface side of the first outer layer structure 5.

[0025] The second outer layer structure 11 is disposed below the inner layer structure 7, i.e., in the negative Z-axis direction. The second outer layer structure 11 is formed of a second insulating resin layer 12, and a conductive member penetrating the second insulating resin layer 12 in the Z-axis direction is formed in the second insulating resin layer 12. The conductive member penetrating the second insulating resin layer 12 connects to the outermost wiring layer of the inner layer structure 7 and can function as a pad for an external connection terminal of the second outer layer structure 11. Furthermore, a pad 15 for an external connection terminal and a second connection terminal (solder) 17 are disposed on the second surface side of the second outer layer structure 11.

[0026] It is desirable that the total thickness of the interposer 100 in the Z-axis direction, including the inner layer structure 7, the first outer layer structure 5, and the second outer layer structure 11, be 50 μm or more. Furthermore, the thicknesses of the first outer layer structure 5 and the second outer layer structure 11 of the interposer 100 in this embodiment are not limited to the thicknesses adopted in this embodiment, but if the first outer layer structure 5 and the second outer layer structure 11 have higher physical rigidity than the inner layer structure 7, it is desirable that the sum of the thicknesses of the first outer layer structure 5 and the second outer layer structure 11 be thicker than the inner layer structure 7. In other words, it is desirable that the first outer layer structure 5 and the second outer layer structure 11 be half or more of the total thickness of the interposer 100.

[0027] <Structure of Semiconductor Package> FIG. 1B shows a semiconductor package 150 in which semiconductor devices 50 and 51 are fixed to the first surface side of the interposer 100 described in FIG. 1A by an underfill 19 and a mold resin 20 .

[0028] Although the first connection terminal 16 and the second connection terminal 17 are made of solder, the present invention does not limit the type or composition of the solder, and any known conductive material can be used. Furthermore, although the first connection terminal 16 in Figures 1(a) and 1(b) is formed flush with the conductive member 4 of the first outer layer structure 5, the positional relationship and shape of the first connection terminal 16 and the conductive member 4 are not limited to this. Similarly, the second connection terminal 17 is formed in alignment with the external terminal pad 15 on the via 14 of the second outer layer structure 11, but is not necessarily limited to this structure.

[0029] 1A as an interposer for a SiP mounting a plurality of semiconductor devices, a wiring rule of at least L / S = 8 / 8 μm or less is required. Therefore, it is desirable that the thickness of the first insulating resin layer 8 constituting the inner layer structure 7 is 25 μm or less. As a result, the inner layer structure 7 is necessarily flexible and lacks physical rigidity, even if the inner layer wiring layer is a multilayer laminated circuit.

[0030] For this reason, in this embodiment, the fine wiring structure required for an SiP interposer mounting multiple semiconductor devices is formed by the inner layer structure 7. Furthermore, the physical rigidity of the input / output terminal portion of the inner layer structure 7 is formed by the first outer layer structure 5 and the second outer layer structure 11. Since the input / output terminal portion has more leeway in the wiring rules compared to the fine wiring in the inner layer structure 7, the first outer layer structure 5 and the second outer layer structure 11 can be formed using a rigid material. Therefore, by sandwiching the inner layer structure 7, which does not have physical rigidity, between the first outer layer structure 5 and the second outer layer structure 11, which do have physical rigidity, the interposer 100 can be configured as a device with rigidity as a whole. In other words, by functionally dividing the fine circuit characteristics and physical rigidity characteristics between the inner layer structure 7 and the two outer layer structures and combining these opposing characteristics, an interposer that combines the excellent characteristics of both is realized.

[0031] <CTE and Elastic Modulus of Outer Layer Structure> The second insulating resin layer constituting the first outer layer structure 5 and the second outer layer structure 11 is preferably selected from a non-photosensitive insulating resin containing a filler. Furthermore, the second insulating resin layer is more preferably a non-photosensitive resin layer containing a filler, and is selected from prepreg, built-up resin, and molded resin having an elastic modulus of 5 GPa or more and a linear thermal expansion coefficient CTE of 20 ppm or less. The first insulating resin layer applicable to the inner layer structure 7 in this embodiment is a photosensitive insulating resin or built-up resin, which is typically a low-elasticity, high-CTE material with a CTE of 20 ppm to 80 ppm / °C and an elastic modulus of 1.5 to 10 GPa or less. Therefore, an interposer formed solely from the above materials would have a CTE lower than the CTE of 18 ppm / °C of FC-BGA, making it difficult to realize an interposer that functions as a buffer against the low CTE of a semiconductor device. In this embodiment, in this respect as well, by selecting the second insulating resin layer used in the first outer layer structure 5 and the second outer layer structure 11 from mold resins, prepregs, and built-up resins having a CTE of 20 ppm / °C or less and a high elastic modulus of 5 GPa or more, it is possible to make the CTE of the entire interposer equal to or less than 15 to 30 ppm / °C, which is the CTE of FC-BGA.

[0032] When the CTE of the second insulating resin layer used in the first outer layer structure 5 and the second outer layer structure 11 is set to 20 ppm / °C or less, the effect of reducing the CTE of the entire interposer 100 is achieved, as explained below. Figure 2 shows the results of a simulation of the relationship between the CTE of the entire interposer with a total thickness of 50 μm in the present invention and the CTE and elastic modulus of the materials used in the first outer layer structure and the second outer layer structure. The Y axis shows the CTE of the entire interposer, and the X axis shows the CTE of the first and second outer wiring layers. The simulation conditions are as follows. Note that the CTE and elastic modulus of the first outer wiring layer and the second outer wiring layer were calculated using the same factors.

[0033] First outer layer structure Thickness: 20 μm, copper wiring volume ratio fixed at 10%, CTE and elastic modulus are factors Second outer layer structure Thickness: 20 μm, copper wiring volume ratio fixed at 30%, CTE and elastic modulus are factors Inner layer structure Thickness: 10 μm, CTE: 65 ppm / °C, elastic modulus 2 GPa, copper wiring thickness 2 μm, copper wiring volume ratio 85%, total interposer thickness 50 μm Reference value: CTE of the entire FC-BGA board is 18 ppm / °C. Dot-dash line in the graph.

[0034] The results of a simulation performed under these conditions are shown in the graph in Figure 2. That is, as is clear from Figure 2, by using first outer layer structure 5 and second outer layer structure 11 with a CTE of 20 ppm / °C or less, it is possible to make the CTE of the entire interposer 100 lower than that of the FC-BGA substrate of the prior art. It is also clear that the more highly elastic materials are used for first outer layer structure 5 and second outer layer structure 11, the greater the effect of reducing the CTE of the entire interposer. From these facts, it has been found that the CTE of the entire interposer can be effectively reduced if the elastic modulus of first outer layer structure 5 and second outer layer structure 11 is 5 GPa or more, and it is desirable to select a CTE of 20 ppm / °C or less and an elastic modulus of 5 GPa or more.

[0035] <Configuration of Outer Layer Structure and Remaining Copper Ratio> The conductive members 4, vias 14, and pads 15 of the first outer layer structure 5 and the second outer layer structure 11 of the interposer 100 of the embodiment shown in FIG. 1( a) function to electrically connect the first connection terminals 16 and the second connection terminals 17 to the wiring of the inner layer structure 7. For this reason, the first outer layer structure 5 and the second outer layer structure 11 are formed with connection paths that are basically in the Z direction. On the other hand, the inner layer structure 7 uses wiring suitable for miniaturization to realize wiring routing in the Z axis direction and a direction perpendicular to the Z axis, i.e., the horizontal direction. Copper is basically used as the conductive member used in the interposer of this embodiment. However, because copper has a relatively high CTE of 16 ppm / °C, if the copper volume fraction in the first outer layer structure 5 and the second outer layer structure 11 is high, it becomes difficult to lower the CTE of the entire interposer 100. For this reason, it is desirable for the remaining copper ratio in the first outer layer structure 5 and the second outer layer structure 11 to be 80% or less. More preferably, it is 50% or less, and even more preferably, it is 30% or less.

[0036] <Method for Evaluating Rigidity of Interposer> Next, a method for evaluating the rigidity of the interposer 100 will be described with reference to Fig. 22 and Fig. 23. Fig. 22 is a diagram for explaining an outline of a four-point bending test. Fig. 23 is a table showing standard values ​​for the test speed in the four-point bending test. The rigidity of the interposer 100 is evaluated based on the load and deflection when a test piece 101 obtained by processing the interposer 100 is subjected to a bending test.

[0037] There are two types of bending tests: a three-point bending test and a four-point bending test. In the three-point bending test, the bending force applied to the test piece is not uniform, and the test piece 101 bends and stretches on both the inside and outside of the bend. For this reason, in a laminate composed of multiple layers such as the interposer 100, the results obtained may vary depending on the arrangement of each material in the thickness direction. On the other hand, in the four-point bending test, the bending force applied to the test piece 101 is uniform, enabling highly accurate measurements.

[0038] The test conditions for the four-point bending test to evaluate the interposer 100 are as follows: Dimensions of the test piece 101: length 80 mm x width 15 mm x height h (thickness of the interposer 100) mm Distance between supporting points L: 66 mm Indenter radius r1: 2 mm Distance between indenters L': 22 mm Support radius r2: 2 mm Deflection velocity V: calculated by the following formula 1

[0039] If the interposer 100 does not have a specific shape and dimensions for use as a test piece, the interposer 100 is first processed to a specific size (80 mm length × 15 mm width × h mm height) for use as a test piece. If the interposer 100 has the specific dimensions specified by the test conditions, it may be used as the test piece 101 as is.

[0040] The test equipment used in the four-point bending test satisfies the test conditions specified as the distance between supports L, the indenter radius r1, the distance between indenters L', the support radius r2, and the test speed shown in Fig. 23. The test equipment used in the four-point bending test satisfies ISO 5893 and includes two cylindrical supports 61 and two cylindrical indenters 60.

[0041] The test speed V is calculated using equation (5). In the present invention, the strain rate is selected to be 0.01 [1 / min] (1% / min).

[0042] In the four-point bending test, a load F / 2 is applied to the indenter 60 to apply a load F to the vertical and horizontal surfaces of the test piece 101. Here, the load F is a load that causes the deflection speed of the test piece 101 to be equal to the test speed V. From the load F and the deflection amount obtained in the four-point bending test, the ratio of the load F to the deflection amount is calculated. The rigidity of the interposer can be evaluated from the ratio of the indenter load F to the deflection amount obtained at this time.

[0043] <Effects of Outer Layer Structure: Suppression of Cracks> Generally, there is a concern that cracks may occur in the inner layer structure 7 due to temperature changes, etc., resulting in defects that lead to disconnections in the wiring layer. In this regard, in the interposer 100 of this embodiment, the first outer layer structure 5 and the second outer layer structure 11 are formed over both entire surfaces of the inner layer structure 7, thereby improving the reliability of the inner layer structure 7, which has a fine wiring structure. Note that, if the first outer layer structure 5 and the second outer layer structure 11 are only partially formed on the upper and lower surfaces of the inner layer structure 7, it has been found that cracks may occur in the inner layer structure 7 due to deformation or stress concentration. For this reason, the first outer layer structure 5 and the second outer layer structure 11 need to be formed over the entire surfaces of both sides of the inner layer structure 7. Note that, in this embodiment, the physical properties and specific materials used of the first outer layer structure 5 and the second outer layer structure 11 are not particularly specified, but it is preferable that the CTEs of the first outer layer structure 5 and the second outer layer structure 11 are similar.

[0044] <Effect of Outer Layer Structure: Inspection> In an electrical testing device, the probe load is 0.05 N and the maximum deflection of the probe is 0.4 mm. Using this ratio, the threshold value of the indenter load / deflection ratio in the electrical testing is set to 0.125 N / mm. If the test piece exhibits a value above this, it can be determined that the test piece has sufficient rigidity. In this embodiment, if the indenter load / deflection ratio in the four-point bending test of the interposer 100 is set to 0.125 N / mm or more, the electrical testing of the interposer 100 can be performed satisfactorily. In other words, a needle-shaped electrode called a probe used in the electrical testing can be brought into contact with the electrode exposed on the outermost layer of the interposer 100, thereby ensuring sufficient electrical contact between the probe and the electrode. For example, if the thickness h of the test piece 101 is 300 μm, the test speed V is 30 mm / sec. In this case, when the load F indicates 5.7 N, the deflection is 7 mm, and the ratio of the load / deflection of the indenter is 0.814 N / mm, which satisfies the requirement.

[0045] 24 is an example of a diagram showing the relationship between the load / deflection ratio of the indenter in a four-point bending test of the interposer as the Y-axis and the thickness of the interposer as the X-axis, with the solid line indicating the relationship. Also shown in FIG. 24 is a dashed line indicating the threshold value of the load / deflection ratio of the probe in an electrical test, 0.125 N / mm. By setting the load / deflection ratio of the indenter in a four-point bending test of the interposer 100 to 0.125 N / mm or higher, the deflection of the probe can exceed the deformation of the interposer due to the deflection of the probe. Therefore, by satisfying this condition, sufficient electrical contact between the probe and the electrodes can be obtained, resulting in more reliable electrical testing.

[0046] 1(a) and 1(b) is composed of a first insulating resin layer 8, wiring 10, and vias 9 of the inner wiring layer that penetrate the first insulating resin layer 8. The thickness of the components of the inner wiring layer in this embodiment, the number of layers, wiring layer pattern, via shape, via taper direction, number of vias, etc. are not limited by this embodiment. The inner layer structure 7 may have a single inner wiring layer or multiple inner wiring layers, and the number and thickness of the layers are not limited by this embodiment, but in the interposer 100 according to this embodiment, when application to SiP is envisaged, it is preferable that the inner wiring layer be formed of multiple layers.

[0047] <Wiring Rules for Inner Wiring Layers> The wiring design rules for the wiring 10 in the inner wiring layer of the inner layer structure 7 shown in Figure 1(a) are preferably wiring design rules applicable to fine connections between chips. Preferably, L / S = 15 / 15 μm or less, more preferably 10 / 10 μm or less. Even more preferably, L / S = 8 / 8 μm or less. If L / S is 15 μm or more, it will be equivalent to the wiring rules for FC-BGA of the prior art, and will not be suitable for implementation such as HBM.

[0048] <Insulating Resin of Outer Layer Structure: Non-Photosensitive Resin> The second insulating resin layer 12, which is a component of the first outer layer structure 5 and the second outer layer structure 11 in Fig. 1(a) , can be a non-photosensitive insulating resin selected from epoxy-phenol resin, epoxy-phenol ester resin, epoxy-cyanate resin, cyanate resin, benzocyclobutene, polyimide, polybenzoxazole, etc. It may further contain a filler or glass cloth.

[0049] <Insulating Resin Layer of Inner Layer Structure: Photosensitive Resin> The material of first insulating resin layer 8, which is a component of inner layer structure 7 in Fig. 1(a), can be a photosensitive insulating resin, and known techniques such as benzocyclobutene, polyimide, polybenzoxazole, epoxy resin, epoxy acrylate, acrylate, etc. For example, since the formation of fine wiring with at least L / S = 8 / 8 µm or less is required, first insulating resin layer 8 may be a photosensitive insulating resin that is advantageous for forming fine wiring.

[0050] <Insulating Resin Layer of Inner Layer Structure: Non-Photosensitive Resin> The first insulating resin layer 8 may be made of a non-photosensitive insulating resin. For example, the first insulating resin layer 8 may be made of epoxy-phenol resin, epoxy-phenol ester resin, epoxy-cyanate resin, cyanate resin, benzocyclobutene, polyimide, or polybenzoxazole. The first insulating resin layer 8 may further contain a filler or glass cloth. This allows the first insulating resin layer 8 to impart high rigidity to the interposer.

[0051] <Advantages of Photosensitive Resin for the First Insulating Resin Layer of the Inner Layer Structure> When the first insulating resin layer 8 is a photosensitive insulating resin, micro vias with a diameter of 20 μm or less can be formed with a photolithographic positional accuracy of ±3 μm or less. This makes it possible to maximize the number of semiconductor devices mounted on the interposer, as well as the number of connection vias. Photosensitive insulating resin has the advantage that the via formation time does not depend on the number of vias, and they can be formed in one go. When a non-photosensitive insulating resin is used, vias are formed by laser processing or the like, but the positional accuracy is approximately ±10 μm, and the processing time increases as the number of vias increases.

[0052] <Thickness of the insulating resin layer of the inner wiring layer> The thickness of the first insulating resin layer 8 is preferably 25 μm or less. The thickness of the first insulating resin layer 8 here refers to the resin thickness between the copper wiring patterns on the upper and lower layers. If the thickness of the first insulating resin layer is 25 μm or more, it becomes difficult to form small diameter vias with a diameter of 20 μm or less, making it difficult to increase the wiring density. More preferably, the thickness of the first insulating resin layer is 15 μm or less. Even more preferably, it is 10 μm or less. The thickness of the first insulating resin layer 8 can be adjusted as appropriate depending on the applied wiring rules and circuit impedance matching.

[0053] <Via diameter of inner wiring layer> The diameter of the via 9 in the inner wiring layer is preferably 40 μm or less. The diameter of the via 9 here refers to the maximum diameter portion. If the diameter of the via 9 is 40 μm or more, it will hinder high-density wiring. A diameter of 30 μm or less is more preferable. A diameter of 20 μm or less is even more preferable, as it contributes to high-density wiring.

[0054] <Thickness of the Wiring Layer of the Inner Wiring Layer> The thickness of the wiring 10 is preferably 15 μm or less. More preferably, it is 10 μm or less. Even more preferably, it is 8 μm or less. If it is 15 μm or more, it becomes difficult to form fine wiring with an L / S of 15 / 15 μm or less, although this depends on the photoresist used. The thickness of the wiring layer is preferably adjusted appropriately depending on the wiring rules to be applied and the impedance matching of the circuit.

[0055] <Wiring Layer Material for Inner Wiring Layer> The material used for the wiring 10 may include elemental metals such as copper, aluminum, nickel, silver, gold, tungsten, iron, niobium, tantalum, titanium, and chromium, as well as alloys or additive elements thereof. It may also be a layered structure of these various materials. Alternatively, it may be a conductive paste containing these materials, or carbon, a conductive resin, or the like. For example, when forming a metal layer on the first insulating resin layer 8 by sputtering, it is common to form a single layer or an alloy layer of titanium, chromium, nickel, or the like, followed by copper. It is also preferable to form a layer by electroless copper plating or electroless nickel plating on the top surface of the first insulating resin layer 8. Electrolytic copper plating is generally used for the wiring 10, which is simple, inexpensive, and desirable.

[0056] <Interposer Thickness> In this embodiment, the thickness of the interposer 100 is preferably at least 50 μm or more. As shown in FIG. 3, if the thickness is thinner than 50 μm, the interposer 100 itself does not have sufficient rigidity, resulting in an extremely high incidence of defects in the subsequent external connection terminal formation process, electrical inspection process, and semiconductor device assembly process. According to the present invention, electrical inspection of the interposer alone is possible before the semiconductor device is mounted, so the yield after manufacturing and inspection of the interposer described in formula (4) can be calculated as follows: (Y INTERPOSER ) = 100% (4) Therefore, the SiP manufacturing yield (Y TOTAL ) can contribute to the improvement of

[0057] 4 to 6, a modification of the interposer of the first embodiment will be described. Fig. 4 shows a modification in which the first connection terminals 16 and the second connection terminals 17 are separated by a solder resist 21. The connection terminals may be separated by a solder resist.

[0058] 5 shows a modified example in which the first outer layer structure 5 is formed of multiple layers. The first outer layer structure 5 may be formed of a single layer or multiple layers. Whether it is a single layer or multiple layers can be adjusted appropriately depending on the rigidity required for the interposer. When the first outer layer structure 5 is formed of multiple layers, the interposer thickness becomes greater than 50 μm, which is preferable because it further increases rigidity.

[0059] FIG. 6 shows a modified example in which the second outer layer structure 11 is formed of multiple layers. The second outer layer structure 11 may be formed of a single layer or multiple layers. Whether it is a single layer or multiple layers can be adjusted appropriately depending on the rigidity required for the interposer. Furthermore, the modified examples shown in FIGS. 4 to 6 may be used in combination on the front and back. Furthermore, the conductive member 4 of the second insulating resin layer 6 may include wiring or pads. Furthermore, the second outer layer structure 11 may include wiring in addition to the pads 15 of the second insulating resin layer 12, and these modified examples are also included within the scope of the present invention. Furthermore, the solder connection interfaces of the first connection terminals 16 and the second connection terminals 17 may be subjected to appropriate surface treatment. The type and thickness of the surface treatment are not particularly limited.

[0060] (Outline of Manufacturing Process) The interposer manufacturing method of the present invention generally comprises the following steps. First, a support substrate is prepared, and then the interposer can be obtained by the following steps: 1) a first step of forming a first outer layer structure on the support substrate; 2) a second step of forming an inner layer structure above the first outer layer structure; 3) a third step of forming a second outer layer structure above the inner layer structure; 4) a fourth step of peeling the first outer layer structure from the support substrate; and a fifth step of forming connection terminals on the outermost layers of the first outer layer structure and the second outer layer structure.

[0061] Once the formation of the first and second outer layer structures is complete, the interposer alone can ensure sufficient rigidity even without a support substrate. Therefore, in subsequent processes, the interposer or semiconductor package can be manufactured by peeling it off from the support substrate. Because there is no support substrate, the connection terminals exposed on both sides of the substrate can be subjected to surface treatment, solder bump formation, and protruding electrode formation. In this way, the first and second connection terminals can be formed on both sides of the interposer.

[0062] (Detailed Description of Manufacturing Method) Hereinafter, the manufacturing method of the interposer and the semiconductor package will be described in detail with reference to FIGS.

[0063] <Support Substrate Preparation Step> As shown in FIG. 7( a), first, a support substrate 1 is prepared. The support substrate 1 may be, for example, a glass substrate having a laser release layer provided thereon and a metal layer 2 provided on the laser release layer. The metal layer 2 may be formed by electroless plating or sputtering. Alternatively, a support substrate may be used in which a carrier copper foil is formed as the metal layer 2 on a CCL (copper clad laminate) substrate via a prepreg. Here, the carrier copper foil has a three-layer structure of carrier copper foil-release layer-ultrathin copper foil, and is a copper foil that can be easily physically peeled off at the release layer interface. The type of support substrate is not limited to those described above, and various known substrates may be used.

[0064] 7(b) shows a substrate on which a resist layer is formed on the metal layer 2 and then patterned to form a resist pattern 3. The thickness of the resist is determined appropriately in consideration of the height of the pads to be formed. In the example of the present invention, a liquid resist was applied at a thickness of 70 μm, and a pattern was formed so that cylindrical pads with a diameter of 25 μm and a pitch of 55 μm could be formed as pads for the first connection terminals.

[0065] FIG. 7(c) shows the conductive member 4 formed by electrolytic copper plating after the process of FIG. 7(b). The resist was then removed. The cylindrical conductive member 4 functions as a pad. In this embodiment, the conductive member 4 was formed by copper plating to an average height of 65 μm in the Z direction. Before forming the first insulating resin layer 8 (non-photosensitive resin) that constitutes the first outer layer structure 5 in the next process, known copper roughening treatment (CZ treatment) or silane coupling treatment after displacement tin plating may be appropriately performed to improve adhesion between the copper pattern and the non-photosensitive insulating resin.

[0066] 7( d ) is a diagram showing the non-photosensitive insulating resin that will become the first outer layer structure 5. The second insulating resin layer 6 made of a non-photosensitive resin in this embodiment is a non-photosensitive resin that contains at least a filler, and is desirably selected from prepreg, built-up resin, and molded resin, each having an elastic modulus of 5 GPa or more and a CTE of 20 ppm or less. In this embodiment, the second insulating resin layer 6 was formed by vacuum lamination using a 70 μm-thick film-like molded resin. The type, thickness, and forming method of the non-photosensitive resin are not limited to those in this embodiment, and appropriate materials and forming methods can be selected.

[0067] 7( e) shows the second insulating resin layer 6 being ground with a grinder to expose the conductive members 4 that will become the pads of the first outer layer structure 5. The method for exposing the pads is not limited to the method of this embodiment, and may be known methods such as grinding with a grinder, buffing, belt polishing, fly-cutting, and CMP. As a result, in this embodiment, the conductive members 4 that will become the pads are formed in the second insulating resin layer 6 of the first outer layer structure 5. In this embodiment, the first outer layer structure 5 was formed to a thickness of 60 μm.

[0068] 8(f) shows the first insulating resin layer 8 of the inner layer structure 7 formed above the first outer layer structure 5, and the vias 9 formed therein. In this embodiment, the first insulating resin layer 8 is formed using a photosensitive insulating resin to a thickness of 6 μm, and the vias 9 have a diameter of 15 μm.

[0069] When a non-photosensitive resin is used for the first insulating resin layer 8, the vias 9 can be formed by laser processing. The laser processing can be performed by a general laser processing, for example, a CO ２ A laser or a UV laser can be used. After the laser processing, a desmearing process may be performed as appropriate. This allows removal of residues left after the laser processing. In this embodiment, the first insulating resin layer 8 is formed to a thickness of 10 μm, and vias 9 with a diameter of 15 μm are formed.

[0070] 8( g ) shows a result of forming a seed metal layer (not shown) on the first insulating resin layer 8, forming a resist pattern 3, and then forming vias 9 and wiring 10 of the inner wiring layer by electrolytic plating. In this embodiment, the seed metal layer was formed by sputtering Ti / Cu=50 / 300 nm, and the resist thickness was 5 μm. As a result, a resist pattern 3 with an L / S=2 / 2 μm was formed, and then wiring 10 with a thickness of 2.3 μm (6 μm + 2.3 μm including the vias) was formed by electrolytic plating.

[0071] In this embodiment, when a non-photosensitive insulating resin is used for the first insulating resin layer 8, electroless copper plating is formed to a thickness of 0.8 μm as a seed metal layer, and a resist is formed to a thickness of 10 μm, as in FIG. 8( g). In this way, a resist pattern 3 with an L / S=5 / 5 μm is formed, and then wiring 10 with a thickness of 5 μm (10 μm + 5 μm when vias are included) is formed using electrolytic plating.

[0072] 8(h) shows a diagram in which the seed metal layer is removed after the resist pattern 3 has been peeled off, and an inner wiring layer consisting of a first insulating resin layer 8, vias 9, and wiring 10 has been formed. Note that the method for forming the wiring and the method for forming the insulating resin layer are not limited to the methods of this embodiment, and any appropriate forming method can be selected.

[0073] Figure 8(i) shows an inner layer structure 7 in which four layers of wiring 10 and first insulating resin layer 8 are laminated, each formed by repeating the steps shown in Figures 8(f) to 8(h) three more times. The thickness of each first insulating resin layer 8 is 6 μm, the thickness of each wiring 10 is 2 μm, and the thickness of the outermost wiring 10 is 12 μm. This is to prevent the wiring from penetrating when via holes are drilled with a laser in the second insulating resin layer 12 of the outer wiring layer. As a result, the thickness of the inner layer structure 7 is 36 μm.

[0074] Even when a non-photosensitive insulating resin is used for the first insulating resin layer 8 of the inner layer structure 7, the steps shown in Figures 8(f) to 8(h) can be repeated three more times, as in Figure 8(i), to obtain a four-layer laminate of wiring 10 and first insulating resin layer 8. In this case, the thickness of each first insulating resin layer 8 is 10 μm, the thickness of each wiring 10 is 5 μm, and as described above, the thickness of the outermost wiring 10 is 12 μm. As a result, the thickness of the inner layer structure 7 is 52 μm.

[0075] FIG. 8( j) is a diagram illustrating the process of forming the second outer layer structure 11. First, a prepreg and a carrier-attached copper foil that will become the second insulating resin layer 12 of the second outer layer structure 11 are formed above the inner layer structure 7 by lamination press. In this example, a carrier foil with a carrier thickness of 18 μm and a copper foil with a carrier thickness of 3 μm on the thin foil side were used, and a 3 μm thin copper foil 13 was placed on the prepreg side. A prepreg with a thickness of 70 μm was used. Note that the processes from FIG. 8( j) onwards are the same as when a photosensitive insulating resin and a non-photosensitive insulating resin are used for the first insulating resin layer 8.

[0076] FIG. 9(k) shows the carrier foil removed from the carrier-attached copper foil. ２ The figure shows vias 14 formed in the second outer layer structure 11 using a laser. After this, the laser openings were subjected to a desmearing process, and further electroless copper plating of 0.6 μm in thickness was formed in the via portions by electroless copper plating (not shown). In this embodiment, vias with a diameter of 60 μm were formed at a pitch of 150 μm.

[0077] 9(l) shows pads 15 formed by electrolytic copper plating after forming the resist pattern 3. In this example, the surface layer of the pad 15 was formed with an 18 μm thick electrolytic copper plating layer. That is, the surface layer thickness of the pad 15 (excluding the vias) is 18 μm, and the thickness including the vias is (via depth 70 μm + 18 μm).

[0078] 9( m) is a diagram showing the second outer layer structure 11 formed by removing the resist pattern 3 and then etching away the thin copper foil 13 and the electroless copper plating layer. In this embodiment, pads 15 having a diameter of 75 μm and a pad thickness of 15 μm are formed at a pitch of 150 μm on the second outer layer structure.

[0079] FIG. 9( n ) is a diagram showing the inverted view of FIG. 9( m ) and illustrates the process of removing the support substrate 1. After providing a protective sheet (not shown) on the surface of the second external layer structure 11, the metal layer 2 is etched away, and the protective sheet of the second external layer structure 11 is further removed (not shown), thereby obtaining an interposer 100 in which the conductive member 4 and the pads 15 are exposed on the first external layer structure 5. According to this embodiment, in the process from FIG. 9( n ) onward, the first external layer structure 5 and the second external layer structure 11, each made of a high-elasticity, low-CTE material, are formed on both sides of the inner layer structure 7, resulting in an interposer 100 having a total thickness of 50 μm or more. The interposer thus formed has sufficient rigidity to be transported as a standalone interposer. Furthermore, since the support has been removed from the interposer, both sides of the interposer are exposed, allowing the formation of first connection terminals 16 and second connection terminals 17 on the front and back of the interposer.

[0080] FIG. 10(o) shows a process for performing surface treatment on the conductive members 4 (pads) serving as the external connection terminals of the first external layer structure 5 and the pads 15 serving as the external connection terminals of the second external layer structure 11. The type and thickness of these surface treatments can be determined by any known method. After the surface treatment, solder can be formed on both pad layers. This solder formation method can also be performed by any known method, such as screen printing, ball mounting, electroplating, or filling with molten solder after forming a resist pattern. In this embodiment, electroless Ni / Pd / Au was applied to both surfaces as the surface treatment, and the solder was formed using a front-back ball mounting method. In this manner, the interposer 100 of this embodiment can be obtained, in which the first connection terminals 16 and the second connection terminals 17 are formed on the first external layer structure 5 and the second external layer structure 11.

[0081] FIG. 10( p ) shows a process of simultaneously contacting the first connection terminals 16 and the second connection terminals 17 on both sides of the interposer 100 with an electrical inspection probe to perform an electrical inspection of the interposer 100 .

[0082] Specific electrical tests and manufacturing procedures utilizing the results thereof are as follows: 1) a first inspection process in which an electrical test is performed on the interposer from the connection terminals, 2) a first determination process in which the quality of the interposer is determined based on the results of the first inspection process, 3) a temporary connection process in which a semiconductor device is mounted on an interposer determined to be "good" in the first determination process, 4) a second inspection process in which an electrical test is performed on the semiconductor package temporarily connected in the temporary connection process, 5) a second determination process in which the quality of the semiconductor package is determined to be "bad" based on the results of the second inspection process, 6) a repair process in which the mounting of a semiconductor device determined to be "bad" in the second determination process is repaired and / or replaced.

[0083] In addition to the above manufacturing procedure, the following steps may be performed: 7) a third inspection step of conducting an electrical inspection on the semiconductor package after the repair step, 8) a third determination step of determining whether the semiconductor package is good or bad based on the results of the third inspection step, and 9) a fixing step of supplying underfill to the gap between the semiconductor device and the interposer of the semiconductor package determined to be "good" in the third determination step.

[0084] Regarding the physical requirements for conducting electrical testing (e.g., the degree of rigidity), it is possible to determine the physical characteristic value from the relationship between the load (N) in a four-point bending test and the corresponding deflection (mm: Z-direction displacement of the bending apex). It is also possible to determine the physical characteristic value from the elastic modulus of bending deformation (Δstress / Δstrain: stress per unit strain) according to JIS 7017 and other standards.

[0085] As described above, the interposer 100 according to the present embodiment has sufficient rigidity to be transported as a single interposer, and since the first connection terminals 16 and the second connection terminals 17 are exposed on both sides of the interposer, an electrical test can be performed on the interposer 100 itself before mounting a semiconductor device thereon, and the quality of the interposer can be determined. Therefore, only interposers that are determined to be non-defective can be provided to the subsequent semiconductor package manufacturing process, which can contribute to improving the SiP assembly yield.

[0086] 10(q) is a diagram showing a process of dicing a panel substrate having a plurality of interposers continuously formed in a grid pattern at the A-A portion to separate the substrate into individual interposers, thereby manufacturing the interposer 100 according to the present embodiment.

[0087] (Modification of First Embodiment) Next, a manufacturing process according to a modification of the first embodiment will be described with reference to Figures 11(a) to 11(e). Figure 11(a) is similar to Figure 7(a) and shows the support substrate 1, for example, in a state in which a laser peeling layer is provided on a glass substrate and a metal layer 2 is provided on the laser peeling layer. The metal layer 2 may be formed by electroless plating or sputtering, or a carrier copper foil may be formed as the metal layer 2 on a CCL (copper clad laminate) substrate via a prepreg. Next, in Figure 11(b), a second insulating resin layer 6, which will become the first outer layer structure 5, is formed on the support substrate 1.

[0088] Thereafter, as shown in FIG. 11( c), vias for forming pads of the first outer layer structure 5 are formed by laser processing. After the vias are formed, desmearing or other processes may be performed as appropriate. Thereafter, as shown in FIG. 11( d), a metal layer (not shown) is formed on the entire surface, including the inside of the vias, to form a resist pattern 3. Then, electrolytic plating is performed to fill the vias with metal and form conductive members 4. Next, as shown in FIG. 11( e), the photoresist is removed, and the exposed unnecessary metal layer is etched away to obtain the first outer layer structure 5. Note that, although a first outer layer structure consisting of a single layer has been described in this modification, a first outer layer structure consisting of multiple layers, as shown in FIG. 5, can also be formed using the method of this modification.

[0089] (Method of Assembling Semiconductor Device) Next, with reference to FIG. 12, a method of manufacturing a semiconductor package by mounting a semiconductor device on the interposer of this embodiment will be described.

[0090] 12A is a schematic cross-sectional view of a process for manufacturing a semiconductor package by mounting semiconductor devices 50 and 51 on an interposer. The interposer used in this embodiment has undergone an electrical test as a stand-alone interposer and has been confirmed to be a non-defective product.

[0091] The semiconductor device can be mounted using known mounting techniques such as mass reflow and thermo-compression bonding (TCB). Using TCB reduces the risk of misalignment during mounting or reflow of multiple semiconductor devices, or CTE mismatch due to high-temperature heating of the interposer. Furthermore, the underfill process in this embodiment preferably uses capillary underfill rather than NCF (non-conductive film) or NCP (non-conductive paste). This is because capillary underfill makes it easy to replace a defective semiconductor device if a defect is found in the semiconductor device during subsequent electrical testing.

[0092] Next, FIG. 12B is a diagram showing an electrical test of the SiP as a semiconductor package in this embodiment. By bringing the test probe 18 into contact with the second connection terminal 17 to perform an electrical test, the "mounting yield (Y )" including the individually mounted semiconductor devices can be calculated. ASSEMBRY ) can be inspected, and mounting defects or defects in the semiconductor device can be identified.

[0093] 12C is a schematic cross-sectional view showing the process of partially removing a semiconductor device 52 with a mounting defect or defect identified in the previous process and replacing it with a non-defective semiconductor device 53. In this embodiment, the mounted semiconductor device is not fixed with a mold resin or underfill, so it is possible to partially repair the mounting defect or the defective semiconductor device. After the repair, (Y ASSEMBRY ) = 100%. Therefore, according to the interposer of this embodiment, the total SiP assembly yield (Y TOTAL ) can be improved. The modification can be performed by performing the reverse process of the TCB implementation.

[0094] 13D is a diagram showing a capillary underfill process in which underfill 19 is formed on a semiconductor package 150 according to this embodiment, on which a plurality of semiconductor devices are mounted, using an underfill supply device 54. After inspection and repair, the semiconductor devices can be fixed to the interposer according to this embodiment using the underfill 19.

[0095] 13(e) is a schematic cross-sectional view showing a state in which a molding resin 20 is further formed on the semiconductor device. This is not an essential step in the fixing process using the molding resin. Fixing using the molding resin can be performed using any suitable known method. Furthermore, the upper surface of the molding resin 20 may be polished to expose the upper end of the semiconductor device.

[0096] As described above, a semiconductor package 150 on which a semiconductor device is mounted can be produced through the steps shown in FIG. 12(a) to FIG. 13(d) or (e). According to this embodiment, the interposer exists independently, and therefore the following advantages are obtained. 1) (Y INTERPOSER ) = 100% inspection-guaranteed interposers can be used in the mounting process. ASSEMBRY ) can approach 100%. This makes it possible to improve the overall yield of SiP assembly. 2) Because the FC-BGA and interposer 100 are independent, it is possible to mount a semiconductor device on the interposer, create a semiconductor package, and then mount it on the FC-BGA or motherboard. Alternatively, it is possible to mount the interposer on the FC-BGA or motherboard and then mount the semiconductor device, thereby improving the flexibility of the manufacturing process. 3) Regarding the CTE of each component, the interposer can be set to an intermediate value between the semiconductor device and the FC-BGA substrate. Therefore, by first assembling the semiconductor device and interposer and then mounting it on the BGA, it is possible to mediate the CTE matching between the semiconductor device and the FC-BGA, contributing to improved connection reliability. 4) It is also possible to appropriately select a form of connection directly to the motherboard without using the FC-BGA.

[0097] Second Embodiment Next, a second embodiment will be described with reference to Fig. 14. Fig. 14 is a schematic cross-sectional view of an interposer 100 according to the second embodiment. The second embodiment differs from the first embodiment in that the formation area of ​​the inner layer structure 7 is smaller than the first outer layer structure 5 and the second outer layer structure 11, and the inner layer structure 7 is not exposed on the side surface of the interposer. In other words, in the interposer 100 of the second embodiment, the side surface of the inner layer wiring layer is encompassed by the second outer layer structure 11.

[0098] (Manufacturing Method of Second Embodiment) Next, a manufacturing method of the second embodiment will be described with reference to FIG. 15. In the following description, components that are the same as or equivalent to those in the first embodiment described above will be given the same reference numerals, and their description will be simplified or omitted, with only the differences from the first embodiment being described. The first half of the manufacturing method of the second embodiment can be produced using the same steps as those in FIGS. 7(a) to 7(e) that describe the manufacturing method of the first embodiment. Hereinafter, the interposer, semiconductor package, and manufacturing method thereof of the second embodiment will be described with reference to FIGS. 15(f) to 15(q) to focus on the differences from the first embodiment.

[0099] 15(f) is a process corresponding to FIG. 7(f). In the second embodiment, after the first insulating resin layer 8 of the inner layer structure 7 is formed on the first outer layer structure 5, the first insulating resin layer 8 on the side surface 30 of the interposer is removed while the via 10 is being formed. If the first insulating resin layer 8 is a non-photosensitive insulating resin, the side surface 30 of the interposer can be removed by laser ablation simultaneously with the formation of the via 10. If the first insulating resin layer 8 is a photosensitive insulating resin, the side surface 30 can be easily removed by development and removal using photolithography.

[0100] FIG. 15(i) is a process schematic diagram after the formation of the inner wiring layer is repeated three times, and corresponds to FIG. 8(i). When the first insulating resin layer 8 is a non-photosensitive insulating resin, the first insulating resin layer 8 on the side surface 30 may be removed collectively using laser ablation after forming multiple inner wiring layers. Alternatively, the insulating resin edge may be removed by half dicing. Furthermore, the first insulating resin layer 8 may be removed by dry etching after forming a resist, or the resin may be dissolved and removed by wet etching. The method for removing the first insulating resin layer 8 on the side surface 30 is not limited to the method described in this embodiment, and any known removal method may be used as appropriate.

[0101] Figure 15(j) is a diagram illustrating a process corresponding to Figure 8(j). First, a prepreg and a carrier-attached copper foil that will become the second insulating resin layer 12 of the second outer layer structure 11 are formed above the inner layer structure 7 by lamination press. In this second embodiment, the side surface 30 of the inner layer structure 7 is covered with the second insulating resin layer 12. Figure 15(j-2) is a schematic diagram showing a three-dimensional view of the structure shown in Figure 15(j). The inner layer structure 7 is formed with an area smaller than the first outer layer structure 5, and the second outer layer structure 11 is formed on its upper surface.

[0102] 15(q) is a diagram illustrating a process corresponding to FIG. 10(q). In the second embodiment, dicing is performed at the A-A portion in FIG. 15(q), so that the inner wiring layer is not exposed on the side surface 30 of the interposer 100, and the interposer 100 can be covered with the second insulating resin layer 6.

[0103] (Effects of the Second Embodiment) This makes it possible to protect the side surfaces of the inner layer structure, and more sufficiently ensures the rigidity of the interposer 100. Furthermore, because the inner structure is covered on all sides by the second insulating resin layer 12, it has higher resistance to stress distortion caused by differences in CTE. More specifically, the first outer layer structure and the second outer layer structure use a highly elastic and low CTE material with an elastic modulus of 5 GPa or less and a CTE of 20 ppm / °C or less, which can protect and reinforce the side surfaces of the inner wiring layers. In particular, this has the effect of suppressing cracks and delamination on the side surfaces 30 of the inner layer structure 7 due to thermal cycle stress.

[0104] (Third Embodiment) Next, a third embodiment will be described with reference to Fig. 16. Fig. 16(a) is a schematic cross-sectional view of an interposer 100 according to a third embodiment of the present invention. The third embodiment differs from the first embodiment in that the first outer layer structure 5 and the second outer layer structure 11 are provided with protruding electrodes.

[0105] An interposer, a semiconductor package, and a manufacturing method thereof according to a third embodiment will now be described with reference to FIG. 16 . In the third embodiment, protruding electrodes 22 are formed above the first outer layer structure 5, i.e., above the conductive member penetrating the first insulating resin layer, or protruding electrodes 23 are formed below the second outer layer structure, i.e., below the conductive member penetrating the second insulating resin layer. By forming solder on the protruding electrodes 22 formed above the first outer layer structure, external connection terminals of different heights can be formed within the first and second connection terminals. In the third embodiment, by forming the first outer layer structure 5 and the second outer layer structure 11 on both sides of the inner layer structure 7, the interposer can be transported independently during the manufacturing process, even after being separated from the support substrate. Furthermore, since there is no support substrate, protruding electrodes can be formed on both sides of the interposer. The protruding electrodes 22 and 23 can be formed using electrode formation methods known in the art.

[0106] 16(b) shows an example of a semiconductor package according to the third embodiment, in which semiconductor devices 50 and 51 are connected and mounted on both sides of an interposer 100. By forming external connection terminals of different heights, it becomes possible to mount the semiconductor device 50 or 51 on both sides of the interposer, thereby improving the degree of freedom in mounting the semiconductor device. Needless to say, an underfill 19 or molded resin 20 may be formed on each of the semiconductor devices 50 and 51. The method or structure for forming the underfill 19 or molded resin 20 on the semiconductor device can be appropriately adopted from known mounting techniques.

[0107] (Manufacturing Method of Third Embodiment) Next, a manufacturing method of the third embodiment will be described with reference to FIG. 17. In the following description, components that are the same as or equivalent to those in the first embodiment described above will be given the same reference numerals, and their description will be simplified or omitted, with only the differences from the first embodiment being described. The first half of the manufacturing method of the third embodiment can be produced using the same steps as those in FIGS. 7(a) to 9(l) that describe the manufacturing method of the first embodiment. Hereinafter, the interposer, semiconductor package, and manufacturing method thereof of the third embodiment will be described with reference to FIGS. 17(l) to 21, focusing on the differences from the first embodiment.

[0108] FIG. 17(l) corresponds to FIG. 8(l) of the first embodiment, and up to this step, the manufacturing method can be the same as that of the first embodiment.

[0109] The process shown in Fig. 17(m) is a cross-sectional view of the interposer 100 from which the resist 3 and the support substrate 1 shown in Fig. 17(l) have been removed. For convenience, Fig. 17(m) is shown upside down compared to Fig. 17(l). In Fig. 17(m), the metal layer 2 and the thin copper foil 13 of the carrier copper foil are formed on the first outer layer structure 5 and the second outer layer structure 11, respectively.

[0110] Next, FIG. 17( n ) is a diagram illustrating the process of forming the first connection terminal 16 and the second connection terminal 17. Following FIG. 17( m ), a resist pattern 3 is formed on both sides of the metal layer 2 and the thin copper foil 13 of the carrier copper foil, followed by electrolytic Ni plating and electrolytic Sn—Ag plating for solder, thereby forming the first connection terminal 16 and the second connection terminal 17. If the thickness and volume of the first connection terminal 16 and the second connection terminal 17 are to be different on the first external layer structure side and the second external layer structure side, the current values ​​passed through the respective seed layers in the electrolytic plating process can be changed to form them into any desired shape. Alternatively, in the process of FIG. 17( m ), a protective layer may be formed on one side and a resist 3 may be formed on the other side, thereby forming the external connection terminals on one side at a time. Furthermore, after forming resist patterns on both sides, a protective sheet may be formed on one side, and then electrolytic plating may be performed on one side at a time. The electrolytic plating method and resist pattern formation method can be selected from known pattern formation methods as appropriate and are not limited to the above methods. After this step, the solder layer may be heated in a reflow furnace to form round bumps.

[0111] FIG. 18(o) is a diagram illustrating the process of forming the protruding electrodes 22 and 23. After the process of FIG. 17(n), the resist pattern is peeled off, and a new resist pattern 3 is formed. Then, electrolytic copper plating, electrolytic Ni plating, and electrolytic Sn—Ag plating are performed to form the protruding electrodes 22 and 23. If the thickness and volume of the first connection terminal 16 and the protruding electrodes 22, and the second connection terminal 17 and the protruding electrodes 23 are to be different between the first outer layer structure side and the second outer layer structure side, the current values ​​passed through the respective seed layers in the electrolytic plating process can be changed to form any desired shape. If the thickness and volume differ significantly, they can also be formed by forming resist patterns on both sides, forming a protective sheet on one side, and then electrolytic plating one side at a time. The electrolytic plating method and resist pattern formation method can be selected from known pattern formation methods as appropriate and are not limited to the above methods. Furthermore, after this process, the solder layer may be heated in a reflow furnace to form round bumps.

[0112] Fig. 18(p) is a diagram showing an interposer 100 according to the third embodiment. After peeling off the resist 3 from the substrate shown in Fig. 18(o), the metal layer 2 and the thin copper foil layer of the carrier copper foil are removed by etching. The solder layer is then heated in a reflow furnace to form round bumps, thereby obtaining the interposer 100 according to the third embodiment.

[0113] (Effects of the third embodiment) According to the interposer of the third embodiment, as will be described later in the fourth embodiment, it is possible to utilize the step created by the protruding electrodes to stack and mount a semiconductor device above the first outer layer structure 5, thereby further improving the integration rate of the SiP.

[0114] (Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIG. 19 . The fourth embodiment is a semiconductor package in which a semiconductor device is mounted on the interposer of the third embodiment. The fourth embodiment differs from the first embodiment in that the protruding electrodes in the third embodiment are used to enable semiconductor devices to be stacked and mounted above the first outer layer structure 5 and below the second outer layer structure 11. Furthermore, in the fourth embodiment, it is also possible to stack interposers 100 on top of each other using the protruding electrodes, which also differs from the first embodiment in this respect.

[0115] Fig. 19(a) shows a fourth embodiment of the interposer according to the present invention, which differs from the third embodiment in that the first and second connection terminals 16 and 17 are not formed on the protruding electrodes 22 and 23 by electrolytic Ni and electrolytic Sn-Ag plating, as described in Fig. 18(o) of the third embodiment.

[0116] FIG. 19B shows a process after semiconductor devices 50 and 51 are mounted on the first connection terminals 16 and second connection terminals 17 on which no protruding electrodes are formed in the interposer 100 of the fourth embodiment.

[0117] 20(c) shows the semiconductor package of this embodiment after molding resin has been formed on both sides of the interposer on which the semiconductor device of FIG. 19(b) is mounted. And FIG. 20(d) shows the semiconductor package shown in FIG. 20(c) after the molding resin formed on the outermost surface of the semiconductor package has been ground away to expose the surfaces of the protruding electrodes 22 and 23 and the semiconductor devices 50 and 51.

[0118] A surface treatment is performed on the exposed protruding electrodes 22 and 23 to form the first connection terminal 16 and the second connection terminal 17. Thereafter, Ni / Pd / Au treatment is performed on the first connection terminal 16 and the second connection terminal 17 as a surface treatment, and solder balls are mounted on each side and reflowed to complete the first connection terminal 16 and the second connection terminal 17. Note that known treatment methods can be appropriately adopted for the type and method of surface treatment, the solder composition and type, and the solder formation method.

[0119] 21 is a diagram showing an example of a semiconductor package in which multiple semiconductor packages are stacked. In the process of FIG. 21, a semiconductor package is shown in which the semiconductor package (upper layer) shown in FIG. 16(b) of the third embodiment is stacked on the semiconductor package (lower layer) shown in FIG. 20(d). Furthermore, such interposer stacking and semiconductor device stacking are not limited to the above-described combinations. It goes without saying that any number of stacked layers can be configured within the physically possible range, and the types of semiconductor devices and interposers to be combined can also be selected arbitrarily. As described above, an interposer stacking structure is also possible using the interposer of this embodiment, which can contribute to the high functionality of semiconductor packages using advanced SiP.

[0120] (Advantages of the Fourth Embodiment) By utilizing an interposer that can be independently transported through manufacturing processes without a support as described above, it is possible to form protruding electrodes on both sides of the interposer, and these protruding electrodes can be used to provide connection terminals with steps on both sides of the interposer. As a result, it is possible to mount multiple semiconductor devices on both sides of the interposer, and it is also possible to connect these interposers to each other, making it possible to significantly improve the integration and high functionality of SiP.

[0121] Fifth Embodiment Next, a fifth embodiment will be described with reference to Fig. 25. Fig. 25(a) is a schematic cross-sectional view of an interposer 100 according to the fifth embodiment, in which an internal component 70 is embedded. Fig. 25(b) is a schematic cross-sectional view of a semiconductor package 150 in which semiconductor devices 50 and 51 are mounted on the interposer 100 according to the fifth embodiment. The fifth embodiment differs from the first embodiment in that an internal component 70 is embedded.

[0122] The built-in component 70 may be electrically connected to the first connection terminal 16 on the upper surface. Alternatively, if there is an built-in component connection terminal (not shown) on the lower surface of the built-in component 70, it may be electrically connected to the first connection terminal 16 or the second connection terminal 17 via the via 9 and wiring 10 of the inner layer structure 7. Alternatively, if there are connection terminals on both the upper and lower surfaces of the built-in component 70, it may be electrically connected to both connection terminals at the same time.

[0123] The size of the embedded components 70 is preferably at least smaller than the area of ​​the interposer 100 and is preferably a size that does not restrict the mounting of the semiconductor device or the routing of wiring, but is not limited by this embodiment. The number of embedded components 70 is preferably such that it does not restrict the mounting of the semiconductor device or the routing of wiring, but is not limited by this embodiment.

[0124] The thickness of the built-in component 70 is preferably thinner than that of the interposer 100, at least when the built-in component 70 is built into the interposer 100. It is desirable that the thickness does not restrict the mounting of the semiconductor device or the routing of wiring, but this is not limited to this embodiment. For example, the thickness of the built-in component 70 is preferably 10 μm or more and 1 mm or less.

[0125] If the thickness of the built-in component 70 is thinner than 10 μm, not only will the interposer itself not be able to exhibit sufficient rigidity, but the built-in component may be damaged, even if a highly rigid material, as described below, is used. If the thickness of the built-in component 70 is thicker than 1 mm, the thickness of the interposer itself must be increased, which not only increases manufacturing time and cost, but also makes it difficult to incorporate the built-in component inside the interposer.

[0126] The embedded components 70 can be selected from silicon, ceramic, glass, and compound semiconductor based components.

[0127] Here, silicon-based components include, for example, capacitors, inductors, chip components with rewiring functions, and semiconductor chips with computing functions formed on a silicon wafer. Furthermore, silicon-based components may also be functional modules that include one or more of these elements.

[0128] The ceramic-based component may be a component having a standalone function such as a capacitor, inductor, or wiring, or may be a functional module containing one or more of these elements.

[0129] The ceramic material may be, for example, alumina, yttria, cordierite, cermet, sapphire, zirconia, steatite, forsterite, silicon carbide, aluminum nitride, silicon nitride, or LTCC (Low Temperature Co-fired Ceramics), but other materials may also be used.

[0130] The glass-based component may be, for example, a component having a single function such as a capacitor, inductor, or wiring. Furthermore, the glass-based component may be a functional module containing one or more of these elements. Examples of glass materials include soda-lime glass, borosilicate glass, crystallized glass, and quartz glass, but other materials may also be used.

[0131] Furthermore, components based on compound semiconductors include, for example, high-frequency devices and optical semiconductors containing compound semiconductors such as GaAs, InP, and InGaAlP, LEDs and laser diodes containing InGaN, and power semiconductor materials containing SiC and GaN, but may also be made of other materials.

[0132] As shown in Table 1, typical insulating resin materials have a linear thermal expansion coefficient (CTE) of 30 to 100 ppm / K and a modulus of elasticity of 1 to 30 GPa. On the other hand, silicon, ceramic, glass, and compound semiconductor materials have a CTE of 12 ppm / K or less and a modulus of elasticity of 60 to 470 GPa, which are lower in thermal expansion and higher in elasticity than insulating resin materials. As a result, by incorporating components into the interposer 100, it is possible to simultaneously impart high thermal dimensional stability and rigidity to the interposer 100. Here, thermal dimensional stability refers to the property of the interposer being less susceptible to thermal deformation due to thermal cycling.

[0133] (Manufacturing Method of Fifth Embodiment) Next, a manufacturing method of the interposer 100 shown in Fig. 25(a), which is the fifth embodiment, will be described with reference to Fig. 26. In the following description, components that are the same as or equivalent to those in the first embodiment, etc. described above, are given the same reference numerals, and their description will be simplified or omitted, with only the differences from the first embodiment, etc. being described.

[0134] Fig. 26(a) shows a process corresponding to Fig. 7(a) of the first embodiment. In the fifth embodiment, first, a support substrate is prepared as shown in Fig. 26(a). The support substrate can be the same as that described in the first embodiment.

[0135] 26(b) is a diagram showing the process of forming a resist pattern 3 in areas other than the area where the embedded component 70 is to be mounted. As shown in Fig. 26(b), a resist pattern 3 is formed in areas other than the area where the embedded component 70 is to be mounted. In this example, a liquid resist is formed to a thickness of 120 µm, and openings are formed so that cylindrical pads can be formed with the same pitch and diameter as in the first embodiment.

[0136] 26( c) shows a state in which a conductive member 4 is formed to an average thickness of 120 μm by electrolytic copper plating, the resist pattern 3 is removed, and an embedded component 70 is then mounted. In this embodiment, a silicon capacitor is mounted as the embedded component 70. The silicon capacitor has, for example, a total thickness of 120 μm and a size of 5 mm×5 mm. In this embodiment, the silicon capacitor is fixed to the support substrate via an adhesive, but it may be fixed by other methods.

[0137] Fig. 26(d) is a process corresponding to Fig. 7(d). Fig. 26(d) is a diagram showing a process of forming the second insulating resin layer 6, which becomes the first outer layer structure 5, by vacuum lamination using a film-shaped molding resin with a thickness of 150 µm. In this embodiment, the second insulating resin layer 6 is formed by vacuum lamination using a film-shaped molding resin with a thickness of 150 µm.

[0138] FIG. 26( e) illustrates a process of polishing the molding resin and the Si substrate of the silicon capacitor using a grinder to expose a portion of the built-in component 70 and the conductive member 4. In the process of FIG. 26( e), the molding resin and the Si substrate of the silicon capacitor are polished using a grinder to expose a portion of the built-in component 70 and the conductive member 4. In this embodiment, the second insulating resin layer 6 that becomes the first external layer structure 5 is polished to adjust the thickness of the first external layer structure 5 to 100 μm. The method for exposing the portion of the built-in component 70 and the conductive member 4 is not limited to the method of this embodiment, and may be known methods such as polishing with a grinder, buffing, belt polishing, fly-cutting, and CMP, as in FIG. 7 . As a result, in this embodiment, the conductive member 4 that becomes the pad is formed in the second insulating resin layer 6 of the first external layer structure 5.

[0139] Thereafter, the inner layer structure 7 is formed in the same manner as described in Figures 8(f) to (i) of the first embodiment, the second outer layer structure 11 is formed in the same manner as described in Figures 8(j) to 9(m), and then the first connection terminals 16 and the second connection terminals 17 are formed using the method of Figures 9(n) to 10(q), thereby forming the interposer 100 in the modified example described in Figure 25(a).

[0140] Furthermore, the semiconductor package 150 can be produced using the inspection method, semiconductor device assembly method, and repair method shown in FIGS. 12(a) to 13(e) of the first embodiment.

[0141] (Variation 1 of the Fifth Embodiment) FIG. 27( a) illustrates an interposer 100 according to a variation of the fifth embodiment, in which an embedded component 70 is housed within the inner layer structure 7 on the underside of the first outer layer structure 5. The manufacturing method for the interposer 100 in FIG. 27( a) is the same as that shown in FIGS. 7( a) to 7( e) of the first embodiment, and is carried out up to the formation of the first outer layer structure 5 shown in FIG. 7( e). The following description will be given by transcribing FIG. 7( e) to FIG. 27( b). The embedded component 70 is mounted on the second insulating resin layer 6 shown in FIG. 27( b) so as to be electrically connected to the conductive member 4, as shown in FIG. 27( c). The mounting method may involve forming a conductive paste on the terminals and connecting them, or soldering. Alternatively, an underfill may be provided in the gap between the embedded component 70 and the first outer layer structure 5. A substrate having four layers of inner layer structures 7 as shown in FIG. 27( d) is obtained using the same method as that shown in FIGS. 8( f) to 8( i) of the first embodiment. The built-in component 70 shown in Fig. 27(d) may be electrically connected to the first connection terminal via the conductive member 4. Alternatively, when the built-in component 70 shown in Figs. 27(c) and (d) has a connection terminal (not shown) on its upper surface, the first and second connection terminals may be electrically connected to the connection terminal (not shown) on the upper surface of the built-in component 70 and the wiring 10 of the inner layer structure via pads 15 and vias 9 as shown in Fig. 27(d) after the steps described in Figs. 8(f) to (i) in the first embodiment. Alternatively, when the built-in component 70 has connection terminals on both its upper and lower surfaces, it may be electrically connected to both connection terminals at the same time.

[0142] (Variation 2 of the Fifth Embodiment) The interposer 100 shown in FIG. 28(a) is a variation in which an embedded component 70 is housed within the second outer layer structure 11. The manufacturing method for the interposer 100 shown in FIG. 28(a) is the same as that shown in FIGS. 7(a) to 7(e) and 8(f) to 8(i) of the first embodiment. Hereinafter, FIG. 8(i) will be transcribed onto FIG. 28(b) for explanation. Similar to FIG. 8(i) of the first embodiment, FIG. 28(b) is a diagram showing the state after four layers of the inner layer structure 7 have been formed. Next, as shown in FIG. 28(c), the embedded component 70 is mounted on a portion of the wiring 10. The mounting method is not limited to this variation. For example, a conductive paste may be applied to the terminals for connection, or solder connection may be used. Next, FIG. 28(d) shows the state after the steps shown in FIGS. 8(j) to 9(m) of the first embodiment have been performed. Furthermore, the interposer 100 of this modified example shown in FIG. 27(a) can be formed by the same method as shown in FIGS. 9(n) to 10(q).

[0143] This modified example may be combined with the fifth embodiment shown in FIG. 25( a) and its modified examples shown in FIGS. 27( a) and 28( a), and the modified example in which the first connection terminals 16 and the second connection terminals 17 on both sides are partitioned using solder resist, as described in FIG. 4. Furthermore, as described in FIG. 5, this may be combined with a structure in which the first outer layer structure 5 is formed of two or more layers. Furthermore, as described in FIG. 6, this may be combined with a structure in which the second outer layer structure 11 is formed of two or more layers. Furthermore, in the manufacturing method described in FIG. 11, a method of forming vias in the first outer layer structure 5 by laser processing may be adopted.

[0144] The methods of the first to fourth embodiments of the present invention may be combined with the fifth embodiment of this modified example. Combinations of the above-described modified examples and embodiments of the present invention can be implemented as appropriate and are within the scope of the present invention.

[0145] (Effects of the Invention of the Fifth Embodiment) According to the interposer 100 of this embodiment, by incorporating a component whose base is made of a highly rigid material into the interposer, it is possible to contribute to improving the independence of the interposer 100. This not only improves the rigidity of the interposer 100, but also makes it possible to add the functions of the embedded component to an interposer whose only function is rewiring, thereby contributing to higher functionality.

[0146] The interposer 100 of this embodiment makes it possible to mount built-in components in close proximity to the semiconductor device, effectively reducing signal and power supply noise, stabilizing the power supply to the chip, etc. Alternatively, it makes it possible to embed optical semiconductor components in the vicinity of the semiconductor device, allowing application to package substrates that combine optical transmission and electrical transmission.

[0147] Summary of Effects of the Embodiments According to the embodiments of the present disclosure, an interposer that can be transported independently without a support body is provided, thereby achieving the following five effects: 1) The interposer itself has the rigidity to withstand electrical testing without a support substrate, making it possible to guarantee electrical testing of the interposer itself before mounting a semiconductor device. This prevents the occurrence of defective semiconductor packages caused by mounting an expensive semiconductor device on a defective interposer.

[0148] 2) By using an interposer that can be transported independently without a support, external connection terminals of different heights can be formed on both sides of the interposer. This allows multiple semiconductor devices to be stacked on both sides of the interposer, and improves the degree of freedom in packaging, such as integration between semiconductor packages. As a result, this can contribute to advanced SiP integration.

[0149] 3) By making it possible to perform electrical testing of the interposer itself, if a defect is found in the semiconductor package, it is possible to repair or replace the semiconductor device mounting to the maximum extent possible without discarding good interposers or semiconductor devices, thereby making it possible to significantly reduce overall manufacturing costs.

[0150] 4) The effects of 1) and 3) above can contribute greatly to improving the yield of SiP assembly, which integrates multiple semiconductor devices.

[0151] 5) The interposer of the present disclosure can exist independently of the support or FC-BGA, making it possible to mount the semiconductor package on the FC-BGA or motherboard, thereby greatly improving the flexibility of mounting.

[0152] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the present invention. For example, in the above-described embodiments, the first outer layer structure is formed before the second outer layer structure, but the order of their formation is not limited in any way, and the second outer layer structure (the side connected to the BGA or motherboard) may be formed on the support substrate first, and the first outer layer structure may be formed thereafter.

[0153] 7(a) to 10(p), which show an outline of the manufacturing method for the interposer embodiment of this embodiment, only one interposer is shown for convenience. However, it goes without saying that the manufacturing method of the present disclosure may also be used to manufacture a single interposer formed on a rectangular panel or a circular wafer on which multiple interposers are arranged. Furthermore, the shape of the manufacturing panel and the thickness and size of the support substrate described in this disclosure are not limited in any way, and any appropriate shape and size can be used.

[0154] The present invention can also take the following forms. (Aspect 1) An interposer comprising an inner layer structure including at least one inner layer wiring layer, a first outer layer structure disposed on a first surface of the inner layer structure and having a higher rigidity than the inner layer structure, and a second outer layer structure disposed on a second surface of the inner layer structure and having a higher rigidity than the inner layer structure, wherein the inner layer wiring layer comprises wiring disposed on a surface of a first insulating resin layer and a conductive member connected to the wiring and penetrating the first insulating resin layer, the first outer layer structure and the second outer layer structure comprise a second insulating resin layer and a conductive member penetrating the second insulating resin layer, and the first outer layer structure and / or the second outer layer structure comprise, on a surface opposite to the surface connected to the inner layer structure, a terminal connectable to a semiconductor device and enabling electrical testing. (Aspect 2) The interposer according to claim 1, wherein the first outer layer structure and the second outer layer structure cover at least the first and second surfaces of the inner layer structure. (Aspect 3) The interposer according to Aspect 1 or 2, wherein the first insulating resin layer is a photosensitive resin, and the second insulating resin layer is a non-photosensitive resin containing a filler. (Aspect 4) The interposer according to any one of Aspects 1 to 3, wherein the first insulating resin layer and the second insulating resin layer are non-photosensitive resins. (Aspect 5) The interposer according to any one of Aspects 1 to 4, wherein the second insulating resin layer is composed of any one of a prepreg, a built-up resin, and a mold resin having physical properties of an elastic modulus of 5 GPa or more and a CTE of 20 ppm or less. (Aspect 6) The interposer according to any one of Aspects 1 to 5, wherein the sum of the thicknesses of the first outer layer structure and the second outer layer structure is greater than the thickness of the inner layer structure.(Aspect 7) The interposer according to any one of Aspects 1 to 6, wherein either the first outer layer structure or the second outer layer structure also covers a side surface of the inner layer structure. (Aspect 8) The interposer according to any one of Aspects 1 to 7, wherein protruding electrodes are provided above the conductive member penetrating the first insulating resin layer and / or below the conductive member penetrating the second insulating resin layer, and the protruding electrodes are usable as connection terminals. (Aspect 9) The interposer according to any one of Aspects 1 to 8, wherein a load / deflection ratio measured on a test piece of the interposer by the following measurement method is 0.125 N / mm or more. <Measurement method> A test piece having dimensions of length 80 mm x width 15 mm x height h (thickness of test piece) mm is clamped between indenters with a support distance L of 66 mm, an indenter radius r1 of 2 mm, and an indenter distance L' of 22 mm relative to the length and width of the test piece, and a four-point bending test is performed at a test speed V calculated using the following formula. (Aspect 10) The interposer according to Aspect 9, wherein when the thickness h of the test piece is 300 μm and the test speed V is 30 mm / sec, the measured load is 5.7 N and the deflection is 7 mm. (Aspect 11) The interposer according to any one of Aspects 1 to 10, further comprising an internal component embedded in the interposer, wherein the first external layer structure or the second external layer structure has a terminal electrically connected to the internal component. (Aspect 12) The interposer according to Aspect 11, wherein the internal component is a component based on silicon, ceramic, glass, or a compound semiconductor. (Aspect 13) A semiconductor package comprising a semiconductor device mounted on the interposer according to any one of Aspects 1 to 12. (Aspect 14) The semiconductor package according to Aspect 13, wherein the semiconductor devices are stacked and mounted with a semiconductor device mounted on a connection terminal formed on a protruding electrode and a semiconductor device mounted on a connection terminal on which the protruding electrode is not formed. (Aspect 15) The semiconductor package according to claim 13 or 14, wherein a plurality of the semiconductor packages are connected and stacked by protruding electrodes. (Aspect 16) A method for manufacturing an interposer, comprising: a first step of forming a first outer layer structure on a support substrate; a second step of forming an inner layer structure above the first outer layer structure; a third step of forming a second outer layer structure below the inner layer structure; a fourth step of peeling the first outer layer structure from the support substrate; and a fifth step of forming connection terminals on the outermost layers of the first outer layer structure and the second outer layer structure. (Aspect 17) A method for manufacturing an interposer according to Aspect 16, comprising a sixth step of mounting an embedded component.(Aspect 18) A method for manufacturing a semiconductor package, comprising: an interposer according to any one of aspects 1 to 12, a first inspection step of conducting an electrical test on the interposer from a connection terminal; a first judgment step of judging whether the interposer is good or bad based on the results of the first inspection step; a temporary connection step of mounting a semiconductor device on an interposer judged to be "good" in the first judgment step; a second inspection step of conducting an electrical test on the temporarily connected semiconductor package; a second judgment step of judging whether the semiconductor package is good or bad based on the results of the second inspection step; and a repair step of repairing and / or replacing the mounting of a semiconductor device judged to be "bad" in the second judgment step. (Aspect 19) A method for manufacturing a semiconductor package according to aspect 18, comprising: a third inspection step of performing an electrical test on the semiconductor package after the repair step; a third judgment step of judging whether the semiconductor package is good or bad based on the results of the third inspection step; and a fixing step of supplying underfill to the gap between the semiconductor device and the interposer of a semiconductor package judged to be "good" in the third judgment step.

[0155] 1: Support substrate 2: Metal layer 3: Resist pattern 4: Conductive member 5: First outer layer structure 6: Second insulating resin layer 7: Inner layer structure 8: First insulating resin layer 9: Via 10: Wiring 11: Second outer layer structure 12: Second insulating resin layer 13: Thin copper foil 14: Via 15: Pad 16: First connection terminal 17: Second connection terminal 18: Inspection probe 19: Underfill 20: Molding resin 21: Solder resist 22: Protruding electrode 23: Protruding electrode 30: Side surface of interposer 50, 51, 52, 53: Semiconductor device 54: Underfill supply device 60: Indenter 61: Support 70: Built-in component 100: Interposer 150: Semiconductor package

Claims

1. an inner layer structure including at least one inner layer wiring layer; a first outer layer structure disposed on a first surface of the inner layer structure and having a higher rigidity than the inner layer structure; An interposer including a second outer layer structure disposed on a second surface of the inner layer structure and having a higher rigidity than the inner layer structure, The first outer layer structure covers at least a first surface of the inner layer structure, the second outer layer structure covers at least a second surface of the inner layer structure, the inner wiring layer includes a wiring arranged on a surface of a first insulating resin layer that is a photosensitive insulating resin, and a conductive member that penetrates the first insulating resin layer and is connected to the wiring, the first outer layer structure includes a second insulating resin layer and a conductive member penetrating the second insulating resin layer, the second outer layer structure includes a third insulating resin layer and a conductive member penetrating the third insulating resin layer, the third insulating resin layer is a non-photosensitive resin containing both a filler and a glass cloth; The first outer layer structure and / or the second outer layer structure are provided with a terminal that can be connected to a semiconductor device and can be used for electrical testing on a surface opposite to the surface connected to the inner layer structure.

1. An interposer comprising:

2. 2. The interposer of claim 1, In the wiring of the inner layer structure including at least one inner layer wiring layer, the thickness of the wiring formed in the outermost layer on the second surface of the inner layer structure is thicker than the thickness of the wiring formed inside the inner layer wiring layer.

1. An interposer comprising:

3. The interposer according to claim 1, The load / deflection ratio of the test piece of the interposer measured by the following measurement method is 0.125 N / mm or more.

1. An interposer comprising: <Measurement method> A test piece having dimensions of 80 mm length × 15 mm width × height h (thickness of the test piece) mm is clamped between indenters with a support distance L of 66 mm, an indenter radius r1 of 2 mm, and an indenter distance L' of 22 mm across the length and width of the test piece, and a four-point bending test is performed at a test speed V calculated by the following formula. [0010]

4. 2. The interposer of claim 1, The second insulating resin layer and the third insulating resin layer have physical properties of an elastic modulus of 5 GPa or more and a CTE of 20 ppm or less, the third insulating resin layer is made of a prepreg, and the second insulating resin layer is made of a built-up resin or a molded resin, The sum of the thicknesses of the first outer layer structure and the second outer layer structure is greater than the thickness of the inner layer structure.

1. An interposer comprising:

5. 2. The interposer of claim 1, Either the first outer layer structure or the second outer layer structure also covers a side surface of the inner layer structure.

1. An interposer comprising:

6. 2. The interposer of claim 1, a built-in component having a base of silicon, ceramic, glass, or compound semiconductor embedded in the interposer; An interposer, wherein the first outer layer structure or the second outer layer structure has a terminal that is electrically connected to the built-in component.

7. A semiconductor device is mounted on the interposer according to claim 1. Semiconductor package.

8. 8. The semiconductor package according to claim 7, The semiconductor device is mounted in a stacked manner, with a semiconductor device mounted on a connection terminal formed on a protruding electrode and a semiconductor device mounted on a connection terminal on which the protruding electrode is not formed. A semiconductor package comprising:

9. 8. The semiconductor package according to claim 7, A plurality of the semiconductor packages are connected by protruding electrodes and stacked. A semiconductor package comprising:

10. A method for manufacturing the interposer according to claim 1, comprising: A first step of forming a first outer layer structure on a supporting substrate; a second step of forming an inner layer structure above the first outer layer structure; a third step of forming a second outer layer structure above the inner layer structure; a fourth step of peeling off the first outer layer structure from a supporting substrate; A fifth step of forming connection terminals on the outermost layers of the first outer layer structure and the second outer layer structure. Including, Furthermore, the process of mounting the built-in parts is also included. A method for manufacturing an interposer.

11. A method for manufacturing an interposer according to claim 10, comprising the steps of: a first inspection step of performing an electrical inspection of the interposer from the connection terminals; a first determination step of determining whether the interposer is good or bad based on a result of the first inspection step; a provisional connection step of mounting a semiconductor device on the interposer judged to be “good” in the first judgment step; a second inspection step of performing an electrical inspection on the semiconductor package temporarily connected in the temporary connection step; a second judgment step of judging whether the semiconductor package is good or bad based on a result of the second inspection step; a repair process for repairing and / or replacing the mounting of the semiconductor device in the semiconductor package determined to be “not acceptable” in the second determination process; a third inspection step of performing an electrical inspection on the semiconductor package after the repair step; a third judgment step of judging whether the semiconductor package is good or bad based on a result of the third inspection step; a fixing step of supplying an underfill to the gap between the semiconductor device and the interposer of the semiconductor package judged to be "good" in the third judgment step; A method for manufacturing a semiconductor package comprising the steps of:

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