Method for suppressing formation of stacking fault, structure produced by this method, and method for evaluating affected layer

Abstract

A problem addressed by the present invention is to provide a novel technology with which it is possible to suppress the formation of stacking fault. The present invention also addresses the problem of providing novel technology with which it is possible to suppress stacking fault that is formed during epitaxial growth on a semiconductor substrate. The present invention provides a method for suppressing the formation of stacking fault, the method comprising: an affected layer removal step S10 in which an affected layer 11 of a semiconductor substrate 10 is removed; and a crystal growth step S20 in which crystal growth is performed on the surface from which the affected layer 11 has been removed.

Description

Method for suppressing formation of stacking faults, structure produced by said method, and method for evaluating process-affected layer

[0001] The present invention relates to a method for suppressing the formation of stacking faults, a structure produced by the method, and a method for evaluating a process-affected layer.

[0002] Typically, semiconductor substrates are manufactured by slicing an ingot of semiconductor material. The surface of the sliced ​​semiconductor substrate contains a surface layer (hereinafter referred to as a process-affected layer) that contains crystal distortions, cracks, etc. introduced during slicing. To avoid reducing yield in the device manufacturing process, it is necessary to planarize the substrate surface while removing this process-affected layer.

[0003] To achieve the removal of the process-affected layer and the planarization of the substrate surface, various techniques have been developed depending on the physical properties of the semiconductor material. For example, in the case of silicon carbide (SiC), a compound semiconductor, the process-affected layer is reduced and the substrate surface is planarized by performing multi-stage mechanical grinding and polishing.

[0004] Patent Document 1 describes a process in which the process-affected layer is reduced and the substrate surface is planarized through a series of steps: a rough grinding step using abrasive grains such as diamond; a finish grinding step using abrasive grains with a smaller grain size than the abrasive grains used in the rough grinding step; and a chemical mechanical polishing (CMP) step in which polishing is performed using a combination of the mechanical action of a polishing pad and the chemical action of a slurry.

[0005] Japanese Patent Application Laid-Open No. 2015-5702

[0006] In order to improve the reliability of semiconductor devices, it is desirable that the epitaxial layer grown on a semiconductor substrate has a low density of various crystal defects and stacking faults (SFs). In particular, stacking faults are considered problematic as a cause of voltage abnormalities in power devices, and it is therefore necessary to form an epitaxial layer with few stacking faults.

[0007] The problem to be solved by the present invention is to provide a novel technique capable of suppressing the formation of stacking faults. Another problem to be solved by the present invention is to provide a novel technique capable of suppressing the formation of stacking faults during epitaxial growth on a semiconductor substrate.

[0008] The present invention, which solves the above-mentioned problems, provides a method for suppressing the formation of stacking faults, which includes a process-damaged layer removal step of removing a process-damaged layer from a semiconductor substrate, and a crystal growth step of growing crystals on the surface from which the process-damaged layer has been removed.

[0009] In a preferred embodiment of the present invention, the process-affected layer removing step is a step of removing a process-affected layer introduced by performing a mechanical process.

[0010] In a preferred embodiment of the present invention, the process-affected layer removing step is a step of etching the semiconductor substrate.

[0011] In a preferred embodiment of the present invention, the damaged layer removing step is a step of removing a layer having a thickness of 1.5 μm or more from the surface of the semiconductor substrate.

[0012] In a preferred embodiment of the present invention, the damaged layer removing step is a step of removing a layer having a thickness of 6.0 μm or more from the surface of the semiconductor substrate.

[0013] In a preferred embodiment of the present invention, the semiconductor substrate is silicon carbide.

[0014] The present invention also relates to a method for evaluating a process-affected layer, which solves the above-mentioned problems and includes an evaluation step of evaluating a process-affected layer of a semiconductor substrate based on stacking faults formed during epitaxial growth on the semiconductor substrate.

[0015] In a preferred embodiment of the present invention, the evaluation step includes an etching step of etching a process-affected layer of the semiconductor substrate, a crystal growth step of growing crystals on the surface from which the process-affected layer has been etched, and a measurement step of measuring the density of stacking faults formed during growth in the crystal growth step.

[0016] In a preferred embodiment of the present invention, the evaluation step is a step of performing measurements multiple times while changing the etching depth.

[0017] In a preferred embodiment of the present invention, the etching step includes a first etching step of etching to a first etching depth and a second etching step of etching to a second etching depth.

[0018] The disclosed technology provides a novel technique for suppressing the formation of stacking faults. The disclosed technology also provides a novel technique for suppressing stacking faults formed during epitaxial growth on a semiconductor substrate.

[0019] Other objects, features and advantages will become apparent from a reading of the following detailed description when taken in conjunction with the drawings and claims.

[0020] It is an explanatory diagram explaining a method for suppressing the formation of stacking faults according to the present invention. It is an explanatory diagram explaining a conventional method. It is an explanatory diagram explaining an etching process in Examples and Comparative Examples. It is an explanatory diagram explaining a crystal growth process in Examples and Comparative Examples. It is a graph showing the relationship between stacking faults IGSF formed during growth and etching depth ED in Examples and Comparative Examples.

[0021] Preferred embodiments of the present invention, including a method for suppressing the formation of stacking faults, a structure produced by the method, and a method for evaluating a process-affected layer, are described in detail below with reference to the accompanying drawings. The technical scope of the present invention is not limited to the embodiments shown in the accompanying drawings, and appropriate modifications are possible within the scope of the claims. In addition, in this specification, in the notation of Miller indices, "-" means a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and duplicate explanations will be omitted.

[0022] <<Method for Suppressing Formation of Stacking Faults>> As shown in FIG. 1 , the method for suppressing formation of stacking faults according to the present invention includes a damaged layer removal step S10 for removing a damaged layer 11 from a semiconductor substrate 10, and a crystal growth step S20 for growing a growth layer 20 on the surface from which the damaged layer 11 has been removed.

[0023] The present invention can suppress the formation of in-grown stacking faults (IGSFs) formed during growth by including the damaged layer removal step S10 of removing the damaged layer 11. That is, it is believed that the stacking faults IGSFs formed during growth are formed due to the damaged layer 11 remaining on the surface of the semiconductor substrate 10.

[0024] 2 is a conceptual diagram of a case where a crystal growth step S20 is performed on the surface of a semiconductor substrate 10 on which a damaged layer 11 remains. This figure shows how stacking faults (IGSFs) formed during growth occur in a growth layer 20 from the interface between the semiconductor substrate 10 and the growth layer 20 when the damaged layer 11 remains.

[0025] In this specification, the term "process-affected layer" refers to a layer introduced by mechanically processing the surface of semiconductor substrate 10. Whether or not this "process-affected layer" has been removed can be confirmed by performing epitaxial growth on semiconductor substrate 10 from which process-affected layer 11 has been removed, and observing and evaluating stacking faults (IGSFs) formed during growth in growth layer 20.

[0026] The semiconductor substrate 10 can naturally be made of any commonly used material. Examples of semiconductor materials include known Group IV materials such as silicon (Si), germanium (Ge), and diamond (C). Examples of materials for the semiconductor substrate 10 include known Group IV-IV compound semiconductor materials such as silicon carbide (SiC). Examples of materials for the semiconductor substrate 10 include known Group II-VI compound semiconductor materials such as zinc oxide (ZnO), zinc sulfide (ZnS), zinc selenide (ZnSe), cadmium sulfide (CdS), and cadmium telluride (CdTe). Examples of materials for the semiconductor substrate 10 include known Group III-V compound semiconductor materials such as boron nitride (BN), gallium arsenide (GaAs), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium phosphide (GaP), indium phosphide (InP), and indium antimonide (InSb). The material of the semiconductor substrate 10 is, for example, aluminum oxide (Al ２ O ３ ), gallium oxide (Ga ２ O ３ The semiconductor substrate 10 may be configured to have known additive atoms appropriately added depending on the material.

[0027] The above-mentioned compound semiconductors can be exemplified as preferred materials for the semiconductor substrate 10 used in the present invention. For example, compound semiconductors such as single-crystal SiC are classified as hard and brittle materials that are extremely difficult to process. The method according to the present invention can suppress the formation of stacking faults (IGSF) during growth by removing the damaged layer 11 before growing the compound semiconductor growth layer 20.

[0028] <Process-Affected Layer Removal Step S10> The process-affected layer removal step S10 according to the present invention will be described in detail below.

[0029] The process-affected layer removal step S10 is a step of removing the process-affected layer 11 introduced into the surface of the semiconductor substrate 10 by a process involving mechanical processing such as slicing, rough grinding, finish grinding, chemical mechanical polishing, etc. In other words, it is a step of removing the process-affected layer 11 of the semiconductor substrate 10 to expose the bulk layer 12.

[0030] By subjecting the semiconductor substrate 10 after the chemical mechanical polishing step to the process-affected layer removal step S10, it is possible to remove the process-affected layer 11 that causes stacking faults IGSF formed during growth.

[0031] Thermal etching can be used to remove the damaged layer 11. For example, H ２ Etching, Si vapor pressure etching, sublimation etching, etc. can be used.

[0032] The etching depth ED from the surface of the semiconductor substrate 10 in the process-damaged layer removal step S10 increases or decreases depending on the depth (thickness) of the process-damaged layer 11 introduced into the semiconductor substrate 10, but is preferably 0.5 μm or more, more preferably 1.0 μm or more, even more preferably 1.5 μm or more, even more preferably 2.0 μm or more, even more preferably 3.0 μm or more, even more preferably 4.0 μm or more, even more preferably 5.0 μm or more, and even more preferably 6.0 μm or more.

[0033] In the region where the damaged layer 11 exists, the greater the etching amount (i.e., the deeper the etching depth ED), the more the formation of stacking faults IGSF formed during epitaxial growth is suppressed. Furthermore, once the damaged layer 11 is removed and the bulk layer 12 is exposed, the formation of stacking faults IGSF formed during growth is almost zero. Therefore, by determining the etching depth ED at which the formation of stacking faults IGSF formed during growth is almost zero, the depth of the damaged layer 11 introduced into the semiconductor substrate 10 can be evaluated.

[0034] <Crystal Growth Step S20> The crystal growth step S20 according to the present invention will be described in detail below.

[0035] The crystal growth step S20 is a step of forming a growth layer 20 by epitaxial growth on the surface of the semiconductor substrate 10 from which the damaged layer 11 has been removed in the damaged layer removal step S10.

[0036] The growth layer 20 can be formed by a known film formation method such as physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0037] The density of stacking faults (IGSF) formed during growth in the growth layer 20 is preferably 3.0 / cm ２ More preferably, 2.0 particles / cm or less. ２ More preferably, 1.0 particles / cm or less. ２ or less, and more preferably almost 0 particles / cm ２ is.

[0038] As a method for measuring the presence or absence and density of stacking faults IGSF formed during growth, known methods used for detecting stacking faults SF, such as photoluminescence (PL), transmission or reflection X-ray topography (XRT), dislocation evaluation by chemical etching, Raman spectroscopy, etc., can be used.

[0039] According to the method for suppressing the formation of stacking faults of the present invention, by including the process-damaged layer removal step S10 of removing the damaged layer 11, it is possible to suppress stacking faults IGSF formed during epitaxial growth.

[0040] According to the method for suppressing the formation of stacking faults according to the embodiment, the process-damaged layer removal step S10 is a step of removing the process-damaged layer 11 introduced by performing mechanical processing. The process-damaged layer removal step S10 is also a step of removing the process-damaged layer 11 introduced by performing a chemical mechanical polishing process.

[0041] The method for suppressing the formation of stacking faults according to the embodiment can be used to manufacture a semiconductor substrate having a low density of stacking faults (IGSF) formed during growth. The method for suppressing the formation of stacking faults according to the embodiment can also be used to manufacture a semiconductor device having a low density of stacking faults (IGSF) formed during growth. Examples of semiconductor devices include Schottky barrier diodes, junction barrier Schottky diodes, thyristors, bipolar junction transistors, and PiN diodes.

[0042] <<Method for Evaluating Process-Affected Layer>> The method for evaluating a process-affected layer according to the present invention includes an evaluation step of evaluating process-affected layer 11 of semiconductor substrate 10 based on stacking faults (IGSF) formed during growth of semiconductor substrate 10. Note that components that are basically the same as those in the configurations described in the previous embodiment are assigned the same reference numerals, and their description will be simplified.

[0043] When a damaged layer 11 is present at the interface between the semiconductor substrate 10 and the growth layer 20, stacking faults IGSF, which are formed during growth due to the damaged layer 11, occur in the growth layer 20 (see FIG. 2).

[0044] Therefore, by forming a growth layer 20 on the semiconductor substrate 10 to be evaluated and evaluating the stacking faults IGSF formed during growth, it is possible to evaluate whether or not a processing-affected layer 11 remains in the semiconductor substrate 10.

[0045] The evaluation process according to the embodiment includes an etching process for etching the process-affected layer 11 of the semiconductor substrate 10, a crystal growth process for growing crystals on the surface from which the process-affected layer 11 has been etched, and a measurement process for measuring the density of stacking faults (IGSFs) formed during the crystal growth process.

[0046] As a method for measuring the presence or absence and density of stacking faults IGSF formed during growth in the measurement step S30, methods that are known to be used for detecting stacking faults SF, such as photoluminescence (PL) method, transmission or reflection X-ray topography (XRT), dislocation evaluation by chemical etching, Raman spectroscopy, etc., can be used.

[0047] The evaluation process according to the embodiment includes a process of performing measurements multiple times while changing the etching depth ED. That is, the semiconductor substrate 10 to be evaluated is subjected to an etching process so as to obtain different etching depths ED, and then subjected to a crystal growth process and a measurement process. By evaluating the correspondence between the different etching depths ED and the density of stacking faults IGSF formed during growth in this way, the depth of the damage layer 11 remaining in the semiconductor substrate 10 to be evaluated can be determined.

[0048] The present invention will be described in more detail below based on examples and comparative examples, but the present invention is not limited to the following contents.

[0049] The substrates used in the following examples and comparative examples were cut to a size of 25 mm x 10 mm from a chemically mechanically polished 4H—SiC wafer tilted 4 degrees in the <11-20> direction. In other words, the substrates used in the examples and comparative examples were cut from the same CMP-finished wafer.

[0050] The apparatus used in the following examples and comparative examples is the apparatus described in International Publication No. 2021 / 025085, which includes a main container 30, a high-melting-point container 40, and a heating furnace that accommodates the main container 30 and the high-melting-point container 40 and can heat the main container 30 and the high-melting-point container 40 so as to form a temperature gradient (see FIGS. 3 and 4).

[0051] (Main container 30) The main container 30 may be configured to accommodate the semiconductor substrate 10 and generate vapor pressures of gaseous species containing Si and C in its internal space during heat treatment. For example, the main container 30 is made of a material containing SiC, preferably polycrystalline SiC. Furthermore, the main container 30 preferably has SiC exposed on at least a portion of its inner surface.

[0052] 3 and 4, the entire main body container 30 is made of polycrystalline SiC. By heating the main body container 30 made of such a material, vapor pressures of gaseous species containing Si element and gaseous species containing C element can be generated within the main body container 30.

[0053] That is, the environment inside the heated main container 30 is preferably a vapor pressure environment of a mixture of gaseous species containing Si element and gaseous species containing C element. ２ , Si ３ , Si ２ C, SiC ２ , SiC. Also, examples of gas phase species containing C element include Si ２ C, SiC ２, SiC, and C. That is, a state is created in which SiC-based gas is present in the main container 30.

[0054] Any structure can be employed as long as it generates vapor pressure of a gaseous species containing Si element and a gaseous species containing C element in the internal space during heat treatment of main container 30. For example, a structure in which polycrystalline SiC is exposed on a part of the inner surface, or a structure in which polycrystalline SiC is separately disposed inside main container 30, etc., can be used.

[0055] 3 and 4, the main container 30 is a fitting container comprising an upper container 31 and a lower container 32 that can fit together. A minute gap 33 is formed at the fitting portion between the upper container 31 and the lower container 32, and the main container 30 is configured to be able to be evacuated (vacuumed) through this gap 33. In other words, the inside of the main container 30 is configured to become a semi-closed space when evacuated.

[0056] The term "semi-closed space" as used herein refers to a space in which a vacuum can be drawn inside the container, but which can contain at least a portion of the vapor generated inside the container. This semi-closed space can be formed inside the container.

[0057] 3 is an explanatory diagram illustrating the arrangement when etching the semiconductor substrate 10, and is a process in which Si atoms and C atoms on the semiconductor substrate 10 side are transported to the main container 30 side using the temperature difference established between the semiconductor substrate 10 and the main container 30 as a driving force. That is, due to the temperature gradient created by the heating furnace, at least a part of the main container 30 (for example, the bottom surface of the lower container 32) becomes colder than the semiconductor substrate 10, thereby generating a driving force for transporting Si atoms and C atoms on the semiconductor substrate 10 side to the main container 30 side.

[0058] More specifically, when the temperature of the surface of the semiconductor substrate 10 to be etched is compared with the temperature of the bottom surface of the lower container 32 facing this surface, heating is performed so that the temperature on the semiconductor substrate 10 side is higher and the temperature on the lower container 32 side is lower. In this way, by forming a space in the main container 30 where a temperature difference is created between the semiconductor substrate 10 and the lower container 32, Si atoms and C atoms on the semiconductor substrate 10 side can be transported to the lower container 32 using the temperature difference as a driving force. Although not shown, a substrate holder for holding the semiconductor substrate 10 may be provided, or the temperature gradient of the heating furnace may be inverted.

[0059] 4 is an explanatory diagram showing the arrangement during epitaxial growth on the semiconductor substrate 10, and is a process in which the temperature difference between the main container 30 and the semiconductor substrate 10 is used as a driving force to transport Si atoms and C atoms from the main container 30 side to the semiconductor substrate 10 side. That is, due to the temperature gradient created by the heating furnace, at least a part of the main container 30 (for example, the top surface of the upper container 31) becomes hotter than the semiconductor substrate 10, generating a driving force to transport the Si atoms and C atoms from the main container 30 side to the semiconductor substrate 10 side.

[0060] More specifically, when the temperature of the surface on which epitaxial growth is performed on the semiconductor substrate 10 is compared with the temperature of the top surface of the upper vessel 31 opposite this surface, heating is performed so that the temperature on the semiconductor substrate 10 side is lower and the temperature on the upper vessel 31 side is higher. In this way, by forming a space in the main vessel 30 where a temperature difference is created between the semiconductor substrate 10 and the upper vessel 31, the temperature difference can be used as a driving force to transport Si atoms and C atoms in the upper vessel 31 to the semiconductor substrate 10. Although not shown, a substrate holder for holding the semiconductor substrate 10 may be provided, or the temperature gradient of the heating furnace may be inverted.

[0061] (High-melting-point container 40) The high-melting-point container 40 is configured to contain a high-melting-point material. For example, it is possible to use C, which is a general-purpose heat-resistant material, W, Re, Os, Ta, Mo, which is a high-melting-point metal, or Ta carbide. ９ C ８ , HfC, TaC, NbC, ZrC, Ta ２ C, TiC, WC, MoC, nitrides HfN, TaN, BN, Ta ２N, ZrN, TiN, and boride HfB ２ , TaB ２ , ZrB ２ , N.B. ２ , TiB ２ , polycrystalline SiC, and the like.

[0062] Like the main container 30, the high-melting-point container 40 is a fitting container having an upper container 41 and a lower container 42 that can fit together, and is configured to be able to house the main container 30. A minute gap 43 is formed at the fitting portion between the upper container 41 and the lower container 42, and the high-melting-point container 40 is configured to be able to be evacuated (vacuumed) through this gap 43. In other words, the interior of the high-melting-point container 40 is configured to become a semi-closed space when evacuated.

[0063] The high-melting-point container 40 has a Si vapor supply source 44 capable of supplying vapor pressure of a gaseous species containing Si element into the high-melting-point container 40. The Si vapor supply source 44 may be configured to generate Si vapor in the high-melting-point container 40 during heat treatment, and examples of the Si vapor supply source 44 include solid Si (single-crystal Si pieces, Si pellets such as Si powder, etc.) and Si compounds. For example, a layer of silicided high-melting-point material may be provided inside the high-melting-point container 40 described above.

[0064] Other than this, any other configuration can be adopted as long as the vapor pressure of the gas phase species containing the Si element is generated in the high melting point container 40 during the heat treatment.

[0065] Example 1 Etching was performed on the (0001) surface (Si surface) of a semiconductor substrate 10 to an etching depth ED of 6.0 μm, and then crystal growth was performed to a growth amount of 14.0 μm. Thereafter, stacking faults IGSF formed during growth were measured by the PL method.

[0066] (Etching Process) In the etching process according to Example 1, the cut semiconductor substrate 10 was placed in a main body container 30, and the main body container 30 was then placed in a high-melting-point container 40 and heated to 1800° C. using a heating furnace, thereby etching the (0001) plane (=Si plane) of the semiconductor substrate 10 by 6.0 μm (see FIG. 3 ).

[0067] (Crystal Growth Process) In the crystal growth process according to Example 1, the semiconductor substrate 10 that had undergone the etching process was placed in a main body container 30, which was then placed in a high-melting-point container 40 and heated to 1800°C using a heating furnace, thereby growing a crystal of 14.0 μm on the (0001) plane (=Si plane) of the semiconductor substrate 10 (see FIG. 4).

[0068] (Measurement step) In the measurement step according to Example 1, the semiconductor substrate 10 that had undergone the crystal growth step was measured by the PL method (incident light: 313 nm, detector: >750 nm). From the PL image of Example 1, no stacking faults (IGSF) formed during growth were observed. Therefore, the density of stacking faults (IGSF) formed during growth was 0 / cm. ２ It is considered that the process-affected layer 11 of the semiconductor substrate 10 has been removed.

[0069] Comparative Example 1: The (0001) plane (=Si plane) of the semiconductor substrate 10 cut from the same wafer as in Example 1 was etched to an etching depth ED of 1.3 μm, and then crystal growth was performed to a growth amount of 14.0 μm. Thereafter, the stacking faults IGSF formed during growth were measured by the PL method.

[0070] (Etching process) In the etching process of Comparative Example 1, the cut semiconductor substrate 10 was placed in a main body container 30, and the main body container 30 was then placed in a high-melting-point container 40 and heated to 1700°C using a heating furnace, thereby etching the (0001) surface (=Si surface) of the semiconductor substrate 10 by 1.3 μm.

[0071] (Crystal Growth Step) In the crystal growth step according to Comparative Example 1, crystal growth was carried out under the same conditions as in Example 1.

[0072] (Measurement step) In the measurement step according to Comparative Example 1, measurement was performed by the PL method under the same conditions as in Example 1. The density of stacking faults (IGSF) formed during growth obtained from the PL image of Comparative Example 1 was 2.5 / cm ２ It was.

[0073] Comparative Example 2: The (0001) plane (=Si plane) of the semiconductor substrate 10 cut from the same wafer as in Example 1 was etched to an etching depth ED of 0.6 μm, and then crystal growth was performed to a growth amount of 14.0 μm. Thereafter, the stacking faults IGSF formed during growth were measured by the PL method.

[0074] (Etching process) In the etching process according to Comparative Example 2, the cut semiconductor substrate 10 was housed in a main body container 30, and the main body container 30 was then housed in a high-melting-point container 40 and heated to 1700°C using a heating furnace, thereby etching the (0001) surface (=Si surface) of the semiconductor substrate 10 by 0.6 μm.

[0075] (Crystal Growth Step) In the crystal growth step according to Comparative Example 2, crystal growth was carried out under the same conditions as in Example 1.

[0076] (Measurement step) In the measurement step according to Comparative Example 2, measurement was performed by the PL method under the same conditions as in Example 1. The density of stacking faults (IGSF) formed during growth obtained from the PL image of Comparative Example 2 was 13.5 / cm ２ It was.

[0077] Comparative Example 3: Crystal growth was performed on the (0001) plane (Si plane) of a semiconductor substrate 10 cut from the same wafer as in Example 1, so that the growth amount was 14.0 μm. That is, crystal growth was performed on a CMP-finished surface without etching. Thereafter, the stacking faults (IGSF) formed during growth were measured by the PL method.

[0078] (Crystal Growth Step) In the crystal growth step according to Comparative Example 3, crystal growth was performed under the same conditions as in Example 1.

[0079] (Measurement step) In the measurement step according to Comparative Example 3, measurement was performed by the PL method under the same conditions as in Example 1. The density of stacking faults (IGSF) formed during growth obtained from the PL image of Comparative Example 3 was 32.0 / cm ２ It was.

[0080] FIG. 5 is a graph showing the relationship between stacking faults IGSF formed during growth and etching depth ED in the examples and comparative examples.

[0081] As shown in FIG. 5, the density of stacking faults (IGSF) formed during growth in the semiconductor substrate 10 that underwent the crystal growth process without undergoing the etching process was 32 / cm. ２ On the other hand, the density of stacking faults IGSF formed during growth in the semiconductor substrate 10 that underwent the crystal growth step after the etching step was 13.5 / cm ２ , 2.5 pieces / cm ２ , and 0 pieces / cm ２ It was revealed that the density of stacking faults (IGSF) formed during growth decreases as the etching depth increases.

[0082] In Example 1, the density of stacking faults (IGSF) formed during growth was 0 / cm ２ However, it is considered that etching until the etching depth ED reached 6.0 μm was excessive.

[0083] In light of the results of Example 1 and Comparative Example 1, it can be estimated that if the etching depth ED is 1.5 μm or more, a growth layer 20 in which stacking faults IGSF are not formed during growth can be obtained.

[0084] According to the examples and comparative examples, it is considered that the process-affected layer removal step S10 is sufficient if it is a step of removing 1.5 μm or more from the surface of the semiconductor substrate 10. It is also considered that the process-affected layer removal step S10 is sufficient if it is a step of removing 6.0 μm or more from the surface of the semiconductor substrate 10.

[0085] Furthermore, according to the examples and comparative examples, it can be understood that the method for evaluating a processed-affected layer includes an evaluation step for evaluating the processed-affected layer 11 of the semiconductor substrate 10 based on stacking faults IGSF formed during epitaxial growth on the semiconductor substrate 10.

[0086] The evaluation process may include an etching process for etching the process-affected layer 11 of the semiconductor substrate 10, a crystal growth process for growing crystals on the surface from which the process-affected layer 11 has been etched, and a measurement process for measuring the density of stacking faults (IGSFs) formed during growth in the crystal growth process.

[0087] The evaluation step performs measurements multiple times while changing the etching depth ED, thereby evaluating the depth of the process-affected layer 11 introduced into the semiconductor substrate 10. Specifically, the depth of the process-affected layer 11 can be estimated by including a first etching step in which etching is performed to a first etching depth and a second etching step in which etching is performed to a second etching depth.

[0088] That is, from the results of Example 1 and Comparative Example 1, it can be estimated that the depth of process-affected layer 11 introduced into semiconductor substrate 10 (wafer used this time) was about 1.5 μm. Note that the depth of process-affected layer 11 varies depending on the surface finish and quality of the wafer.

[0089] REFERENCE SIGNS LIST 10 semiconductor substrate 11 process-affected layer 12 bulk layer 20 growth layer 30 main body vessel 31 upper vessel 32 lower vessel 33 gap 40 high-melting-point vessel 41 upper vessel 42 lower vessel 43 gap 44 Si vapor supply source S10 process-affected layer removal step S20 crystal growth step ED etching depth IGSF stacking faults formed during growth

Claims

1. a process-affected layer removal step of removing a process-affected layer from the semiconductor substrate; a crystal growth step of growing crystals on the surface from which the damaged layer has been removed.

2. The method according to claim 1 , wherein the process-affected layer removing step is a step of removing a process-affected layer introduced by performing a mechanical process.

3. 3. The method according to claim 1, wherein the damaged layer removing step is a step of etching the semiconductor substrate.

4. 3. The method according to claim 1, wherein the damaged layer removing step is a step of removing a thickness of 1.5 [mu]m or more from the surface of the semiconductor substrate.

5. 3. The method according to claim 1, wherein the damaged layer removing step is a step of removing a thickness of 6.0 μm or more from the surface of the semiconductor substrate.

6. The method of claim 1 or claim 2, wherein the semiconductor substrate is silicon carbide.

7. A semiconductor substrate manufactured by the method of claim 1 or 2.

8. A semiconductor device manufactured using the semiconductor substrate according to claim 7.

9. A method for evaluating a process-affected layer, comprising an evaluation step of evaluating a process-affected layer of a semiconductor substrate based on stacking faults formed during epitaxial growth on the semiconductor substrate.

10. The evaluation step includes an etching step of etching a process-affected layer of a semiconductor substrate; a crystal growth step of growing crystals on the etched surface of the process-affected layer; The method of claim 9, further comprising a measuring step of measuring a density of stacking faults formed during growth of the crystal growing step.

11. The method according to claim 10 , wherein the evaluation step is a step of performing measurements multiple times while changing the etching depth.

12. 11. The method of claim 10, wherein the etching step includes a first etching step of etching to a first etching depth and a second etching step of etching to a second etching depth.