Semiconductor device

Abstract

A semiconductor device (1) includes: a chip (9) having a main surface (10); a trench insulating structure (17) formed in the main surface; a gate insulating film (28) covering the main surface so as to connect to the trench insulating structure; a polysilicon gate (29) covering the trench insulating structure and the gate insulating film; a first semiconductor region (30) formed in a portion of the polysilicon gate covering the gate insulating film, and having a first threshold voltage of a relatively low absolute value; and a second semiconductor region (31) formed in a portion of the polysilicon gate covering a boundary between the gate insulating film and the trench insulating structure, and having a second threshold voltage of an absolute value that is relatively higher than the first threshold voltage.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Patent Application No. 2022-061157 filed with the Japan Patent Office on March 31, 2022, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] For example, U.S. Patent No. 6,277,949 discloses a method for limiting the formation of divots in shallow trench isolation (STI) structures, which method includes providing a deposited oxide in a trench formed in a silicon region, oxidizing an upper layer of the silicon region to form a thermal oxide layer on the upper surface of the silicon region, and etching the thermal oxide selectively to the deposited oxide.

[0004] Special Publication No. 2005-510080

[0005] An embodiment of the present disclosure provides a semiconductor device capable of suppressing the occurrence of a hump phenomenon in the drain current-gate voltage (Ids-Vgs) characteristics.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a chip having a main surface, a trench insulation structure formed on the main surface, a gate insulating film covering the main surface so as to be connected to the trench insulation structure, a polysilicon gate covering the trench insulation structure and the gate insulating film, a first semiconductor region formed in a portion of the polysilicon gate covering the gate insulating film and having a first threshold voltage having a relatively low absolute value, and a second semiconductor region formed in a portion of the polysilicon gate covering a boundary between the gate insulating film and the trench insulation structure and having a second threshold voltage having an absolute value relatively higher than the first threshold voltage.

[0007] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating a cross section taken along line II-II in FIG. 1. FIG. 3 is a diagram illustrating a cross section taken along line III-III in FIG. 1. FIG. 4 is a diagram illustrating a cross section taken along line IV-IV in FIG. 1. FIG. 5 is a diagram illustrating a cross section taken along line V-V in FIG. 1. FIG. 6 is an enlarged view of a portion surrounded by a two-dot chain line VI in FIG. 4. FIG. 7A is a diagram illustrating a part of a manufacturing process of the semiconductor device. FIG. 7B is a diagram illustrating a process subsequent to FIG. 7A. FIG. 7C is a diagram illustrating a process subsequent to FIG. 7B. FIG. 7D is a diagram illustrating a process subsequent to FIG. 7C. FIG. 7E is a diagram illustrating a process subsequent to FIG. 7D. FIG. 8A is a diagram illustrating a process (first pattern) related to the formation of a gate electrode. FIG. 8B is a diagram illustrating a process subsequent to FIG. 8A. FIG. 8C is a diagram illustrating a process subsequent to FIG. 8B. FIG. 9A is a diagram illustrating a process (second pattern) related to the formation of a gate electrode. FIG. 9B is a diagram illustrating a process subsequent to FIG. 9A. 9C is a diagram showing a step subsequent to FIG. 9B. FIG. 10A is a diagram showing a step (third pattern) related to the formation of a gate electrode. FIG. 10B is a diagram showing a step subsequent to FIG. 10A. FIG. 10C is a diagram showing a step subsequent to FIG. 10B. FIG. 11 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. FIG. 12 is a diagram showing a cross section taken along line XII-XII in FIG. 11. FIG. 13 is a diagram showing a cross section taken along line XIII-XIII in FIG. 11. FIG. 14 is a diagram showing static characteristics of a low-voltage p-channel transistor.

[0008] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] Hereinafter, the direction in which the gate electrode 29 of each transistor extends is defined as a first direction X, the direction in which the source region and drain region of each transistor oppose each other is defined as a second direction Y, and the thickness direction of the semiconductor substrate 2 is defined as a third direction Z. Note that the definitions of the first direction X, the second direction Y, and the third direction Z are not limited thereto. For example, the arrangement direction of multiple transistors may be defined as the first direction X, or the direction perpendicular to the arrangement direction may be defined as the second direction Y. [Overview of Semiconductor Device 1] FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure. Referring to FIG. 1 , the semiconductor device 1 is, for example, a composite element in which multiple elements are mounted on a common semiconductor substrate 2, and includes a CMOS area 3. A CMOS transistor 4 is formed in the CMOS area 3. Although not shown in FIG. 1 , the semiconductor substrate 2 may also be formed with, in addition to the CMOS area 3, a DMOS area in which a DMOS transistor is formed, a bipolar area in which a bipolar transistor is formed, a passive element area in which passive elements such as resistors and capacitors are formed, and the like.

[0010] In the CMOS area 3, for example, a low-voltage CMOS transistor 5, a medium-voltage CMOS transistor, and a high-voltage transistor may be formed as the CMOS transistors 4. The low-voltage CMOS transistor 5 may be, for example, a CMOS transistor having a rated voltage of 1.0 V or more and 4.0 V or less. The medium-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 4.0 V or more and 7.0 V or less. The high-voltage CMOS transistor may be, for example, a CMOS transistor having a rated voltage of 7 V or more and 60 V or less. The rated voltage may be defined as the range of the maximum allowable value of the voltage applied between the source and drain of each CMOS transistor. The rated voltage of each CMOS transistor may also be rephrased as the breakdown voltage of each CMOS transistor 4.

[0011] The structure of the low-voltage CMOS transistor 5, particularly the structure of the low-voltage p-channel transistor 6p, will be described in detail below. However, the structure of the gate electrode 29 of the low-voltage p-channel transistor 6p can also be applied to the low-voltage n-channel transistor 6n, the medium-voltage CMOS transistor, and the high-voltage CMOS transistor. [Structure of the Low-Voltage P-Channel Transistor 6p] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is an enlarged view of the portion surrounded by the two-dot chain line VI in FIG. 4.

[0012] 1, the low-voltage CMOS transistor 5 includes a low-voltage p-channel transistor 6p and a low-voltage n-channel transistor 6n. The low-voltage p-channel transistor 6p and the low-voltage n-channel transistor 6n are formed on a common semiconductor substrate 2. In this embodiment, the semiconductor substrate 2 may be a p-type silicon substrate. The impurity concentration of the semiconductor substrate 2 is, for example, 1.0×10 １３ cm －３ Above 1.0 x 10 ２０ cm －３ The semiconductor substrate 2 has a first main surface 7 and a second main surface 8 on the opposite side thereof. The first main surface 7 and the second main surface 8 may be rephrased as the front and back surfaces of the semiconductor substrate 2, respectively. ＋ "," "p － "," "n ＋ ", "n" and "n － The notation " " merely indicates the relative magnitude relationship of each impurity region (semiconductor region) containing p-type impurities or n-type impurities for the sake of convenience, and does not define a specific range of impurity concentration.

[0013] An epitaxial layer 9 is formed on the semiconductor substrate 2. In this embodiment, the epitaxial layer 9 may be an n-type silicon semiconductor layer. The impurity concentration of the epitaxial layer 9 is, for example, 1.0×10 １３ cm －３ Above 1.0 x 10１７ cm －３ The epitaxial layer 9 may have a first main surface 10 and a second main surface 11 opposite to the first main surface 10. The first main surface 10 and the second main surface 11 may also be referred to as the front and back surfaces of the epitaxial layer 9, respectively. The second main surface 11 of the epitaxial layer 9 may be a junction surface with the first main surface 7 of the semiconductor substrate 2.

[0014] The epitaxial layer 9 is formed with an element isolation portion 12 that divides a region on a first main surface 10 of the epitaxial layer 9 into a plurality of active regions. Referring to FIG. 1 , the element isolation portion 12 divides the first main surface 10 of the epitaxial layer 9 into an LV-active region 13 for the low-voltage CMOS transistor 5. The LV-active region 13 is further divided into a p-side active region 13p for the low-voltage p-channel transistor 6p and an n-side active region 13n for the low-voltage n-channel transistor 6n. The p-side active region 13p and the n-side active region 13n are adjacent to each other in the second direction Y, separated by the element isolation portion 12. The p-side active region 13p and the n-side active region 13n may be formed in rectangular shapes of the same size and long along the first direction X, in a plan view seen from the normal direction to the first main surface 10.

[0015] 4 and 5 , the p-side active region 13p may have, in the first direction X, a first end 14 on one side, a second end 15 on the opposite side, and a central portion 16 between the first end 14 and the second end 15. There may not be a clear boundary between the first end 14 and the second end 15 and the central portion 16. For example, the first end 14 and the second end 15 may be in a range of 0.1 μm or more and 2.0 μm or less inward in the first direction X from the boundary between the p-side active region 13p and the element isolation portion 12, and the central portion 16 may be the remaining portion.

[0016] In this embodiment, the element isolation portion 12 includes a trench 17 formed in the epitaxial layer 9 and a buried insulator 18 buried in the trench 17 .

[0017] Trench 17 has side surfaces 19 and a bottom surface 20. Side surfaces 19 of trench 17 may be surfaces that are perpendicular to first main surface 10 of epitaxial layer 9 as shown in Figures 2 to 5, or may be surfaces that are inclined with respect to first main surface 10 of epitaxial layer 9 as shown in Figure 6. In the case of Figure 6, trench 17 may have a tapered shape in cross-section that narrows from first main surface 10 toward bottom surface 20 in third direction Z.

[0018] The buried insulator 18 is, for example, silicon oxide (SiO ２ ), silicon nitride (SiN), or the like. In this embodiment, the buried insulator 18 is made of silicon oxide. The buried insulator 18 exposes an opening end 21 of the trench 17. The element isolation portion 12 may also be generally called STI (Shallow Trench Isolation).

[0019] 1 to 5, in the p-side active region 13p, a p-side planar gate structure 22p is formed on the first main surface 10 of the epitaxial layer 9. The p-side planar gate structure 22p is formed on the first main surface 10 so as to cover the first channel region 23 and the second channel region 24 (described later). The p-side planar gate structure 22p integrally includes a gate body portion 25 that controls the on / off of the first channel region 23 and the second channel region 24, and a gate contact portion 26 that receives a voltage supply.

[0020] 1 , the gate body 25 includes a pair of gate bodies 25 extending parallel to each other along the first direction X. The pair of gate bodies 25 are formed to cross the boundary between the p-side active region 13p and the element isolation portion 12, and may have both ends formed on the element isolation portion 12. Each gate body 25 is formed in an elongated shape along the first direction X.

[0021] The gate contact portions 26 are formed on the element isolation portion 12 and are connected to the gate main body portions 25 on the element isolation portion 12. One gate contact portion 26 is formed at each longitudinal end of the pair of gate main body portions 25. The gate contact portions 26 are formed in a longitudinal shape along a direction crossing the pair of gate main body portions 25 (direction along the second direction Y). As a result, the p-side planar gate structure 22p is formed in a generally rectangular ring shape in plan view as shown in FIG. 1, and has a gate opening 27 in its central portion 16. The gate opening 27 is formed in a generally elliptical shape in plan view. Both longitudinal ends of the gate opening 27 may be formed within the p-side active region 13p as shown in FIG. 1, or may be formed on the element isolation portion 12.

[0022] The p-side planar gate structure 22p includes a gate insulating film 28 and a gate electrode 29 stacked in this order from the first main surface 10 side. The gate insulating film 28 may include a silicon oxide film. The gate insulating film 28 preferably includes a silicon oxide film made of an oxide of the epitaxial layer 9. The gate electrode 29 preferably includes conductive polysilicon.

[0023] In this embodiment, the gate electrode 29 includes a first semiconductor region 30 and a second semiconductor region 31. The first semiconductor region 30 and the second semiconductor region 31 are distinguished by a boundary that extends in the thickness direction of the gate electrode 29 from the upper surface to the lower surface of the gate electrode 29. For example, the first, second, and third patterns shown below have different properties.

[0024] In the first pattern, the first semiconductor region 30 may be composed of a region doped with either n-type impurities or p-type impurities, and the second semiconductor region 31 may be composed of a region doped with both n-type impurities and p-type impurities. More specifically, the second semiconductor region 31 may be composed of a region in which at least a portion of the conductivity type of the first semiconductor region 30 is offset by the opposite conductivity type. In this embodiment, the first semiconductor region 30 is composed of a region doped with p-type impurities, and the second semiconductor region 31 is a region in which a portion of the p-type is offset by the n-type.

[0025] The p-type impurity contained in the first semiconductor region 30 may be, for example, at least one of boron (B) and aluminum (Al). The p-type impurity contained in the second semiconductor region 31 may be, for example, at least one of boron (B) and aluminum (Al), and the n-type impurity may be, for example, at least one of phosphorus (P), arsenic (As), and antimony (Sb). The impurity concentrations of the first semiconductor region 30 and the second semiconductor region 31 are different from each other. For example, the impurity concentration of the first semiconductor region 30 may be higher than the impurity concentration of the second semiconductor region 31. For example, the impurity concentration of the first semiconductor region 30 may be 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The impurity concentration of the second semiconductor region 31 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ It may be the following:

[0026] In the second pattern, the first semiconductor region 30 and the second semiconductor region 31 may have different conductivity types. In this embodiment, the first semiconductor region 30 may be p-type, and the second semiconductor region 31 may be n-type. The p-type impurity contained in the first semiconductor region 30 may be, for example, at least one of boron (B) and aluminum (Al). The n-type impurity contained in the second semiconductor region 31 may be, for example, at least one of phosphorus (P), arsenic (As), and antimony (Sb). The impurity concentrations of the first semiconductor region 30 and the second semiconductor region 31 are different from each other. For example, the impurity concentration of the first semiconductor region 30 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The impurity concentration of the second semiconductor region 31 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ It may be the following:

[0027] In the third pattern, the first semiconductor region 30 may be made of an impurity-doped region, and the second semiconductor region 31 may be made of an impurity-undoped region. The conductivity type of the first semiconductor region 30 may be either n-type or p-type, but in this embodiment, it is p-type. The p-type impurity contained in the first semiconductor region 30 may be, for example, at least one of boron (B) and aluminum (Al). The impurity concentrations of the first semiconductor region 30 and the second semiconductor region 31 are different from each other. For example, the impurity concentration of the first semiconductor region 30 is 1.0×10 １７ cm －３ Above 1.0 x 10 ２１ cm －３ The impurity concentration of the second semiconductor region 31 is 1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３ It may be the following:

[0028] By having the first semiconductor region 30 and the second semiconductor region 31 differentiated as in the first to third patterns, the gate electrode 29 provides different threshold voltages to the regions facing the first semiconductor region 30 and the second semiconductor region 31. For example, the gate electrode 29 provides a first threshold voltage to the channel region (first channel region 23) facing the first semiconductor region 30, and a second threshold voltage to the channel region (second channel region 24) facing the second semiconductor region 31. Comparing the first threshold voltage and the second threshold voltage, the second threshold voltage has an absolute value that is relatively higher than the first threshold voltage.

[0029] Here, the cross-sectional structure of the gate electrode 29 at the first end 14 and the second end 15 of the p-side active region 13p will be described in detail with reference to Fig. 6. Fig. 6 shows the structure at the first end 14 as an example of the first end 14 and the second end 15, but the structure of the first end 14 can also be applied to the second end 15.

[0030] A recess 32 is selectively formed in the buried insulator 18 near the first end 14 of the p-side active region 13p. The recess 32 is generated due to a cleaning process (such as light etching with a hydrofluoric acid solution) performed each time before a thermal oxidation process for forming the gate insulating film 28, which will be described later, and may also be called a divot. The recess 32 may be formed continuously over the entire periphery of the p-side active region 13p so as to surround the p-side active region 13p.

[0031] The gate insulating film 28 covers the opening end 21 of the trench 17 so as to be integrally connected to the buried insulator 18 in the recess 32. At a boundary 33 between the buried insulator 18 and the gate insulating film 28 near the recess 32, a significant thin-film portion 34 is formed in the gate insulating film 28. For example, the thickness T １ is 50 Å or more and 250 Å or less, and the thickness T ２ is the thickness T of the gate insulating film 28 in the central portion 16 １ This thin film portion 34 causes leakage and reduces the breakdown voltage of the gate insulating film 28. Furthermore, this thin film portion 34 partially forms a low threshold region, which leads to deterioration of the static characteristics of the low breakdown voltage p-type channel transistor 6p (such as unstable threshold). Therefore, this embodiment provides a structure that does not cause such deterioration of the static characteristics. More specifically, this is the structure of the gate electrode 29 in which the above-mentioned second semiconductor region 31 is formed.

[0032] 6 , the second semiconductor region 31 of the gate electrode 29 covers the boundary portion 33 and the recess 32 of the buried insulator 18, and may include a buried portion 61 buried in the recess 32. As a result, the second semiconductor region 31 straddles both the element isolation portion 12 side and the p-side active region 13p side of the boundary portion 33 at the first end 14 of the p-side active region 13p.

[0033] 1 , the second semiconductor region 31 is formed in the gate contact portion 26 on the element isolation portion 12 along the longitudinal direction of the gate contact portion 26, and may straddle a pair of gate body portions 25. The second semiconductor region 31 is formed in an inner region of the gate electrode 29, spaced apart from each of the outer and inner edges (the periphery of the gate opening 27) of the gate electrode 29, so that the second semiconductor region 31 is surrounded by the first semiconductor region 30 in a plan view. In other words, the majority of the gate electrode 29 is formed of the first semiconductor region 30, and the second semiconductor region 31 is selectively formed in the vicinity of the boundary portion 33.

[0034] 2 to 5, silicide 35 is formed in a surface layer portion on the upper surface side of gate electrode 29. Silicide 35 is integrally formed over the entire gate electrode 29, and is present in both first semiconductor region 30 and second semiconductor region 31.

[0035] A sidewall 36 is formed around the gate electrode 29. The sidewall 36 is formed continuously over the entire periphery of the gate electrode 29 so as to cover the side surfaces of the gate electrode 29. The sidewall 36 is made of, for example, silicon oxide (SiO ２ ), silicon nitride (SiN), or the like.

[0036] 2 to 5, an n-type well 37 for a low-breakdown-voltage p-type channel transistor 6p is formed in a surface layer portion of epitaxial layer 9. The impurity concentration of n-type well 37 is higher than the impurity concentration of epitaxial layer 9, and is, for example, 1.0×10 １７ cm －３ Above 1.0 x 10 １９ cm －３ In the n-type well 37, a low-breakdown-voltage p-type channel transistor 6p is formed.

[0037] A p-type source region 38p and a p-type drain region 39p are formed at an interval in the surface layer portion of the n-type well 37. The impurity concentrations of the p-type source region 38p and the p-type drain region 39p are higher than the impurity concentration of the n-type well 37, and are, for example, 1.0×10 １９cm －３ Above 1.0 x 10 ２１ cm －３ It may be the following:

[0038] 1 , in this embodiment, p-type source regions 38p are formed on both sides of the p-type drain region 39p in the second direction Y, sandwiching the p-type drain region 39p. The p-type source region 38p and the p-type drain region 39p are formed elongated along the first direction X. The p-type source region 38p and the p-type drain region 39p extend parallel to each other along the first direction X. The p-type source region 38p and the p-type drain region 39p extend continuously in the first direction X from the first end 14 of the p-side active region 13p through the central portion 16 to the second end 15. Referring to FIGS. 2 and 3 , the p-type source region 38p and the p-type drain region 39p are formed in a self-aligned manner with respect to the sidewalls 36.

[0039] The p-side active region 13p further includes a p-type source extension region 40 and a p-type drain extension region 41 that extend integrally from the p-type source region 38p and the p-type drain region 39p along the second direction Y. The impurity concentrations of the p-type source extension region 40 and the p-type drain extension region 41 are lower than the impurity concentrations of the p-type source region 38p and the p-type drain region 39p, and are, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ 2 and 3, the p-type source extension region 40 and the p-type drain extension region 41 are formed in a self-aligned manner with respect to the gate electrode 29.

[0040] The p-side active region 13p further includes an n-type source pocket implantation region 42 and an n-type drain pocket implantation region 43 that extend integrally from the p-type source region 38p and the p-type drain region 39p along the second direction Y. The impurity concentrations of the n-type source pocket implantation region 42 and the n-type drain pocket implantation region 43 are higher than that of the n-type well 37, and are, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２０ cm －３ 2 and 3 , the n-type source pocket implantation region 42 and the n-type drain pocket implantation region 43 cross the boundary between the sidewall 36 and the gate electrode 29 in the second direction Y and face the gate electrode 29 with the gate insulating film 28 interposed therebetween.

[0041] The n-type source pocket implantation region 42 and the n-type drain pocket implantation region 43 respectively cover the bottom and side portions of the p-type source extension region 40 and the p-type drain extension region 41. With reference to Fig. 4, the n-type drain pocket implantation region 43 extends continuously along the first direction X. Although not shown in the figure, the n-type source pocket implantation region 42 also extends continuously along the first direction X.

[0042] 2, in the central portion 16 of the p-side active region 13p, the region sandwiched between the n-type source pocket implantation region 42 and the n-type drain pocket implantation region 43 is the first channel region 23 formed of a part of the n-type well 37. The first semiconductor region 30 of the gate electrode 29 faces the first channel region 23 over its entirety, with the gate insulating film 28 sandwiched therebetween.

[0043] 3, at the first end 14 of the p-side active region 13p, the region sandwiched between the n-type source pocket implantation region 42 and the n-type drain pocket implantation region 43 is a second channel region 24 formed of a part of the n-type well 37. The second semiconductor region 31 of the gate electrode 29 faces the second channel region 24 over its entirety, with the gate insulating film 28 sandwiched therebetween. Although not shown in the figure, the second channel region 24 is also formed at the second end 15 of the p-side active region 13p.

[0044] Since the p-type source region 38p and the p-type source extension region 40 are both p-type and integral p-type impurity regions, they may be collectively referred to simply as the p-type source region 38p. Similarly, since the p-type drain region 39p and the p-type drain extension region 41 are both p-type and integral p-type impurity regions, they may be collectively referred to simply as the p-type drain region 39p.

[0045] The p-type source extension region 40 and the n-type source pocket implant region 42 extending from the p-type source region 38p to below the gate electrode 29 may be collectively referred to as a p-side source LDD (Lightly Doped Drain) region. Similarly, the p-type drain extension region 41 and the n-type drain pocket implant region 43 extending from the p-type drain region 39p to below the gate electrode 29 may be collectively referred to as a p-side drain LDD (Lightly Doped Drain) region.

[0046] An n-type back gate region 44 is formed in a surface layer portion of the n-type well 37. The n-type back gate region 44 is electrically connected to the n-type well 37. The n-type back gate region 44 is omitted in FIG. 1 .

[0047] An interlayer insulating film 45 is formed on the first main surface 10 of the epitaxial layer 9. The interlayer insulating film 45 is made of, for example, silicon oxide (SiO ２ ), silicon nitride (SiN), etc. In this embodiment, the interlayer insulating film 45 is made of silicon oxide.

[0048] A source contact 46, a drain contact 47, and a gate contact 48 are formed in the interlayer insulating film 45. These contacts are buried in the interlayer insulating film 45. The contacts may be made of a metal material such as tungsten (W). Referring to FIG. 1 , a plurality of source contacts 46 and a plurality of drain contacts 47 are formed at intervals from one another along the first direction X. A plurality of gate contacts 48 are formed at intervals from one another along the second direction Y.

[0049] A source wiring 49, a drain wiring 50, and a gate wiring 51 are formed on the interlayer insulating film 45. The wiring may be made of a metal material such as aluminum (Al). The source wiring 49 is electrically connected to the p-type source region 38p via a source contact 46. The drain wiring 50 is electrically connected to the p-type drain region 39p via a drain contact 47. The gate wiring 51 is electrically connected to the gate electrode 29 (gate contact portion 26) via a gate contact 48. The portion of the gate electrode 29 connected to the gate contact 48 is preferably the first semiconductor region 30. [Method of Manufacturing the Semiconductor Device 1] FIGS. 7A to 7E are diagrams showing, in order of process, some of the manufacturing processes for the semiconductor device 1. FIGS. 8A to 8C are diagrams showing processes related to the formation of the gate electrode 29 (first pattern). FIGS. 9A to 9C are diagrams showing processes related to the formation of the gate electrode 29 (second pattern). FIGS. 10A to 10C are diagrams showing processes related to the formation of the gate electrode 29 (third pattern). 7A to 7E, a manufacturing process for the structure common to the first to third patterns will be described, followed by a description of the manufacturing process for each of the first to third patterns.

[0050] Referring to FIG. 7A , to manufacture the semiconductor device 1, for example, an n-type epitaxial layer 9 is grown on a p-type semiconductor substrate 2. Specifically, silicon crystals are epitaxially grown while adding n-type impurities (e.g., phosphorus). The thickness of the epitaxial layer 9 may be, for example, 0 μm or more and 20 μm or less. Next, the element isolation portion 12 is formed. Specifically, a hard mask made of an insulating film such as a silicon nitride (SiN) film is formed on the first main surface 10 of the epitaxial layer 9. The hard mask has openings corresponding to regions where the element isolation portions 12 are to be formed. Next, the epitaxial layer 9 is selectively etched by reactive ion etching (RIE) using the hard mask. This forms trenches 17. Next, an insulating material is formed on the entire surface of the first main surface 10 of the epitaxial layer 9 by, for example, CVD (chemical vapor deposition), followed by planarization by CMP (chemical mechanical polishing). This forms a buried insulator 18.

[0051] Next, referring to FIG. 7B , impurity ion implantation and impurity ion diffusion processes are performed to form the n-type well 37 and the like. Specifically, n-type impurity ions are implanted into the region where the n-type well 37 and the like are to be formed. For example, during each of these impurity ion implantation and impurity ion diffusion processes, the epitaxial layer 9 is subjected to a cleaning (light etching) process using hydrofluoric acid. As a result, the buried insulator 18 (silicon oxide film) is thinned. However, this thinning progresses isotropically, and the epitaxial layer 9 is insoluble in hydrofluoric acid. Therefore, by the time the gate insulating film 28 is formed, as shown in FIG. 6 , the corners of the buried insulator 18 are recessed inward from the upper edge of the trench 17, resulting in the formation of a recess 32 at the boundary 33 with the active region (in this embodiment, the p-side active region 13 p).

[0052] 7C , after the gate insulating film 28 is formed, the gate electrode 29 is formed. At this stage, it is not necessary to implant impurity ions into the gate electrode 29. In other words, the gate electrode 29 may be formed without adding impurities.

[0053] 7D, ion implantation is performed to form p-side source LDD regions and p-side drain LDD regions. Specifically, an n-type ion implantation step is performed for n-type source pocket implantation regions 42 and n-type drain pocket implantation regions 43, followed by a p-type ion implantation step for p-type source extension regions 40 and p-type drain extension regions 41. Next, referring to FIG. 7E, sidewalls 36 are formed around the gate electrode 29.

[0054] Next, the gate electrodes 29 of the first pattern, the second pattern, and the third pattern are formed through the steps of FIGS. 8A to 8C, 9A to 9C, and 10A to 10C, respectively.

[0055] 8A , with regard to the first pattern, a resist mask 52 is formed on the first main surface 10. The resist mask 52 has openings 53 corresponding to regions where the second semiconductor region 31 and the n-type back gate region 44 are to be formed. N-type impurity ions are implanted into the gate electrode 29 and the n-type well 37 through the resist mask 52. As a result, the gate electrode 29 is divided into the second semiconductor region 31 doped with n-type impurity ions and the first semiconductor region 30 to which no impurity ions are added. Furthermore, the n-type back gate region 44 is formed in the n-type well 37.

[0056] 8B , a resist mask 54 covering the n-type back gate region 44 is formed on the first main surface 10. P-type impurity ions are implanted into the gate electrode 29 and the n-type well 37 through the resist mask 54. As a result, a p-type source region 38p and a p-type drain region 39p are formed in a self-aligned manner with the gate electrode 29. In the second semiconductor region 31 of the gate electrode 29, p-type impurity ions are implanted, but this p-type is offset by the previously implanted n-type impurity ions. As a result, the second semiconductor region 31 is formed in which part of the p-type is offset by the n-type. Meanwhile, the first semiconductor region 30 is formed as a region doped with p-type impurities by the implanted p-type impurity ions.

[0057] 8C , silicide 35 is formed on gate electrode 29 by, for example, RTA (Rapid Thermal Annealing) processing. Next, interlayer insulating film 45 is formed, contacts are formed, and wiring is formed. By going through the above steps, the above-described semiconductor device 1 is obtained.

[0058] 9A , with regard to the second pattern, a resist mask 55 is formed on the first main surface 10. The resist mask 55 has openings 56 corresponding to regions where the second semiconductor region 31 and the n-type back gate region 44 are to be formed. N-type impurity ions are implanted into the gate electrode 29 and the n-type well 37 through the resist mask 55. This divides the gate electrode 29 into the second semiconductor region 31 doped with n-type impurity ions and the first semiconductor region 30 to which no impurity ions are added. Furthermore, the n-type back gate region 44 is formed in the n-type well 37.

[0059] 9B , a resist mask 57 is formed on the first main surface 10 to cover the second semiconductor region 31 and the n-type back gate region 44. P-type impurity ions are implanted into the gate electrode 29 and the n-type well 37 through the resist mask 57. As a result, a p-type source region 38p and a p-type drain region 39p are formed in a self-aligned manner with the gate electrode 29. In the first semiconductor region 30 of the gate electrode 29, a region doped with p-type impurities is formed by implanting the p-type impurity ions. On the other hand, since the second semiconductor region 31 is covered with the resist mask 57, the n-type property due to the previously implanted n-type impurity ions is maintained.

[0060] 9C , silicide 35 is then formed on gate electrode 29 by, for example, RTA (Rapid Thermal Annealing) processing. Next, interlayer insulating film 45 is formed, contacts are formed, and wiring is formed. By going through the above steps, the above-described semiconductor device 1 is obtained.

[0061] 10A , with regard to the third pattern, a resist mask 58 is formed on the first main surface 10. The resist mask 58 has an opening 59 corresponding to a region where the n-type back gate region 44 is to be formed. N-type impurity ions are implanted into the n-type well 37 through the resist mask 58. At this time, since the resist mask 58 is formed so as to cover the entire gate electrode 29, both the first semiconductor region 30 and the second semiconductor region 31 of the gate electrode 29 are regions to which no impurity ions are added.

[0062] 10B , a resist mask 60 is formed on the first main surface 10 to cover the second semiconductor region 31 and the n-type back gate region 44. P-type impurity ions are implanted into the gate electrode 29 and the n-type well 37 through the resist mask 60. As a result, a p-type source region 38p and a p-type drain region 39p are formed in a self-aligned manner with the gate electrode 29. In the first semiconductor region 30 of the gate electrode 29, a region doped with p-type impurities is formed by implanting the p-type impurity ions. On the other hand, since the second semiconductor region 31 is covered with the resist mask 60, it remains in a state where no impurity ions are added.

[0063] Thereafter, referring to FIG. 10C , silicide 35 is formed on the gate electrode 29 by, for example, RTA (Rapid Thermal Annealing). Next, an interlayer insulating film 45 is formed, contacts are formed, and wiring is formed. Through the above steps, the aforementioned semiconductor device 1 is obtained. [Effects of Semiconductor Device 1] According to the semiconductor device 1 according to the present disclosure, referring to FIG. 4 , the second semiconductor region 31 of the gate electrode 29 is formed at the first end 14 and the second end 15 of the p-side active region 13p so as to face the second channel region 24. This allows the gate threshold voltage at the first end 14 and the second end 15 of the p-side active region 13p to be higher than that at the central portion 16 of the p-side active region 13p. This allows the first channel region 23 to be preferentially and stably formed when a gate voltage is applied. As a result, the occurrence of a hump in the drain current-gate voltage (Ids-Vgs) characteristic can be suppressed. This effect can also be achieved in the n-side active region 13n by applying the same structure as the p-side planar gate structure 22p to the n-side planar gate structure 22n.

[0064] In FIG. 1, the structure of the low-breakdown-voltage n-channel transistor 6n corresponding to the p-type source region 38p, p-type drain region 39p, source contact 46, drain contact 47, and gate contact 48 is shown as an n-type source region 38n, an n-type drain region 39n, a source contact 46n, a drain contact 47n, and a gate contact 48n, respectively.

[0065] Furthermore, as shown in FIGS. 8A to 8C , 9A to 9C , and 10A to 10C , the first semiconductor region 30 and the second semiconductor region 31 of the gate electrode 29 are formed using resist masks 52, 54, 55, 57, 58, and 60 used when implanting impurity regions necessary for forming the CMOS transistor 4. In other words, since no additional layers are required, the semiconductor device can be manufactured using an existing manufacturing line, thereby suppressing cost increases. [Another Embodiment of Semiconductor Device 1] FIG. 11 is a schematic plan view of a semiconductor device 1 according to another embodiment of the present disclosure. FIG. 12 is a diagram showing a cross section taken along line XII-XII in FIG. 11 . FIG. 13 is a diagram showing a cross section taken along line XIII-XIII in FIG. 11 . Hereinafter, structures corresponding to those shown in FIGS. 1 to 6 are designated by the same reference numerals and will not be described again. In FIG. 11 , a recess 32 surrounding the entire periphery of each of the p-side active region 13p and the n-side active region 13n is indicated by a dashed line.

[0066] 11 to 13, a p-type well 62 for a low-breakdown-voltage n-channel transistor 6n is formed in a surface layer portion of epitaxial layer 9. The impurity concentration of p-type well 62 is higher than the impurity concentration of epitaxial layer 9, and is, for example, 1.0×10 １７ cm －３ Above 1.0 x 10 １９ cm －３ 11 , the p-type well 62 may have a structure similar to that shown in FIG. 11 . A low-breakdown-voltage n-channel transistor 6 n is formed in the p-type well 62. A p-type back gate region 63 is formed in the surface layer of the p-type well 62. The p-type back gate region 63 is electrically connected to the p-type well 62. The p-type back gate region 63 is omitted from FIG. 11 .

[0067] The p-type source region 38p and the p-type drain region 39p are formed as a pair with a gap therebetween in a surface layer portion of the n-type well 37. The p-type source region 38p and the p-type drain region 39p extend parallel to each other along the first direction X. The p-type source region 38p and the p-type drain region 39p may be formed in rectangular shapes of the same size and elongated along the first direction X in a plan view.

[0068] The n-type source region 38n and the n-type drain region 39n are formed as a pair with a gap therebetween in a surface layer portion of the p-type well 62. The n-type source region 38n and the n-type drain region 39n extend parallel to each other along the first direction X. The n-type source region 38n and the n-type drain region 39n may be formed in rectangular shapes of the same size and elongated along the first direction X in a plan view.

[0069] In both the p-side planar gate structure 22p and the n-side planar gate structure 22n, the gate body 25 is formed as a straight line extending along the first direction X. In the second direction Y, a p-type source region 38p is arranged on one side of the gate body 25 of the p-side planar gate structure 22p, and a p-type drain region 39p is arranged on the other side. In the second direction Y, an n-type source region 38n is arranged on one side of the gate body 25 of the n-side planar gate structure 22n, and an n-type drain region 39n is arranged on the other side.

[0070] 12 and 13 show a first channel region 23n, a second channel region 24n, an n-type source extension region 40n, an n-type drain extension region 41n, a p-type source pocket implantation region 42n, a p-type drain pocket implantation region 43n, a source wiring 49n, and a drain wiring 50n as the structure of the low-voltage n-type channel transistor 6n corresponding to the first channel region 23, the second channel region 24, the p-type source extension region 40, the p-type drain extension region 41, the n-type source pocket implantation region 42, the n-type drain pocket implantation region 43, the source wiring 49, and the drain wiring 50 of the low-voltage p-type channel transistor 6p, respectively.

[0071] The rest of the structure is similar to that shown in FIGS. 1 to 6 , and similar effects can be achieved. [Verification of Hump Suppression] FIG. 14 is a diagram showing the static characteristics of a low-voltage p-channel transistor 6p. FIG. 14 shows the change in drain current Ids versus gate voltage Vgs when the source is grounded and the drain voltage Vds is 0.1V. The dashed line shows the characteristics when the second semiconductor region 31 is not formed in the gate electrode 29 as a structure facing the second channel region 24, and the solid line shows the characteristics when the second semiconductor region 31 is formed. Furthermore, several characteristic curves show the characteristics when the back gate voltage BGV applied to the n-type back gate region 44 is set to 0V, −1V, −2V, −3V, −4V, and −5V, respectively.

[0072] 14 shows that if measures such as forming the second semiconductor region 31 in the gate electrode 29 are not taken, a hump, which is a phenomenon in which multiple threshold values ​​appear, occurs, and this tendency becomes more pronounced as the back gate voltage BGV increases. Note that while Fig. 14 shows an example of the characteristics of the low-voltage p-channel transistor 6p, a similar decrease also occurs in the low-voltage n-channel transistor 6n, medium-voltage CMOS transistors (n-type and p-type), and high-voltage CMOS transistors (n-type and p-type).

[0073] The hump is caused by the formation of a thin film portion 34 (see FIG. 6) in the gate oxide film corresponding to the recess 32, which causes partial conduction in this thin film portion 34. In the configuration in which the second semiconductor region 31 is formed in the gate electrode 29, the first channel region 23 can be preferentially and stably formed, thereby suppressing the hump. As a result, good static characteristics can be achieved even when the back gate voltage is increased.

[0074] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0075] For example, in the above description of the embodiments and accompanying drawings, n-type regions may be replaced with p-type regions, and p-type regions may be replaced with n-type regions.

[0076] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0077] The following characteristics can be extracted from the description of this specification and the drawings.

[0078] [Supplementary Note 1-1] A semiconductor device comprising: a chip having a main surface; a trench insulation structure formed on the main surface; a gate insulation film covering the main surface so as to be connected to the trench insulation structure; a polysilicon gate covering the trench insulation structure and the gate insulation film; a first semiconductor region formed in a portion of the polysilicon gate covering the gate insulation film, the first semiconductor region having a first threshold voltage having a relatively low absolute value; and a second semiconductor region formed in a portion of the polysilicon gate covering a boundary between the gate insulation film and the trench insulation structure, the second semiconductor region having a second threshold voltage having an absolute value relatively higher than the first threshold voltage.

[0079] [Supplementary Note 1-2] The semiconductor device according to Supplementary Note 1-1, wherein the second semiconductor region has an impurity concentration different from that of the first semiconductor region.

[0080] [Appendix 1-3] The semiconductor device according to appendix 1-1 or appendix 1-2, wherein the first semiconductor region is made of a region doped with either an n-type impurity or a p-type impurity, and the second semiconductor region is made of a region doped with both an n-type impurity and a p-type impurity.

[0081] [Supplementary Note 1-4] The semiconductor device according to Supplementary Note 1-3, wherein the second semiconductor region is formed by a region in which at least a portion of the conductivity type of the first semiconductor region is offset by an opposite conductivity type.

[0082] [Supplementary Note 1-5] The semiconductor device according to Supplementary Note 1-3 or Supplementary Note 1-4, wherein the second semiconductor region has a different conductivity type from that of the first semiconductor region.

[0083] [Supplementary Note 1-6] The semiconductor device according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the first semiconductor region is made of an impurity-doped region, and the second semiconductor region is made of an impurity-undoped region.

[0084] [Supplementary Note 1-7] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the second semiconductor region is formed at a distance from the periphery of the polysilicon gate.

[0085] [Supplementary Note 1-8] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-7, wherein the second semiconductor region is surrounded by the first semiconductor region.

[0086] [Supplementary Note 1-9] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-8, wherein the trench isolation structure includes a trench formed in the main surface and an insulator embedded in the main surface so as to expose an open end of the trench.

[0087] [Supplementary Note 1-10] The semiconductor device described in Supplementary Note 1-9, wherein the trench isolation structure includes a divot at an upper end of the insulator recessed toward a bottom wall of the trench so as to expose the open end of the trench, and the polysilicon gate has the second semiconductor region in a portion covering the divot.

[0088] [Supplementary Note 1-11] The semiconductor device according to any one of Supplementary Note 1-1 to Supplementary Note 1-10, wherein the trench isolation structure includes an isolation portion that partitions an active region on the main surface, the polysilicon gate extends across the active region in a first direction, and the semiconductor device includes a source region and a drain region that are formed in a surface layer portion of the main surface and are spaced apart from each other across the polysilicon gate in a second direction that intersects the first direction.

[0089] [Supplementary Note 1-12] The semiconductor device according to Supplementary Note 1-11, wherein the active region includes a low-breakdown-voltage active region in which a low-breakdown-voltage element having a rated voltage of 1.0 V or more and 4.0 V or less is formed.

[0090] [Supplementary Note 1-13] The semiconductor device according to Supplementary Note 1-11 or Supplementary Note 1-12, wherein the active region includes a medium-voltage active region in which a medium-voltage element having a rated voltage of 4.0V or more and 7.0V or less is formed.

[0091] 1: Semiconductor device 2: Semiconductor substrate 3: CMOS area 4: CMOS transistor 5: Low-voltage CMOS transistor 6n: Low-voltage n-channel transistor 6p: Low-voltage p-channel transistor 7: First main surface 8: Second main surface 9: Epitaxial layer 10: First main surface 11: Second main surface 12: Element isolation portion 13: LV-active region 13n: n-side active region 13p: p-side active region 14: First end 15: Second end 16: Central portion 17: Trench 18: Buried insulator 19: Side surface 20: Bottom surface 21: Opening end 22n: n-side planar gate structure 22p: p-side planar gate structure 23: First channel region 23n: First channel region 24 : Second channel region 24n : Second channel region 25 : Gate main body portion 26 : Gate contact portion 27 : Gate opening 28 : Gate insulating film 29 : Gate electrode 30 : First semiconductor region 31 : Second semiconductor region 32 : Recess 33 : Boundary portion 34 : Thin film portion 35 : Silicide 36 : Sidewall 37 : N-type well 38n : N-type source region 38p : P-type source region 39n : N-type drain region 39p : P-type drain region 40 : P-type source extension region 40n : N-type source extension region 41 : P-type drain extension region 41n : N-type drain extension region 42 : N-type source pocket implant region 42n : P-type source pocket implant region 43 : N-type drain pocket implant region 43n : p-type drain pocket implantation region 44 : n-type back gate region 45 : interlayer insulating film 46 : source contact 46n : source contact 47 : drain contact 47n : drain contact 48 : gate contact 48n : gate contact 49 : source wiring 49n : source wiring 50 : drain wiring 50n : drain wiring 51 : gate wiring 52 : resist mask 53 : opening 54 : resist mask 55 : resist mask 56 : opening57: Resist mask 58: Resist mask 59: Opening 60: Resist mask 61: Buried portion 62: P-type well 63: P-type back gate region

Claims

1. a chip having a major surface; a trench isolation structure formed in the major surface; a gate insulating film covering the main surface so as to be connected to the trench insulating structure; a polysilicon gate covering the trench insulating structure and the gate insulating film; a first semiconductor region formed in a portion of the polysilicon gate that covers the gate insulating film and having a first threshold voltage having a relatively low absolute value; a second semiconductor region formed in a portion of the polysilicon gate covering a boundary between the gate insulating film and the trench insulating structure, the second semiconductor region having a second threshold voltage having an absolute value relatively higher than the first threshold voltage.

2. The semiconductor device according to claim 1 , wherein said second semiconductor region has an impurity concentration different from that of said first semiconductor region.

3. the first semiconductor region is a region doped with either an n-type impurity or a p-type impurity, 3. The semiconductor device according to claim 1, wherein the second semiconductor region is a region doped with both n-type impurities and p-type impurities.

4. 4. The semiconductor device according to claim 3, wherein said second semiconductor region is formed by a region in which at least a part of the conductivity type of said first semiconductor region is offset by an opposite conductivity type.

5. The semiconductor device according to claim 3 , wherein the second semiconductor region has a different conductivity type from that of the first semiconductor region.

6. the first semiconductor region is an impurity doped region, 3. The semiconductor device according to claim 1, wherein the second semiconductor region is an undoped region.

7. 3. The semiconductor device according to claim 1, wherein said second semiconductor region is formed at a distance from a periphery of said polysilicon gate.

8. The semiconductor device according to claim 1 , wherein the second semiconductor region is surrounded by the first semiconductor region.

9. 3. The semiconductor device according to claim 1, wherein said trench isolation structure includes a trench formed in said main surface, and an insulator buried in said main surface so as to expose an open end of said trench.

10. the trench isolation structure includes a divot at an upper end of the insulator recessed toward a bottom wall of the trench to expose the open end of the trench; The semiconductor device according to claim 9 , wherein the polysilicon gate has the second semiconductor region in a portion covering the divot.

11. the trench isolation structure includes an isolation portion that defines an active region in the main surface; the polysilicon gate extends across the active area in a first direction; 3. The semiconductor device according to claim 1, further comprising a source region and a drain region formed in a surface layer portion of said main surface and spaced apart from each other with said polysilicon gate therebetween in a second direction intersecting said first direction.

12. 12. The semiconductor device according to claim 11, wherein said active region includes a low-voltage active region in which a low-voltage element having a rated voltage of 1.0 V or more and 4.0 V or less is formed.

13. 12. The semiconductor device according to claim 11, wherein said active region includes a medium withstand voltage active region in which a medium withstand voltage element having a rated voltage of 4.0V or more and 7.0V or less is formed.