Semiconductor device and method for producing semiconductor device

Abstract

This semiconductor device comprises a substrate, a passivation film that covers the substrate, a first resin film that is provided on the passivation film, a capacitor that is provided on the passivation film and is positioned above the first resin film, and an inductor that is provided on the passivation film and is formed in a layer differing from that of the capacitor.

Description

Semiconductor device and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] An LC resonant circuit, which includes a capacitor and an inductor, is an electrical circuit consisting of a coil, represented by L, and a capacitor, represented by C. The current between the coil and the capacitor varies depending on the resonant frequency of the circuit.

[0003] On the other hand, WL-CSP (Wafer Level-Chip Size Package) is known as one form of packaging for semiconductor devices. WL-CSP is a type of ultra-small integrated circuit known as CSP (Chip Size Package). WL-CSP is a technology in which devices such as inductors are fabricated on a wafer through a process in which a resin layer and conductive patterns are formed, and then the wafer is diced to separate the devices. In other words, it is a manufacturing method in which packaging is carried out on the wafer as is.

[0004] For example, Japanese Patent Application Laid-Open No. 2010-268304 discloses a resin multilayer device having a capacitor and a laminate circuit including an inductor. The resin multilayer device includes a substrate, a first resin layer formed on the substrate, a first conductive pattern group provided on the first resin layer, a second resin layer formed on the first resin layer and the first conductive pattern group, a second conductive pattern group provided on the second resin layer, and a third resin layer formed on the second resin layer and the second conductive pattern group. The capacitor includes a lower electrode of the first conductive pattern group and an upper electrode of the second conductive pattern group. The laminate circuit includes a lower circuit pattern of the first conductive pattern group and an upper circuit pattern of the second conductive pattern group. The lower electrode is provided so that the distance between the upper surface of the lower electrode and the lower surface of the upper electrode is smaller than the distance between the upper surface of the lower circuit pattern and the lower surface of the upper circuit pattern.

[0005] However, in order to adjust the resonant frequency of an LC resonant circuit, it is desirable to increase the inductance, but the coil diameter cannot be increased due to size restrictions of semiconductor devices. In the structure described in JP 2010-268304 A, the inductor and capacitor are formed on the same layer, so the device becomes larger in size in order to obtain the desired resonant frequency.

[0006] FIG. 11 is a cross-sectional view schematically showing a semiconductor device 100 according to the prior art.

[0007] 11, a semiconductor device 100 has a passivation film 102 and a pad electrode 106 provided on a substrate 101. A first resin film 201 is provided on the passivation film 102. A second resin film 202 is provided on the first resin film 201, and a third resin film 203 is provided on the second resin film 202. An electrode 105A is connected to the pad electrode 106. An electrode 105B is provided on the first resin film 201, and electrodes 105C and 105D are provided on the second resin film 202. These electrodes 105A to 105D form an inductor 105. The substrate 101 has an inherent capacitance that the IC has.

[0008] However, in the conventional structure shown in Fig. 11, since it depends on the inherent capacitance of the IC, the capacitance cannot be increased, making it difficult to obtain a desired resonant frequency.

[0009] The present disclosure has been made in consideration of the above circumstances, and aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can obtain a desired resonant frequency while miniaturizing the device.

[0010] In order to solve the above problem, a semiconductor device according to one embodiment of the present disclosure comprises a substrate, a passivation film covering the substrate, a first resin film provided on the passivation film, a capacitor provided on the passivation film and positioned above the first resin film, and an inductor provided on the passivation film and formed in a layer different from the capacitor.

[0011] Furthermore, in order to solve the above problem, a manufacturing method of a semiconductor device according to one embodiment of the present disclosure includes the steps of: forming a first resin film on a substrate on which a passivation film is formed; forming a first electrode of a capacitor on the first resin film; forming a high dielectric layer of the capacitor on the first electrode of the capacitor by an ALD method; forming a second electrode of the capacitor on the high dielectric layer of the capacitor; forming a second resin film on the second electrode of the capacitor; forming an inductor on the second resin film, and forming a circuit unit including the capacitor and the inductor; and forming a third resin film on the inductor included in the circuit unit.

[0012] Furthermore, in order to solve the above problem, another method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of: forming a first resin film on a substrate on which a passivation film is formed; forming a first electrode of a capacitor on the first resin film; forming a high dielectric layer of the capacitor on the first electrode of the capacitor by an ALD method; forming a second electrode of the capacitor on the high dielectric layer of the capacitor; forming a first magnetic film on the second electrode of the capacitor; forming an inductor on the first magnetic film, and forming a circuit unit including the capacitor and the inductor; and forming a second magnetic film on the inductor included in the circuit unit.

[0013] The technique of the present disclosure has the effect of making it possible to obtain a desired resonant frequency while miniaturizing the device.

[0014] 1A and 1B are cross-sectional views schematically illustrating a semiconductor device according to a first embodiment; FIG. 1B is a cross-sectional view schematically illustrating a semiconductor device according to a second embodiment; FIG. 1A is a cross-sectional view schematically illustrating a semiconductor device according to a third embodiment; FIG. 1B is a plan view schematically illustrating a semiconductor device according to a third embodiment; FIG. 1A and 1B are cross-sectional views schematically illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment; FIG. 1B is a cross-sectional view schematically illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment; FIG. 1B is a cross-sectional view schematically illustrating an example of a method for manufacturing a semiconductor device according to a third embodiment; FIG. 1C is a cross-sectional view schematically illustrating a semiconductor device according to a fourth embodiment; FIG. 1B is a plan view schematically illustrating a semiconductor device according to a fourth embodiment; FIG. 1C is a diagram illustrating an example of a simulation model according to the fourth embodiment; FIG. 1D is a diagram illustrating an example of a simulation model according to the fourth embodiment; FIG. 1A is a cross-sectional view schematically illustrating a semiconductor device according to a fifth embodiment; FIG. 1B is a plan view schematically illustrating a semiconductor device according to a fifth embodiment; and FIG. 1C is a cross-sectional view schematically illustrating a semiconductor device according to a conventional technique.

[0015] An example of an embodiment of the technology of the present disclosure will be described in detail below with reference to the drawings. Note that components and processes that perform the same operations, actions, and functions are given the same reference numerals throughout the drawings, and duplicated descriptions may be omitted as appropriate. Each drawing is merely a schematic illustration to allow a sufficient understanding of the technology of the present disclosure. Therefore, the technology of the present disclosure is not limited to the illustrated examples. Furthermore, in this embodiment, descriptions of configurations that are not directly related to the present disclosure or well-known configurations may be omitted.

[0016] First Embodiment FIG. 1 is a cross-sectional view schematically showing a semiconductor device 10 according to a first embodiment.

[0017] As shown in FIG. 1 , the semiconductor device 10 includes a substrate 11, a passivation film 12, a circuit unit 13, and a first resin film 21. The circuit unit 13 includes a capacitor 14 and an inductor 15. A semiconductor is formed on the substrate 11. The passivation film 12 covers the substrate 11. The circuit unit 13 is provided on the passivation film 12 and includes the capacitor 14 and the inductor 15. The first resin film 21 is provided between the passivation film 12 and the circuit unit 13. The capacitor 14 and the inductor 15 are provided in different layers. That is, the capacitor 14 is provided on the passivation film 12 and is located above the first resin film 21, and the inductor 15 is provided on the passivation film 12 and is formed in a different layer from the capacitor 14.

[0018] In this semiconductor device 10, the capacitor 14 and the inductor 15 are provided on different layers. That is, the capacitor 14 and the inductor 15 are arranged in the stacking direction within one chip. This structure allows the size of the capacitor 14 and the inductor 15 to be increased while miniaturizing the device, thereby making it possible to obtain a desired resonant frequency.

[0019] 1, the inductor 15 is provided above the capacitor 14, but the hierarchical relationship between the capacitor 14 and the inductor 15 may be reversed. In other words, the capacitor 14 may be provided above the inductor 15.

[0020] 1 , a substrate 11 has a pad electrode 16, and the pad electrode 16 is provided on the substrate 11. A passivation film 12 covers the main surface of the substrate 11 and has an opening above the pad electrode 16. The passivation film 12 is provided between a first resin film 21 and the substrate 11, and in this embodiment, the first resin film 21 is in contact with the passivation film 12. The first resin film 21 covers the passivation film 12 and the pad electrode 16 and has an opening above the pad electrode 16.

[0021] The semiconductor device 10 includes a first electrode 141. The first electrode 141 is connected to the pad electrode 16 through an opening in the first resin film 21 above the pad electrode 16. The opening in the first resin film 21 is aligned with the pad electrode 16. In other words, the first electrode 141 is formed integrally with the wiring conductor, is provided on the first resin film 21, extends along the first resin film 21 toward the pad electrode 16, and is connected to the pad electrode 16 through the opening in the first resin film 21.

[0022] The semiconductor device 10 includes an interlayer resin layer 24, a second electrode 142, a second resin film 22, and a third resin film 23. The interlayer resin layer 24 is provided on the first resin film 21 and the first electrode 141, and in this embodiment, is in contact with the first resin film 21 and the first electrode 141. The second electrode 142 is provided on the interlayer resin layer 24. The interlayer resin layer 24 is provided between the first electrode 141 and the second electrode 142. In other words, the capacitor 14 is configured to include the first electrode 141, the second electrode 142, and the interlayer resin layer 24. The capacitor 14 is provided between the first resin film 21 and the inductor 15. The second resin film 22 is provided on the interlayer resin layer 24 and the second electrode 142, and is a first layer provided between the capacitor 14 and the inductor 15. The third resin film 23 is provided on the second resin film 22 and the inductor 15.

[0023] 1, a second resin film 22 is provided between the inductor 15 and the capacitor 14, realizing a structure in which the inductor 15 and the capacitor 14 are aligned in the direction from the circuit section 13 toward the substrate 11, i.e., in the stacking direction. When viewed in the stacking direction, the inductor 15 is arranged so as to overlap at least a portion of the capacitor 14. This allows for further miniaturization of the device compared to a case in which the inductor 15 does not overlap the capacitor 14.

[0024] Here, for example, a silicon semiconductor substrate is used for the substrate 11. For example, aluminum (Al) is used for the pad electrode 16. For example, an inorganic insulating film, for example, a silicon nitride (SiN) film is used for the passivation film 12.

[0025] The first electrode 141 includes a titanium seed layer and a plated copper film (a conductive layer having the same level as the first electrode 141). An exemplary thickness range for the titanium seed layer is 100 nm to 300 nm, and an exemplary thickness range for the plated copper film is 1000 nm to 5000 nm. Similarly, the second electrode 142 includes a titanium seed layer and a plated copper film (a conductive layer having the same level as the second electrode 142). An exemplary thickness range for the titanium seed layer is 100 nm to 300 nm, and an exemplary thickness range for the plated copper film is 1000 nm to 5000 nm.

[0026] The first electrode 141 and the second electrode 142 can be formed of a metal such as platinum (Pt), iridium (Ir), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), molybdenum (Mo), tantalum (Ta), or ruthenium (Ru). These metals are formed by low-temperature film formation methods such as sputtering, electroless plating, and electrolytic plating. These film formation methods satisfy the constraints imposed on the processing temperature in processes after forming a resin film as an insulating film in the manufacturing process.

[0027] The first resin film 21 may be made of, for example, photosensitive polyimide, and the exemplary thickness range of the first resin film 21 directly below the capacitor 14 may be 2000 nm or more and 5000 nm or less. The first resin film 21 may be made of, for example, at least one of polyimide, polybenzoxazole, novolac resin, benzocyclobutene, phenol, and epoxy. These resins may have photosensitivity if possible.

[0028] The interlayer resin layer 24, the second resin film 22, and the third resin film 23 may be made of, for example, a photosensitive polyimide, with an exemplary thickness range of 2000 nm to 12000 nm. The interlayer resin layer 24 may be made of, for example, at least one of polyimide, polybenzoxazole, novolac resin, benzocyclobutene, phenol, and epoxy. These resins may have photosensitivity, if possible.

[0029] A coil is formed as the inductor 15. The coil is formed by arranging a wire having a substantially rectangular shape in a spiral when viewed from above. The shape of the coil is not limited to this, and the coil may be formed by arranging a wire having a circular or elliptical shape in a spiral.

[0030] As described above, the semiconductor device 10 according to this embodiment has a structure in which the capacitors 14 and the inductors 15 are aligned in the stacking direction, which allows the size of the capacitors 14 and the inductors 15 to be increased while miniaturizing the device, thereby making it possible to obtain a desired resonant frequency.

[0031] Second Embodiment In the first embodiment, a structure in which an interlayer resin layer is provided between a first electrode and a second electrode constituting a capacitor is described. In the second embodiment, a structure in which a high-dielectric layer is provided between the first electrode and the second electrode constituting a capacitor is described.

[0032] 2 is a cross-sectional view schematically illustrating a semiconductor device 10A according to a second embodiment. Note that the same components as those included in the semiconductor device 10 described in the first embodiment are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0033] The semiconductor device 10A shown in FIG. 2 includes a substrate 11, a passivation film 12, a circuit unit 13, a pad electrode 16, a first resin film 21, a second resin film 22, and a third resin film 23. The circuit unit 13 includes a capacitor 14 and an inductor 15. The capacitor 14 includes a first electrode 141, a second electrode 142, and a high-dielectric layer 143. That is, the semiconductor device 10A includes the high-dielectric layer 143 instead of the interlayer resin layer 24. The high-dielectric layer 143 is provided on the first electrode 141 and between the first electrode 141 and the second electrode 142. The capacitor 14 is provided between the first resin film 21 and the inductor 15. The second resin film 22 is provided on the first resin film 21, the first electrode 141, and the second electrode 142, and is a first layer provided between the capacitor 14 and the inductor 15. The third resin film 23 is provided on the second resin film 22 and the inductor 15 .

[0034] The high dielectric layer 143 may be made of, for example, tantalum oxide (Ta２ O ５ The high dielectric layer 143 is made of, for example, alumina (Al ２ O ３ ) is used, and the film thickness is, for example, 40 nm to 80 nm.

[0035] The high-dielectric layer 143 can be formed of at least one of, for example, tantalum oxide, alumina, hafnium oxide, titanium oxide, zirconium oxide, aluminum titanate, aluminum oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicate, and nitrogen-doped hafnium silicate. In the semiconductor device 10A, these inorganic films are formed while satisfying the constraints imposed on the processing temperature in the process after forming the resin film (e.g., the first resin film 21) in the manufacturing process. Specifically, the high-dielectric layer 143 is formed by, for example, atomic layer deposition (ALD). This ALD method can provide the reliability of the resin film.

[0036] As described above, in the semiconductor device 10A according to this embodiment, the high-dielectric layer 143 is uniformly formed between the first electrode 141 and the second electrode 142 that constitute the capacitor 14 using the ALD method. The high-dielectric layer 143, such as tantalum oxide or alumina, has a higher dielectric constant than the interlayer resin layer 24, such as polyimide, and therefore can stably obtain a large capacitance. In other words, since the capacitance can be increased without changing the size of the capacitor, it is possible to further miniaturize the device. Therefore, it is possible to obtain a desired resonant frequency while miniaturizing the device.

[0037] Third Embodiment In a third embodiment, a structure of a semiconductor device applied to an RF (Radio Frequency) tag will be described.

[0038] Fig. 3(A) is a cross-sectional view schematically showing a semiconductor device 10B according to a third embodiment. Fig. 3(B) is a plan view schematically showing the semiconductor device 10B according to the third embodiment. Fig. 3(A) shows a cross section taken along line XX' in Fig. 3(B). Note that the same components as those included in the semiconductor device 10A described in the second embodiment above are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0039] 3A includes a substrate 11, a passivation film 12, a circuit section 13, a pad electrode 16, a first resin film 21, a second resin film 22, a third resin film 23, and an electrode post 144. The circuit section 13 includes a capacitor 14 and an inductor 15. The capacitor 14 includes a first electrode 141, a second electrode 142, and a high-dielectric layer 143. The high-dielectric layer 143 is provided on the first resin film 21 and the first electrode 141. An electrode post 144 is connected to the central pad electrode 16 of the three pad electrodes 16.

[0040] The electrode post 144 can be formed from a metal such as platinum (Pt), iridium (Ir), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), molybdenum (Mo), tantalum (Ta), or ruthenium (Ru).

[0041] As shown in Fig. 3(B), when viewed from above, a coil is formed in a spiral shape as inductor 15. Also, when viewed from above, capacitor 14 is formed in a ring shape. The square in the center of the coil is electrode post 144 in Fig. 3(A), and the square of capacitor 14 is the point where first electrode 141 and pad electrode 16 are connected.

[0042] The semiconductor device 10B according to this embodiment is not provided with external electrodes because it is used in an RF tag. The semiconductor device 10B provides an RF tag having an LC resonant circuit that can obtain a desired resonant frequency within a size that fits within the dimensions of the device.

[0043] Next, a method for manufacturing the semiconductor device 10B according to this embodiment will be described with reference to FIGS. 4A, 4B, 5A, 5B, 6A, 6B, and 7.

[0044] 4A, 4B, 5A, 5B, 6A, 6B, and 7 are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 10B according to the third embodiment. The semiconductor device 10B according to this embodiment is manufactured by WL-CSP.

[0045] As shown in FIG. 4A, a substrate 11 on which a capacitor 14 is to be formed is prepared. As an example, one or more pad electrodes 16 (three in the example of FIG. 4A) and a passivation film 12 are formed on the substrate 11. The passivation film 12 is formed on the substrate 11 and is formed to have an opening above the pad electrode 16. For example, a silicon-based inorganic insulating film is used as the material for the passivation film 12. A first resin film 21 is formed on the passivation film 12. The first resin film 21 is formed to have an opening above the pad electrode 16.

[0046] Specifically, first, a resin layer for the first resin film 21 is formed by coating. The resin layer may contain a photosensitive or non-photosensitive resin, for example, at least one of polyimide, polybenzoxazole, novolac resin, benzocyclobutene, phenol, and epoxy. According to this manufacturing method, the resin layer covers the passivation film 12 that coats the substrate 11, providing a flat resin surface. In this embodiment, photosensitive polyimide is coated on the substrate 11.

[0047] After forming the resin layer, the resin layer is exposed using a photomask (e.g., a reticle) for pattern formation and the exposed resin layer is developed to form a first resin film 21 having one or more openings. In this embodiment, the openings are located above the pad electrodes 16 and reach the pad electrodes 16. Specifically, the first resin film 21 is formed from the resin layer by applying, exposing, developing, and baking the resin.

[0048] 4B, a first electrode 141 of the capacitor 14 is formed on the first resin film 21. The first electrode 141 is formed to extend along the first resin film 21 toward the pad electrode 16. The electrode post 144 is formed in an opening in the first resin film 21 above the pad electrode 16. As an example, a metal layer for the first electrode 141 and the electrode post 144 is formed using a plating method (electroless plating or electrolytic plating).

[0049] Specifically, after the first resin film 21 is formed, a seed film is formed on the entire surface of the substrate 11. The seed film is deposited by, for example, a sputtering method. The seed film includes, for example, a titanium (Ti) layer and has a film thickness of, for example, 100 nm to 300 nm. The film formation temperature by the sputtering method can be, for example, in the range of 25° C. to 150° C. The seed film is an integral film that covers the surface of the first resin film 21, the side surfaces of the openings in the first resin film 21, and the exposed upper surfaces of the pad electrodes 16.

[0050] Then, a mask is formed using photolithography to define the pattern of the plating film. The seed film appears in the openings of the mask. The openings of the mask define the areas where the first electrodes 141 and electrode posts 144 are to be formed.

[0051] In the plating process, a plating film is grown in the openings of the mask. Here, copper (Cu) is grown by plating. The plating film is not limited to copper (Cu) and is a conductive film that can be formed by electroless plating or electrolytic plating. The plating film has a thickness of, for example, 1000 nm to 5000 nm. The film formation temperature using the plating method can be, for example, in the range of 25°C to 50°C. When the mask is peeled off after the plating film is grown, a seed film appears in the area not covered by the plating film.

[0052] After the plating film is grown, the seed film is patterned by etching using the plating film as a mask to form a patterned seed layer. The first electrode 141 includes the seed layer and the plating film and is formed on the substrate 11. In one example, this etching is performed by wet etching. For example, an etchant such as hydrogen peroxide and potassium hydroxide is used to etch the titanium layer. The substrate temperature during the wet etching method may be, for example, in the range of 25°C to 50°C. When the patterning is complete, the surface of the first resin film 21 is revealed.

[0053] Sputtering can be used instead of plating to deposit the first electrode 141. By using sputtering, a metal layer for the first electrode 141 can be formed over the entire substrate surface after forming the first resin film 21 without forming a seed film. The substrate temperature during film formation by sputtering can be, for example, in the range of 25°C to 250°C. The formed metal film can be etched using a photolithography mask to form the first electrode 141. The substrate temperature during dry etching can be, for example, in the range of 25°C to 200°C.

[0054] The first electrode 141 may include at least one metal selected from the group consisting of platinum (Pt), iridium (Ir), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), molybdenum (Mo), tantalum (Ta), and ruthenium (Ru).

[0055] Next, as shown in FIG. 5A, a high dielectric layer 143 of the capacitor 14 is formed on the first electrode 141 of the capacitor 14 by the ALD method.

[0056] Specifically, after forming the first electrode 141, an insulating film for the high-dielectric layer 143 of the capacitor 14 is deposited on the entire surface of the substrate 11 by the ALD method. Here, the insulating film is a high-dielectric material, and the high-dielectric material may include at least one of tantalum oxide, alumina, hafnium oxide, titanium oxide, zirconium oxide, aluminum titanate, aluminum oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicate, and nitrogen-doped hafnium silicate. The film formation temperature in the ALD method may be, for example, 150° C. or higher and 300° C. or lower. Deposition of the insulating film by the ALD method enables the formation of a high-dielectric film for the capacitor 14 while satisfying the constraints imposed on the processing temperature in processes after forming the first resin film 21 in the manufacturing process.

[0057] Photolithography and etching are then used to fabricate the high-k dielectric layer 143 from the insulating film. A mask is formed on the insulating film by photolithography. The mask may be, for example, a resist, and covers the areas of the insulating film that are to remain as the high-k dielectric layer 143.

[0058] The insulating film is processed using a mask to form the high dielectric layer 143. For example, dry etching is used for the processing. For example, the tantalum oxide (Ta ２ O ５ ) is etched using CDCl3 + Cl2 (for example). ２ O ３ To etch the silicon dioxide film, CDCl3 + Cl2 (for example) is used as an etchant. The substrate temperature during the etching process can be in the range of, for example, 25 degrees Celsius to 150 degrees Celsius.

[0059] When the etching is completed, the openings in the mask reveal the top surfaces of the first electrodes 141 and the electrode posts 144. When the mask is peeled off after the etching, the high-dielectric layer 143 is revealed.

[0060] Next, as shown in FIG. 5B , the second electrode 142 of the capacitor 14 is formed on the high-dielectric layer 143 of the capacitor 14. Here, the second electrode 142 is formed on a portion of the high-dielectric layer 143. The portion where the first electrode 141, the second electrode 142, and the high-dielectric layer 143 are formed in the stacking direction serves as a capacitor. As an example, similar to the first electrode 141, metal layers for the second electrode 142 and the electrode post 144 are formed using a plating method (electroless plating or electrolytic plating). Note that the manufacturing method of the second electrode 142 is similar to the manufacturing method of the first electrode 141, and therefore a detailed description thereof will be omitted.

[0061] 6A, a second resin film 22 is formed on the second electrode 142 of the capacitor 14 and on the high-dielectric layer 143. As an example, similar to the first resin film 21, the second resin film 22 is formed from a resin layer by applying a resin, exposing it to light, developing it, and baking it. Note that the manufacturing method of the second resin film 22 is similar to the manufacturing method of the first resin film 21, and therefore a detailed description thereof will be omitted.

[0062] 6B, the inductor 15 is formed on the second resin film 22 to form the circuit section 13 including the capacitor 14 and the inductor 15. In other words, the second resin film 22 is a first layer provided between the capacitor 14 and the inductor 15.

[0063] Specifically, the inductor 15 is formed as a coil. This coil is formed by using photolithography and etching on the second resin film 22, for example, by forming a substantially rectangular wiring spirally in a top view. The capacitor 14 and the inductor 15 form the circuit unit 13. Note that it is desirable that the inductor 15 is formed so as to overlap at least a portion of the capacitor 14 when viewed in the stacking direction, which is the direction from the circuit unit 13 toward the substrate 11.

[0064] 7, a third resin film 23 is formed on the second resin film 22 and the inductor 15 included in the circuit section 13. As an example, similar to the first resin film 21, the third resin film 23 is formed from a resin layer by applying resin, exposing it to light, developing it, and baking it. Note that the manufacturing method of the third resin film 23 is similar to the manufacturing method of the first resin film 21, and therefore a detailed description thereof will be omitted.

[0065] The semiconductor device 10B is manufactured through the above steps. According to the manufacturing method of the semiconductor device 10B, the structure for the capacitor 14 is manufactured on the first resin film 21, and the structure for the inductor 15 is manufactured on the second resin film 22. This makes it possible to obtain a desired resonant frequency while miniaturizing the device, similar to the semiconductor device 10 described above. The resin film imposes restrictions on the processing temperature in processes after the resin film is formed in the manufacturing process, while providing a flat base for the capacitor 14 and the inductor 15. The ALD method enables film formation that satisfies the restrictions on the processing temperature in processes after the resin film is formed in the manufacturing process. By providing a flat base, the ALD method makes it possible to deposit a thin high-dielectric layer 143 for the capacitor 14.

[0066] Fourth Embodiment In a fourth embodiment, a structure will be described in which the second resin film and the third resin film in the structure of the semiconductor device described in the third embodiment are each replaced with a magnetic film.

[0067] Fig. 8(A) is a cross-sectional view schematically showing a semiconductor device 10C according to the fourth embodiment. Fig. 8(B) is a plan view schematically showing the semiconductor device 10C according to the fourth embodiment. Fig. 8(A) shows a cross section taken along line XX' in Fig. 8(B). Note that the same components as those included in the semiconductor device 10B described in the third embodiment above are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0068] 8A includes a substrate 11, a passivation film 12, a circuit section 13, a pad electrode 16, a first resin film 21, a first magnetic film 31, a second magnetic film 32, and an electrode post 144. The circuit section 13 includes a capacitor 14 and an inductor 15. The capacitor 14 includes a first electrode 141, a second electrode 142, and a high-dielectric layer 143. An electrode post 144 is connected to the central pad electrode 16 of the three pad electrodes 16. That is, the semiconductor device 10C includes a first magnetic film 31 instead of the second resin film 22 and a second magnetic film 32 instead of the third resin film 23.

[0069] As shown in Fig. 8(B), when viewed from above, a coil is formed in a spiral shape as inductor 15. Also, when viewed from above, capacitor 14 is formed in a ring shape. The square in the center of the coil is electrode post 144 in Fig. 8(A), and the square of capacitor 14 is the point where first electrode 141 and pad electrode 16 are connected.

[0070] As described above, according to the semiconductor device 10C of this embodiment, by providing the first magnetic film 31 acting as a shield between the inductor 15 and the capacitor 14, and preferably by providing the second magnetic film 32 also on the inductor 15, it is possible to eliminate restrictions on the placement of the capacitor 14. The first magnetic film 31 is a first layer provided between the inductor 15 and the capacitor 14.

[0071] Regarding the process for forming the magnetic film of the semiconductor device 10C, in the manufacturing process of the semiconductor device 10B described above, the process for forming the second resin film 22 can be changed to the process for forming the first magnetic film 31, and the process for forming the third resin film 23 can be changed to the process for forming the second magnetic film 32.

[0072] Next, with reference to FIGS. 9A to 9D, the results of a simulation carried out to verify whether or not the inductance changes depending on the placement location of the capacitor will be described.

[0073] 9A to 9D are diagrams showing an example of a simulation model according to the fourth embodiment. The capacitor is formed on the top surface, and an example of a pattern in which the capacitor is disposed on a magnetic body is shown. The capacitor is made of copper (Cu).

[0074] The actual inductance (unit: nH) was measured for each of the capacitor arrangement patterns shown in Figures 9(A) to 9(D). In this simulation example, the volume of the arranged capacitor was 0.09124 mm ３ ] and the frequency is 6.00 [MHz]. The inductance of the simulation model (Sim Model Ref) without a capacitor was 114 [nH] (this is the reference value). On the other hand, the measured values ​​for each of the capacitor layout patterns shown in Figures 9(A) to 9(D) were within a range of approximately 96% or more of the reference value, indicating that there was almost no difference. In other words, it can be said that there are no restrictions on the layout of the capacitors as long as no current is applied to the board.

[0075] Fifth Embodiment In a fifth embodiment, a structure of a semiconductor device applied to a DA (Digital-Analog) converter or the like will be described.

[0076] Fig. 10(A) is a cross-sectional view schematically showing a semiconductor device 10D according to the fifth embodiment. Fig. 10(B) is a plan view schematically showing the semiconductor device 10D according to the fifth embodiment. Fig. 10(A) shows a cross section taken along line XX' in Fig. 10(B). Note that the same components as those included in the semiconductor device 10B described in the third embodiment above are denoted by the same reference numerals, and repeated description thereof will be omitted.

[0077] The semiconductor device 10D shown in FIG. 10A includes a substrate 11, a passivation film 12, a circuit section 13, pad electrodes 16, a first resin film 21, a second resin film 22, a third resin film 23, an electrode post 144, and an external electrode 40. The circuit section 13 includes a capacitor 14 and an inductor 15. The capacitor 14 includes a first electrode 141, a second electrode 142, and a high-dielectric layer 143. Of the five pad electrodes 16, three pad electrodes 16 at the center and both ends are connected to electrode posts 144. External electrodes 40 are provided on the electrode posts 144 connected to the pad electrodes 16 at both ends. The external electrodes 40 are connected to the pad electrodes 16 via the electrode posts 144 and protrude outward. The external electrodes 40 are, for example, solder terminals. The solder for the solder terminals may be, for example, Sn3.0Ag0.5Cu.

[0078] As shown in Fig. 10(B), when viewed from above, a coil is formed in a spiral shape as inductor 15. Also, when viewed from above, capacitor 14 is formed in a ring shape. The square in the center of the coil is electrode post 144 in Fig. 10(A), and the square of capacitor 14 is the point where first electrode 141 and pad electrode 16 are connected. Also, when viewed from above, a plurality of external electrodes 40, indicated by circles, are formed along the outer frame of substrate 11.

[0079] The semiconductor device 10D according to this embodiment is applied to a DA converter or the like, and is therefore formed with an external electrode 40. The semiconductor device 10D provides a DA converter or the like that includes an LC resonant circuit that can obtain a desired resonant frequency in a size that fits within the dimensions of the device.

[0080] The process for manufacturing the semiconductor device 10D can be achieved by adding a process for forming the electrode posts 144 and the external electrodes 40 on both ends to the process for manufacturing the semiconductor device 10B.

[0081] It should be noted that the configurations of the semiconductor device and the manufacturing method thereof described in the above embodiments are merely examples, and it goes without saying that the configurations may be changed within the scope of the gist of the embodiments.

[0082] The disclosure of Japanese Patent Application No. 2022-060512, filed on March 31, 2022, is incorporated herein by reference in its entirety. All documents, patent applications, and technical standards described herein are incorporated herein by reference to the same extent as if each individual document, patent application, and technical standard was specifically and individually indicated to be incorporated by reference.

Claims

1. A substrate; a passivation film covering the substrate; a first resin film provided on the passivation film; a capacitor provided on the passivation film and positioned above the first resin film; an inductor provided on the passivation film and formed in a layer different from that of the capacitor; A semiconductor device comprising:

2. The inductor overlaps at least a portion of the capacitor in a lamination direction that is a direction from the capacitor and the inductor toward the substrate. The semiconductor device according to claim 1 .

3. The capacitor is A first electrode; A second electrode; an interlayer resin layer provided between the first electrode and the second electrode; Includes The semiconductor device according to claim 1 or 2.

4. The capacitor is A first electrode; A second electrode; a high dielectric layer provided between the first electrode and the second electrode; Includes The semiconductor device according to claim 1 or 2.

5. The high dielectric layer is formed of at least one of tantalum oxide, alumina, hafnium oxide, titanium oxide, zirconium oxide, aluminum titanate, aluminum oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicate, and nitrogen-added hafnium silicate. The semiconductor device according to claim 4.

6. the substrate has a pad electrode; the first electrode is connected to the pad electrode through an opening in the first resin film; The opening of the first resin film is aligned with the pad electrode. The semiconductor device according to claim 3 .

7. The semiconductor device further includes a second resin film provided between the capacitor and the inductor. The semiconductor device according to claim 1 or 2.

8. The semiconductor device further includes a third resin film provided on a circuit portion including the capacitor and the inductor. The semiconductor device according to claim 7.

9. The semiconductor device further includes a first magnetic film provided between the capacitor and the inductor. The semiconductor device according to claim 1 or 2.

10. a second magnetic film provided on the circuit portion including the capacitor and the inductor; Prepared The semiconductor device according to claim 9.

11. The capacitor is provided between the first resin film and the inductor. The semiconductor device according to claim 1 or 2.

12. forming a first resin film on the substrate on which the passivation film is formed; forming a first electrode of a capacitor on the first resin film; forming a high dielectric layer of the capacitor on the first electrode of the capacitor by an ALD method; forming a second electrode of the capacitor on the high dielectric layer of the capacitor; forming a second resin film on the second electrode of the capacitor; forming an inductor on the second resin film and forming a circuit portion including the capacitor and the inductor; forming a third resin film on the inductor included in the circuit portion; Includes A method for manufacturing a semiconductor device.

13. forming a first resin film on the substrate on which the passivation film is formed; forming a first electrode of a capacitor on the first resin film; forming a high dielectric layer of the capacitor on the first electrode of the capacitor by an ALD method; forming a second electrode of the capacitor on the high dielectric layer of the capacitor; forming a first magnetic film on the second electrode of the capacitor; forming an inductor on the first magnetic film and forming a circuit portion including the capacitor and the inductor; forming a second magnetic film on the inductor included in the circuit section; Includes A method for manufacturing a semiconductor device.