Semiconductor device

Abstract

Provided is a transistor that can be miniaturized. Provided is a transistor that occupies a small area. A semiconductor device for providing a transistor having a short channel length has a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first electroconductive layer. The side surface of the first insulating layer is positioned on the first electrode. The second electrode is positioned on the first insulating layer. The semiconductor layer is in contact with the first electrode, the side surface of the first insulating layer, and the second electrode. The gate insulating layer has a portion facing the side surface with the semiconductor layer interposed therebetween. The gate electrode has a portion facing the side surface with the gate insulating layer and the semiconductor layer interposed therebetween. The first electroconductive layer is in contact with the gate electrode, has a portion facing the side surface with the gate electrode, the gate insulating layer, and the semiconductor layer interposed therebetween, and has a portion that is thicker than the gate electrode.

Description

Semiconductor Devices

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] There is a demand for miniaturization of transistors. For example, when applying transistors to high-definition display devices, efforts are being made to reduce the area occupied by transistors in order to reduce pixel size.

[0004] In recent years, display panels have become increasingly high-definition. As devices requiring high-definition display panels, for example, devices for virtual reality (VR) or augmented reality (AR) have been actively developed in recent years. High-definition display panels mainly use light-emitting elements such as organic electroluminescence (EL) elements or light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a high-definition display device using an organic EL device (also called an organic EL element).

[0006] International Publication No. 2016 / 038508

[0007] An object of one embodiment of the present invention is to provide a transistor that can be miniaturized. Another object is to provide a transistor whose channel length can be shortened. Another object is to provide a transistor that occupies a small area. Another object is to provide a semiconductor device with reduced wiring resistance. Another object is to provide a display device that can easily be made high-definition. Another object is to provide a highly reliable transistor and semiconductor device.

[0008] An object of one embodiment of the present invention is to provide a transistor, a display device, and an electronic device each having a novel structure.An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention is a semiconductor device including a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first conductive layer. The first insulating layer has a side surface located on the first electrode. The second electrode is located on the first insulating layer. The semiconductor layer is in contact with the first electrode, the side surface of the first insulating layer, and the second electrode. The gate insulating layer has a portion facing the side surface of the first insulating layer with the semiconductor layer interposed therebetween. The gate electrode has a portion facing the side surface of the first insulating layer with the gate insulating layer and the semiconductor layer interposed therebetween. The first conductive layer is in contact with the gate electrode and has a portion facing the side surface of the first insulating layer with the gate electrode, gate insulating layer, and semiconductor layer interposed therebetween, and has a portion that is thicker than the gate electrode.

[0011] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first conductive layer. The first insulating layer has an opening. A side surface of the first insulating layer in the opening is located on the first electrode. The second electrode is located on the first insulating layer. The semiconductor layer, the gate insulating layer, the gate electrode, and the first conductive layer each have portions located inside the opening. The semiconductor layer is in contact with the first electrode, the side surface of the first insulating layer, and the second electrode. The gate insulating layer has a portion facing the side surface of the first insulating layer with the semiconductor layer interposed therebetween. The gate electrode has a portion facing the side surface of the first insulating layer with the gate insulating layer and the semiconductor layer interposed therebetween. The first conductive layer is in contact with the gate electrode and has a portion facing the side surface of the first insulating layer with the gate electrode, the gate insulating layer, and the semiconductor layer interposed therebetween, and has a portion that is thicker than the gate electrode.

[0012] Another embodiment of the present invention is a semiconductor device including a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first conductive layer. The first insulating layer has a slit. A side surface of the first insulating layer is located on the first electrode. The second electrode is located on the first insulating layer. The semiconductor layer, the gate insulating layer, the gate electrode, and the first conductive layer each have a portion located inside the slit. The semiconductor layer is in contact with the first electrode, a side surface of the first insulating layer, and the second electrode. The gate insulating layer has a portion facing the side surface of the first insulating layer with the semiconductor layer interposed therebetween. The gate electrode has a portion facing the side surface of the first insulating layer with the gate insulating layer and the semiconductor layer interposed therebetween. The first conductive layer is in contact with the gate electrode and has a portion facing the side surface of the first insulating layer with the gate electrode, the gate insulating layer, and the semiconductor layer interposed therebetween, and has a portion that is thicker than the gate electrode.

[0013] In any of the above, it is preferable that a second insulating layer is further provided, and in this case, it is preferable that the height of the upper surface of the first conductive layer and the height of the upper surface of the second insulating layer are approximately the same.

[0014] In any of the above, the semiconductor layer preferably contains a metal oxide, and in this case, the first electrode preferably contains a metal oxide having a different composition from that of the semiconductor layer.

[0015] In the above, it is preferable that a second conductive layer is provided. In this case, it is preferable that the first electrode has a portion in contact with an upper surface of the second conductive layer. It is also preferable that the second conductive layer contains a metal or an alloy.

[0016] In any of the above, the semiconductor layer preferably has a first portion in contact with the upper surface of the first electrode, a second portion in contact with the side surface of the first insulating layer, and a third portion located above the first insulating layer, and in this case, the thickness of the second portion is preferably thinner than the first and third portions.

[0017] In any of the above, it is preferable that the first electrode has a portion where the angle formed between the side surface of the first insulating layer and the upper surface of the first electrode is 90 degrees or more and 120 degrees or less.

[0018] In any of the above, it is preferable that the side surface of the first insulating layer has an uneven shape.

[0019] In any of the above, the semiconductor layer is preferably in contact with an upper surface of the second electrode. The semiconductor layer preferably contains a metal oxide. The second electrode preferably contains a metal oxide having a different composition from that of the semiconductor layer.

[0020] In the above, it is preferable that the device further includes a third conductive layer. In this case, it is preferable that the second electrode has a portion in contact with the third conductive layer. It is preferable that the third conductive layer further includes a metal or an alloy.

[0021] According to one embodiment of the present invention, a transistor that can be miniaturized can be provided. Alternatively, a transistor whose channel length can be reduced can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a semiconductor device with reduced wiring resistance can be provided. Alternatively, a display device that can easily be made high-definition can be provided. Alternatively, a highly reliable transistor and semiconductor device can be provided.

[0022] According to one aspect of the present invention, it is possible to provide a transistor, a display device, and an electronic device having a novel configuration, and it is possible to at least alleviate at least one of the problems of the prior art.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0024] FIGS. 1A to 1C are diagrams showing structural examples of a semiconductor device. FIGS. 2A and 2B are diagrams showing structural examples of a semiconductor device. FIGS. 3A to 3D are diagrams showing structural examples of a semiconductor device. FIGS. 4A and 4B are diagrams showing structural examples of a semiconductor device. FIGS. 5A and 5B are diagrams showing structural examples of a semiconductor device. FIGS. 6A and 6B are diagrams showing structural examples of a semiconductor device. FIGS. 7A and 7B are diagrams showing structural examples of a semiconductor device. FIG. 8 is a diagram showing a structural example of a semiconductor device. FIGS. 9A to 9H are diagrams showing structural examples of a semiconductor device. FIGS. 10A1, 10A2, 10B1, and 10B2 are diagrams showing structural examples of a semiconductor device. FIGS. 11A1, 11A2, 11B1, and 11B2 are diagrams showing structural examples of a semiconductor device. FIGS. 12A1, 12A2, 12B1, 12B2, 12C1, and 12C2 are diagrams illustrating a manufacturing method of a semiconductor device. 13A1, 13A2, 13B1, 13B2, 13C1, and 13C2 are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 14A and 14B are diagrams illustrating a structural example of a semiconductor device. FIGS. 15A and 15B are diagrams illustrating a structural example of a display device. FIG. 16 is a diagram illustrating a structural example of a display device. FIG. 17 is a diagram illustrating a structural example of a display device. FIG. 18 is a diagram illustrating a structural example of a display device. FIGS. 19A to 19C are diagrams illustrating a structural example of a display device. FIGS. 20A and 20B are diagrams illustrating a structural example of a display device. FIGS. 21A to 21D are diagrams illustrating a structural example of an electronic device. FIGS. 22A to 22F are diagrams illustrating a structural example of an electronic device. FIGS. 23A to 23G are diagrams illustrating a structural example of an electronic device.

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0028] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0029] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0032] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.

[0033] In this specification, the phrase "top surface shapes generally match" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where only a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In this case, the phrase "top surface shapes generally match" may also be used. In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. Furthermore, a plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.

[0034] In the following description, expressions indicating directions such as "up" and "down" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided in the drawing (such as the surface to be formed, the supporting surface, the adhesive surface, or the flat surface) is located above the laminate, the direction toward the surface may be expressed as "down" and the opposite direction as "up."

[0035] Embodiment 1 In this embodiment, a structure example of a transistor and a manufacturing method thereof will be described as an example of a semiconductor device according to one embodiment of the present invention.

[0036] A transistor according to one embodiment of the present invention includes a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, and a second electrode. The first electrode functions as one of a source electrode and a drain electrode, and the second electrode functions as the other.

[0037] The second electrode is provided above the first electrode. An insulating layer functioning as a spacer is provided between the first electrode and the second electrode. An opening or a slit (groove) reaching the first electrode is provided in the insulating layer, and the semiconductor layer is provided in contact with the first electrode, the second electrode, and a sidewall (also referred to as a side surface) in the opening of the insulating layer or a sidewall of the slit. A gate insulating layer and a gate electrode are provided to cover the semiconductor layer.

[0038] In a transistor having the above structure, the source electrode and the drain electrode are located at different heights, so that a current flows in the semiconductor layer in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can also be called a vertical transistor, a vertical channel transistor, or the like.

[0039] In the above transistor, the source electrode, the semiconductor layer, and the drain electrode can be provided in a stacked manner, and therefore the occupied area can be dramatically reduced compared to a so-called planar transistor in which the semiconductor layer is arranged on a plane.

[0040] Furthermore, since the channel length of a transistor can be precisely controlled by the thickness of the insulating layer, the variation in channel length can be significantly reduced compared to planar transistors. Furthermore, by thinning the insulating layer, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using conventional exposure equipment for mass production of flat panel displays (e.g., minimum line widths of approximately 2 μm or 1.5 μm) can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0041] The channel length of a transistor can be controlled not only by the thickness of the insulating layer but also by its shape. For example, if the side surface of the insulating layer is inclined upward, the channel length can be made longer than when it is vertical. Also, if the side surface of the insulating layer has an uneven shape, the channel length can be made longer than when it is flat.

[0042] The semiconductor layer is preferably made of a metal oxide (also called an oxide semiconductor) having semiconductor properties, since it can achieve both high performance and high productivity. In particular, the use of a crystalline oxide semiconductor is more preferable, since it can provide high reliability.

[0043] When a transistor is provided using an opening in an insulating layer, the inner diameter of the opening corresponds to the channel width of the transistor. The smaller the diameter of the opening, the finer the transistor can be manufactured. On the other hand, since a semiconductor layer, a gate insulating layer, and a gate electrode are provided inside the opening, it is preferable that the thicknesses of these layers are sufficiently thin compared to the diameter of the opening (for example, 1 / 10 or less of the diameter of the opening).

[0044] On the other hand, since a thin gate electrode increases electrical resistance, it is preferable to use a conductive layer (first conductive layer) that functions as wiring separately from the gate electrode. In this case, the first conductive layer and the gate electrode are preferably connected at a position that overlaps an opening provided in the insulating layer. This allows the connection portion between the first conductive layer and the gate electrode to be arranged overlapping the transistor. Furthermore, the first conductive layer is preferably provided so as to fill a recess in the surface of the gate electrode caused by the opening in the insulating layer. This increases the contact area between the gate electrode and the first conductive layer, thereby reducing their contact resistance.

[0045] Furthermore, when an oxide semiconductor is used for the semiconductor layer, when a film containing the oxide semiconductor (oxide semiconductor film) is formed on the first electrode, a part of the first electrode is oxidized and becomes highly resistive, which may increase the contact resistance between the semiconductor layer and the first electrode or prevent electrical continuity between them. Therefore, it is preferable to use, for the first electrode, a conductive material that is resistant to oxidation (such as a metal, an alloy, or a metal nitride), a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0046] On the other hand, when the first electrode is made of the conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material, the conductivity may be insufficient. Therefore, it is preferable to provide a second conductive layer that electrically connects to the first electrode. In this case, it is preferable to arrange the second conductive layer below the first electrode. Furthermore, it is preferable to connect the second conductive layer and the first electrode at a position that overlaps with an opening provided in the insulating layer. This allows the connection portion between the first electrode and the second conductive layer to be arranged overlapping the transistor.

[0047] A more specific example will be described below with reference to the drawings.

[0048] [Configuration Example 1] Fig. 1A shows a schematic top view of a transistor 10. Fig. 1B and Fig. 1C show schematic cross-sectional views corresponding to the cutting lines A1-A1 and B1-B2 in Fig. 1A, respectively. Note that in the schematic top view, some components (e.g., insulating layers) are not shown to make the view easier to see.

[0049] The transistor 10 is provided over a substrate 11 and includes a semiconductor layer 21, an insulating layer 22, a conductive layer 23, a conductive layer 24, and a conductive layer 25. A part of the insulating layer 22 functions as a gate insulating layer, a part of the conductive layer 23 functions as a gate electrode, a part of the conductive layer 24 functions as one of a source electrode and a drain electrode, and a part of the conductive layer 25 functions as the other of the source electrode and the drain electrode.

[0050] A conductive layer 14 is provided on the substrate 11. The conductive layer 14 is electrically connected to the conductive layer 24 and functions as wiring. As shown in FIG. 1B and other figures, the conductive layer 14 is preferably embedded in an insulating layer 31 that functions as an interlayer insulating layer. In this case, it is preferable that the height of the upper surface of the conductive layer 14 and the height of the upper surface of the insulating layer 31 are approximately the same.

[0051] In this specification and the like, "approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the surface of a substrate) are approximately the same in a cross-sectional view. For example, the heights of the processed surfaces when a planarization process (typically a CMP (Chemical Mechanical Polishing) process) is performed are approximately the same. However, even when the planarization process is performed, the heights may not strictly match depending on the film material, etc., but in this specification and the like, this case is also considered to be "approximately the same height."

[0052] A conductive layer 24 is provided in contact with the upper surface of the conductive layer 14. As shown in Fig. 1B and other figures, the conductive layer 24 may be embedded in an insulating layer 32 that functions as an interlayer insulating layer.

[0053] Insulating layers 29a, 28, and 29b are provided to cover a portion of conductive layer 24 and insulating layer 32. Furthermore, conductive layer 25 is provided on insulating layer 29b. Furthermore, openings 20 that reach conductive layer 24 are provided in conductive layer 25, insulating layer 29b, insulating layer 28, and insulating layer 29a. In other words, the side walls (side surfaces) of conductive layer 25, insulating layer 29b, insulating layer 28, and insulating layer 29a at openings 20 overlap conductive layer 24.

[0054] The semiconductor layer 21 is in contact with the upper surface of the conductive layer 24 located at the bottom of the opening 20, the side surfaces of the insulating layer 29a, the side surfaces of the insulating layer 28, the side surfaces of the insulating layer 29b, and the side surfaces of the conductive layer 25 in the opening 20, and the upper surface of the conductive layer 25. The portion of the semiconductor layer 21 in contact with the conductive layer 25 functions as one of the source region or the drain region, and the portion in contact with the conductive layer 24 functions as the other, and the region between them (particularly the region in contact with the insulating layer 28) functions as a region where a channel is formed (channel formation region). It is preferable that the region of the semiconductor layer 21 in contact with the insulating layer 29a and the region in contact with the insulating layer 29b have a higher carrier concentration and lower resistance than the channel formation region.

[0055] An insulating layer 22 functioning as a gate insulating layer is provided to cover the insulating layer 29b, the conductive layer 25, and the semiconductor layer 21. Further, a conductive layer 23 functioning as a gate electrode is provided to cover the insulating layer 22.

[0056] As described above, the semiconductor layer 21 has a portion that contacts the side surface of the insulating layer 28 and functions as a channel formation region. The insulating layer 22 has a portion that faces the side surface of the insulating layer 28 with the semiconductor layer 21 interposed therebetween. The conductive layer 23 also has a portion that faces the side surface of the insulating layer 28 with the semiconductor layer 21 and the insulating layer 22 interposed therebetween. The interface between the semiconductor layer 21 and the insulating layer 22 and the interface between the insulating layer 22 and the conductive layer 23 have portions that are parallel to the side surface of the insulating layer 28.

[0057] Insulating layer 33 and insulating layer 39 are laminated to cover insulating layer 22 and conductive layer 23. An insulating layer 34, which functions as an interlayer insulating layer, and a conductive layer 13 embedded in insulating layer 34 are provided on insulating layer 39. Openings are provided in insulating layer 39 and insulating layer 33 at positions overlapping conductive layer 24. Conductive layer 23 is provided to cover opening 20, and thus has a recess (depression) on its upper surface. Conductive layer 13 is provided to fill the openings in insulating layer 39 and insulating layer 33, and the recesses in conductive layer 23. This increases the contact area between conductive layer 23 and conductive layer 13, thereby reducing the contact resistance therebetween and also increasing mechanical strength.

[0058] The conductive layer 13 is electrically connected to the conductive layer 23 and functions as wiring. Since the conductive layer 23 is provided inside the opening 20, its thickness needs to be sufficiently thinner than the diameter of the opening 20 (for example, 1 / 5 or less, or 1 / 10 or less), and therefore the electrical resistance may not be sufficiently reduced. For this reason, it is preferable to dispose a conductive layer 13 that is thicker than the conductive layer 23 and has low electrical resistance in contact with the conductive layer 23.

[0059] The conductive layer 13 is located above the insulating layer 39, and the portion embedded in the insulating layer 34 functions as wiring. The upper surfaces of the conductive layer 13 and the insulating layer 34 are planarized, and the heights of the upper surfaces are approximately the same.

[0060] The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0061] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, ZO, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with gallium being more preferred. Hereinafter, a metal oxide containing indium, M, and zinc may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0062] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0063] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0064] The semiconductor layer 21 may be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, etc. Ga—Zn oxide may also be used.

[0065] Note that the metal oxide may contain one or more metal elements with a large periodicity instead of or in addition to indium. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a large periodicity may improve the field-effect mobility of a transistor. Examples of metal elements with a large periodicity include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0066] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0067] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). When the metal oxide is formed by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.

[0068] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B ｘ / (B ｘ +B Ｙ +B Ｚ ) can be shown as

[0069] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0070] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0071] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0072] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0073] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers having different compositions are stacked may also be used.

[0074] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0075] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0076] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0077] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because an OS transistor has a higher source-drain breakdown voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0078] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger gradation in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0079] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of variations in light-emitting devices," and the like.

[0080] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, proton rays, and neutron rays).

[0081] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0082] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0083] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0084] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0085] The upper surfaces of the conductive layers 24 and 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used for the conductive layer 24 or the conductive layer 25, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use, for the conductive layer 24 and the conductive layer 25, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material.

[0086] For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used for the conductive layers 24 and 25. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferred.

[0087] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, silicon-containing In—Sn oxide, and zinc oxide doped with gallium can be used. In particular, conductive oxides containing indium are preferred because of their high conductivity.

[0088] The insulating layer 22 functions as a gate insulating layer. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0089] In this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen.

[0090] The conductive layer 23 functions as a gate electrode and may be made of various conductive materials. The conductive layer 23 may be made of, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the above-mentioned metals. The nitrides and oxides that can be used for the conductive layers 24 and 25 may also be used for the conductive layer 23.

[0091] The insulating layer 28 has a portion in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide for at least the portion of the insulating layer 28 in contact with the semiconductor layer 21 in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 28. For example, silicon oxide or silicon oxynitride can be suitably used.

[0092] It is more preferable to use a film that releases oxygen when heated for the insulating layer 28. This allows oxygen to be supplied to the semiconductor layer 21 by heat applied during the manufacturing process of the transistor 10, thereby reducing oxygen vacancies in the semiconductor layer 21 and improving reliability. Methods for supplying oxygen to the insulating layer 28 include heat treatment in an oxygen atmosphere and plasma treatment in an oxygen atmosphere. Alternatively, oxygen may be supplied by forming an oxide film on the top surface of the insulating layer 28 in an oxygen atmosphere by sputtering. The oxide film may then be removed.

[0093] The insulating layer 28 is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. In particular, by using a sputtering method without using hydrogen gas as a deposition gas, a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0094] It is preferable that the insulating layers 29a and 29b are made of films through which oxygen does not easily diffuse. This prevents oxygen contained in the insulating layer 28 from permeating through the insulating layer 29a to the insulating layer 32 side and from permeating through the insulating layer 29b to the insulating layer 33 side due to heating. In other words, by sandwiching the insulating layer 28 between the insulating layers 29a and 29b, through which oxygen does not easily diffuse, the oxygen contained in the insulating layer 28 can be trapped. This allows oxygen to be effectively supplied to the semiconductor layer 21.

[0095] The insulating layer 29 a and the insulating layer 29 b can be made of, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. In particular, silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 29 a and the insulating layer 29 b because they emit little impurities (for example, water and hydrogen) and are less permeable to oxygen and hydrogen.

[0096] Since the conductive layers 13 and 14 function as wiring, they preferably have low electrical resistance. The conductive layers 13 and 14 preferably contain a metal or an alloy. Furthermore, the conductive layer 13 is preferably thicker than the conductive layer 23, and the conductive layer 14 is preferably thicker than the conductive layer 24.

[0097] The conductive layers 13 and 14 can be made of the same conductive material as can be used for the conductive layer 23 .

[0098] The insulating layers 33, 34, and 39 function as interlayer insulating films. Furthermore, the insulating layer 39 preferably functions as an etching stopper when processing the insulating layer 34. Therefore, it is preferable that the insulating layer 39 be made of a material different from the insulating layers 33 and 34. For example, the insulating layers 33 and 34 may be made of silicon oxide, and the insulating layer 39 may be made of silicon nitride. However, without being limited thereto, the insulating layers 33 and 34 may be made of a material that can be used for the insulating layer 28, and the insulating layer 39 may be made of a material that can be used for the insulating layers 29a and 29b.

[0099] Here, like the insulating layer 28, the insulating layer 33 is preferably made of an oxide that releases oxygen when heated. Thus, oxygen released from the insulating layer 33 is supplied to the semiconductor layer 21 through the insulating layer 22. Here, like the insulating layers 29a and 29b, the insulating layer 39 is preferably made of an insulating material that is not easily permeable to oxygen. Furthermore, like the conductive layer 24, a conductive material that is not easily oxidized or a material that maintains conductivity even when oxidized is preferably used for the portion of the conductive layer 13 that contacts the insulating layer 33. For example, the conductive layer 13 is preferably a stacked film of a film containing a conductive material that is not easily oxidized or a material that maintains conductivity even when oxidized, and a film containing a low-resistance conductive material. For the conductive material that is not easily oxidized or a material that maintains conductivity even when oxidized, the above descriptions of the conductive layers 24 and 25 can be referred to.

[0100] FIG. 2A shows an enlarged cross section.

[0101] 2A , the channel length L of the transistor 10 refers to the shortest distance between the portion of the semiconductor layer 21 that contacts the conductive layer 24 and the portion that contacts the conductive layer 25. When the side surfaces of the openings in the insulating layers 29 a, 28, and 29 b are perpendicular to the substrate surface, the channel length L is shortest and equals the sum of the thicknesses of the insulating layers 29 a, 28, and 29 b.

[0102] The semiconductor layer 21 is formed along the side surfaces of the openings in the insulating layer 29a, the insulating layer 28, and the insulating layer 29b. At this time, films formed using a film formation method such as sputtering or plasma CVD tend to be thinner on surfaces inclined or perpendicular to the substrate surface than on surfaces horizontal to the substrate surface. Therefore, when the semiconductor layer 21 is formed by sputtering, as shown in FIG. 2B , the thickness of the portion of the semiconductor layer 21 in contact with the top surface of the conductive layer 24 is t1, the thickness of the portion in contact with the insulating layer 28 is t2, and the thickness of the portion in contact with the top surface of the conductive layer 25 is t3. Note that the portions of the semiconductor layer 21 in contact with the side surfaces of the conductive layer 25, the insulating layer 29a, and the insulating layer 29b can also be formed thinner than t1 and t3.

[0103] Similarly, the insulating layer 22 and the conductive layer 23 can be formed so that the thickness of the portions formed along the side surfaces of the openings in the insulating layer 28, etc., is thinner than the portions formed on the upper surfaces of the conductive layers 24 and 25.

[0104] On the other hand, when forming the layers by the ALD method or the like, a film of uniform thickness can be formed regardless of the inclination angle of the surface on which the layers are formed, and therefore, there may be almost no difference in thickness as shown in FIG. 2B between the semiconductor layer 21, the insulating layer 22, the conductive layer 23, etc.

[0105] The shapes of the side surfaces of the insulating layer 28, the insulating layer 29a, and the insulating layer 29b in the opening 20 are not limited to those described above, and may take various shapes depending on the processing method.

[0106] 3A shows an example in which the side surfaces of the insulating layer 28, the insulating layer 29a, and the insulating layer 29b in the opening 20 are each inclined upward, i.e., have a so-called tapered shape. In this case, when the angle θ between the side surface of the insulating layer 28 in the opening 20 and the upper surface of the conductive layer 24 located at the bottom of the opening 20 is defined as angle θ, the angle θ is preferably 90 degrees or more and 135 degrees or less, preferably 125 degrees or less, more preferably 120 degrees or less, and more preferably 110 degrees or less. The closer the angle θ is to a right angle, i.e., the closer the side surface of the insulating layer 28 is to vertical, the smaller the area occupied by the transistor 10 can be. Note that, if the stack of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 can cover the side surface of the insulating layer 28, the angle θ may be less than 90 degrees.

[0107] 3B shows an example in which insulating layer 28 has portions with different inclination angles of the side surfaces. For example, by changing the etching conditions during the etching process to form opening 20 in insulating layer 28, it is possible to form the shape shown in FIG. 3B. For example, when dry etching is used, opening 20 with portions with different inclination angles can be formed by changing the power, bias power, pressure, gas type, gas flow rate, etc.

[0108] 3C and 3D show examples in which the side surfaces of insulating layer 28 are located more inward than the side surfaces of insulating layer 29a and insulating layer 29b. In other words, the side surfaces of insulating layer 29a and insulating layer 29b protrude further than the side surfaces of insulating layer 28. FIG. 3C shows an example in which the side surfaces of insulating layer 28 are approximately perpendicular to the upper surface of conductive layer 24, and FIG. 3D shows an example in which the side surfaces of insulating layer 28 are inclined upward. When opening 20 has such a shape, it is preferable to form semiconductor layer 21, insulating layer 22, and conductive layer 23 using a film formation method with high step coverage, such as an ALD method.

[0109] Furthermore, the side surfaces of the insulating layer 28, the insulating layer 29a, and the insulating layer 29b may have a wavy or uneven shape. The larger the surface area of ​​the side surfaces of the insulating layer 28, the insulating layer 29a, and the insulating layer 29b, the longer the channel length L of the transistor. In this way, the channel length L of the transistor can be controlled by the shape of the side surfaces of the insulating layer 28, the insulating layer 29a, and the insulating layer 29b.

[0110] 4A and 4B show examples in which unevenness is formed on the side surfaces of insulating layer 28, insulating layer 29a, and insulating layer 29b. FIG. 4A shows an example in which the cross section is zigzag-shaped, and FIG. 4B shows an example in which the cross section is wave-shaped. For example, by repeatedly performing an etching process and a polymer deposition process when etching insulating layer 28, insulating layer 29a, and insulating layer 29b, it is possible to form a periodic uneven shape on the side surfaces of insulating layer 28, insulating layer 29a, and insulating layer 29b. Even when opening 20 has such a shape, it is preferable to form semiconductor layer 21, insulating layer 22, and conductive layer 23 using a film formation method with high step coverage, such as an ALD method.

[0111] [Configuration Example 2] The following describes a configuration example that is partially different from the above-described configuration example 1. Note that the following description may omit descriptions of parts that overlap with the above-described configuration example 1.

[0112] 5A illustrates an example in which the insulating layer 33 in FIG. 1B is not provided. An insulating layer 39 is provided to cover the top surfaces of the insulating layer 22 and the conductive layer 23. With this structure, the manufacturing process of the transistor 10 can be simplified.

[0113] 5B shows an example in which the insulating layer 32 in FIG. 1B is not provided. A conductive layer 24 is provided on the conductive layer 14, and an insulating layer 29a is provided to cover the end of the conductive layer 24. In addition, the insulating layer 28, the insulating layer 29b, the conductive layer 25, and the insulating layer 22 each have an uneven shape on their upper surfaces, reflecting the stepped shape of the layers below them.

[0114] 6A shows an example in which a conductive layer 15 is provided in contact with the conductive layer 25. The conductive layer 15 functions as a wiring. The conductive material that can be used for the conductive layer 14 can be used for the conductive layer 15.

[0115] As illustrated in Configuration Example 1, when an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use a conductive oxide or the like for the conductive layer 25 in contact with the lower surface of the semiconductor layer 21. However, the conductivity may be insufficient for use as wiring. Therefore, it is preferable to provide a conductive layer 15 having a higher conductivity than the conductive layer 25 on and in contact with the conductive layer 25.

[0116] 6B , the conductive layer 15 may be provided on the insulating layer 22. In this case, the conductive layer 15 and the conductive layer 25 may be electrically connected to each other through an opening provided in the insulating layer 22. The opening in the insulating layer 22 and the conductive layer 15 can both be formed after the conductive layer 23 of the transistor 10 is formed. Therefore, the insulating layer 22 functioning as a gate insulating layer and the conductive layer 23 functioning as a gate electrode can be formed successively, thereby realizing a highly reliable transistor.

[0117] 7A, the lower surface of conductive layer 25 may be in contact with conductive layer 15. In this case, as shown in FIG. 7B, conductive layer 25 and conductive layer 15 may be processed using the same photomask. In this case, conductive layer 25 and conductive layer 15 may be stacked, and a configuration in which their ends are generally aligned may be achieved. In the configuration shown in FIG. 7B, an oxide film may be formed at the interface between semiconductor layer 21 and conductive layer 15.

[0118] 8 shows an example in which the conductive layer 25 in FIG. 1B is replaced with a conductive layer 25A. The conductive layer 25A is provided in contact with the upper surface of the semiconductor layer 21. With this configuration, even when an oxide semiconductor is used for the semiconductor layer 21, a low-resistance metal film or alloy film can be used for the conductive layer 25A. For example, the conductive material that can be used for the conductive layer 14 can be used for the conductive layer 25A.

[0119] Configuration Example 3 The following describes an example of the shape of the opening 20 in which the transistor 10 is provided and how a plurality of transistors are connected.

[0120] 9A shows a schematic top view of the opening 20 and its periphery. In Fig. 9A, the conductive layer 14, the conductive layer 25, and the semiconductor layer 21 are indicated by solid lines, and the contours of the opening 20, the conductive layer 23, the conductive layer 24, and the conductive layer 13 are indicated by dashed lines.

[0121] 3A and other figures, the diameter of the opening 20 may be the average value of the diameter at the highest point of the insulating layer 28 in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these. However, without being limited to this, the diameter of the opening 20 may be any one of the diameter at the highest point of the insulating layer 28, the diameter at the lowest point, or the diameter at the midpoint between these.

[0122] 9A , conductive layers 23 and 24 are provided inside the contour of conductive layer 13, semiconductor layer 21 is provided inside the contour of conductive layer 23 and the contour of conductive layer 24, and opening 20 is provided inside the contour of semiconductor layer 21. The conductive layers 23 and 24 have generally the same top surface shape. The width of conductive layer 14 and the width of conductive layer 25 are generally the same, and conductive layers 23, 24, semiconductor layer 21, and opening 20 are provided inside the contour of conductive layer 14. The top surface shape of each layer is not limited to the above. It is sufficient that at least opening 20 is located inside the contours of semiconductor layer 21, conductive layer 23, and conductive layer 24. For example, semiconductor layer 21, conductive layer 23, conductive layer 24, etc. may have portions located outside conductive layer 14, conductive layer 25, or conductive layer 13. The contours of conductive layer 23 and conductive layer 24 may be different.

[0123] 9A shows a case where the top surface shape of opening 20 is a circle with a diameter R. In this case, the channel width W of transistor 10 is equal to the circumferential length of opening 20. In other words, the channel width W is π×R. In this way, by making the top surface shape of opening 20 circular, a transistor with the smallest channel width W can be realized.

[0124] 9B shows an example in which the top surface shape of the opening 20 is a square with a side length A. In this case, the channel width W of the transistor 10 is 4×A.

[0125] Fig. 9C shows an example in which the top surface shape of the opening 20 is a regular hexagon. Fig. 9D shows an example in which the top surface shape of the opening 20 is a regular octagon. However, the shape is not limited to these, and various polygonal shapes may be used.

[0126] In photolithography, the finer the pattern to be processed, the more significant the effect of light diffraction becomes. This reduces the fidelity of the photomask pattern when it is transferred by exposure, making it difficult to process the resist mask into the desired shape. Therefore, even if the photomask pattern is rectangular, a pattern with rounded corners is likely to be formed. Consequently, the top surface shape of the light-emitting element may become polygonal with rounded corners, elliptical, or circular. Therefore, a technique for correcting the mask pattern in advance (OPC (Optical Proximity Correction) technique) may be used to match the design pattern with the transferred pattern. Specifically, OPC technique adds correction patterns to the corners of the figures on the mask pattern.

[0127] Fig. 9E shows an example in which the top surface shape of the opening 20 is a combination of a semicircle and a straight line, and Fig. 9F shows an example in which the top surface shape of the opening 20 is a rectangle with rounded corners.

[0128] Furthermore, the greater the perimeter of opening 20, the larger the channel width W of the transistor can be. For example, as shown in Figures 9G and 9H, if the top surface shape of the opening is a polygon with at least one interior angle exceeding 180 degrees, a so-called concave polygon, the channel width W can be increased without increasing the occupied area. Figure 9G shows an example where the top surface shape of opening 20 is a star-shaped hexagon, and Figure 9H shows an example where it is a star-shaped dodecagon.

[0129] 10A1 is a schematic top view of a region including two transistors connected in parallel. Two openings (opening 20a and opening 20b) are provided between conductive layer 14 and conductive layer 13, and a transistor is formed in each of openings 20a and 20b.

[0130] 10A1 corresponds to the circuit shown in Fig. 10A2, where P is a wiring corresponding to conductive layer 14, Q is a wiring corresponding to conductive layer 25, and R is a wiring corresponding to conductive layer 13, transistor TRa is a transistor corresponding to opening 20a, and transistor TRb is a transistor corresponding to opening 20b.

[0131] 10A1 and 10A2, two transistors are connected in parallel. If the channel length L and channel width W of the two transistors are equal, the configurations shown in Fig. 10A1 and 10A2 can be regarded as one transistor with a channel length L and a channel width 2 × W.

[0132] Fig. 10B1 shows an example of a schematic top view of four transistors connected in parallel. In Fig. 10B1, four openings (openings 20a, 20b, 20c, and 20d) are provided. Fig. 10B2 shows a circuit diagram corresponding to Fig. 10B1. Transistors TRa, TRb, TRc, and TRd correspond to openings 20a, 20b, 20c, and 20d, respectively.

[0133] 10B1 and 10B2, four transistors are connected in parallel. If the channel length L and channel width W of the four transistors are equal, the configurations shown in Fig. 10B1 and 10B2 can be regarded as one transistor with a channel length of L and a channel width of 4 × W.

[0134] In this way, by arranging multiple openings 20 between conductive layer 13 and conductive layer 14 (or between conductive layer 24 and conductive layer 23), a transistor with a channel width W that is an integer multiple can be constructed.

[0135] 11A1 is a schematic top view of two transistors connected in series, including a pair of conductive layers 14 (conductive layer 14a, conductive layer 14b), a pair of conductive layers 23 (conductive layer 23a, conductive layer 23b), and a pair of conductive layers 24 (conductive layer 24a, conductive layer 24b).

[0136] Provided on the conductive layer 14a are a conductive layer 24a, an opening 20a, a semiconductor layer 21, a conductive layer 23a, and a conductive layer 13. Provided on the conductive layer 14b are a conductive layer 24b, an opening 20b, a semiconductor layer 21, a conductive layer 23b, and a conductive layer 13.

[0137] The two transistors share the conductive layer 25 and the semiconductor layer 21, and the conductive layers 23a and 23b are electrically connected by the conductive layer 13. Fig. 11A2 shows a circuit diagram corresponding to Fig. 11A1. P is a wiring corresponding to the conductive layer 14a, Q is a wiring corresponding to the conductive layer 14b, and R is a wiring corresponding to the conductive layer 13.

[0138] Although the example in which the conductive layer 23 a and the conductive layer 23 b are provided is shown here, the conductive layer 23 may be a continuous layer shared between two transistors. Also, although the example in which the semiconductor layer 21 is shared by two transistors is shown here, the semiconductor layer 21 may be provided separately.

[0139] The configuration shown in FIGS. 11B1 and 11B2 includes a pair of conductive layers 25 (conductive layers 25a and 25b) and a pair of semiconductor layers 21 (semiconductor layers 21a and 21b).

[0140] On the conductive layer 14, there is a region where the conductive layer 24, the opening 20a, the conductive layer 25a, the semiconductor layer 21a, the conductive layer 23, and the conductive layer 13 are stacked, and a region where the conductive layer 24, the opening 20b, the conductive layer 25b, the semiconductor layer 21b, the conductive layer 23, and the conductive layer 13 are stacked.

[0141] The two transistors share conductive layers 14, 24, 23, and 13. Fig. 11B2 shows a circuit diagram corresponding to Fig. 11B1. P denotes a wiring corresponding to conductive layer 25a, Q denotes a wiring corresponding to conductive layer 25b, and R denotes a wiring corresponding to conductive layer 13.

[0142] In FIG. 11B2, the conductive layer 23 and the conductive layer 24 do not have to be provided in common between the two transistors, but may be disposed individually for each transistor.

[0143] In this way, two transistors can be connected in series by sharing the gate and one of the source electrode and drain electrode. For example, if the channel length L and channel width W of two transistors are equal, they can be regarded as a transistor with a channel length of L×2 and a channel width of W. In other words, by arranging multiple transistors in series, a transistor with a length L that is an integer multiple can be configured.

[0144] [Manufacturing Method Example] An example of a manufacturing method of a transistor according to one embodiment of the present invention will be described below, taking the transistor 10 described in Structure Example 1 as an example.

[0145] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0146] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0147] Furthermore, when processing a thin film that constitutes a semiconductor device, it can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0148] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0149] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0150] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0151] 12A1 to 13C1 are schematic cross-sectional views illustrating steps in a manufacturing process of the transistor 10, which will be described below. Also, FIGS. 12A2 to 13C2 are perspective views illustrating steps in the manufacturing process. Note that in FIGS. 12A2 to 13C2, some components are omitted or only outlines are shown by dashed lines for ease of understanding.

[0152] [Preparation of Substrate 11] First, the substrate 11 is prepared.

[0153] The substrate may be a substrate having heat resistance sufficient to withstand at least a subsequent heat treatment. When an insulating substrate is used, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like may be used. Alternatively, a semiconductor substrate such as a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium or gallium nitride, or an SOI substrate may be used.

[0154] [Formation of Conductive Layer 14 ] An insulating layer 31 is formed on the substrate 11 .

[0155] The insulating layer 31 functions as an interlayer insulating layer or a base insulating layer. For the insulating layer 31, an inorganic insulating film having a relatively low dielectric constant, such as silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies, can be used.

[0156] The insulating layer 31 is preferably formed by sputtering or PECVD.

[0157] Next, the insulating layer 31 is etched away at positions where the conductive layer 14 is to be embedded, thereby forming grooves. Specifically, a resist mask is formed on the insulating layer 31, and the portions not covered by the resist mask are removed by etching, thereby forming the grooves.

[0158] Subsequently, a conductive film that becomes the conductive layer 14 is formed so as to fill the grooves, and then planarization treatment is performed, thereby forming the conductive layer 14 that is embedded in the insulating layer 31. The conductive layer 14 can be formed by a film formation method such as a sputtering method, a CVD method, or an ALD method.

[0159] [Formation of Conductive Layer 24] Subsequently, the insulating layer 32 is formed on the insulating layer 31 and the conductive layer 14. The insulating layer 32 can be formed using the same material and method as the insulating layer 31. Thereafter, a groove portion is formed in the insulating layer 32, reaching the conductive layer 14.

[0160] Next, a conductive layer 24 is formed so as to fill the grooves of the insulating layer 32. When an oxide conductive film is used as the conductive layer 24, it is preferable to form the conductive layer 24 by using a sputtering method or an ALD method. Thereafter, planarization treatment is performed, thereby forming the conductive layer 24 (FIGS. 12A1 and 12A2).

[0161] When the conductive layer 24 is provided to prevent oxidation of the conductive layer 14, the effect may be obtained even if the conductive layer 24 is a film that is thinner than the conductive layer 14 (for example, 30 nm or less, 20 nm or less, or 10 nm or less, and 2 nm or more). In that case, the conductive layer 14 may be formed without using the insulating layer 32, thereby achieving the configuration illustrated in FIG. 5B .

[0162] [Formation of Insulating Layer 29a, Insulating Layer 28, Insulating Layer 29b] Subsequently, the insulating layer 29a, the insulating layer 28, and the insulating layer 29b are formed in this order on the conductive layer 24 and the insulating layer 32.

[0163] Here, it is preferable that the insulating layers 29a and 29b and the insulating layer 28 are made of insulating films having different compositions or constituent elements.

[0164] Since the insulating layer 28 is a film that will later come into contact with the semiconductor layer 21, it is preferable to use an oxide film that contains a large amount of oxygen to the extent that oxygen is released by heating and that contains a small amount of hydrogen. The insulating layer 28 can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is particularly preferably formed by a sputtering method. In particular, by forming the insulating layer 28 using a gas containing oxygen and not using a gas containing hydrogen as a film formation gas, the insulating layer 28 can be formed with an extremely small amount of hydrogen and an excess amount of oxygen.

[0165] [Formation of Conductive Layer 25] Subsequently, a conductive film that will become the conductive layer 25 is formed on the insulating layer 29b, and then unnecessary portions are removed by etching, thereby forming the conductive layer 25.

[0166] [Formation of opening 20] Next, a resist mask is formed on the conductive layer 25 and the insulating layer 29b, and portions of the conductive layer 25, the insulating layer 29b, the insulating layer 28, and the insulating layer 29a are etched to form an opening 20 therein that reaches the conductive layer 24 (FIGS. 12B1 and 12B2).

[0167] The conductive layer 25, the insulating layer 29b, the insulating layer 28, and the insulating layer 29a are each etched by dry etching, whereby minute openings 20 can be formed.

[0168] [Formation of Semiconductor Layer 21] Subsequently, a semiconductor film that will become the semiconductor layer 21 is formed, and unnecessary portions are removed by etching to form island-shaped semiconductor layers 21 (FIGS. 12C1 and 12C2).

[0169] It is preferable that the semiconductor layer 21 be formed as a film with as uniform a thickness as possible on the side surfaces of the opening 20 of the insulating layer 28, the insulating layer 29a, the insulating layer 29b, and the conductive layer 25. For this reason, it is preferable to form the film by the ALD method.

[0170] As a specific example, it is preferable to use a film formation method such as a thermal ALD (Atomic Layer Deposition) method or a PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0171] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0172] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0173] As the precursor containing indium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and the like can be used.

[0174] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0175] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0176] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0177] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form films with different compositions successively.

[0178] Heat treatment may be performed after the semiconductor film that becomes the semiconductor layer 21 is formed. The heat treatment can reduce water and hydrogen contained in the semiconductor film and supply oxygen from the insulating layer 28. Note that the heat treatment may be performed after the semiconductor film is processed.

[0179] It should be noted that the semiconductor layer 21 is not limited to the ALD method, and other film formation methods can be used as long as the opening 20 can be sufficiently covered. For example, sputtering is preferable because it is relatively easy to obtain a film with a low hydrogen content.

[0180] [Formation of Insulating Layer 22] Subsequently, the insulating layer 22 is formed to cover the conductive layer 25, the semiconductor layer 21, and the insulating layer 29b (FIGS. 13A1 and 13A2).

[0181] As with the semiconductor layer 21, the insulating layer 22 is also preferably formed by a film formation method with high step coverage, and is preferably formed by the ALD method. Note that, if the insulating layer 22 can sufficiently cover the semiconductor layer 21 located in the opening 20, the insulating layer 22 may be formed by a method other than the ALD method, and a film formation method such as the PECVD method or the sputtering method can be used.

[0182] [Formation of Conductive Layer 23] Subsequently, a conductive film that will become the conductive layer 23 is formed to cover the insulating layer 22, and unnecessary portions are removed by etching to form island-shaped conductive layers 23 (FIGS. 13B1 and 13B2).

[0183] Like the semiconductor layer 21 and the insulating layer 22, the conductive layer 23 is also preferably formed by a film formation method with high step coverage, and is preferably formed by the ALD method. Alternatively, the conductive layer 23 can be formed by a thermal CVD method. Note that, if the conductive layer 23 can sufficiently cover the insulating layer 22 located in the opening 20, the conductive layer 23 may be formed by a method other than the ALD method, and a film formation method such as a sputtering method can be used.

[0184] [Formation of Insulating Layer 33, Insulating Layer 39, and Insulating Layer 34] Subsequently, the insulating layer 33, the insulating layer 39, and the insulating layer 34 are formed in this order to cover the conductive layer 23 and the insulating layer 22.

[0185] The insulating layer 33 and the insulating layer 34 can be formed, for example, using the same material and method as the insulating layer 31. Furthermore, since the insulating layer 39 functions as an etching stopper when the insulating layer 34 is etched, it is preferable to use a film having a different composition from the insulating layer 34.

[0186] The insulating layer 33 is preferably a film containing a small amount of hydrogen and a large amount of oxygen, as exemplified for the insulating layer 28. When such an insulating layer 33 is provided in contact with the insulating layer 22, oxygen can be supplied from the insulating layer 33 to the semiconductor layer 21 through the insulating layer 22 by heat applied during the manufacturing process.

[0187] [Formation of Conductive Layer 13] Subsequently, a first etching is performed to form openings in the insulating layers 34, 39, and 33, reaching the conductive layer 23. The openings are provided at positions overlapping the openings 20. The openings correspond to contact portions between the conductive layers 13 and 23 later.

[0188] Next, a second etching is performed to form a groove in the insulating layer 34 into which the conductive layer 13 is to be embedded. After the second etching, the insulating layer 39, which functions as an etching stopper, is exposed at the bottom of the groove. At this time, the groove is formed so that the opening is located inside the groove in a plan view.

[0189] Thereafter, a conductive film that will become the conductive layer 13 is formed so as to fill the openings formed by the first etching and the grooves formed by the second etching, and then a planarization process is performed until the top surface of the insulating layer 34 is exposed, thereby forming the conductive layer 13 (FIGS. 13C1 and 13C2). The conductive film is preferably formed by plating.

[0190] If the upper surface of the conductive layer 23 is exposed after the first etching, it may be damaged during the second etching. In this case, it is preferable to provide a thin film that functions as an etching stopper between the conductive layer 23 and the insulating layer 33, and to etch the insulating layers 34, 39, and 33 in the first etching so as to leave the thin film. This prevents the conductive layer 23 from being exposed during the second etching. The thin film may be removed by etching using the insulating layer 39 as a mask after the second etching and before the formation of the conductive film that will become the conductive layer 13.

[0191] Through the above steps, the transistor 10 can be manufactured.

[0192] [Modifications] Hereinafter, examples of transistor configurations different from those described above will be described.

[0193] The above describes a configuration in which a semiconductor layer is provided along the side surface of an insulating layer in an opening provided in the insulating layer, etc. Below, a configuration in which a semiconductor layer is provided along the side surface of a groove (slit) provided in the insulating layer, etc., rather than an opening, will be described.

[0194] Fig. 14A shows a schematic perspective view of a region including transistor 10a. In Fig. 14, some components (such as insulating layer 22) are shown with dashed outlines, while other components (such as conductive layer 13) are not shown. Fig. 14A also shows the X-axis, Y-axis, and Z-axis to make the orientations easier to understand. Fig. 14B shows the X-Z cross section of the region including transistor 10a.

[0195] Slits 20S parallel to the Y direction are provided in insulating layers 29a, 28, and 29b. Conductive layer 24 and insulating layer 32 are provided at the bottom of slits 20S. Conductive layer 25 is provided on insulating layer 29b, and is processed so that the end on the slit 20S side coincides with insulating layer 29b.

[0196] The semiconductor layer 21 is provided in contact with the upper surface of the conductive layer 25, the side surfaces of the insulating layer 29b in the slit 20S, the side surfaces of the insulating layer 28, the side surfaces of the insulating layer 29a, and the upper surface of the conductive layer 24. A part of the semiconductor layer 21 contacts the insulating layer 32 within the slit 20S.

[0197] The insulating layer 33 is provided to cover the insulating layer 29b, the conductive layer 25, the semiconductor layer 21, the insulating layer 32, etc. In Fig. 14A, in addition to the outline of the insulating layer 22, a part of the outline of the semiconductor layer 21 when cut along a plane parallel to the side surface along the X direction is shown by a dashed line.

[0198] The conductive layer 23 is provided on the insulating layer 22. The conductive layer 23 has a portion overlapping with the semiconductor layer 21.

[0199] Within the slit 20S, the semiconductor layer 21 has a portion that contacts the side surface of the insulating layer 28. Furthermore, within the slit 20S, the insulating layer 22 has a portion that faces the side surface of the insulating layer 28 with the semiconductor layer 21 interposed therebetween. Furthermore, within the slit 20S, the conductive layer 23 has a portion that faces the side surface of the insulating layer 28 with the insulating layer 22 and the semiconductor layer 21 interposed therebetween. Furthermore, within the slit 20S, the interface between the semiconductor layer 21 and the insulating layer 28, the interface between the semiconductor layer 21 and the insulating layer 22, and the interface between the insulating layer 22 and the conductive layer 23 have portions that are parallel to one another.

[0200] An insulating layer 33 is provided on the insulating layer 22 and the conductive layer 23 so as to fill a part of the slit 20S, and an insulating layer 39 and an insulating layer 34 are provided on the insulating layer 33. A conductive layer 13 is provided in contact with the conductive layer 23 so as to be embedded in the insulating layer 34, the insulating layer 39, and the insulating layer 33.

[0201] 14A , the channel width W of the transistor 10a can be considered to be the width in the Y direction of the portion of the semiconductor layer 21 and the conductive layer 23 stacked along the side surface of the insulating layer 33 in the slit 20S. Therefore, the channel width W can be freely changed by design, increasing the degree of design freedom. Furthermore, compared to when an opening is used, it is possible to fabricate a transistor with a smaller channel length W. Note that the channel length L of the transistor 10a can be considered to be the distance between the portion of the semiconductor layer 21 that contacts the conductive layer 25 and the portion that contacts the conductive layer 24, as in the above-described configuration example 1.

[0202] The above is a description of the modified example.

[0203] Embodiment 2 In this embodiment, a structural example of a display device to which a semiconductor device of one embodiment of the present invention can be applied will be described.

[0204] Since the semiconductor device of one embodiment of the present invention can be extremely fine, a display device using the semiconductor device of one embodiment of the present invention can be a display device with extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD) such as a glasses-type AR device.

[0205] 15A shows a perspective view of display module 280. Display module 280 has a display device 200A and an FPC 290. Note that the display panel of display module 280 is not limited to display device 200A, and may be a display device 200B or a display device 200C, which will be described later.

[0206] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0207] 15B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 composed of a plurality of wirings.

[0208] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 15B. The pixel 284a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0209] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0210] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0211] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0212] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0213] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0214] Display Device 200A The display device 200A shown in FIG. 16 includes a substrate 331, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 240, and a transistor 320.

[0215] Substrate 331 corresponds to substrate 291 in FIG. 15A.

[0216] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed, and includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, and a conductive layer 326.

[0217] Any of the various transistors exemplified in Embodiment 1 can be used as the transistor 320 .

[0218] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0219] A conductive layer 327 is provided over the insulating layer 332, and a conductive layer 325 is provided over the conductive layer 327. An insulating layer 334 is provided over the conductive layer 325, and a conductive layer 326 is provided over the insulating layer 334. Openings are provided in the insulating layer 334 and the conductive layer 326, and a semiconductor layer 321 is provided in the opening. An insulating layer 264 is provided to cover the semiconductor layer 321 and the conductive layer 326, and an insulating layer 323 and a conductive layer 324 are stacked in this order in the opening provided in the insulating layer 264. An insulating layer 264 and an insulating layer 265 are stacked to cover the insulating layer 323 and the conductive layer 324, and a conductive layer 328 in contact with the conductive layer 324 is embedded in the insulating layer 264 and the insulating layer 265. An insulating layer 266 is provided over the insulating layer 265 and the conductive layer 328.

[0220] The insulating layer 264, the insulating layer 265, and the insulating layer 266 function as interlayer insulating layers. A barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like into the transistor 320 may be provided between the insulating layer 266 and the insulating layer 265. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0221] A plug 274 electrically connected to one side of the conductive layer 326 is provided to be embedded in the insulating layer 266, the insulating layer 265, the insulating layer 264, and the insulating layer 323. Here, the plug 274 preferably has a conductive layer 274a covering the side surfaces of the openings of the insulating layer 266, the insulating layer 265, the insulating layer 264, and the insulating layer 323 and part of the top surface of the conductive layer 326, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0222] Furthermore, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0223] The conductive layer 241 is provided over the insulating layer 266 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0224] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0225] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0226] The light-emitting elements 110R, 110G, and 110B are provided over the insulating layer 255c. Details of the light-emitting elements 110R, 110G, and 110B will be described in Embodiment 3.

[0227] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0228] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0229] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 112R, 112G, and 112B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0230] In the region between adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0231] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 326 of the transistor 320 via a plug 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0232] A protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 with an adhesive layer 171.

[0233] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0234] [Display Device 200B] The following describes a display device that has a configuration that is partially different from that described above. Note that parts that are common to the above will be referred to, and descriptions thereof may be omitted.

[0235] 17 shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has a similar configuration to the transistor 320 in the display device 200A.

[0236] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0237] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0238] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0239] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0240] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352.

[0241] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0242] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be formed using an insulating film similar to the insulating layer 352.

[0243] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0244] [Display Device 200C] A display device 200C shown in FIG. 18 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 320.

[0245] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0246] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0247] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0248] In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device exemplified below can be used for the pixel portion 284 in Embodiment 2, for example.

[0249] One embodiment of the present invention is a display device having a light-emitting element (also referred to as a light-emitting device). The display device has two or more pixels that emit light of different colors. Each pixel has a light-emitting element. Each light-emitting element has a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements that emit light of different colors each have an EL layer containing a different light-emitting material. For example, a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light, respectively.

[0250] When fabricating a display device having multiple light-emitting elements that emit different colors of light, it is necessary to form at least one layer containing a light-emitting material (light-emitting layer) in an island shape. When fabricating a partial or entire EL layer, a method of forming island-shaped organic films by vapor deposition using a shadow mask such as a metal mask is known. However, this method can cause deviations in the shape and position of the island-shaped organic films from the design due to various factors such as the accuracy of the metal mask, misalignment between the metal mask and the substrate, deflection of the metal mask, and spreading of the contours of the deposited film due to vapor scattering, making it difficult to achieve high-definition and high-aperture display devices. Furthermore, during vapor deposition, the contours of the layer can become blurred, resulting in thinning of the edges. In other words, the thickness of the island-shaped light-emitting layer can vary depending on the location. Furthermore, when fabricating large, high-resolution, or high-definition display devices, there is a concern that low dimensional accuracy of the metal mask and deformation due to heat, etc., can reduce manufacturing yield. Therefore, measures have been taken to artificially increase the resolution (also known as pixel density) by adopting special pixel arrangements such as a pentile array.

[0251] In this specification, the term "island-like" refers to a state in which two or more layers formed using the same material in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0252] In one embodiment of the present invention, an EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which have been difficult to achieve until now. Furthermore, since the EL layer can be individually fabricated, a display device with extremely vivid images, high contrast, and high display quality can be realized. Note that, for example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

[0253] Furthermore, the EL layer can be partially or entirely separated physically. This can suppress leakage current between adjacent light-emitting elements through a layer shared between the light-emitting elements (also referred to as a common layer). This can prevent crosstalk caused by unintended light emission, thereby realizing a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.

[0254] One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element and a color filter. In this case, light-emitting elements provided in pixels (subpixels) that emit light of different colors can have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, thereby achieving a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, thereby achieving a display device that combines high brightness, high definition, and high contrast.

[0255] When the EL layer is processed by photolithography, a portion of the light-emitting layer may be exposed, which may cause deterioration. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer may also be configured to cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that is less likely to diffuse water or oxygen can be used. This suppresses deterioration of the EL layer, thereby achieving a highly reliable display device.

[0256] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. When a common electrode, or a common electrode and a common layer, is formed to cover the recess, a phenomenon in which the common electrode is separated by a step at the edge of the EL layer (also called a step discontinuity) may occur, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer functioning as a planarization film (also called LFP: Local Filling Planarization). The resin layer functions as a planarization film. This suppresses step discontinuity of the common layer or common electrode, thereby achieving a highly reliable display device.

[0257] A more specific example of the structure of the display device of one embodiment of the present invention will be described below with reference to the drawings.

[0258] 19A shows a schematic top view of a display device 100 of one embodiment of the present invention. The display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101. In FIG. 19A , the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements to easily distinguish the light-emitting elements from one another.

[0259] The light emitting elements 110R, 110G, and 110B are arranged in a matrix. Fig. 19A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, or a pentile arrangement, a diamond arrangement, or the like may also be used.

[0260] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used. Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0261] 19A also shows a connection electrode 111C that is electrically connected to the common electrode 113. The connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.

[0262] The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided over two or more sides of the periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.

[0263] 19B and 19C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 19A, respectively. Fig. 19B shows a schematic cross-sectional view of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, and Fig. 19C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 113 are connected.

[0264] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0265] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0266] Hereinafter, when describing matters common to light emitting element 110R, light emitting element 110G, and light emitting element 110B, they may be referred to as light emitting element 110. Similarly, when describing matters common to components distinguished by alphabets, such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabets.

[0267] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 may have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 may have an electron injection layer.

[0268] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element. The common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film transmissive to visible light is used for either the pixel electrode or the common electrode 113, and a conductive film reflective to visible light is used for the other. By making each pixel electrode transmissive and the common electrode 113 reflective, a bottom-emission display device can be obtained. Conversely, by making each pixel electrode reflective and the common electrode 113 transmissive, a top-emission display device can be obtained. Note that by making both the pixel electrodes and the common electrode 113 transmissive, a dual-emission display device can be obtained.

[0269] A protective layer 121 is provided on the common electrode 113 to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0270] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also have a tapered shape. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0271] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0272] The organic layer 112 is processed into an island shape by photolithography. As a result, the angle between the top surface and the side surface of the organic layer 112 at its edge is close to 90 degrees. On the other hand, an organic film formed using a fine metal mask (FMM) or the like tends to become gradually thinner as it approaches the edge. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm up to the edge, making it difficult to distinguish between the top surface and the side surface.

[0273] Between two adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0274] Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with the resin layer 126 sandwiched therebetween. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the region between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided to cover the upper surface of the resin layer 126.

[0275] The resin layer 126 functions as a planarization film that fills in a step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent a phenomenon (also called step disconnection) in which the common electrode 113 is divided by a step at the end of the organic layer 112, and the common electrode 113 on the organic layer 112 is isolated. The resin layer 126 can also be called an LFP (Local Filling Planarization) layer.

[0276] An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, precursors of these resins, etc. can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.

[0277] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0278] The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. For example, the resin layer 126 may be a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

[0279] The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is provided in contact with the upper surface of the substrate 101.

[0280] The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

[0281] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, by using an inorganic insulating film such as a metal oxide film, an aluminum oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

[0282] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0283] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method because it has good coverage.

[0284] Furthermore, a reflective film (e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) may be provided between the insulating layer 125 and the resin layer 126, so that the light emitted from the light-emitting layer is reflected by the reflective film, thereby improving the light extraction efficiency.

[0285] The layer 128 is a remaining portion of a protective layer (also referred to as a mask layer or a sacrificial layer) for protecting the organic layer 112 during etching of the organic layer 112. The layer 128 can be made of a material that can be used for the insulating layer 125. In particular, it is preferable to use the same material for the layer 128 and the insulating layer 125 because a common processing device or the like can be used for both.

[0286] In particular, inorganic insulating films such as metal oxide films such as aluminum oxide films and hafnium oxide films, or silicon oxide films formed by the ALD method have few pinholes and therefore have an excellent function of protecting the EL layer, and can be suitably used for the insulating layer 125 and the layer 128.

[0287] The protective layer 121 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 121 may be made of a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide.

[0288] The protective layer 121 may also be a laminated film of an inorganic insulating film and an organic insulating film. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 121 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 121, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0289] 19C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected in the opening.

[0290] 19C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected, but the common electrode 113 may be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used for the common layer 114, the electrical resistivity of the material used for the common layer 114 is sufficiently low and the common layer 114 can be formed thin, so there are many cases where no problem occurs even if the common layer 114 is located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same masking mask, thereby reducing manufacturing costs.

[0291] [Configuration Example 2] The following describes a display device that has a configuration that is partially different from that of the above-described configuration example 1. Note that parts that are common to the above-described configuration example 1 will be referred to, and descriptions thereof may be omitted.

[0292] 20A shows a schematic cross-sectional view of a display device 100a. The display device 100a differs from the display device 100 in that the configuration of the light-emitting element is different and that the display device 100a has a colored layer.

[0293] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may be configured to include two or more light-emitting materials whose emitted light colors are complementary to each other. For example, the organic layer 112W may be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Alternatively, the organic layer 112W may be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0294] The organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, thereby suppressing crosstalk caused by the leakage current. As a result, a display device with high contrast and color reproducibility can be realized.

[0295] An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0296] The insulating layer 122 can be an organic resin film or an inorganic insulating film with a planarized upper surface. The insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed. Therefore, the planar upper surface of the insulating layer 122 allows the thickness of the colored layers 116R and the like to be uniform, thereby improving the color purity of the light extracted from each light-emitting device. Note that if the thickness of the colored layers 116R and the like is uneven, the amount of light absorption varies depending on the location of the colored layer 116R, which may result in a decrease in color purity.

[0297] Configuration Example 3 FIG. 20B shows a schematic cross-sectional view of a display device 100b.

[0298] The light-emitting element 110R has a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B each have light-transmitting properties and function as an optical adjustment layer.

[0299] A microresonator (microcavity) structure can be realized by using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113. In this case, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when the organic layer 112 that emits white light is used, light of different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.

[0300] Furthermore, colored layers 116R, 116G, and 116B are provided on the optical paths of the light emitting elements 110R, 110G, and 110B, respectively, so that light with high color purity can be obtained.

[0301] An insulating layer 123 is also provided to cover the edges of the pixel electrode 111 and the optical adjustment layer 115. The edges of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, it is possible to improve the coverage of the organic layer 112W, the common electrode 113, the protective layer 121, and the like that are formed thereon.

[0302] The organic layer 112W and the common electrode 113 are each provided as a continuous film in common to each light-emitting element, which is preferable because it can greatly simplify the manufacturing process of the display device.

[0303] Here, it is preferable that the edge of pixel electrode 111 is nearly perpendicular to the upper surface of substrate 101. This allows a steeply inclined portion to be formed on the surface of insulating layer 123, and makes it possible to form a thin portion in part of organic layer 112W covering this portion, or to divide part of organic layer 112W. Therefore, it is possible to suppress leakage current occurring through organic layer 112W between adjacent light-emitting elements without processing organic layer 112W by photolithography or the like.

[0304] The above is a description of an example of the configuration of the display device.

[0305] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0306] Embodiment 4 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0307] The electronic devices of this embodiment include a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0308] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0309] In particular, the display panel of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0310] The display panel of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0311] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0312] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0313] 21A to 21D , examples of wearable devices that can be worn on the head will be described. These wearable devices have one or both of a function to display AR content and a function to display VR content. Note that these wearable devices may also have a function to display SR or MR content in addition to AR and VR. By having an electronic device have a function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0314] The electronic device 700A shown in FIG. 21A and the electronic device 700B shown in FIG. 21B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0315] A display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided.

[0316] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0317] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0318] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0319] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0320] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0321] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0322] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0323] The electronic device 800A shown in Figure 21C and the electronic device 800B shown in Figure 21D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0324] A display panel of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0325] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0326] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0327] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0328] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 21C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0329] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0330] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0331] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0332] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0333] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 21A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 21C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0334] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 21B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0335] Similarly, the electronic device 800B shown in Fig. 21D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, which is preferable as it makes storage easier.

[0336] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0337] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0338] The electronic device 6500 shown in FIG. 22A is a portable information terminal that can be used as a smartphone.

[0339] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like. The display portion 6502 has a touch panel function.

[0340] The display panel of one embodiment of the present invention can be applied to the display portion 6502 .

[0341] FIG. 22B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0342] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0343] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0344] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0345] The flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0346] 22C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0347] 22C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0348] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0349] 22D shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The housing 7211 includes a display portion 7000.

[0350] 22E and 22F show an example of digital signage.

[0351] 22E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0352] 22F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0353] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0354] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0355] 22E and 22F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0356] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0357] 22C to 22F, a display panel of one embodiment of the present invention can be applied to the display portion 7000.

[0358] The electronic device shown in Figures 23A to 23G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0359] The electronic devices shown in Figures 23A to 23G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0360] The electronic devices shown in FIGS. 23A to 23G will be described in detail below.

[0361] FIG. 23A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 23A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0362] 23B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0363] 23C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0364] FIG. 23D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0365] 23E to 23G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 23E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 23G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 23F is a perspective view of a state in the process of changing from one of FIGS. 23E and 23G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0366] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0367] 10a: transistor, 10: transistor, 11: substrate, 13: conductive layer, 14a: conductive layer, 14b: conductive layer, 14: conductive layer, 15: conductive layer, 20a: opening, 20b: opening, 20c: opening, 20d: opening, 20S: slit, 20: opening, 21a: semiconductor layer, 21b: semiconductor layer, 21: semiconductor layer, 22: insulating layer, 23a: conductive layer, 23b: conductive layer, 23: conductive layer, 24a: conductive layer, 24b: conductive layer, 24: conductive layer, 25A: conductive layer, 25a: conductive layer, 25b: conductive layer, 25: conductive layer, 28: insulating layer, 29a: insulating layer, 29b: insulating layer, 31: insulating layer, 32: insulating layer, 33: insulating layer, 34: insulating layer, 39: insulating layer

Claims

1. It comprises a first insulating layer, a semiconductor layer, a gate insulating layer, a gate electrode, a first electrode, a second electrode, and a first conductive layer. The first insulating layer has a slit, The first insulating layer has a side surface in the slit that is positioned on the first electrode. The second electrode is located on the first insulating layer, The semiconductor layer, the gate insulating layer, the gate electrode, and the first conductive layer each have a portion located inside the slit. The semiconductor layer is in contact with the first electrode, the side surface of the first insulating layer, and the second electrode. The gate insulating layer has a portion that faces the side surface of the first insulating layer via the semiconductor layer, The gate electrode has a portion facing the side surface of the first insulating layer via the gate insulating layer and the semiconductor layer, The first conductive layer is in contact with the gate electrode and has a portion that faces the side surface of the first insulating layer via the gate electrode, the gate insulating layer, and the semiconductor layer, and has a portion that is thicker than the gate electrode. Semiconductor equipment.

2. In claim 1, Having a second insulating layer, The height of the upper surface of the first conductive layer and the height of the upper surface of the second insulating layer are approximately the same. Semiconductor equipment.

3. In claim 1 or 2, The semiconductor layer has a metal oxide, The first electrode has a metal oxide with a different composition from the semiconductor layer. Semiconductor equipment.

4. In claim 3, It has a second conductive layer, The first electrode has a portion that contacts the upper surface of the second conductive layer, The second conductive layer includes a metal or alloy. Semiconductor equipment.

5. In any one of claims 1 to 4, The semiconductor layer has a first portion that contacts the upper surface of the first electrode, a second portion that contacts the side surface of the first insulating layer, and a third portion that is located above the first insulating layer. The thickness of the second part is thinner than that of the first and third parts. Semiconductor equipment.

6. The present invention relates to any one of claims 1 to 5, wherein the angle between the side surface of the first insulating layer and the upper surface of the first electrode is 90 degrees or more and 120 degrees or less in a portion thereof. Semiconductor equipment.

7. In any one of claims 1 to 6, The side surface of the first insulating layer has an uneven shape, Semiconductor equipment.

8. In any one of claims 1 to 7, The semiconductor layer is in contact with the upper surface of the second electrode, The semiconductor layer has a metal oxide, The second electrode has a metal oxide with a different composition from the semiconductor layer. Semiconductor equipment.

9. In claim 8, It has a third conductive layer, The second electrode has a portion that is in contact with the third conductive layer, The third conductive layer includes a metal or alloy. Semiconductor equipment.