Semiconductor device, and storage device

Abstract

Provided is a semiconductor device capable of miniaturization or high integration. This semiconductor device includes: an oxide on a substrate; a first conductor and a second conductor that are on the oxide and are separated from each other; a third conductor contacting an upper surface of the first conductor; a fourth conductor contacting an upper surface of the second conductor; a first insulator that is on the third conductor and the fourth conductor and has an opening; a second insulator that is disposed inside the opening of the first insulator, and contacts the upper surface of the first conductor, the upper surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator on the second insulator; and a fifth conductor on the third insulator, wherein the opening of the first insulator has a region overlapping with a region between the third conductor and the fourth conductor, the third insulator contacts an upper surface of the oxide in a region between the first conductor and the second conductor, and the distance between the first conductor and the second conductor is less than the distance between the third conductor and the fourth conductor in a cross-sectional view in a channel length direction of a transistor.

Description

Semiconductor device and storage device

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Furthermore, Patent Document 3 discloses a transistor with a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] JP 2012-257187 A JP 2011-151383 A International Publication No. 2016-125052

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0011] Another object of one embodiment of the present invention is to provide a storage device with a large storage capacity.Another object of one embodiment of the present invention is to provide a storage device with high operation speed.Another object of one embodiment of the present invention is to provide a storage device with low power consumption.Another object of one embodiment of the present invention is to provide a novel storage device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One aspect of the present invention is a semiconductor device comprising: an oxide on a substrate; a first conductor and a second conductor spaced apart from each other on the oxide; a third conductor in contact with an upper surface of the first conductor; a fourth conductor in contact with an upper surface of the second conductor; a first insulator having an opening on the third conductor and the fourth conductor; and a second insulator disposed in the opening of the first insulator and in contact with the upper surface of the first conductor, the upper surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor. A semiconductor device has a third insulator on the second insulator and a fifth conductor on the third insulator, an opening overlaps a region between the third conductor and the fourth conductor, the fifth conductor has a region overlapping with an oxide via the third insulator, the third insulator contacts an upper surface of the oxide in the region between the first conductor and the second conductor, and the distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor.

[0014] In the above, the first conductor and the second conductor preferably contain a metal nitride. Also, in the above, the first conductor and the second conductor preferably contain tantalum nitride. Also, in the above, it is preferable that the first conductor and the second conductor contain tantalum nitride, and the third conductor and the fourth conductor contain tungsten.

[0015] In the above, the second insulator preferably includes a nitride. In the above, the second insulator preferably includes silicon nitride.

[0016] In the above, the third insulator preferably includes an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0017] In the above, the third insulator preferably includes an aluminum oxide film, a silicon oxide film over the aluminum oxide film, and a silicon nitride film over the silicon oxide film.

[0018] In the above, the third insulator preferably includes an aluminum oxide film, a silicon oxide film over the aluminum oxide film, a hafnium oxide film over the silicon oxide film, and a silicon nitride film over the hafnium oxide film.

[0019] In the above, it is preferable that the second insulator contacts a side surface of the first insulator.

[0020] In the above, it is preferable that the third insulator contacts the top surface and side surface of the second insulator, the side surface of the first conductor, and the side surface of the second conductor.

[0021] Another embodiment of the present invention is a memory device including the above semiconductor device and a capacitor, in which one electrode of the capacitor is electrically connected to a third conductor of the semiconductor device.

[0022] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0023] According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. Alternatively, according to one embodiment of the present invention, a storage device with a high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a storage device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a novel storage device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0025] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2C are cross-sectional views showing an example of a semiconductor device. FIGS. 3A to 3C are cross-sectional views showing an example of a semiconductor device. FIG. 4A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 4B to 4D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 5A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 5B to 5D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 6A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 6B to 6D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 7A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 7B to 7D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 8A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 8B to 8D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIGS. 9A to 9D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 10A is a plan view showing an example of a manufacturing method of a semiconductor device. 10B to 10D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 11A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 11B to 11D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIGS. 12A to 12D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 13A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 13B to 13D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 14A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 14B to 14D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 15A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 15B to 15D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 16 is a block diagram illustrating an example of a memory device. FIGS. 17A and 17B are a schematic diagram and a circuit diagram illustrating an example of a memory device. FIGS. 18A and 18B are schematic diagrams illustrating an example of a memory device. FIG. 19 is a circuit diagram illustrating an example of a memory device. FIG. 20 is a cross-sectional view illustrating an example of a memory device. FIG. 21 is a cross-sectional view showing an example of a storage device.FIGS. 22A to 22C are circuit diagrams showing an example of a memory device. FIGS. 23A and 23B are diagrams showing an example of a semiconductor device. FIGS. 24A and 24B are diagrams showing an example of an electronic component. FIGS. 25A and 25B are diagrams showing an example of an electronic device, and FIGS. 25C to 25E are diagrams showing an example of a mainframe computer. FIG. 26 is a diagram showing an example of space equipment. FIG. 27 is a diagram showing an example of a storage system applicable to a data center. FIGS. 28A and 28B are graphs according to an example. FIG. 29 is a cross-sectional STEM image according to an example. FIGS. 30A to 30C are cross-sectional STEM images according to an example. FIGS. 31A and 31B are cross-sectional STEM images according to an example. FIGS. 32A and 32B are graphs of electrical characteristics according to an example. FIGS. 33A and 33B are graphs of electrical characteristics according to an example. FIGS. 34A and 34B are graphs of electrical characteristics according to an example.

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0029] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0030] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0031] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0032] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is approximately perpendicular to the substrate surface or the surface where the insulator is formed, the sidewall may have a tapered shape.

[0033] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0034] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0035] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device will be described with reference to FIGS. 1 to 3. FIGS. 1A to 1D are plan views and cross-sectional views of a semiconductor device (transistor 200). FIG. 1A is a plan view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the plan view of FIG. 1A for clarity. FIGS. 2A to 3C are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0036] The transistor 200 includes an insulator 216 on the insulator 215, a conductor 205 (conductor 205a and conductor 205b) embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0037] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. Furthermore, an insulator 255 is provided between the insulator 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280 and the insulator 250. The insulators 255, 250, and conductor 260 are embedded inside openings provided in the insulators 280 and 275. Furthermore, an insulator 282 is provided on the insulator 280 and the conductor 260. Furthermore, an insulator 283 is provided on the insulator 282.

[0038] The oxide 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 224 and the insulator 222 each have a region that functions as a second gate insulator of the transistor 200.

[0039] The conductor 242a has a region which functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 242b has a region which functions as the other of the source electrode and the drain electrode of the transistor 200.

[0040] Conductor 242a has a layered structure of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b has a layered structure of conductor 242b1 and conductor 242b2 on conductor 242b1. Conductors 242a1 and 242b1 in contact with oxide 230b are preferably conductors that are resistant to oxidation, such as metal nitrides. This prevents excessive oxidation of conductors 242a and 242b by oxygen contained in oxide 230b. Conductors 242a2 and 242b2 are preferably conductors, such as metal layers, that have higher conductivity than conductors 242a1 and 242b1. This allows conductors 242a and 242b to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided in which the conductors 242a and 242b, which function as wirings or electrodes, are provided in contact with the top surface of the oxide 230, which functions as an active layer.

[0041] As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. This configuration allows the distance between the source and the drain to be shortened, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. By miniaturizing the semiconductor device in this way, it is possible to provide a semiconductor device with improved operating speed.

[0042] The openings in the insulators 280 and 275 overlap the region between the conductors 242a2 and 242b2. Furthermore, portions of the conductors 242a1 and 242b1 are formed to protrude into the openings. Therefore, the insulator 255 contacts the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the openings. Furthermore, the insulator 250 contacts the top surface of the oxide 230 in the region between the conductors 242a1 and 242b1.

[0043] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductors 242a2 and 242b2. As will be described in detail later, after the conductors 242a1 and 242b1 are separated, it is preferable to perform heat treatment in an atmosphere containing oxygen before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented.

[0044] The oxide 230 preferably has an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0045] In this embodiment, the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b, but is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b, or a stacked structure of three or more layers.

[0046] In the oxide 230b, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the transistor 200. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0047] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0048] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0049] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0050] Note that when the carrier concentration of the oxide 230b is reduced, the impurity concentration in the oxide 230b is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0051] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. Furthermore, in order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0052] Note that the channel formation region, the source region, and the drain region may each be formed not only with the oxide 230b but also with the oxide 230a.

[0053] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0054] The oxide 230 (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0055] The band gap of a metal oxide functioning as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. A transistor having a metal oxide in a channel formation region like this is called an OS transistor. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0056] The oxide 230 preferably includes a metal oxide (oxide semiconductor). Examples of metal oxides that can be used for the oxide 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0057] The oxide 230 may be, for example, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also written as GZO), aluminum zinc oxide (aluminum zinc oxide), or indium aluminum zinc Examples of usable oxides include In-Al-Zn oxide (IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (IGZO), indium gallium tin zinc oxide (IGZTO), and indium gallium aluminum zinc oxide (IGAZO or IAGZO). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide) can be used.

[0058] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0059] Note that the metal oxide may contain one or more metal elements with a larger periodic number instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, including a metal element with a larger periodic number may improve the field-effect mobility of a transistor. Examples of metal elements with a larger periodic number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0060] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0061] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0062] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0063] As described above, the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0064] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0065] In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. With this structure, the transistor 200 can have large on-state current and high frequency characteristics.

[0066] Furthermore, since the oxide 230 a and the oxide 230 b contain a common element other than oxygen as a main component, the density of defect states at the interface between the oxide 230 a and the oxide 230 b can be reduced, which reduces the effect of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0067] Specifically, the oxide 230a can be a metal oxide having an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, an atomic ratio of In:M:Zn = 1:3:4 or a similar composition, or an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition. The oxide 230b can be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, or an atomic ratio of In:M:Zn = 4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M. Furthermore, when a single layer of oxide 230b is provided as oxide 230, the metal oxide that can be used for oxide 230a may be used for oxide 230b. Furthermore, the compositions of metal oxides that can be used for oxide 230a and oxide 230b are not limited to those described above. For example, the composition of a metal oxide that can be used for oxide 230a may be used for oxide 230b. Similarly, the composition of a metal oxide that can be used for oxide 230b may be used for oxide 230a.

[0068] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0069] The oxide 230b preferably has crystallinity. In particular, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0070] CAAC-OS is a metal oxide having a highly crystalline and dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by performing heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0071] Furthermore, since it is difficult to identify clear crystal boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal boundaries is unlikely to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0072] Furthermore, by using a crystalline oxide such as CAAC-OS as the oxide 230b, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be suppressed, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0073] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and the channel formation region be i-type (intrinsic) or substantially i-type.

[0074] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0075] Therefore, in an oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0076] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0077] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide 230b. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0078] 2A, the insulator 250 preferably has a layered structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, it is preferable that the insulator 250a has the function of capturing and fixing hydrogen.

[0079] Examples of insulators that have the function of capturing and fixing hydrogen include metal oxides with an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 250a. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0080] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 250a. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulator 250a makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0081] For the above reasons, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 250a, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. In this case, the insulator 250a is an insulator containing at least oxygen and aluminum. Furthermore, the aluminum oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0082] Next, it is preferable to use an insulator with a thermally stable structure, such as silicon oxide or silicon oxynitride, for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0083] 2C, a structure may be adopted in which an insulator 250d is provided on the insulator 250b. In this case, the insulator 250d may be an insulator that can be used for the insulator 250a. For example, hafnium oxide may be used for the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0084] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250c, the insulator 250d, the insulator 255, and the insulator 275.

[0085] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0086] Examples of oxygen barrier insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, 255, and 275 each preferably have a single-layer structure or a stacked-layer structure of the oxygen barrier insulators.

[0087] The insulators 250a and 255 preferably have barrier properties against oxygen. The insulators 250a and 255 are preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a1 and the side surface of the conductor 242b1. The insulator 255 has a region in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. The insulator 250a also contacts the top surface and side surface of the insulator 255. The insulators 250a and 255 have barrier properties against oxygen, which can prevent the side surfaces of the conductors 242a and 242b from being oxidized and oxide films from being formed on the side surfaces. This can prevent a decrease in the on-state current or field-effect mobility of the transistor 200.

[0088] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide 230b when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the oxide 230a and the oxide 230b can be reduced.

[0089] Furthermore, by providing the insulators 250a and 255, even if the insulator 280 contains an excessive amount of oxygen, the oxygen can be prevented from being excessively supplied to the oxides 230a and 230b, and an appropriate amount of oxygen can be supplied to the oxides 230a and 230b. Therefore, excessive oxidation of the source and drain regions can be prevented, which can cause a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0090] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen and can therefore be suitably used as the insulator 250a. Silicon nitride also has a barrier property against oxygen and can therefore be suitably used as the insulator 255.

[0091] The insulator 250c preferably has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This structure can prevent oxygen contained in the channel formation region of the oxide 230 from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide 230. Furthermore, it can prevent oxygen contained in the oxide 230 and oxygen contained in the insulator 280 from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250c is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250c. In this case, the insulator 250c is an insulator containing at least nitrogen and silicon.

[0092] The insulator 250c preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide 230b.

[0093] The insulator 275 preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a, and between the insulator 280 and the conductor 242b. This configuration can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242a and the conductor 242b. Therefore, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized by the oxygen contained in the insulator 280, thereby increasing their resistivity and reducing their on-state current. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0094] To prevent a decrease in the hydrogen concentration in the source and drain regions in the oxide 230, it is preferable to provide a barrier insulator against hydrogen near each of the source and drain regions. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0095] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0096] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions, thereby making the source and drain regions n-type.

[0097] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0098] The insulators 250a to 250d function as part of the first gate insulator. The insulators 250a to 250d, together with the insulator 255 and the conductor 260, are provided in an opening formed in the insulator 280. To miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above thickness at least in part.

[0099] To thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to form the insulators using an atomic layer deposition (ALD) method. ALD methods include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, which enables film formation at a lower temperature.

[0100] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling extremely thin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 255 and the insulator 250 can be formed with good coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b, etc., with the thin film thickness as described above.

[0101] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0102] Although the above description has been given of a structure in which the insulator 250 has a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can also have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0103] For example, as shown in FIG. 2B , the insulator 250 may have a two-layer structure. In this case, it is preferable that the insulator 250 has a stacked structure of an insulator 250a and an insulator 250c on the insulator 250a. A high-k material can be used for at least one of the insulators 250a and 250c. This allows the equivalent oxide thickness (EOT) to be reduced while maintaining the thicknesses of the insulators 250a and 250c at a level that suppresses leakage current.

[0104] 2B , in the transistor 200 according to this embodiment, a region overlapping with the insulator 250 in contact with the side surface of the conductor 242a1 and a region overlapping with the insulator 250 in contact with the side surface of the conductor 242b1 (hereinafter referred to as an Loff region) are formed in the oxide 230b. The Loff region does not overlap with the conductor 242a1 or the conductor 242b1 and does not properly overlap with the conductor 260 via the insulator 250, and therefore functions as a resistor.

[0105] In the transistor 200 shown in FIG. 2B , the insulator 250 is formed only from the insulator 250 a and the insulator 250 c, and the thicknesses of the insulators 250 a and 250 c can be thinned as described above. For example, the insulator 250 a can be formed using aluminum oxide to a thickness of 2.0 nm, and the insulator 250 c can be formed using silicon nitride to a thickness of 1.5 nm, resulting in a thickness of the insulator 250 of 3.5 nm. By thinning the thickness of the insulator 250 in this manner, the width of the Loff region can also be reduced. Therefore, the frequency characteristics of the transistor 200 can be improved, and the operating speed of the semiconductor device according to one embodiment of the present invention can be increased.

[0106] Furthermore, in this embodiment, an insulator 255 is provided between the insulator 250 and the conductor 242a, and between the insulator 250 and the conductor 242b. This allows the distance between the conductor 260 and the conductor 242a and the distance between the conductor 260 and the conductor 242b to be increased by the thickness of the insulator 255. Therefore, the film thickness of the insulator 250 can be made thinner to reduce the Loff region while reducing the parasitic capacitance between the conductor 260 and the conductor 242a and between the conductor 242b and the conductor 242b.

[0107] In addition to the above structure, in this embodiment, the semiconductor device preferably has a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, an insulator that has a function of suppressing hydrogen diffusion is preferably provided so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 282 or an insulator 283. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0108] It is preferable that one or more of the insulators 282 and 283 function as a barrier insulator that prevents impurities such as water and hydrogen from diffusing from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 282 and 283 may be a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0109] The insulators 282 and 283 preferably have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulator 283 is preferably made of silicon nitride, which has a higher hydrogen barrier property. Furthermore, the insulator 282 preferably has aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen. This can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 283 to the transistor 200. Furthermore, oxygen contained in the insulator 280 can be suppressed from diffusing upward from the transistor 200 via the insulator 282. Furthermore, by using the insulator 215 with a structure similar to that of one or both of the insulators 282 and 283, impurities such as water and hydrogen can be prevented from diffusing from the substrate side to the transistor 200 and the like through the insulator 215. Furthermore, oxygen contained in the insulator 224 and the like can be prevented from diffusing to the substrate side. In this way, it is preferable to have a structure in which the top and bottom of the transistor 200 and the like are surrounded by insulators that have a function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0110] In the transistor 200, the conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 1A and 1C. With this structure, when a plurality of transistors are provided, the conductor 205 functions as a wiring.

[0111] The conductor 205 may have a single-layer structure or a multilayer structure. In FIG. 1 and other figures, the conductor 205 includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill a recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 is approximately the same as the height of the upper surface of the insulator 216.

[0112] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0113] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 216, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress oxidation of the conductor 205b and a decrease in conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0114] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0115] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0116] Furthermore, the electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. Furthermore, the film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0117] Insulator 222 and insulator 224 function as a second gate insulator.

[0118] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0119] The insulator 222 preferably includes an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator. Alternatively, an oxide containing hafnium and zirconium, such as hafnium zirconium oxide, is preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with oxygen contained in the insulator 224 and the oxide 230.

[0120] Alternatively, the insulator may be doped with, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

[0121] The insulator 222 may have a single-layer structure or a multi-layer structure of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. The insulator 222 may also be made of lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), (Ba,Sr)TiO ３ In some cases, a material with a high dielectric constant such as (BST) can be used.

[0122] The insulator 224 in contact with the oxide 230 preferably contains, for example, silicon oxide or silicon oxynitride, which allows oxygen to be supplied from the insulator 224 to the oxide 230 and reduces oxygen vacancies.

[0123] Furthermore, like the oxide 230, the insulator 224 is preferably processed into an island shape. As a result, when multiple transistors 200 are provided, the insulators 224 are provided with approximately the same size for each transistor 200. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed. However, this is not limited thereto, and like the insulator 222, the insulator 224 may also be configured without being patterned.

[0124] Each of the insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structures are not limited to those made of the same material, and may be stacked structures made of different materials.

[0125] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0126] In FIG. 1B, the conductors 242a and 242b are shown as a two-layer structure. The conductor 242a is a laminated film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the layer in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1). This can prevent the conductivity of the conductors 242a and 242b from decreasing. In addition, it can prevent oxygen from being extracted from the oxide 230b, thereby preventing excessive oxygen vacancies from being formed. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide 230b (the conductor 242a1 and the conductor 242b1), since this can reduce the hydrogen concentration in the oxide 230b.

[0127] For the conductors 242a1 and 242b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0128] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, by using a nitride containing tantalum for the conductors 242a1 and 242b1, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0129] Furthermore, it is preferable that the conductors 242a2 and 242b2 have higher conductivity than the conductors 242a1 and 242b1. For example, it is preferable that the film thickness of the conductors 242a2 and 242b2 be greater than the film thickness of the conductors 242a1 and 242b1. Conductors that can be used for the conductor 205b may be used for the conductors 242a2 and 242b2. By using the above structure, the resistance of the conductors 242a2 and 242b2 can be reduced. This can improve the operating speed of the semiconductor device according to this embodiment.

[0130] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0131] Furthermore, to prevent a decrease in the conductivity of the conductors 242a and 242b, it is preferable to use a crystalline oxide such as CAAC-OS as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. Furthermore, a decrease in the conductivity of the conductors 242a and 242b can be prevented.

[0132] 1B and 1C , the insulator 255 is disposed in an opening formed in the insulator 280, etc., and contacts the side surfaces of the insulator 280, the side surfaces of the insulator 275, the side surfaces of the insulator 271a, the side surfaces of the insulator 271b, the side surfaces of the conductors 242a2, 242b2, 242a1, and 242b1, and the top surface of the insulator 222. In other words, the openings in the insulator 255 can be said to be formed so as to expose the island-shaped oxide 230 in the openings. Furthermore, in the region where the openings in the insulator 255 are formed, the insulator 250 contacts the oxide 230 and the insulator 222. Note that in FIG. 1C , the insulator 255 has openings only near the oxide 230, but the present invention is not limited to this. The insulator 255 only needs to have an opening in at least the region of the oxide 230b that is sandwiched between the conductors 242a1 and 242b1. Therefore, for example, the insulator 255 may have almost no region in contact with the insulator 222 and may be formed in a sidewall shape in the opening formed in the insulator 280.

[0133] The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and is an inorganic insulator that protects the conductors 242a2 and 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is resistant to oxidation. Furthermore, because the insulator 255 is in contact with the conductors 242a2 and 242b2, it is preferably an inorganic insulator that is resistant to oxidation of the conductors 242a2 and 242b2. Therefore, it is preferable that the insulator 255 be made of an insulating material that can be used for the insulator 250c, which has oxygen barrier properties. For example, silicon nitride can be used as the insulator 255.

[0134] By using such an insulator 255, the conductors 242a2 and 242b2 are not excessively oxidized even if heat treatment is performed in an oxygen-containing atmosphere after separating the conductors 242a1 and 242b1 and before forming the insulator 250. For example, the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0135] The insulator 255 is preferably thicker than any one of the insulators 250a to 250d. The thickness of the insulator 255 is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and even more preferably 3 nm to 10 nm; for example, the thickness can be approximately 5 nm. By setting the insulator 255 to the above thickness, the distance between the conductor 260 and the conductor 242a or 242b can be increased, and parasitic capacitance can be reduced. Note that the insulator 255 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulator 255 is provided in the opening formed in the insulator 280, it is preferable to form the insulator 255 using an ALD method or the like, which has good coverage.

[0136] The insulator 255 may also have a stacked structure of two or more layers using the above-mentioned inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. When the insulator 255 has a stacked structure of two or more layers, at least one layer may be the above-mentioned inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film. For example, the insulator 255 may have a two-layer structure of an aluminum oxide film and a silicon oxide film on the aluminum oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and a silicon nitride film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and a silicon oxide film on the silicon oxide film. For example, the insulator 255 may have a two-layer structure of a silicon oxide film and an aluminum oxide film on the silicon oxide film.

[0137] Furthermore, the insulator 255 functions as part of a mask when dividing the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 1B , in a cross-sectional view of the transistor 200, it is preferable that the side edges of the insulator 255 roughly coincide with the side edges of the conductor 242a1 and the conductor 242b1.

[0138] In addition, when the side edges are aligned or approximately aligned in a cross-sectional view, and when the top surface shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a top view. For example, this includes a case where the lower portion of the side edge of the upper layer contacts the upper portion of the side edge of the lower layer. It also includes a case where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In this case, too, it is said that the side edges are approximately aligned or the top surface shapes are approximately aligned.

[0139] Here, the portion of the conductor 242a1 on which the insulator 255 is formed on the upper surface protrudes toward the conductor 260 more than the conductor 242a2. Similarly, the portion of the conductor 242b1 on which the insulator 255 is formed on the upper surface protrudes toward the conductor 260 more than the conductor 242b2. As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2.

[0140] The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably small because it affects the channel length of the transistor 200. For example, the distance L2 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. For example, the distance L2 is more preferably approximately 2 nm or more and 20 nm or less. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0141] 2A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are approximately perpendicular to the top surface of the oxide 230b, but the present invention is not limited to this. For example, as shown in FIG. 3A, the opposing side surfaces of the conductor 242a1 and the conductor 242b1 may be tapered. By adopting such a shape, the distance between the conductor 260 and the oxide 230b is reduced near the side ends of the conductor 242a1 and the conductor 242b1, thereby reducing the influence of the Loff region.

[0142] Furthermore, as shown in FIG. 3B, the opposing side surfaces of the conductors 242a1 and 242b1 may be tapered, and the opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered.

[0143] 3C, the taper angles of the conductors 242a1 and 242b1 may be configured to be more acute than the taper angles of the conductors 242a2 and 242b2. By configuring in this manner, the distance between the conductor 260 and the oxide 230b becomes smaller near the side ends of the conductor 242a1 and the conductor 242b1, thereby reducing the influence of the Loff region.

[0144] The insulators 271a and 271b are inorganic insulators that function as etching stoppers and protect the conductors 242a2 and 242b2 when processing the conductors 242a2 and 242b2. Furthermore, since the insulators 271a and 271b contact the conductors 242a2 and 242b2, they are preferably inorganic insulators that are less likely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 2A , it is preferable that the insulator 271a has a layered structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a layered structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably made of a nitride insulator that can be used for the insulator 250c so as to prevent oxidation of the conductors 242a2 and 242b2, and the insulators 271a2 and 271b2 are preferably made of an oxide insulator that can be used for the insulator 250b so as to function as an etching stopper.

[0145] Here, the insulator 271a1 is in contact with the upper surface of the conductor 242a2 and a portion of the insulator 275, and the insulator 271b1 is in contact with the upper surface of the conductor 242b2 and a portion of the insulator 275. The insulator 271a2 is in contact with the upper surface of the insulator 271a1 and a lower surface of the insulator 275, and the insulator 271b2 is in contact with the upper surface of the insulator 271b1 and a lower surface of the insulator 275. For example, silicon nitride can be used for the insulators 271a1 and 271b1, and silicon oxide can be used for the insulators 271a2 and 271b2.

[0146] The insulators that form the insulators 271a and 271b function as masks for the conductors that form the conductors 242a and 242b, so the conductors 242a and 242b do not have curved surfaces between their side surfaces and top surfaces. As a result, the ends where the side surfaces and top surfaces of the conductors 242a and 242b intersect are angular. The angular ends where the side surfaces and top surfaces of the conductors 242a and 242b intersect are larger in cross-sectional area than when the ends have curved surfaces. Furthermore, using a nitride insulator that does not easily oxidize metals for the insulators 271a1 and 271b1 can prevent the conductors 242a and 242b from being excessively oxidized. As a result, the resistance of the conductors 242a and 242b is reduced, thereby increasing the on-state current of the transistor.

[0147] 1B and 1C, the conductor 260 is disposed in an opening formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening so as to cover the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. Note that a portion of the conductor 260 is disposed so as to overlap the conductor 242a1 and the conductor 242b1. The conductor 260 is disposed so that its top surface is approximately at the same height as the top of the insulator 250 and the top surface of the insulator 280.

[0148] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be approximately perpendicular to the upper surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the insulators 255 and 250, etc., provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0149] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0150] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as a rounded shape).

[0151] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductors 242a and 242b, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably 1 nm or larger and 15 nm or smaller, and more preferably 2 nm or larger and 10 nm or smaller. By using such a shape, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0152] In this specification, a transistor structure in which a channel formation region is electrically surrounded by the electric field of at least the first gate electrode is referred to as a surrounded channel (S-channel) structure. The S-channel structure disclosed in this specification is different from the Fin structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin structure. In this specification, a Fin structure refers to a structure in which a gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By employing the Fin structure and the S-channel structure, resistance to the short channel effect can be increased, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0153] By forming the transistor 200 in the S-channel structure, the channel formation region can be electrically surrounded. Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a Gate All Around (GAA) structure or a Lateral Gate All Around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be improved, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0154] In this embodiment, the insulator 224 is provided in an island shape. Therefore, as shown in FIG. 1C , at least a portion of the lower surface of the conductor 260 can be provided below the lower surface of the oxide 230b. This allows the conductor 260 to be provided facing the upper surface and side surface of the oxide 230b, so that the electric field of the conductor 260 can be applied to the upper surface and side surface of the oxide 230b. By providing the insulator 224 in an island shape in this way, the transistor 200 can have an S-channel structure.

[0155] 1C illustrates an example of a transistor with an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, the transistor structure that can be used in one embodiment of the present invention may be one or more selected from a planar structure, a Fin structure, and a GAA structure.

[0156] In Figure 1B and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0157] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0158] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0159] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0160] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0161] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0162] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0163] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0164] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0165] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0166] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0167] <<Substrate>> Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include semiconductor substrates having an insulator region within the semiconductor substrate, such as SOI (Silicon-On-Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductor substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0168] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0169] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select a material depending on the function of the insulator.

[0170] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0171] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0172] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0173] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0174] <<Conductor>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal element as a component, or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0175] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0176] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0177] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0178] <<Metal Oxide>> A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Metal oxides that can be used as the oxide 230 of one embodiment of the present invention are described below.

[0179] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, antimony, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, or the like.

[0180] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, tin, or antimony. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, element M may be a combination of multiple elements. In particular, element M is preferably one or more elements selected from gallium, aluminum, yttrium, and tin.

[0181] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0182] Hereinafter, an In—Ga—Zn oxide will be described as an example of a metal oxide.

[0183] Examples of the crystal structure of an oxide semiconductor include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0184] Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0185] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0186] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0187] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the maximum diameter of the crystalline region may be several tens of nanometers.

[0188] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0189] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS does not exhibit regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

[0190] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and the CAAC-OS.

[0191] Next, the above-mentioned CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0192] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0193] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0194] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions (first regions) mainly containing In and regions (second regions) mainly containing Ga is randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0195] The CAC-OS can be formed by sputtering without heating the substrate, for example. When forming the CAC-OS by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas can be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is set to 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0196] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0197] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0198] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and functions as a semiconductor as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0199] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is ideal for various semiconductor devices such as display devices.

[0200] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0201] <<Other Semiconductor Materials>> A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer of a transistor. For example, a semiconductor of a simple element such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0202] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer of the transistor. Specifically, molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-described transition metal chalcogenide to the semiconductor layer of a transistor, a semiconductor device with a large on-state current can be provided.

[0203] 4A to 15D, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 1D will be described as an example.

[0204] In Figures 5 to 8, 10, 11, and 13 to 15, A in each figure represents a plan view. B in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in A of each figure, and is also a cross-sectional view of the transistor 200 in the channel length direction. C in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in A of each figure, and is also a cross-sectional view of the transistor 200 in the channel width direction. D in each figure represents a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in A of each figure, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted from the plan view A in each figure for clarity. Figures 9A to 9D and 12A to 12D are enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0205] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed as a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0206] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0207] CVD methods can be classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0208] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0209] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0210] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0211] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0212] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0213] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 4A to 4D ). As described above, the insulator 215 can be formed using an insulator similar to one or more of the insulators 224, 282, and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0214] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0215] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0216] Next, an opening is formed in the insulator 216, reaching the insulator 215. The opening may be formed by wet etching, but dry etching is preferable for fine processing. Furthermore, it is preferable to select an insulator for the insulator 215 that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 215 may be made of silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0217] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film that becomes the conductor 205a preferably includes a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film can be a stacked film of a conductor that has a function of suppressing oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0218] In this embodiment, titanium nitride is formed as the conductive film that becomes the conductor 205a. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0219] Next, a conductive film to be the conductor 205b is formed. For the conductive film to be the conductor 205b, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film to be the conductor 205b.

[0220] Next, CMP treatment is performed to remove a portion of the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, thereby exposing the insulator 216 (see FIGS. 4A to 4D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP treatment may remove a portion of the insulator 216.

[0221] Next, an insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 5A to 5D).

[0222] The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. As the insulator containing one or both of aluminum and hafnium oxides, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0223] Alternatively, the insulator 222 can be a stacked film of an insulator containing an oxide of one or both of aluminum and hafnium, and silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide.

[0224] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method. Alternatively, the insulator 222 may be a stacked film of silicon nitride formed by a PEALD method and hafnium oxide formed by an ALD method.

[0225] Next, an insulating film 224f is formed over the insulator 222 (see FIGS. 5A to 5D). As the insulating film 224f, an insulator corresponding to the insulator 224 may be used.

[0226] The insulating film 224f can be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is formed as the insulating film 224f by sputtering. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f will come into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0227] Note that heat treatment may be performed before the formation of the insulating film 224f. The heat treatment may be performed under reduced pressure, and the insulating film 224f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 222 can be removed and the moisture and hydrogen concentrations in the insulator 222 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0228] Next, an oxide film 230af is formed on the insulating film 224f, and an oxide film 230bf is formed on the oxide film 230af (see FIGS. 5A to 5D ). The oxide film 230af may be a metal oxide corresponding to the oxide 230a, and the oxide film 230bf may be a metal oxide corresponding to the oxide 230b. It is preferable to form the oxide films 230af and 230bf consecutively without exposing them to the air. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air from adhering to the oxide films 230af and 230bf, and to keep the vicinity of the interface between the oxide films 230af and 230bf clean.

[0229] The oxide film 230af and the oxide film 230bf can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the oxide film 230af and the oxide film 230bf are formed by a sputtering method.

[0230] For example, when the oxide film 230af and the oxide film 230bf are formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, an In-M-Zn oxide target or the like can be used.

[0231] In particular, during the formation of the oxide film 230af, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the proportion of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and even more preferably 100%.

[0232] When the oxide film 230bf is formed by a sputtering method, an oxygen-excess oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230bf is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0233] In this embodiment, the oxide film 230af is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2 or an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. The oxide film 230bf is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1, an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2, an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, or an oxide target with an atomic ratio of In:Ga:Zn = 1:1:2. The oxide films 230a and 230b can be formed according to the desired characteristics of the oxides 230a and 230b by appropriately selecting the deposition conditions and atomic ratios.

[0234] Note that the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus is preferably used. This can reduce the inclusion of hydrogen in the insulating film 224f, the oxide film 230af, and the oxide film 230bf between film formation steps.

[0235] Next, heat treatment is preferably performed within a temperature range in which the oxide film 230af and the oxide film 230bf are not polycrystallized. The temperature of the heat treatment is preferably 100° C. or higher, 250° C. or higher, or 350° C. or higher, and 650° C. or lower, 600° C. or lower, or 550° C. or lower.

[0236] The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0237] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the oxide film 230af and the oxide film 230bf as much as possible.

[0238] In this embodiment, the heat treatment is performed at 450° C. for 1 hour with a nitrogen gas / oxygen gas flow ratio of 4:1. This heat treatment using oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. Reducing the impurities in the film in this manner improves the crystallinity of the oxide film 230bf, resulting in a denser, more compact structure. This increases the crystalline regions in the oxide film 230af and the oxide film 230bf, reducing the in-plane variation of the crystalline regions in the oxide film 230af and the oxide film 230bf. This reduces the in-plane variation of the electrical characteristics of the transistor.

[0239] Furthermore, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentrations in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decrease.

[0240] In particular, the insulating film 224f (later the insulator 224) functions as a second gate insulator of the transistor 200, and the oxide film 230af and the oxide film 230bf (later the oxide 230a and the oxide 230b) function as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentrations are reduced has good reliability and is therefore preferable.

[0241] Next, a conductive film 242_1f is formed on the oxide film 230bf, and a conductive film 242_2f is formed on the conductive film 242_1f (see FIGS. 5A to 5D ). Conductors corresponding to the conductors 242a1 and 242b1 may be used as the conductive film 242_1f, and conductors corresponding to the conductors 242a2 and 242b2 may be used as the conductive film 242_2f. By forming the conductive film 242_1f on and in contact with the oxide film 230bf without performing an etching process or the like after the oxide film 230bf is formed, the top surface of the oxide film 230bf can be protected by the conductive film 242_1f. This can reduce diffusion of impurities into the oxide 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0242] The conductive films 242_1f and 242_2f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0243] In this embodiment, tantalum nitride is deposited as the conductive film 242_1f and tungsten is deposited as the conductive film 242_2f by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film 242_1f. The heat treatment may be performed under reduced pressure, and the conductive film 242_1f may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0244] Next, an insulating film 271f is formed over the conductive film 242_1f (see FIGS. 5A to 5D ). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271f may be formed by a sputtering method to form a stacked film of a silicon nitride film and a silicon oxide film over the silicon nitride film.

[0245] Here, when the insulating film 271f is a stacked film, it is preferable to deposit the films successively without exposing them to the air. By depositing the films without exposing them to the air, the vicinity of the interface of the stacked film of the insulating film 271f can be kept clean. It is more preferable to deposit the conductive film 242_1f to the insulating film 271f successively without exposing them to the air.

[0246] Note that heat treatment may be performed before the formation of the insulating film 271f. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surfaces of the conductive films 242_1f and 242_2f can be removed, and the moisture and hydrogen concentrations in the conductive films 242_1f and 242_2f can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0247] Next, the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are processed into island shapes using lithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 (see Figures 6A to 6D).

[0248] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. The insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f may be processed under different conditions.

[0249] Here, the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are preferably collectively processed into an island shape. In this case, the side edges of the conductor 242_1 and the conductor 242_2 preferably roughly coincide with the side edges of the oxide 230a and the oxide 230b. Furthermore, the side edges of the insulator 224 preferably roughly coincide with the side edges of the oxide 230. Furthermore, the side edges of the insulator 271 preferably roughly coincide with the side edges of the conductor 242_2. Such a structure can reduce the number of steps required to manufacture a semiconductor device according to one embodiment of the present invention. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0250] The insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed so as to at least partially overlap with the conductor 205. The insulator 222 is exposed in a region that does not overlap with the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, or the insulator 271.

[0251] 6B , the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be, for example, greater than or equal to 60° and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0252] Furthermore, without being limited to the above, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may be approximately perpendicular to the top surface of the insulator 222. With such a structure, a reduction in area and a high density can be achieved when providing multiple transistors.

[0253] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, an etching process is performed through the resist mask, allowing a conductor, semiconductor, or insulator to be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0254] Note that the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma treatment, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0255] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. Etching of the insulating film 271f and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the oxide film 230bf and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0256] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. The configuration in which an SOC film, an SOG film, and a resist mask are sequentially formed on the workpiece and then lithography is performed is described in the steps shown in FIGS. 9A to 9D and 12A to 12D, which will be described later, and the descriptions in those sections can be referenced.

[0257] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr３ Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0258] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0259] Furthermore, in the etching process, the insulator 271 can function as an etching stopper that protects the conductor 242_2. For example, if a metal hard mask is formed on the insulator 271 in the etching process, it may be difficult to obtain an etching selectivity with respect to the conductor 242_2 when removing the hard mask. However, by forming the insulator 271 on the conductor 242_2, the insulator 271 can function as an etching stopper that protects the conductor 242_2 in the etching process for removing the hard mask. This prevents a curved surface from being formed between the side surface and the top surface of the conductor 242_2, so that the conductors 242a2 and 242b2, which will be formed later, have angular ends where the side surface and the top surface intersect. The angular ends where the side surface and the top surface of the conductor 242_2 intersect increase the cross-sectional area of ​​the conductor 242_2 compared to when the ends have a curved surface. Furthermore, excessive oxidation of the conductor 242_2 can be prevented by using a nitride insulator that does not easily oxidize metal for the insulator 271. This reduces the resistance of the conductor 242a2 and the conductor 242b2, thereby increasing the on-state current of the transistor.

[0260] Furthermore, by processing the insulator 224 into an island shape, insulator 275 can be provided in contact with the side surface of insulator 224 and the top surface of insulator 222 in a process described later. In other words, insulator 224 can be separated from insulator 280, which will be formed in a later process, by insulator 275. This structure can prevent excessive amounts of oxygen and impurities such as hydrogen from being mixed into oxide 230 from insulator 280 via insulator 224.

[0261] Furthermore, by processing the insulator 224 into an island shape, when multiple transistors 200 are provided, the insulators 224 are provided with approximately the same size for each transistor 200. As a result, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed. However, this is not limited thereto, and the insulator 224 may be configured without being patterned, similar to the insulator 222.

[0262] Next, an insulator 275 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271, and then an insulator 280 is formed over the insulator 275 (see FIGS. 7A to 7D). The insulators described above may be used for the insulators 275 and 280.

[0263] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0264] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0265] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0266] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0267] In this manner, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275, which has a function of suppressing oxygen diffusion. This reduces direct diffusion of oxygen from the insulator 280 or the like to the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, and the conductor 242_2 in a later process.

[0268] Furthermore, it is preferable to form a silicon oxide film as the insulator 280 by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc., can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0269] Next, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed using lithography to form openings that reach the conductor 242_1 and the insulator 222 (see FIGS. 8A to 8D ). Here, the conductor 242_2 is divided to form the conductors 242a2 and 242b2, and the insulator 271 is divided to form the insulators 271a and 271b. The opening that reaches the conductor 242_1 is formed in a region where the oxide 230b and the conductor 205 overlap. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L1, which corresponds to the distance L1 between the conductor 242a2 and the conductor 242b2 described above.

[0270] The lithography method can be any of the above-mentioned methods, as appropriate. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0271] Below, specific examples of processing the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 will be described with reference to FIGS. 9A to 9D.

[0272] First, a coating film 277f is formed on the insulator 280, and then a coating film 278f is formed ( FIG. 9A ). The coating films 277f and 278f may have the function of improving adhesion with a resist mask. The coating films 277f and 278f may be formed using, for example, a spin coating method. A non-photosensitive organic resin may be used as the coating films 277f and 278f. In this embodiment, an SOC film is formed as the coating film 277f, and an SOG film is formed as the coating film 278f. Here, the coating films 277f and 278f contain an organic solvent such as alcohol during application. However, the organic matter contained therein may be reduced or removed during subsequent processes or upon completion of the semiconductor device. Note that the coating film may be provided as needed. The coating film may be configured as a single layer, or if a resist mask, as described below, is sufficient, a coating film may not be provided.

[0273] Next, a resist mask 279 is formed on the coating film 278f using lithography ( FIG. 9A ). The resist mask 279 has an opening with a width L1 when viewed cross-sectionally in the channel length direction. The resist mask 279 may be made of a photosensitive organic resin also known as photoresist. For example, a positive photoresist or a negative photoresist may be used. The photoresist that becomes the resist mask 279 can be formed to a uniform thickness by, for example, forming the resist mask 279 using a spin coating method.

[0274] 9B to 9D, the structure shown in FIG. 9A is etched using a dry etching method. Dry etching is capable of anisotropic etching, making it suitable for forming an opening with a width L1 and a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found above. The etching of the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 may be performed under different conditions.

[0275] First, a coating film 278f is processed using a resist mask 279 to form a coating film 278, and then a coating film 277f is processed to form a coating film 277 (FIG. 9B). Here, openings with a width L1 are formed in the coating films 278 and 277. For example, when an SOG film is used for the coating film 278f, CF ４ For example, when an SOC film is used as the coating film 277f, H ２ and N ２ can be used as the etching gas.

[0276] The resist mask 279 may disappear before the coating film 277 is formed. If the resist mask 279 remains after the coating film 277 is formed, the resist mask 279 may be removed.

[0277] Next, using the coating film 277 as a mask, the insulator 280 is processed to form an opening with a width L1, and the insulator 275 is further processed to form an opening with a width L1 (FIG. 9C). For example, when silicon oxide is used for the insulator 280, ４ F ８ and C ４ F ６ and O ２ For example, when silicon nitride is used for the insulator 275, CH ２ F ２ and O ２ and Ar can be used as etching gases.

[0278] Next, using the coating film 277 as a mask, the insulator 271 is processed and divided to form insulators 271a and 271b (FIG. 9C). Here, the region between the insulators 271a and 271b overlaps with an opening of width L1, and the distance between the insulators 271a and 271b is L1. For example, when a stacked film of silicon nitride and silicon oxide is used for the insulator 271, the insulator 271 is formed by etching with CHF ３ and O ２ The etching process can be carried out using the above as an etching gas.

[0279] Next, using the coating film 277 as a mask, the conductor 242_2 is processed and divided to form the conductor 242a2 and the conductor 242b2 (FIG. 9D). Here, the region between the conductor 242a2 and the conductor 242b2 overlaps with an opening of width L1, and the distance between the conductor 242a2 and the conductor 242b2 is L1. For example, when tungsten is used for the conductor 242_2 and tantalum nitride is used for the conductor 242_1, CF ４ and Cl ２ and O ２ The etching process can be carried out using the above as an etching gas.

[0280] Here, in order to form conductors 242a1 and 242b1, which are spaced apart by L2, below conductors 242a2 and 242b2 in a later step, the etching process in this step needs to be stopped at the top surface of conductor 242_1. Therefore, in this step, the etching process is performed using an ICP etching device under conditions where the etching rate of conductor 242_2 is greater than the etching rate of conductor 242_1 (hereinafter referred to as the etching selectivity of conductor 242_2).

[0281] By lowering the bias power applied to the lower electrode of the ICP etching apparatus, the ion incident energy can be reduced, and the etching rate of the conductor 242_1 can be reduced. For example, the bias power applied to the lower electrode of the ICP etching apparatus can be set to less than 50 W, preferably about 25 W or less.

[0282] Also, CF ４ and Cl ２and O ２ As an etching gas, the tungsten of the conductor 242_2 is etched with WF ６ , or WOCl, resulting in a highly volatile reaction product, which increases the etching rate. On the other hand, tantalum nitride on the surface of the conductor 242_1 becomes a very low-volatility reaction product, such as tantalum oxide or tantalum oxynitride, which suppresses etching. Therefore, by increasing the flow rate ratio of oxygen gas in the etching gas, the etching selectivity of the conductor 242_2 can be increased. For example, the flow rate ratio of oxygen gas in the etching gas may be set to be greater than 35%, approximately 48% or greater.

[0283] By performing the etching process on the conductor 242_2 under the above conditions, the etching selectivity of the conductor 242_2 can be increased. Therefore, the conductor 242_1 can be divided into the conductor 242a2 and the conductor 242b2 without being excessively etched. This allows processing as designed even in a semiconductor device having a fine structure.

[0284] The coating film 277 may be removed by performing a dry etching process such as ashing using oxygen plasma, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0285] Furthermore, the processing of the insulator 271 and the conductor 242_2 and the removal of the coating film 277 can be performed successively without exposure to the outside air. For example, the processing can be performed using a multi-chamber etching apparatus without exposure to the outside air.

[0286] In this manner, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 can be processed to form an opening with a width L1.

[0287] Next, an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 10A to 10D ). The insulating film 255A is an insulating film that will become the insulator 255 in a later process, and any of the above-described insulators can be used. The insulating film 255A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0288] The insulating film 255A preferably has good coverage because it is formed along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280. Therefore, the insulating film 255A is preferably formed using an ALD method or the like that has good coverage. For example, it is preferable to form the insulating film 255A using silicon nitride using the PEALD method.

[0289] Next, the conductor 242_1 and the insulating film 255A are processed using lithography within the opening formed in the insulator 280 to form an opening reaching the oxide 230b (see FIGS. 11A to 11D ). Here, an insulator 255 having an opening is formed from the insulating film 255A, and the conductor 242_1 is divided to form the conductor 242a1 and the conductor 242b1. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L2, which corresponds to the distance L2 between the conductor 242a1 and the conductor 242b1. Because the opening is formed inside the opening formed in the insulator 280, the distance L2 between the conductor 242a1 and the conductor 242b1 is shorter than the distance L1 between the conductor 242a2 and the conductor 242b2.

[0290] The lithography method can be any of the above-described methods, as appropriate. In order to finely process the openings in the insulator 255, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0291] 11A and 11C , the insulator 255 has an opening formed therein so as to expose the island-shaped oxide 230, but the present invention is not limited to this. In this process, it is sufficient that the conductors 242a1 and 242b1 are separated by a distance L2. Therefore, for example, an opening substantially identical to the opening formed in the insulator 280 may be formed in the insulator 255, except for the portions contacting the upper surfaces of the conductors 242a1 and 242b1. However, in this case, the insulator 255 may be formed in a sidewall shape in contact with the sidewall of the opening formed in the insulator 280.

[0292] Below, specific examples of processing the conductor 242_1 and the insulating film 255A will be described with reference to FIGS. 12A to 12D.

[0293] First, a coating film 287f is formed on the insulating film 255A, and then a coating film 288f is formed ( FIG. 12A ). Here, the coating film 287f is provided so as to fill the recesses in the insulating film 255A. Note that the coating film 287f can have the same configuration as the coating film 277f, and the coating film 288f can have the same configuration as the coating film 278f, so the above descriptions can be referenced.

[0294] Next, a resist mask 289 is formed on the coating film 288f by lithography (FIG. 12A). An opening with a width L2 is formed in the resist mask 289 when viewed cross-sectionally in the channel length direction. The resist mask 289 is formed so that the opening with width L2 is located inside the opening of the insulator 280 when viewed from above and overlaps with the oxide 230b. Note that the resist mask 289 can have the same structure as the resist mask 279, and therefore the above description can be referred to.

[0295] 12B to 12D, the structure shown in FIG. 12A is etched using a dry etching method. Dry etching is capable of anisotropic etching, making it suitable for forming an opening with a width L2 and a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found above. The etching of the conductor 242_2 and the etching of the insulating film 255A may be performed under different conditions.

[0296] First, using a resist mask 289, the coating film 288f is processed to form the coating film 288, and then the coating film 287f is processed to form the coating film 287 ( FIG. 12B ). Here, openings with a width L2 are formed in the coating films 288 and 287, exposing the insulating film 255A. Note that the processing of the coating films 288f and 287f is similar to the processing of the coating films 278f and 277f, and therefore the above description can be referred to.

[0297] Next, the coating film 287 is used as a mask to process the insulating film 255A to form an opening, and the insulator 255 is formed. Here, the width of the opening in the insulator 255 is L2. For example, when silicon nitride is used for the insulating film 255A, the insulating film 255A is formed by etching with CHF ３ and O ２ The etching process can be carried out using the above as an etching gas.

[0298] Next, the conductor 242_1 is processed and divided using the coating film 287 and the insulator 255 as a mask to form the conductor 242a1 and the conductor 242b1 (FIG. 12D). For example, when tantalum nitride is used for the conductor 242_1, Cl ２ The etching process can be performed using Ar as an etching gas.

[0299] Here, the region between the conductor 242a1 and the conductor 242b1 overlaps with the opening of width L2, and the distance between the conductor 242a1 and the conductor 242b1 is L2. By processing the insulating film 255A and the conductor 242_1 using the same mask in this manner, the side edges of the insulator 255A are formed to roughly coincide with the side edges of the conductor 242a1 and the conductor 242b1 in a cross-sectional view of the transistor 200.

[0300] The coating film 287 may be removed by performing a dry etching process such as ashing using oxygen plasma, a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0301] Furthermore, the processing of the insulating film 255A and the conductor 242_1 and the removal of the coating film 287 can be performed successively without exposure to the outside air. For example, the processing can be performed using a multi-chamber etching apparatus without exposure to the outside air.

[0302] In this manner, the conductors 242a1 and 242b1, which are spaced apart by a distance L2, can be formed below the conductors 242a2 and 242b2, which are spaced apart by a distance L1. This configuration shortens the distance between the source and drain of the transistor 200, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0303] The etching process may result in impurities adhering to the side surfaces of the oxide 230a, the top and side surfaces of the oxide 230b, and the side surfaces of the conductors 242a and 242b, or diffusing into these surfaces. A process for removing such impurities may be performed. Furthermore, the dry etching may result in damaged regions being formed on the surface of the oxide 230b. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulators 280, 275, 271a and 271b, and the conductors 242a and 242b, components contained in the components of the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0304] In particular, impurities such as aluminum and silicon may reduce the crystallinity of the oxide 230b. Therefore, it is preferable to remove impurities such as aluminum and silicon from the surface of the oxide 230b and its vicinity. It is also preferable to reduce the concentration of these impurities. For example, the concentration of aluminum atoms on the surface of the oxide 230b and its vicinity is preferably 5.0 atomic % or less, more preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0305] In addition, in the region where the crystallinity of the oxide 230b is low due to impurities such as aluminum and silicon, the density of the crystal structure is reduced. Ｏ A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the region of low crystallinity in the oxide 230b be reduced or removed.

[0306] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom end of the drain. Here, in the transistor, it is preferable that the conductor 242a or the conductor 242b functions as the drain. In other words, it is preferable that the oxide 230b near the bottom end of the conductor 242a or the conductor 242b has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the low-crystalline region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor can be further suppressed. Furthermore, the reliability of the transistor can be improved.

[0307] A cleaning process is performed to remove impurities and the like that have adhered to the surface of the oxide 230b during the etching process. Cleaning methods include wet cleaning using a cleaning solution (also called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0308] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0309] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0310] In addition, ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably uses a frequency of 900 kHz or more, since use of such a frequency can reduce damage to the oxide 230b and the like.

[0311] The cleaning process may be repeated multiple times, and different cleaning solutions may be used for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0312] In this embodiment, the cleaning process is performed by wet cleaning using diluted ammonia water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0313] It is preferable to perform heat treatment after the etching or cleaning. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen, for example, at a temperature of 350°C for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. Furthermore, performing such heat treatment can improve the crystallinity of the oxide 230b. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide 230a and the oxide 230b, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide 230a and the oxide 230b is recombined with the oxygen vacancies to form V. ＯThe formation of H can be suppressed. This can improve the electrical characteristics of the transistor provided with the oxide 230 and improve reliability. Furthermore, it can suppress variations in the electrical characteristics of multiple transistors formed on the same substrate. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0314] When heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide 230b, the sheet resistance may decrease in the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b. The carrier concentration may also increase. Therefore, the resistance of the region of the oxide 230b that overlaps with the conductor 242a and the region of the oxide 230b that overlaps with the conductor 242b can be reduced in a self-aligned manner.

[0315] As described above, the insulator 255, which has an inorganic insulator that is resistant to oxidation, is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if the conductors 242a2 and 242b2 are made of a tungsten film that is relatively easily oxidized.

[0316] Next, an insulating film 250A that will become the insulator 250 is deposited so as to fill the opening formed in the insulator 280 (see FIGS. 13A to 13D). Here, the insulating film 250A is deposited so as to be in contact with the insulator 255, but in the region where the opening is formed in the insulator 255, the insulating film 250A is in contact with the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b.

[0317] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably formed using an ALD method. Like the insulator 250 described above, the insulating film 250A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulating film 250A to be formed with good coverage on the opening.

[0318] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) as an oxidizing agent, hydrogen diffusing into the oxide 230b can be reduced.

[0319] The insulator 250 can have a stacked structure, as shown in FIG. 2A , etc. In the structure shown in FIG. 2A , an insulating film that becomes the insulator 250 a can be formed by depositing aluminum oxide by thermal ALD, an insulating film that becomes the insulator 250 b can be formed by depositing silicon oxide by PEALD, and an insulating film that becomes the insulator 250 c can be formed by depositing silicon nitride by PEALD. In the structure shown in FIG. 2B , an insulating film that becomes the insulator 250 a can be formed by depositing aluminum oxide by thermal ALD, and an insulating film that becomes the insulator 250 c can be formed by depositing silicon nitride by PEALD. In addition, in the structure shown in Figure 2C, aluminum oxide can be deposited by thermal ALD as the insulating film that becomes insulator 250a, silicon oxide can be deposited by PEALD as the insulating film that becomes insulator 250b, hafnium oxide can be deposited by thermal ALD as the insulating film that becomes insulator 250d, and silicon nitride can be deposited by PEALD as the insulating film that becomes insulator 250c.

[0320] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device with a power source that generates high-density plasma using microwaves. Furthermore, in this specification and elsewhere, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. However, when the insulator 250 has a stacked structure, the microwave treatment does not necessarily need to be performed after the formation of all of the insulating films 250A. For example, in the structure shown in FIG. 2A , microwave treatment may be performed after the formation of the insulating film that will become insulator 250a and the insulating film that will become insulator 250b, and then the insulating film that will become insulator 250c may be formed. Furthermore, in the structure shown in FIG. 2B , microwave treatment may be performed after the formation of the insulating film that will become insulator 250a, and then the insulating film that will become insulator 250c may be formed. 2C , for example, a microwave treatment may be performed after forming an insulating film to be insulator 250 a and an insulating film to be insulator 250 b, and then a microwave treatment may be performed after forming an insulating film to be insulator 250 d, and then an insulating film to be insulator 250 c may be formed. In this way, the microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least two times or more).

[0321] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave treatment device is preferably 1000 W or more and 10,000 W or less, and preferably 2000 W or more and 5,000 W or less. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide 230b.

[0322] The microwave treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0323] Furthermore, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. In this way, by performing microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide 230b can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration in the oxide 230b can be prevented.

[0324] By performing microwave processing in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region of the oxide 230b between the conductors 242a and 242b. ＯThe H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when the structure shown in FIGS. 2A to 2C is used, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing and fixing hydrogen as the insulating film that becomes the insulator 250a. With such a structure, hydrogen generated by microwave treatment can be captured or fixed to the insulator 250a. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0325] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0326] On the other hand, the oxide 230b has a region that overlaps with either the conductors 242a or 242b. This region can function as a source region or a drain region. Here, the conductors 242a and 242b preferably function as a shielding film against the effects of microwaves, high-frequency waves such as RF, oxygen plasma, and the like when performing microwave treatment in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have the function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0327] Conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc., so that these effects do not reach the regions of oxide 230b that overlap with either of conductors 242a and 242b. This allows microwave processing to prevent V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0328] Furthermore, insulators 255 and 250, which have a barrier property against oxygen, are provided in contact with the side surfaces of the conductors 242a and 242b, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductors 242a and 242b by microwave treatment.

[0329] In this manner, oxygen vacancies and V Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low resistance region state) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0330] In microwave treatment, thermal energy may be transferred directly to the oxide 230b due to electromagnetic interaction between the microwaves and molecules in the oxide 230b. This thermal energy may heat the oxide 230b. This type of heat treatment is sometimes called microwave annealing. Performing microwave treatment in an oxygen-containing atmosphere may produce an effect equivalent to oxygen annealing. Furthermore, if the oxide 230b contains hydrogen, it is thought that this thermal energy is transferred to the hydrogen in the oxide 230b, thereby activating and releasing the hydrogen from the oxide 230b.

[0331] It is to be noted that the microwave treatment may be performed before the insulating film 250A is formed, rather than after the insulating film 250A is formed.

[0332] Furthermore, after the microwave treatment following the formation of the insulating film 250A, a heat treatment may be performed while maintaining the reduced pressure. By performing such a treatment, hydrogen in the insulating film, the oxide 230b, and the oxide 230a can be efficiently removed. Some of the hydrogen may be gettered to the conductors 242a and 242b. Alternatively, a heat treatment step may be performed multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The microwave treatment, i.e., microwave annealing, may also serve as the heat treatment. If the oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0333] Furthermore, by modifying the film quality of the insulating film 250A by microwave treatment, the diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 can be suppressed by post-processing such as film formation of a conductive film that becomes the conductor 260, or by post-treatment such as heat treatment. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0334] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are formed in this order (see FIGS. 14A to 14D ). The conductive films 260A and 260B can be formed by, for example, sputtering, CVD, MBE, PLD, plating, or ALD. In this embodiment, titanium nitride is formed as the conductive film 260A by ALD, and tungsten is formed as the conductive film 260B by CVD.

[0335] Next, the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the openings are removed. As a result, the insulator 255, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the openings overlapping the conductor 205 (see FIGS. 15A to 15D).

[0336] As a result, the insulator 255 is provided in contact with the sidewall and part of the bottom surface of the opening formed in the insulator 280. The insulator 250 is also provided in the opening in contact with the insulator 255 and the oxide 230, the insulator 224, and the insulator 222 exposed from the insulator 255. The conductor 260 is also arranged to fill the opening with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0337] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 1A to 1D). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0338] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by using a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate.

[0339] In this embodiment, aluminum oxide is deposited as the insulator 282 by sputtering using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate during sputtering. For example, the smaller the RF power, the less oxygen is implanted into the layer below the insulator 282, and the amount of oxygen is likely to saturate even if the insulator 282 is thin. Furthermore, the larger the RF power, the more oxygen is implanted into the layer below the insulator 282. Reducing the RF power can suppress the amount of oxygen implanted into the insulator 282. Alternatively, the insulator 282 may be deposited to have a two-layer stacked structure. In this case, for example, the lower layer of the insulator 282 is deposited without applying RF power to the substrate, and the upper layer of the insulator 282 is deposited by applying RF power to the substrate.

[0340] The RF frequency is preferably 10 MHz or higher, typically 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0341] Alternatively, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0342] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 1A to 1D). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0343] Here, it is preferable to successively deposit the insulators 282 and 283 without exposing them to the air environment. Depositing the insulators 282 and 283 without exposing them to the air environment can prevent impurities or moisture from the air environment from adhering to the insulators 282 and 283, and can keep the vicinity of the interface between the insulators 282 and 283 clean.

[0344] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0345] The semiconductor device according to this embodiment has a two-layer structure of conductors on an oxide semiconductor, with a conductor that is resistant to oxidation used in the lower layer and a conductor with high conductivity used in the upper layer. This structure provides conductors that function as electrodes or wirings in contact with the top surface of the oxide semiconductor. The conductors function as source and drain electrodes of an OS transistor. The semiconductor device according to this embodiment has a shorter distance between the conductors in the lower layers of the source and drain electrodes than between the conductors in the upper layers of the source and drain electrodes, thereby achieving miniaturization. This allows the frequency characteristics and operating speed of the semiconductor device to be improved. Furthermore, the semiconductor device according to this embodiment provides an insulator that functions as a protective film in contact with the side surfaces of the conductors in the upper layers of the source and drain electrodes. This structure prevents excessive oxidation of the upper layers of the source and drain electrodes.

[0346] The semiconductor device according to this embodiment includes an OS transistor. The OS transistor has a small off-state current, which enables a semiconductor device or storage device with low power consumption. Furthermore, the OS transistor has high frequency characteristics, which enables a semiconductor device or storage device with high operation speed. Furthermore, by using an OS transistor, a semiconductor device with favorable electrical characteristics, a semiconductor device with little variation in the electrical characteristics of transistors, a semiconductor device with large on-state current, and a highly reliable semiconductor device or storage device can be realized.

[0347] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0348] Embodiment 2 In this embodiment, a comparison between the OS transistor described in the above embodiment and a transistor having silicon in a channel formation region (also referred to as a Si transistor) will be described.

[0349] [OS Transistor] An OS transistor is preferably formed using an oxide semiconductor with a low carrier concentration. For example, the carrier concentration of a channel formation region of an oxide semiconductor is preferably 1×10 １８ cm −３ Below 1 × 10, preferably １７ cm −３ less than 1×10 １６ cm −３ less than 1×10 １３ cm −３ less than 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0350] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Charges trapped in trap states of the oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0351] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0352] Furthermore, when impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and reliability may be reduced. Ｏ H) and generate electrons that become carriers. Ｏ When H is formed, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may vary. Therefore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H is reduced as much as possible.

[0353] The band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more. By using an oxide semiconductor having a band gap larger than that of silicon, the off-state current (also referred to as Ioff) of the transistor can be reduced.

[0354] Furthermore, as the size of Si transistors is reduced, a short channel effect (also referred to as SCE) occurs. This makes it difficult to reduce the size of Si transistors. One of the reasons for the short channel effect is the small band gap of silicon. On the other hand, an OS transistor uses an oxide semiconductor, which is a semiconductor material with a wide band gap, and therefore the short channel effect can be suppressed. In other words, an OS transistor is a transistor that does not have the short channel effect or has an extremely small short channel effect.

[0355] The short-channel effect is a degradation of electrical characteristics that becomes apparent as transistors are miniaturized (channel lengths are reduced). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in subthreshold swing (sometimes referred to as S value), and an increase in leakage current. Here, the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.

[0356] Furthermore, the characteristic length is widely used as an index of resistance to the short channel effect. The characteristic length is an index of how easily the potential in the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to the short channel effect.

[0357] An OS transistor is an accumulation-mode transistor, while a Si transistor is an inversion-mode transistor. Therefore, compared with a Si transistor, an OS transistor has a smaller characteristic length between a source region and a channel formation region and a smaller characteristic length between a drain region and a channel formation region. Therefore, an OS transistor is more resistant to the short-channel effect than a Si transistor. That is, when a transistor with a short channel length is to be manufactured, an OS transistor is more suitable than a Si transistor.

[0358] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region becomes i-type or substantially i-type, the conduction band minimum of the channel formation region in a short-channel transistor is lowered due to the conduction-band-lowering (CBL) effect, and therefore the energy difference between the conduction band minimums of the source or drain region and the channel formation region can be reduced to 0.1 eV or more and 0.2 eV or less. − The source and drain regions are n-type regions. ＋ The region of type n ＋ / n − / n ＋ an accumulation-type junction-less transistor structure, or ＋ / n − / n ＋ This can also be regarded as an accumulation type non-junction transistor structure.

[0359] By using an OS transistor with the above structure, good electrical characteristics can be obtained even when a semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of an OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more. On the other hand, a Si transistor may have difficulty achieving a gate length of 20 nm or less or 15 nm or less due to the short-channel effect. Therefore, an OS transistor can be suitably used as a transistor having a shorter channel length than a Si transistor. Note that the gate length refers to the length of a gate electrode in the direction in which carriers move inside a channel formation region during transistor operation, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.

[0360] Furthermore, miniaturization of an OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the cutoff frequency of the transistor can be improved. When the gate length of an OS transistor is within the above range, the cutoff frequency of the transistor can be set to, for example, 50 GHz or higher, preferably 100 GHz or higher, and further preferably 150 GHz or higher at room temperature.

[0361] As described above, compared to Si transistors, OS transistors have excellent advantages such as a smaller off-state current and the ability to be manufactured as transistors with a short channel length.

[0362] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0363] Embodiment 3 In this embodiment, a memory device including a transistor of one embodiment of the present invention will be described with reference to FIGS.

[0364] This embodiment will describe a configuration example of a memory device using a memory cell including the transistor described in the above embodiment, in which a layer including a functional circuit having a function of amplifying and outputting a data potential held in the memory cell is provided between layers including stacked memory cells.

[0365] [Configuration Example of Storage Device] FIG. 16 illustrates a block diagram of a storage device of one embodiment of the present invention.

[0366] 16 includes a drive circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 including a plurality of functional circuits 51.

[0367] 16 shows an example in which the memory array 20 has a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). Also, Fig. 16 shows an example in which a functional circuit 51 is provided for each wiring BL that functions as a bit line, and an example in which the functional layer 50 has a plurality of functional circuits 51 provided corresponding to the n wirings BL.

[0368] In FIG. 16 , the memory cell 10 in the first row and first column is indicated as memory cell 10[1,1], and the memory cell 10 in the mth row and nth column is indicated as memory cell 10[m,n]. In addition, in the present embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in the present embodiment and the like, the memory cell 10 in the ith row and jth column is indicated as memory cell 10[i,j]. In addition, in the present embodiment and the like, when "i+α" (α is a positive or negative integer) is indicated, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is indicated, "j+α" is not less than 1 or more than n.

[0369] The memory array 20 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n].

[0370] The memory cells 10 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 10 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0371] The memory array 20 may be a DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, with the access transistor being an OS transistor. The current flowing between the source and drain of an OS transistor in the off state, i.e., leakage current, is extremely small. By turning off (non-conducting) the access transistor, DOSRAM can retain charge corresponding to data stored in a capacitance element (capacitor) for a long period of time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAMs composed of transistors having silicon in their channel formation regions (Si transistors). As a result, power consumption can be reduced. Furthermore, the high frequency characteristics of OS transistors enable high-speed read and write operations. This allows for a memory device with high operating speed.

[0372] 16, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10.

[0373] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conduction state or non-conduction state) of an access transistor functioning as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring CL (not shown) can be separately provided as a wiring that has a function of transmitting a back-gate potential to the back-gate of an OS transistor that is an access transistor. The wiring PL may also have a function of transmitting the back-gate potential.

[0374] The memory cells 10 included in each of the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 via wiring BL. The wiring BL can be arranged in a direction perpendicular to the substrate surface on which the driver circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. This shortens the signal propagation distance between two circuits connected to the bit line, significantly reducing the resistance and parasitic capacitance of the bit line, thereby realizing reduced power consumption and signal delay. Furthermore, the memory cells 10 can be operated even if the capacitance of the capacitive element included in the memory cell 10 is reduced.

[0375] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 of the driver circuit 21 via a wiring GBL (not shown), which will be described later. This configuration allows a slight potential difference in the wiring BL to be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the driver circuit 21 is provided, similar to the wiring BL. By arranging the wirings BL and GBL extending from the memory cells 10 of the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, the signal propagation distance between two circuits connected to the wiring GBL can be shortened, and the resistance and parasitic capacitance of the wiring GBL are significantly reduced, thereby realizing reduced power consumption and signal delay.

[0376] The wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in contact with a conductor provided in contact with a region functioning as the source or drain of the semiconductor layer of the transistor included in the memory cell 10. In other words, the wiring BL can be said to be a wiring for electrically connecting one of the source or the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0377] The memory array 20 can be provided overlapping the drive circuit 21. By providing the drive circuit 21 and the memory array 20 overlapping, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20, thereby realizing reductions in power consumption and signal delay. In addition, the storage device 300 can be made smaller.

[0378] The functional circuit 51 is configured with OS transistors similar to the transistors included in the DOSRAM memory cells 10, and can be freely arranged on a circuit using Si transistors similar to the memory arrays 20[1] to 20[m], thereby facilitating integration. The signal amplification configuration in the functional circuit 51 allows for the miniaturization of subsequent circuits such as the sense amplifier 46, thereby enabling the miniaturization of the memory device 300.

[0379] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0380] In the storage device 300, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0381] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 32.

[0382] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.

[0383] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0384] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cells 10. The peripheral circuit 41 is also a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0385] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, the function of reading data from the memory cell 10, the function of holding the read data, etc.

[0386] The input circuit 47 has a function of holding a signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is data (Din) to be written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. The output circuit 48 also has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is a signal RDA.

[0387] The PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has a function of controlling the supply of VHM to the row driver 43. In this example, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW22 is controlled by the signal PON1, and the on / off of the PSW23 is controlled by the signal PON2. In FIG. 16, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0388] The memory array 20 having memory arrays 20[1] to 20[m] (m is an integer of 2 or more) and a functional layer 50 can be provided by stacking multiple layers of memory arrays 20 on a drive circuit 21. By stacking multiple layers of memory arrays 20, the memory density of the memory cells 10 can be increased. Figure 17A shows a perspective view of a storage device 300 having a functional layer 50 and five layers (m = 5) of memory arrays 20[1] to 20[5] stacked on a drive circuit 21.

[0389] 17A, the memory array 20 provided in the first layer is shown as memory array 20[1], the memory array 20 provided in the second layer is shown as memory array 20[2], and the memory array 20 provided in the fifth layer is shown as memory array 20[5]. Also shown in FIG. 17A are wiring WL, wiring PL, and wiring CL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that, to make the drawing easier to understand, the wiring WL and wiring PL of each memory array 20 are partially omitted.

[0390] 17B is a schematic diagram illustrating a configuration example of a functional circuit 51 connected to the wiring BL illustrated in FIG. 17A and memory cells 10 included in memory arrays 20[1] to 20[5] connected to the wiring BL. Also, FIG. 17B illustrates a wiring GBL provided between the functional circuit 51 and the driver circuit 21. Note that a configuration in which multiple memory cells (memory cells 10) are electrically connected to one wiring BL is also referred to as a "memory string." Note that in the drawings, the wiring GBL may be illustrated with a thick line to improve visibility.

[0391] 17B illustrates an example of a circuit configuration of a memory cell 10 connected to a wiring BL. The memory cell 10 includes a transistor 11 and a capacitor 12. The transistor 11, the capacitor 12, and the wirings (such as a wiring BL and a wiring WL) may also be referred to as wirings BL[1] and WL[1], for example. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1.

[0392] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to a wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of a capacitor 12. The other electrode of the capacitor 12 is connected to a wiring PL. The gate of the transistor 11 is connected to a wiring WL. The back gate of the transistor 11 is connected to a wiring CL.

[0393] The wiring PL is a wiring that applies a constant potential to maintain the potential of the capacitor 12. The wiring CL is a constant potential to control the threshold voltage of the transistor 11. The wiring PL and the wiring CL may have the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 10 can be reduced.

[0394] The wiring GBL shown in Fig. 17B is provided to electrically connect the driver circuit 21 and the functional layer 50. Fig. 18A is a schematic diagram of a memory device 300 in which a functional circuit 51 and memory arrays 20[1] to 20[m] are repeated as a repeating unit 70. Note that although Fig. 18A shows one wiring GBL, the wiring GBL may be provided as needed depending on the number of functional circuits 51 provided in the functional layer 50.

[0395] The wiring GBL is provided in contact with a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as a source or a drain of a semiconductor layer of a transistor included in the functional circuit 51. In other words, the wiring GBL can be said to be a wiring for electrically connecting one of the source or the drain of a transistor included in the functional circuit 51 in the functional layer 50 to the driver circuit 21 in the vertical direction.

[0396] The repeating unit 70 including the functional circuit 51 and the memory arrays 20[1] to 20[m] may be further stacked. The memory device 300A of one embodiment of the present invention can have repeating units 70[1] to 70[p] (p is an integer of 2 or more) as illustrated in FIG. 18B . The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be provided as appropriate depending on the number of functional circuits 51.

[0397] In one embodiment of the present invention, OS transistors are stacked, and wirings functioning as bit lines are arranged in a direction perpendicular to the surface of a substrate on which the driver circuit 21 is provided. By providing the wirings functioning as bit lines extending from the memory array 20 in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit lines can be significantly reduced.

[0398] In one embodiment of the present invention, a layer in which the memory array 20 is provided includes a functional layer 50 having a functional circuit 51 that has a function of amplifying and outputting a data potential held in the memory cell 10. With this configuration, a slight potential difference of the wiring BL that functions as a bit line can be amplified when reading data, and the sense amplifier 46 included in the driver circuit 21 can be driven. Since circuits such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. Furthermore, the memory device 300 can operate even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced.

[0399] Although the above description illustrates an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) configuration, the present invention is not limited to this. For example, as shown in FIG. 22A, a 3T1C memory cell may be used in a storage device. The memory cell shown in FIG. 22A includes transistors 11a, 11b, and 11c and a capacitor 12a. Here, the transistors 11a, 11b, and 11c may have the same configuration as the transistor 11, and the capacitor 12a may have the same configuration as the capacitor 12. A RAM with such a configuration may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0400] 22A , one of the source and drain of transistor 11a is electrically connected to one electrode of capacitor 12a and the first gate of transistor 11b. One of the source and drain of transistor 11b is electrically connected to one of the source and drain of transistor 11c. Wiring may be provided as appropriate in the first gate, the other of the source and drain, and the second gate of transistor 11a, the other of the source and drain and the second gate of transistor 11b, the first gate, the other of the source and drain, and the second gate of transistor 11c, and the other electrode of capacitor 12a. The structure of the memory device can also be modified as appropriate in accordance with these wirings.

[0401] Also, as shown in FIG. 22B, a 2T1C type memory cell may be formed without providing the transistor 11c, and having only the transistors 11a and 11b and the capacitance element 12a.

[0402] 22C, if the parasitic capacitance of the transistors 11a and 11b is sufficiently large, the capacitance element 12a may not be provided, in which case the memory cell is formed only by the transistors 11a and 11b.

[0403] 19 will be used to describe a configuration example of the functional circuit 51 described with reference to FIGS. 16 to 18 and a configuration example of the sense amplifier 46 included in the memory array 20 and the driver circuit 21. FIG. 19 illustrates a driver circuit 21 connected to wirings GBL (wirings GBL_A and GBL_B) that are connected to functional circuits 51 (functional circuits 51_A and 51_B) that are connected to memory cells 10 (memory cells 10_A and 10_B) that are connected to different wirings BL (wirings BL_A and BL_B). As the driver circuit 21 illustrated in FIG. 19, in addition to the sense amplifier 46, precharge circuits 71_A, precharge circuits 71_B, switch circuits 72_A, switch circuits 72_B, and a write / read circuit 73 are illustrated.

[0404] 19 are OS transistors similar to the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked in the same manner as the memory arrays 20[1] to 20[m].

[0405] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the sources or drains of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the sources or drains of the transistors 53_b and 54_b. The wirings GBL_A and GBL_B are provided in the vertical direction like the wirings BL_A and BL_B, and are connected to the transistors included in the driver circuit 21. As shown in FIG. 19 , the selection signal MUX, the control signal WE, and the control signal RE are applied to the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b, respectively.

[0406] 19, transistors 81_1 to 81_6 and 82_1 to 82_4 constituting the sense amplifier 46, precharge circuit 71_A, and precharge circuit 71_B are configured with Si transistors. Switches 83_A to 83_D constituting the switch circuits 72_A and 72_B can also be configured with Si transistors. One of the sources or drains of transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistors or switches constituting the precharge circuits 71_A, 71_B, sense amplifier 46, and switch circuit 72_A.

[0407] The precharge circuit 71_A includes n-channel transistors 81_1 to 81_3. The precharge circuit 71_A is a circuit for precharging the wirings BL_A and BL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal applied to a precharge line PCL1.

[0408] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6. The precharge circuit 71_B is a circuit for precharging the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in response to a precharge signal applied to a precharge line PCL2.

[0409] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to a wiring VHH or a wiring VLL. The wiring VHH or the wiring VLL has a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors that form an inverter loop. The potentials of the precharged wirings BL_A and BL_B change when the memory cells 10_A and 10_B are selected, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change. The potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 83_C and 83_D and the write / read circuit 73. The wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs. The write / read circuit 73 controls the writing of data signals in response to the signal EN_data.

[0410] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wirings GBL_A and GBL_B. The switch circuit 72_A is switched on or off under the control of a switching signal CSEL1. When the switches 83_A and 83_B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write / read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B is switched on or off under the control of a switching signal CSEL2. The switches 83_C and 83_D may be configured in the same manner as the switches 83_A and 83_B.

[0411] 19 , the memory device 300 can be configured such that the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected via wirings BL and GBL that are provided in the vertical direction, which is the shortest distance. Although the number of functional layers 50 having transistors that configure the functional circuit 51 increases, the load on the wirings BL is reduced, thereby shortening the write time and making it easier to read data.

[0412] 19 , each transistor included in the functional circuits 51_A and 51_B is controlled in response to control signals WE and RE and a selection signal MUX. Each transistor can output the potential of the wiring BL to the driver circuit 21 via the wiring GBL in response to the control signal and the selection signal. The functional circuits 51_A and 51_B can function as sense amplifiers including OS transistors. This configuration allows a slight potential difference in the wiring BL to be amplified during read operation, thereby driving the sense amplifier 46 using Si transistors.

[0413] <Configuration Example of Memory Cell> A configuration example of the memory cell 10 used in the memory device will be described with reference to FIG.

[0414] In FIG. 20, the X direction is parallel to the channel width direction of the illustrated transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0415] As shown in FIG. 20 , the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided over the transistor 11, and an insulator 284 is provided over the insulator 285. The insulators 285 and 284 may be the same as those that can be used for the insulator 216. The transistor 11 has a structure similar to that of the transistor 200 described in the above embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200, the above embodiment can be referred to. A conductor 240 is provided in contact with one of the source and drain (conductor 242 a) of the transistor 11. The conductor 240 extends in the Z direction and functions as a wiring BL.

[0416] The capacitor 12 includes a conductor 153 on the conductor 242b, an insulator 154 on the conductor 153, and a conductor 160 (conductor 160a and conductor 160b) on the insulator 154.

[0417] At least a portion of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the openings formed in the insulators 271b, 275, 280, 282, 283, and 285. The ends of the conductors 153, 154, and 160 are located at least on the insulator 282, and preferably on the insulator 285. The insulator 154 is disposed so as to cover the end of the conductor 153. This allows the conductors 153 and 160 to be electrically insulated from each other.

[0418] The deeper the openings provided in the insulators 271b, 275, 280, 282, 283, and 285 are (that is, the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12. Increasing the capacitance per unit area of ​​the capacitor 12 allows for miniaturization or high integration of the semiconductor device.

[0419] The conductor 153 has a region that functions as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region that functions as a dielectric of the capacitor 12. The conductor 160 has a region that functions as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 constitutes a metal-insulator-metal (MIM) capacitor.

[0420] In addition, the conductor 242 b provided so as to overlap the oxide 230 functions as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0421] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using any of the conductors that can be used for the conductor 205 or the conductor 260. The conductor 153 and the conductor 160 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductor 153 can be formed using titanium nitride or tantalum nitride formed by an ALD method or a CVD method.

[0422] The upper surface of the conductor 242b2 is in contact with the lower surface of the conductor 153. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0423] Alternatively, the conductor 160a may be made of titanium nitride formed by ALD or CVD, and the conductor 160b may be made of tungsten formed by CVD. Note that if the adhesion of tungsten to the insulator 154 is sufficiently high, the conductor 160 may have a single-layer structure of tungsten formed by CVD.

[0424] A high-dielectric (high-k) material (a material with a high relative dielectric constant) is preferably used for the insulator 154 of the capacitor 12. The insulator 154 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0425] Examples of high-dielectric-constant (high-k) insulators include oxides, oxynitrides, oxynitrides, and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium. Silicon may also be contained in the oxides, oxynitrides, oxynitrides, or nitrides. Insulators made of the above materials may also be stacked.

[0426] For example, examples of insulators made of high dielectric constant (high-k) materials include aluminum oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, oxides containing silicon and zirconium, oxynitrides containing silicon and zirconium, oxides containing hafnium and zirconium, and oxynitrides containing hafnium and zirconium. By using such high-k materials, the insulator 154 can be made thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor 12.

[0427] Furthermore, it is preferable to use a laminated structure of insulators made of the above materials, and it is preferable to use a laminated structure of a high-dielectric constant (high-k) material and a material having a higher dielectric strength than the high-dielectric constant (high-k) material. For example, an insulator formed by laminating zirconium oxide, aluminum oxide, and zirconium oxide in this order can be used as the insulator 154. Alternatively, an insulator formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order can be used. Alternatively, an insulating film formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order can be used. By using a laminated structure of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 12 can be suppressed.

[0428] The deeper the openings in the insulators 271b, 275, 280, 282, 283, and 285 are (i.e., the thicker one or more of the insulators 271b, 275, 280, 282, 283, and 285 are), the larger the capacitance of the capacitor 12 can be. Here, the insulators 271b, 275, 282, and 283 function as barrier insulators, so their thicknesses are preferably set according to the barrier properties required for the semiconductor device. Furthermore, the thickness of the insulator 280 determines the thickness of the conductor 260 that functions as a gate electrode, so the thickness of the insulator 280 is preferably set according to the thickness of the conductor 260 required for the semiconductor device.

[0429] Therefore, it is preferable to set the capacitance of the capacitor 12 by adjusting the film thickness of the insulator 285. For example, the film thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm. Forming the capacitor 12 in such a range allows the capacitor 12 to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that a configuration may be adopted in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In such a configuration, for example, the film thickness of the insulator 285 provided in each memory cell layer may be different.

[0430] In the opening provided in the insulator 285 or the like in which the capacitor element 12 is disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, the coverage of the conductor 153 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.

[0431] Furthermore, the conductor 242a provided so as to overlap the oxide 230 functions as wiring that is electrically connected to the conductor 240. For example, in Fig. 20, the upper surface and side end of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. In particular, in Fig. 20, the upper surface and side end of the conductor 242a2 and the side end of the conductor 242a1 are in contact with the conductor 240.

[0432] By directly contacting the conductor 240 with at least one of the upper surface and side end of the conductor 242a, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, thereby increasing the memory capacity of the memory device. It is preferable that the conductor 240 contacts a portion of the upper surface and side end of the conductor 242a. By contacting multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced. In particular, as shown in FIG. 20 , by contacting a portion of the upper surface and side end of the highly conductive conductor 242a2, the contact resistance between the conductor 240 and the conductor 242a can be further reduced.

[0433] Conductor 240 is disposed within openings formed in insulators 216 , 222 , 275 , 280 , 282 , 283 , 285 and 284 .

[0434] The conductor 240 preferably has a layered structure of a conductor 240a and a conductor 240b. For example, as shown in FIG. 20 , the conductor 240 can have a structure in which the conductor 240a is provided in contact with the inner wall of the opening, and the conductor 240b is provided further inside. That is, the conductor 240a is arranged closer to the insulators 216, 222, 275, 280, 282, 283, 285, and 284 than the conductor 240b. The conductor 240a also contacts the upper surface and side end of the conductor 242a.

[0435] The conductor 240a is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. The conductor 240a can have a single-layer structure or a multi-layer structure using one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide, for example. This can suppress impurities such as water and hydrogen from entering the oxide 230 through the conductor 240.

[0436] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 240b can be made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0437] For example, it is preferable to use titanium nitride as the conductor 240a and tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0438] The conductor 240 may have a single layer structure or a laminated structure of three or more layers.

[0439] 20 , it is preferable that an insulator 241 be provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 216, 222, 275, 280, 282, 283, 285, and 284. The insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a, which are formed to protrude into the openings. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the interior of the opening via the insulator 241.

[0440] 20, the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the upper surface of the conductor 242a. This configuration allows the conductor 240 to contact at least a portion of the side end of the conductor 242a. The insulator 241 formed below the conductor 242a preferably has an area that contacts the side surface of the oxide 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductor 240.

[0441] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. This structure can prevent impurities such as water and hydrogen contained in the insulator 280, etc. from mixing into the oxide 230 through the conductor 240. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240.

[0442] 20 shows a structure in which the insulator 241 is a single layer, the present invention is not limited to this. The insulator 241 may have a stacked structure of two or more layers.

[0443] When the insulator 241 has a two-layer stacked structure, a first layer in contact with the inner wall of the opening of the insulator 280 or the like may be a barrier insulating film against oxygen, and a second layer inside the first layer may be a barrier insulating film against hydrogen. For example, the first layer may be made of aluminum oxide deposited by the ALD method, and the second layer may be made of silicon nitride deposited by the PEALD method. This structure can suppress oxidation of the conductor 240 and further reduce the intrusion of hydrogen from the conductor 240 into the oxide 230 or the like. This can improve the electrical characteristics and reliability of the transistor 11.

[0444] In the opening where the conductor 240 and the insulator 241 are disposed, the sidewall of the opening may be approximately perpendicular to the top surface of the insulator 222 or may have a tapered shape. By making the sidewall tapered, coverage of the insulator 241 and the like provided in the opening is improved.

[0445] <Configuration Example of Storage Device 300> A configuration example of the storage device 300 will be described with reference to FIG.

[0446] The memory device 300 includes a driver circuit 21, which is a layer including a transistor 310 and the like; a functional layer 50, which is a layer including transistors 52, 53, 54, 55, and the like, on the driver circuit 21; and memory arrays 20[1] to 20[m] on the functional layer 50. Only the memory arrays 20[1] and 20[2] are illustrated in Fig. 21. Note that the transistor 52 corresponds to the transistors 52_a and 52_b, the transistor 53 corresponds to the transistors 53_a and 53_b, the transistor 54 corresponds to the transistors 54_a and 54_b, and the transistor 55 corresponds to the transistors 55_a and 55_b.

[0447] 21 illustrates a transistor 310 included in the driver circuit 21. The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single crystal silicon substrate.

[0448] Here, in the transistor 310 shown in FIG. 21 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0449] Note that the transistor 310 illustrated in FIG. 21 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or the driving method.

[0450] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0451] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0452] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0453] 21 also illustrates transistors 52, 53, and 55 included in the functional layer 50. The transistors 52, 53, and 55 have the same configuration as the transistor 11 included in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0454] An insulator 208 is provided over the transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided over the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided over the insulator 210, and an insulator 214 is provided over the insulator 212. Parts of a conductor 240 provided in the memory array 20[1] are buried in the openings formed in the insulators 212 and 214. Here, the insulators 208 and 210 can be made of an insulator that can be used for the insulator 216. The insulator 212 can be made of an insulator that can be used for the insulator 283. The insulator 214 can be made of an insulator that can be used for the insulator 282.

[0455] The bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 52. The top surface of the conductor 207 is in contact with the bottom surface of the conductor 209. The top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. With this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0456] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 of each memory cell 10 is electrically connected to the conductor 240 in the upper layer and the conductor 240 in the lower layer.

[0457] 21, adjacent memory cells 10 share a conductor 240. In addition, in the adjacent memory cells 10, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.

[0458] Here, the conductor 160 functioning as the upper electrode of the capacitor 12 in the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 261 functioning as the second gate electrode of the transistor 11 in the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer can be formed so as to be embedded in an opening formed in the same insulator 216. The conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer are formed by processing a single conductive film, resulting in the above-described configuration. In this case, the conductor 160 of the capacitor 12 in the lower layer has the same material as the conductor 261 of the transistor 11 in the upper layer.

[0459] As described above, by simultaneously forming the conductor 160 of the capacitor 12 in the lower layer and the conductor 261 of the transistor 11 in the upper layer, the manufacturing process of the memory device according to this embodiment can be reduced, and the productivity of the memory device can be improved.

[0460] In the memory array 20 described above, multiple memory arrays 20[1] to 20[m] can be stacked. The memory arrays 20[1] to 20[m] included in the memory array 20 can be arranged in the vertical direction of the substrate surface on which the drive circuit 21 is provided, thereby improving the memory density of the memory cells 10. Furthermore, the memory array 20 can be fabricated using the same manufacturing process repeatedly in the vertical direction. The storage device 300 can reduce the manufacturing cost of the memory array 20.

[0461] This embodiment mode can be combined with other embodiment modes as appropriate.

[0462] Embodiment 4 In this embodiment, an example of a chip on which a memory device of one embodiment of the present invention is mounted will be described with reference to FIGS.

[0463] 23A and 23B, multiple circuits (systems) are implemented on a chip 1200. The technology for integrating multiple circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0464] As shown in FIG. 23A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0465] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of package substrate 1201 as shown in Fig. 23B. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of package substrate 1201, which are connected to motherboard 1203.

[0466] The motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. This allows the DRAM 1221 to have low power consumption, high speed, and large capacity.

[0467] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the above embodiment, it becomes possible to perform image processing or multiply-and-accumulate operations with low power consumption.

[0468] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0469] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0470] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0471] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a Universal Serial Bus (USB) or a High-Definition Multimedia Interface (HDMI (registered trademark)) can be used.

[0472] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0473] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0474] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be called a GPU module 1204.

[0475] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a smaller size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, the product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0476] This embodiment mode can be combined with other embodiment modes as appropriate.

[0477] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0478] [Electronic Component] FIG. 24A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 24A has semiconductor device 710 inside mold 711. FIG. 24A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0479] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0480] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0481] Furthermore, it is preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0482] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0483] 24B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0484] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).

[0485] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0486] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0487] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0488] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0489] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0490] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0491] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 24B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0492] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0493] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 25A . The electronic device 6500 shown in FIG. 25A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0494] 25B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention in the control device 6509 and the control device 6616 is preferable because power consumption can be reduced.

[0495] 25C shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 25C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0496] The computer 5620 can have the configuration shown in the perspective view in Fig. 25D, for example. In Fig. 25D, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0497] PC card 5621 shown in Figure 25E is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 25E illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced.

[0498] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0499] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0500] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0501] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0502] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0503] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0504] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as equipment for processing and storing information.

[0505] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0506] Fig. 26 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 26, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0507] 26 , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0508] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0509] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0510] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0511] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the semiconductor device of one embodiment of the present invention is preferably used for the control device 6807. An OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0512] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0513] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0514] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0515] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to install storage and servers for storing a huge amount of data, to ensure a stable power supply for maintaining the data, or to ensure cooling equipment required for maintaining the data.

[0516] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0517] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0518] Fig. 27 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 27 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0519] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0520] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0521] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0522] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0523] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0524] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0525] In this example, a structure including an oxide 230 was fabricated by carrying out the processing shown in FIGS. 8A to 12D, and the results of cross-sectional STEM observation will be described.

[0526] In this example, as shown in Fig. 7B, a sample was prepared in which an island-shaped stacked body was provided on a hafnium oxide film (hereinafter referred to as HfOx film) on a silicon substrate, and a silicon nitride film (hereinafter referred to as SiNx_1 film) and a silicon oxide film (hereinafter referred to as SiOx_2 film) were stacked in this order to cover the island-shaped stacked body, and the sample was subjected to the processing shown in Fig. 8A to Fig. 12D. Here, the island-shaped stacked body was a stacked film in which a silicon oxide film (hereinafter referred to as SiOx_1 film), an In-Ga-Zn oxide film (hereinafter referred to as IGZO film), a tantalum nitride film (hereinafter referred to as TaNx film), a tungsten film (hereinafter referred to as W film), and a stacked film of silicon nitride and silicon oxide (hereinafter referred to as SiNx\SiOx film) were stacked in this order.

[0527] Here, the HfOx film corresponds to the insulator 222. The SiOx_1 film corresponds to the insulator 224. The IGZO film corresponds to the stacked film of the oxide 230a and the oxide 230b. The TaNx film corresponds to the conductor 242_1. The W film corresponds to the conductor 242_2. The SiNx\SiOx film corresponds to the insulator 271. The SiNx_1 film corresponds to the insulator 275. The SiOx_2 film corresponds to the insulator 280.

[0528] First, the etching conditions required for the process shown in Fig. 9D were selected. As in Fig. 9D, when etching the W film, it is necessary to ensure a sufficient selectivity with the TaNx film so that the etch can be stopped on the TaNx film. Specifically, the conditions of bias power and oxygen gas flow rate ratio were selected so that a sufficient selectivity with the TaNx film can be ensured.

[0529] In selecting the conditions of bias power and oxygen gas flow rate ratio, dry etching was performed on the TaNx film and the W film using an ICP etching device, and the etching rates of each were measured. Furthermore, the etching selectivity of the W film to the TaNx film (hereinafter referred to as the W / TaNx selectivity) was calculated.

[0530] First, the bias power conditions were selected. ４ Gas 55 sccm, Cl ２ Gas 45 sccm, and O ２ A gas flow rate of 55 sccm was used, the pressure was 0.67 Pa, the ICP power was 1000 W, and the substrate temperature was −10° C. The bias power was set to 25 W, 50 W, and 100 W, and the etching rate was measured under each condition.

[0531] The measurement results of the etching rate and etching selectivity ratio under the selected bias power conditions are shown in Figure 28A. In Figure 28A, the horizontal axis represents the bias power (Bias [W]), the left vertical axis represents the etching rate [nm / min], and the right vertical axis represents the etching selectivity ratio. In Figure 28A, the black circles represent the etching rate of the W film, the black diamonds represent the etching rate of the TaNx film, and the white circles represent the W / TaNx selectivity ratio.

[0532] 28A, as the bias power increases, the etching rates of the TaNx film and the W film increase, and the etching rate of the W film in particular becomes significantly higher. Therefore, as the bias power decreases, the W / TaNx selectivity ratio becomes relatively larger, and the W / TaNx selectivity ratio becomes maximum at a bias power of 25 W. Therefore, a bias power of 25 W was adopted for the etching process of the W film.

[0533] Next, the oxygen gas flow rate ratio was further selected under the condition of a bias power of 25 W. In selecting the oxygen gas flow rate ratio, CF ４ Gas, Cl ２ gas, and O ２ The gas was used under a pressure of 0.67 Pa, a bias power of 25 W, an ICP power of 1000 W, and a substrate temperature of −10° C. The oxygen gas flow rate ratio was set to the three conditions shown in Table 1, and the etching rate was measured.

[0534]

[0535] Here, the oxygen gas flow rate ratio (O ２ Ratio) is the ratio of the oxygen gas flow rate to the total etching gas flow rate, and O ２ / (CF ４ +Cl ２ +O ２ ) is defined as

[0536] The measurement results of the etching rate and etching selectivity when the oxygen gas flow rate ratio condition was selected are shown in FIG. 28B. In FIG. 28B, the horizontal axis represents the oxygen gas flow rate ratio (O ２ 28B, the left vertical axis represents the etching rate [nm / min], and the right vertical axis represents the etching selectivity. In Fig. 28B, black circles represent the etching rate of the W film, black diamonds represent the etching rate of the TaNx film, and white circles represent the W / TaNx selectivity.

[0537] As shown in Figure 28B, as the oxygen gas flow rate ratio increases, the etching rates of the TaNx film and the W film decrease, and the etching rate of the W film in particular decreases significantly. Therefore, as the oxygen gas flow rate ratio decreases, the W / TaNx selectivity increases relatively, and the W / TaNx selectivity reaches its maximum under the third condition with an oxygen gas flow rate ratio of 0.484 (CF ４ Gas 44 sccm, Cl ２ Gas 36 sccm, O ２ The conditions were adopted: 75 sccm of gas.

[0538] Next, a method for processing a sample having the above structure will be described.

[0539] In the above structure, the HfOx film is formed by ALD and has a thickness of 20 nm. The SiOx_1 film is formed by sputtering and has a thickness of 20 nm. The IGZO film is formed by sputtering and is a stacked film of a 10 nm thick IGZO (132) film and a 15 nm thick IGZO (111) film on top of it. The IGZO film (132) is formed using a target with an atomic ratio of In:Ga:Zn = 1:3:2, and the IGZO film (111) is formed using a target with an atomic ratio of In:Ga:Zn = 1:1:1.2. The TaNx film is formed by sputtering and has a thickness of 5 nm. The W film is formed by sputtering and has a thickness of 15 nm. The SiNx and SiOx films were successively deposited by sputtering, with the SiNx film having a thickness of 5 nm and the SiOx film having a thickness of 10 nm. The SiNx_1 film was deposited by PEALD, with a thickness of 5 nm. The SiOx_2 film was deposited by sputtering.

[0540] First, as in FIG. 9A, an SOC film (corresponding to the coating film 277f) was formed on the SiOx_2 film by spin coating, and an SOG film (corresponding to the coating film 278f) was further formed thereon by spin coating.

[0541] Next, similarly to FIG. 9A, a positive resist film was formed, and the resist film was irradiated with an electron beam to form a resist mask (corresponding to the resist mask 279) in which openings were formed.

[0542] Next, using the resist mask with the openings formed therein, a dry etching process corresponding to Fig. 9B was performed, thereby forming openings in the SOC film and the SOG film.

[0543] Next, the dry etching process shown in FIG. 9C was performed using the SOC film and the SOG film with the openings formed therein. As a result, openings were formed in the SiOx_2 film and the SiNx_1 film. The SOG film disappeared during the etching of the SiOx_2 film.

[0544] Next, the SOC film with the openings formed therein was subjected to a dry etching process corresponding to FIG. 9C. This resulted in the formation of openings in the SiNx / SiOx film. The dry etching process was performed using an ICP etching device. The etching conditions were CHF as the etching gas. ３ Gas 67 sccm, and O ２ The gas was 13 sccm, the pressure was 0.67 Pa, the ICP power was 3000 W, the bias power was 25 W, and the substrate temperature was -10°C.

[0545] Furthermore, without exposing to the atmosphere, a dry etching process corresponding to FIG. 9D was carried out continuously. As a result, an opening was formed in the W film and the W film was divided. Here, the dry etching process was carried out using an ICP etching device. As described above, the etching conditions were set to conditions that ensured a sufficient selectivity with the TaNx film. That is, the bias power was set to 25 W, and the oxygen gas flow rate ratio was set to 0.484 (CF ４ Gas 44 sccm, Cl ２ Gas 36 sccm, O ２ The other conditions were a pressure of 0.67 Pa, an ICP power of 1000 W, and a substrate temperature of -10°C.

[0546] Furthermore, without exposing the substrate to the atmosphere, the SOC film was removed by plasma ashing using oxygen gas, thereby forming a structure having an opening with a width L1 corresponding to those shown in FIGS.

[0547] 10A to 10D, a SiNx_2 film (corresponding to the insulating film 255A) was formed to cover the above-described structure. The SiNx_2 film was formed by the PEALD method and had a thickness of 5 nm.

[0548] Next, similarly to FIG. 12A, an SOC film (corresponding to the coating film 287f) was formed on the SiNx_2 film by spin coating, and an SOG film (corresponding to the coating film 288f) was further formed thereon by spin coating.

[0549] 12A , a positive resist film was formed, and the resist film was irradiated with an electron beam to form a resist mask (corresponding to resist mask 289) with an opening. Here, the width L2 of the opening formed in the resist mask in this process is smaller than the width L1 of the opening formed in the W film in the above process. In top view, the opening formed in the resist mask in this process is located inside the opening formed in the W film.

[0550] Next, using the resist mask with the openings formed therein, a dry etching process corresponding to Fig. 12B was performed, thereby forming openings in the SOC film and the SOG film.

[0551] Next, the SOC film and the SOG film with the openings formed therein were subjected to a dry etching process corresponding to FIG. 12C. This resulted in the formation of an opening in the SiNx_2 film. The SOG film also disappeared during the etching of the SiNx_2 film. The dry etching process was performed using an ICP etching device. The etching conditions were as follows: CHF ３ Gas 67 sccm, and O ２ The gas was 13 sccm, the pressure was 0.67 Pa, the ICP power was 3000 W, the bias power was 25 W, and the substrate temperature was -10°C.

[0552] Furthermore, without exposing to the atmosphere, a dry etching process corresponding to FIG. 12D was carried out. As a result, openings were formed in the TaNx film, and the TaNx film was divided. Here, the dry etching process was carried out using an ICP etching device. The etching conditions were: Cl 2 as an etching gas; ２ Gas 80 sccm and Ar gas 20 sccm were used, the pressure was 0.51 Pa, the ICP power was 1000 W, and the substrate temperature was −10° C. The bias power was initially 100 W and then increased to 10 W.

[0553] Furthermore, without exposing to the atmosphere, the SOC film was removed by plasma ashing using oxygen gas, thereby forming a structure in which the distance between the divided W film and the distance between the divided TaNx film were L1 and L2, respectively, as shown in Figures 11A to 11D.

[0554] Cross-sectional STEM images were taken of the samples prepared as described above. The cross-sectional STEM images were taken using a Hitachi High-Technologies "HD-2700" microscope at an accelerating voltage of 200 kV.

[0555] A cross-sectional STEM image of the sample is shown in Figure 29. Figure 29 is a cross section corresponding to Figure 11B. As shown in Figure 29, in the sample according to this example, the distance L2 between the TaNx films could be made shorter than the distance L1 between the W films. Here, in the region not overlapping with the W film, the upper surface of the TaNx film was not over-etched, and the protruding portion of the TaNx film was formed as designed. Furthermore, a SiNx_2 film could be formed in contact with the inner side surface of the W film and the upper surface of the TaNx film.

[0556] By performing the above processing, the source and drain electrodes of an OS transistor can be formed into a stacked structure of a TaNx film with high oxidation resistance and a W film with high conductivity. By providing a SiNx_2 film in contact with the inner surface of the W film, oxidation of the W film can be prevented and the conductivity of the W film can be maintained high. Furthermore, by providing the TaNx film protruding from the W film, the distance between the source and drain electrodes can be shortened, thereby improving the frequency characteristics of the OS transistor.

[0557] This embodiment can be combined with the embodiment mode and other embodiments as appropriate.

[0558] In this example, semiconductor devices including the transistor 200 shown in FIGS. 1A to 1D (hereinafter referred to as Sample 2A and Sample 2B) were fabricated, and the results of observing cross-sectional STEM images and evaluating electrical characteristics are described. In this example, Sample 2A and Sample 2B were fabricated using the method described in FIGS. 4A to 15D. However, Sample 2B was not subjected to the heat treatment after forming the conductors 242a1 and 242b1, as described in the above embodiment.

[0559] 1A to 1D, each of Sample 2A and Sample 2B includes an insulator 215 disposed on a substrate (not shown), an insulator 216 on the insulator 215, a conductor 205 (conductors 205a and 205b) embedded in the insulator 216, an insulator 222 on the insulator 216 and the conductor 205, an insulator 224 on the insulator 222, and an oxide 230 (oxide 230a and oxide 230b) on the insulator 224. The oxide 230 includes a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2), an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 (insulator 250a, insulator 250b, and insulator 250c) on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. The oxide 230 also includes an insulator 255 between the insulator 250 and the conductor 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, and the insulator 280. Furthermore, an insulator 275 is provided over the insulators 271a and 271b, and an insulator 280 is provided over the insulator 275. The insulators 255, 250, and conductor 260 are embedded inside openings provided in the insulator 280 and the insulator 275. Furthermore, an insulator 282 is provided over the insulator 280 and the conductor 260, and an insulator 283 is provided over the insulator 282.

[0560] The insulator 215 is a stacked film of a 60-nm-thick silicon nitride film and a 40-nm-thick aluminum oxide film on the silicon nitride film. The silicon nitride film and the aluminum oxide film were each formed by sputtering. The insulator 216 is a 200-nm-thick silicon oxide film formed by sputtering.

[0561] The conductor 205 is a stacked film of a conductor 205a and a conductor 205b, and is provided so as to be embedded in the opening of the insulator 216. The conductor 205a is a tantalum nitride film formed by sputtering. The conductor 205b is a titanium nitride film and a tungsten film on the titanium nitride film, both formed by CVD.

[0562] The insulator 222 is a laminated film of a 3-nm-thick silicon nitride film and a 17-nm-thick hafnium oxide film on the silicon nitride film. The silicon nitride film was formed by PEALD, and the hafnium oxide film was formed by thermal ALD.

[0563] The insulator 224 is a silicon oxide film having a thickness of 20 nm and formed by sputtering.

[0564] The oxide 230a was a 10-nm-thick In—Ga—Zn oxide film formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:2.

[0565] The oxide 230b was an In—Ga—Zn oxide film formed by sputtering to a thickness of 15 nm using a target with an atomic ratio of In:Ga:Zn=1:1:1.2.

[0566] The conductors 242a1 and 242b1 are tantalum nitride films with a thickness of 5 nm formed by sputtering, and the conductors 242a2 and 242b2 are tungsten films with a thickness of 15 nm formed by sputtering.

[0567] The insulators 271a and 271b are stacked films of a silicon nitride film with a thickness of 5 nm and a silicon oxide film with a thickness of 10 nm on the silicon nitride film. The silicon nitride film and the silicon oxide film were each formed by sputtering.

[0568] The insulator 275 is a silicon nitride film with a thickness of 5 nm formed by sputtering, and the insulator 280 is a silicon oxide film formed by sputtering.

[0569] The insulator 255, the insulator 250, and the conductor 260 are provided so as to be embedded inside the openings provided in the insulator 280 and the insulator 275. The insulator 255 is a silicon nitride film with a thickness of 5 nm formed by a PEALD method.

[0570] The insulator 250 is a stacked film of insulators 250a, 250b, and 250c. The insulator 250a is an aluminum oxide film with a thickness of 1 nm formed by thermal ALD. The insulator 250b is a silicon oxide film with a thickness of 3 nm formed by PEALD. The insulator 250c is a silicon nitride film with a thickness of 3 nm formed by PEALD.

[0571] The conductor 260 is a laminated film of a conductor 260a and a conductor 260b. The conductor 260a is a titanium nitride film formed by CVD. The conductor 260b is a tungsten film formed by CVD.

[0572] The insulator 282 is an aluminum oxide film with a thickness of 10 nm formed by sputtering, and the insulator 283 is a silicon nitride film with a thickness of 20 nm formed by sputtering.

[0573] 9A to 9D , the opening in the insulator 280, the opening in the insulator 275, the insulator 271 a, the insulator 271 b, the conductor 242 a 2, and the conductor 242 b 2 were formed using the methods shown in Fig. 9A to 9D . Since the formation was performed using the same method as in Example 1, the description of Example 1 can be referred to for details.

[0574] 12A to 12D. Since the insulator 255, the conductor 242a1, and the conductor 242b1 are formed by the same method as in Example 1, the description of Example 1 can be referred to for details.

[0575] In the sample 2A, a heat treatment was performed after the formation of the conductor 242a1 and the conductor 242b1 shown in FIG. ２ Gas flow rate 4 slm, O ２ The sample was subjected to atmospheric pressure heat treatment at 350° C. for 1 hour in a mixed atmosphere with a gas flow rate of 1 slm. Sample 2B was not subjected to this heat treatment.

[0576] Furthermore, for each of Sample 2A and Sample 2B, microwave treatment was performed after the formation of the insulating film that would become the insulator 250b. The microwave treatment was performed using 150 sccm of argon gas and 50 sccm of oxygen gas as treatment gases, with a power of 4000 W, a pressure of 400 Pa, a treatment temperature of 250° C., and a treatment time of 600 seconds.

[0577] Sample 2A and Sample 2B manufactured as described above are test element groups (TEGs) including a transistor with a channel length of 30 nm and a channel width of 30 nm and a transistor with a channel length of 60 nm and a channel width of 60 nm. Nine transistors each having a channel length of 30 nm and a channel width of 30 nm and a transistor with a channel length of 60 nm and a channel width of 60 nm were manufactured in Sample 2A and Sample 2B.

[0578] First, cross-sectional STEM images were taken of the transistors having a channel length of 30 nm and a channel width of 30 nm of Sample 2A and Sample 2B. The cross-sectional STEM images were taken using a Hitachi High-Technologies “HD-2700” at an accelerating voltage of 200 kV.

[0579] Cross-sectional STEM images of sample 2A are shown in FIGS. 30A to 30C, and cross-sectional STEM images of sample 2B are shown in FIGS. 31A and 31B. FIGS. 30A and 31A are TE images of a cross section of the transistor of each sample in the channel length direction. FIGS. 30B and 31B are ZC images that are enlarged views of the vicinity of the conductor 242a2 in FIGS. 30A and 31A, respectively. FIG. 30C is a TE image of a cross section of the transistor of sample 2A in the channel width direction.

[0580] 30A, in the transistor of Sample 2A, the distance between conductor 242a1 and conductor 242b1 could be made shorter than the distance between conductor 242a2 and conductor 242b2. In other words, protrusions of conductor 242a1 and conductor 242b1 could be formed as designed, and the protrusions could be formed so as to overlap a portion of conductor 260. Furthermore, as shown in FIG. 31A, Sample 2B could also be formed to have a structure similar to that of Sample 2A.

[0581] 30A, the boundary between insulator 255 and insulator 250 is difficult to see, but it can be seen that insulator 255 is formed because the portion on conductors 242a1 and 242b1 where insulator 255 and insulator 250 are stacked is thicker than the portion consisting of only insulator 250. Also, in Fig. 30C, in the portion where conductor 260 and insulator 255 overlap, the shape of the bottom surface of conductor 260 is deformed to reflect the shape of insulator 255.

[0582] As shown in Figure 30B, the thickness of the oxide film on the side surface of the conductor 242a2 of Sample 2A was 1.5 nm. Also, as shown in Figure 31B, the thickness of the oxide film on the side surface of the conductor 242a2 of Sample 2B was 1.3 nm. In other words, the thickness of the oxide film on the side surface of the conductors 242a2 and 242b2 of the transistors hardly changed regardless of whether or not heat treatment was performed after the formation of the conductors 242a1 and 242b1. This is thought to be because providing the insulator 255 in contact with the side surfaces of the conductors 242a2 and 242b2 suppressed oxidation of the side surfaces.

[0583] Next, the electrical characteristics of nine transistor elements with a channel length of 30 nm and a channel width of 30 nm and nine transistor elements with a channel length of 60 nm and a channel width of 60 nm formed in Sample 2A and Sample 2B were evaluated. The electrical characteristics were evaluated by measuring the Id-Vg characteristics (drain current-gate voltage characteristics) of each element using a semiconductor parameter analyzer manufactured by Keysight Technologies. The Id-Vg characteristics were measured by setting the drain potential Vd to 0.1 V or 1.2 V, the source potential Vs to 0 V, the bottom gate potential Vbg to 0 V, and sweeping the top gate potential Vg from −4.0 V to 4.0 V in 0.1 V steps.

[0584] 32A to 33B show the measurement results of Id-Vg characteristics. FIG. 32A shows the measurement results of nine transistors of Sample 2A with a channel length of 30 nm and a channel width of 30 nm. FIG. 32B shows the measurement results of nine transistors of Sample 2B with a channel length of 30 nm and a channel width of 30 nm. FIG. 33A shows the measurement results of nine transistors of Sample 2A with a channel length of 60 nm and a channel width of 60 nm. FIG. 33B shows the measurement results of nine transistors of Sample 2B with a channel length of 60 nm and a channel width of 60 nm. In FIGS. 32A to 33B, the horizontal axis represents the top gate potential Vg [V], and the vertical axis represents the drain current Id [A]. The thin solid line indicates the drain current when Vd = 0.1 V, and the thick solid line indicates the drain current when Vd = 1.2 V.

[0585] 34A and 34B show graphs in which the graphs of FIGS. 32A and 32B for Vd = 1.2 V are normalized with Vg - Vsh [V] on the horizontal axis. Here, the shift voltage Vsh is defined as the Vg at the point where the tangent to the point where the slope of the Id - Vg curve of the transistor is maximum intersects with the line for Id = 1 pA. The dashed lines in FIGS. 34A and 34B represent Vg - Vsh = 2.5 V.

[0586] 32A to 33B, the shift voltage Vsh, on-current Ion, and S value were calculated from the measurement results of the Id-Vg characteristics. The on-current Ion is defined as Id at the point where the Id-Vg curve, normalized by Vg-Vsh on the horizontal axis, intersects with the line Vg-Vsh=2.5V. The S value is the value of Vg required for Id to change by one order of magnitude in the subthreshold region of the Id-Vg curve where Vd=1.2V.

[0587] Table 2 shows the median shift voltage Vsh_m (V), the variation in shift voltage Vsh_σ (mV), the median on-state current (μA), and the median S value (mV / dec) of nine transistors with a channel length of 30 nm and a channel width of 30 nm in Sample 2A and Sample 2B.

[0588]

[0589] 32A, 32B, and Table 2, the transistors of Sample 2A and Sample 2B have a positive shift voltage Vsh near 0 V, and the variation in the shift voltage Vsh within the substrate surface is small. This is thought to be because, in Sample 2A and Sample 2B, as described above, oxidation of the side surfaces of the conductors 242a2 and 242b2 is suppressed, so that a sufficient amount of oxygen is supplied to the oxide 230, and oxygen vacancies in the oxide 230 are reduced.

[0590] 34A and 34B and Table 2, the transistors of Samples 2A and 2B exhibit good S values. As a result, the drain current Id is sufficiently large at a voltage of Vg−Vsh=2.5 V, at which the on-current is calculated.

[0591] As shown in FIGS. 33A and 33B, the transistors of Samples 2A and 2B with a channel length of 60 nm and a channel width of 60 nm also had electrical characteristics that were equal to or better than those of the transistors of Samples 2A and 2B with a channel length of 30 nm and a channel width of 30 nm.

[0592] As described above, by performing the processing according to this embodiment, the source and drain electrodes of the OS transistor can be formed into a stacked structure of conductors 242a1 and 242b1 with high oxidation resistance and conductors 242a2 and 242b2 with high conductivity. By providing the insulator 255 in contact with the inner surfaces of the conductors 242a2 and 242b2, oxidation of the conductors 242a2 and 242b2 can be prevented, and high conductivity can be maintained. Furthermore, by providing the conductors 242a1 and 242b1 to protrude beyond the conductors 242a2 and 242b2, the distance between the source and drain electrodes can be shortened. As described above, a semiconductor device including a transistor with good electrical characteristics and little variation in electrical characteristics can be provided.

[0593] This embodiment can be combined with the embodiment mode and other embodiments as appropriate.

[0594] ADDR: signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11a: transistor, 11b: transistor, 11c: transistor, 11: transistor, 12a: capacitor, 12: capacitor, 20[1]: memory array, 20[2]: memory array, 20[5]: memory array, 20[m]: memory array, 20: memory array, 21: driver circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage Generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 52: transistor, 53_a: transistor, 53_b: transistor, 53: transistor, 54_a: transistor, 54_b: transistor, 54: transistor, 55_a: transistor, 55_b: transistor, 55: transistor, 70 [1]: repeat unit, 70: repeat unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write / read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 153: conductor, 154: insulator, 160a: conductor,160b: conductor, 160: conductor, 200: transistor, 205a: conductor, 205b: conductor, 205: conductor, 207: conductor, 208: insulator, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 215: insulator, 216: insulator, 222: insulator, 224f: insulating film, 224: insulator, 230a: oxide, 230af: oxide film, 230b: oxide, 230bf: oxide film, 230: oxide, 240a: conductor, 240b: conductor, 240: conductor, 241: insulator, 242_1: conductor, 242_1f: conductive film, 242_2: Conductor, 242_2f: Conductive film, 242a: Conductor, 242a1: Conductor, 242a2: Conductor, 242b: Conductor, 242b1: Conductor, 242b2: Conductor, 250a: Insulator, 250A: Insulator, 250b: Insulator, 250c: Insulator, 250d: Insulator, 250: Insulator, 255A: Insulator, 255: Insulator, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 260: Conductor, 261: Conductor, 271a: Insulator, 271a1: Insulator, 271a2: Insulator, 271b: Insulator, 271b1: Insulator, 271b2: Insulator Insulator, 271f: insulating film, 271: insulator, 275: insulator, 277f: coating film, 277: coating film, 278f: coating film, 278: coating film, 279: resist mask, 280: insulator, 282: insulator,...

Claims

1. an oxide on the substrate; a first conductor and a second conductor spaced apart from each other on the oxide; a third conductor in contact with an upper surface of the first conductor; a fourth conductor in contact with an upper surface of the second conductor; a first insulator having an opening on the third conductor and the fourth conductor; a second insulator disposed within the opening of the first insulator and in contact with an upper surface of the first conductor, an upper surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator on the second insulator; and a fifth conductor on the third insulator; and and the oxide has a channel forming region of a transistor; the fifth conductor functions as a gate of the transistor, the opening overlaps a region between the third conductor and the fourth conductor; the fifth conductor has a region overlapping with the oxide via the third insulator, the third insulator contacts an upper surface of the oxide in a region between the first conductor and the second conductor; A semiconductor device, wherein a distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor.

2. In claim 1, The semiconductor device, wherein the first conductor and the second conductor include a metal nitride.

3. In claim 1, The semiconductor device, wherein the first conductor and the second conductor comprise tantalum nitride.

4. In claim 1, the first conductor and the second conductor comprise tantalum nitride; The semiconductor device, wherein the third conductor and the fourth conductor include tungsten.

5. In claim 1, The semiconductor device, wherein the second insulator comprises a nitride.

6. In claim 1, The semiconductor device, wherein the second insulator comprises silicon nitride.

7. In claim 1, The semiconductor device, wherein the third insulator has an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

8. In claim 1, the third insulator includes an aluminum oxide film, a silicon oxide film on the aluminum oxide film, and a silicon nitride film on the silicon oxide film.

9. In claim 1, the third insulator has an aluminum oxide film, a silicon oxide film on the aluminum oxide film, a hafnium oxide film on the silicon oxide film, and a silicon nitride film on the hafnium oxide film.

10. In claim 1, The second insulator contacts a side surface of the first insulator.

11. In claim 1, The third insulator contacts the top surface and side surfaces of the second insulator, the side surfaces of the first conductor, and the side surfaces of the second conductor.

12. A semiconductor device comprising: a semiconductor device according to any one of claims 1 to 11; and a capacitive element; a first electrode of the capacitance element electrically connected to the third conductor of the semiconductor device;