Semiconductor device and electric power conversion device

Abstract

In a semiconductor device (100) for controlling driving of a semiconductor element (10), a current control unit (1) is provided for passing a pulsed current between a negative electrode terminal (S) and a control terminal (G) of the semiconductor element (10). A peak detection circuit (5) detects a peak value of a voltage between the control terminal (G) or negative electrode terminal (S) and a reference potential during the period of a current supply by the current control unit (1). A temperature estimation unit (7) calculates an estimated temperature of the semiconductor element on the basis of an output voltage of the peak detection circuit (5) sampled by a voltage detection unit (6). A timing control unit (3) causes the current control unit (1) to operate so as to provide the current supply period in an on-period after the semiconductor element has transitioned to an on-state and / or in an off-period after the semiconductor element has transitioned to an off-state.

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a semiconductor device and a power conversion device.

[0002] BACKGROUND ART In power converters using power semiconductor elements (power semiconductor elements) such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), efforts are being made to increase the current density flowing through the power semiconductor elements in order to reduce their size.

[0003] However, increasing the current density increases the energy loss of the power semiconductor element, leading to a rise in the temperature of the power semiconductor element. Power semiconductor elements have a maximum allowable operating temperature determined by the semiconductor material properties, etc., and above this temperature, the power semiconductor element may experience thermal runaway and be destroyed. For this reason, temperature management of power semiconductor elements has become increasingly important in recent years.

[0004] To manage the temperature of such power semiconductor elements, a known method is to attach a temperature sensor such as a thermistor to the fins that cool the power semiconductor elements, thereby indirectly estimating the temperature of the power semiconductor elements. However, because the thermal time constant from the power semiconductor elements to the fins is generally large, this method may not be able to measure sudden changes in the temperature of the power semiconductor elements due to short-term load fluctuations.

[0005] One method for solving this problem is disclosed in Japanese Patent Laid-Open No. 2020-72569 (Patent Document 1). This method pre-stores information indicating the relationship between the time change in gate voltage during switching operation of a semiconductor device and the temperature of the power semiconductor element, and estimates the temperature of the power semiconductor element from the gate voltage rise time.

[0006] Japanese Patent Application Laid-Open No. 2020-72569

[0007] However, the technology disclosed in Patent Document 1 requires a high-precision measurement mechanism and a high-speed processor to measure the time it takes for the gate voltage to rise, and providing such a measurement mechanism can restrict the miniaturization of the power module.

[0008] The present disclosure has been made in consideration of the above-mentioned problems, and one of its objectives is to provide a semiconductor device that drives and controls a power semiconductor element and has a temperature estimation function for the power semiconductor element, which does not require a high-precision measurement mechanism or a high-speed processor.

[0009] According to one aspect of the present disclosure, a semiconductor device that drives and controls a semiconductor element includes a driver circuit, a current control unit, a timing control unit, a peak detection circuit, a voltage detection unit, and a temperature estimation unit. The semiconductor element has a positive terminal, a negative terminal, and a control terminal to which a drive voltage is applied that controls a main current flowing between the positive terminal and the negative terminal. The driver circuit transitions the semiconductor element between an ON state and an OFF state by supplying a drive voltage to the control terminal. The current control unit is provided to flow a pulsed current between the control terminal and the negative terminal. The timing control unit controls the timing at which the current control unit supplies the current. The peak detection circuit outputs a peak value of an input voltage, which is the potential difference between the control terminal or the negative terminal and the reference potential relative to a reference potential, during a period in which the current control unit supplies current. The voltage detection unit samples the output voltage of the peak detection circuit. The temperature estimation unit calculates an estimated temperature of the semiconductor element based on the voltage detected by the voltage detection unit. The timing control section operates the current control section so as to provide a current supply period during at least one of an ON period after the semiconductor element has transitioned to an ON state and an OFF period after the semiconductor element has transitioned to an OFF state.

[0010] According to the present disclosure, it is possible to provide a semiconductor device that can estimate the temperature of a semiconductor element based on the peak value of the voltage between a control terminal or a negative terminal and a reference potential when a current is supplied between the control terminal and the negative terminal, even without a high-speed measurement mechanism or a high-speed processor.

[0011] 1B is a circuit diagram illustrating a configuration example of a power module according to a first embodiment; FIG. 1C is a circuit diagram illustrating a configuration example of a current control unit of FIG. 1A; FIG. 1D is a circuit diagram illustrating a first example of a connection position of a current control unit shown in FIG. 1B; FIG. 1E is a circuit diagram illustrating a second example of a connection position of a current control unit shown in FIG. 1B; FIG. 1F is a configuration diagram illustrating a modification of the power module of FIG. 1A; FIG. 1G is a circuit diagram illustrating a configuration example of a peak detection circuit shown in FIG. 1A; FIG. 1H is a timing chart for illustrating a temperature estimation method by a semiconductor device according to the first embodiment; FIG. 1I is a circuit diagram illustrating a configuration of a peak detection circuit according to a modification of the first embodiment; FIG. 1J is a timing chart for illustrating a temperature estimation method by a semiconductor device according to a modification of the first embodiment; FIG. 1J is a circuit diagram illustrating a first configuration example of a peak detection circuit according to a second embodiment; FIG. 1J is a timing chart for illustrating a temperature estimation method by a semiconductor device according to a third embodiment; FIG. 1L is a configuration diagram illustrating an example of a power module according to a fourth embodiment; FIG. 1L is a timing chart for illustrating a method of estimating thermal resistance and thermal impedance by a semiconductor device according to the fourth embodiment;

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their description will not be repeated in principle.

[0013] Embodiment 1 Fig. 1A is a configuration diagram showing an example of a power module 101 according to embodiment 1. Fig. 1B is a circuit diagram showing an example of the configuration of the current control unit 1 of Fig. 1A. The configuration of the power module 101 will be described below with reference to Figs. 1A and 1B.

[0014] 1A, a power module 101 includes a power semiconductor element 10 and a semiconductor device 100 that drives and controls the power semiconductor element 10. The semiconductor device 100 controls the switching of the power semiconductor element 10 and measures the element temperature of the power semiconductor element 10.

[0015] The power semiconductor element 10 includes a positive terminal (drain) D, a negative terminal (source) S, and a control terminal (gate) G. A main current Imt flowing between the positive terminal D and the negative terminal S is controlled by a drive voltage applied to the control terminal G.

[0016] The power semiconductor element 10 may be any of a MOSFET, an IGBT, a MESFET (Metal-Semiconductor Field-Effect Transistor), a bipolar transistor, etc. In the following, a MOSFET will be described as an example. In addition to Si, the material of the power semiconductor element 10 may be SiC, GaN, Ga ２ O ３ , diamond, etc. may also be used.

[0017] The semiconductor device 100 includes a gate driver 4, a current controller 1, a gate wiring unit 2, a timing controller 3, a peak detector 5, a voltage detector 6, and a temperature estimator 7. The gate driver 4 includes a driver circuit 42 as a drive controller connected to the power semiconductor element 10 to drive the power semiconductor element 10, and a main controller 41 that controls the driver circuit 42.

[0018] The control terminal G of the power semiconductor element 10 is connected to the driver circuit 42 through a resistive element 21 provided in the gate wiring portion 2. The gate wiring portion 2 represents a series of loop wiring that connects the control terminal G of the power semiconductor element 10, the negative terminal S, and the driver circuit 42. In the example of FIG. 1A , the resistive element 21 is connected between the driver circuit 42 and the control terminal G of the power semiconductor element 10.

[0019] The current control unit 1 is connected to a driver circuit 42 and supplies a current to a path formed between the control terminal G and the negative terminal S of the power semiconductor element 10 via the driver circuit 42. As shown in FIG. 1B , the current control unit 1 includes a pulse current source 20 for supplying a pulsed current. More specifically, the pulse current source 20 includes, for example, a current source 11 that supplies a constant current, and a current control switch 12 connected in parallel with the current source 11. The current control switch 12 is turned on or off in response to a switch control signal 31 from the timing control unit 3.

[0020] When the current control switch 12 is switched from on to off, the pulse current source 20 starts outputting current, and when the current control switch 12 is switched from off to on, the pulse current source 20 stops outputting current. In this way, the output current of the current control unit 1 is controlled to be pulsed in response to the on / off of the current control switch 12.

[0021] The current source 11 may be, for example, a bipolar transistor, a current mirror, or a constant voltage source with a resistor on the output side. Various commonly known current sources may be used. Depending on the circuit configuration, the current source 11 may be configured as a current source that outputs current or as a current sink that sinks current. The current control switch 12 may be, for example, a switching element that operates at a relatively high speed, such as a MOSFET. When measurement accuracy is required, an ultrafast device such as a GaN HEMT (High Electron Mobility Transistor) may be used as the current control switch 12.

[0022] 1B, one end of each of the current source 11 and the current control switch 12 is connected to a reference potential node 90 that provides a reference potential. Here, the reference potential is, for example, the control ground of the driver circuit 42 or the power supply voltage of the driver circuit 42.

[0023] The other ends of the current source 11 and the current control switch 12 are electrically connected directly or indirectly to the control terminal G or the negative terminal S of the power semiconductor element 10. When they are indirectly connected, the other ends of the current source 11 and the current control switch 12 are connected to the control terminal G (gate) or the negative terminal S (source) of the power semiconductor element 10 via other electronic components mounted in the driver circuit 42, such as a semiconductor switching element or a resistor.

[0024] 2A and 2B show circuit diagrams illustrating first and second examples of the connection position of the current control unit 1. FIG.

[0025] 2A shows a configuration example in which the other ends (the ends not connected to the reference potential node 90) of the current source 11 and the current control switch 12 are electrically connected to the negative terminal S of the power semiconductor element 10. In FIG. 2A, the current control unit 1 is connected to a position where a current is supplied from the negative terminal S side of the power semiconductor element 10.

[0026] 2B shows a configuration example in which the other ends of the current source 11 and the current control switch 12 are electrically connected to the control terminal G of the power semiconductor element 10. In Fig. 2B, the current control unit 1 is indirectly connected to the control terminal G via a driver circuit 42, and is thereby connected to a position where current is supplied from the control terminal G side of the power semiconductor element 10. Below, as an example, a case in which the other ends of the current source 11 and the current control switch 12 are electrically connected to the negative terminal S of the power semiconductor element 10 (Fig. 2A) will be described.

[0027] 1A again, the timing control unit 3 outputs a switch control signal 31 for controlling the current control switch 12 of the current control unit 1 based on a command 412 from the main control unit 41 of the gate drive unit 4. As already explained, the main control unit 41 controls the driver circuit 42 and the timing control unit 3. As the main control unit 41, for example, a functional device such as a microprocessor, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field Programmable Gate Array) is used.

[0028] 1A, for the sake of explanation, the timing control unit 3 and the gate drive unit 4 are explicitly shown as separate units, but the timing control unit 3 may be included in the main control unit 41. Furthermore, the driver circuit 42 and the timing control unit 3 may be mounted on the same substrate, or the main control unit 41, the driver circuit 42, the timing control unit 3, and the current control unit 1 may all be mounted on the same substrate.

[0029] The peak detection circuit 5 is connected to the driver circuit 42 so as to receive the voltage across both ends (terminal voltage) of the current source 11. An example of the configuration of the peak detection circuit 5 will be described later.

[0030] The voltage detection unit 6 detects the output voltage of the peak detection circuit 5. The temperature estimation unit 7 calculates an estimated temperature of the power semiconductor element 10 from the output voltage value of the peak detection circuit 5 at a predetermined timing, based on the detection value of the voltage detection unit 6 and the control information 32 of the timing control unit 3. For example, as will be described below, the temperature estimation unit 7 calculates the resistance value of the power semiconductor element 10 from the output voltage value. Furthermore, the temperature estimation unit 7 generates temperature information 71 including an estimated temperature obtained by converting the newly measured resistance value of the power semiconductor element 10 into temperature by comparing it with conversion data that indicates the relationship between resistance value and element temperature, which is predetermined based on measurement values ​​obtained in an advance experiment using an actual device.

[0031] The temperature information 71 is fed back to the main control unit 41. When the temperature exceeds a predetermined value, the main control unit 41 can change the drive pattern to reduce the loss of the power semiconductor elements, or can output warning information to a higher-level system. For the sake of explanation, in FIG. 1A, the main control unit 41 and the temperature estimation unit 7 are shown as separate components, but the function of the temperature estimation unit 7 may be included in the main control unit 41.

[0032] FIG. 3 is a configuration diagram showing a modified example of the power module 101 of FIG. 1A. The power module 101 shown in FIG. 3 differs from the power module 101 of FIG. 1A in that, in the gate wiring section 2, the resistive element 21 is connected to the wiring (source wiring) connected to the negative terminal S, rather than to the wiring (gate wiring) connected to the control terminal G. In this case, the resistive element 21 still generates a voltage drop in the gate wiring section 2 according to the current flowing between the control terminal G and the negative terminal S. Other aspects of FIG. 3 are similar to those of FIG. 1A, and therefore identical or corresponding parts are designated by the same reference numerals and will not be described again. Furthermore, although the resistive element 21 is clearly shown external to the power semiconductor element 10 in each of FIGS. 1A and 3, depending on the application, a gate resistor may not be provided external to the power semiconductor element 10.

[0033] [Temperature Estimation Method of Power Semiconductor Element] A more specific description will now be given of a method of estimating the temperature of the power semiconductor element 10 using the semiconductor device 100 shown in Fig. 1A. Fig. 4 shows an example of the configuration of the peak detection circuit 5 shown in Fig. 1A. Fig. 5 shows a timing chart for explaining a temperature estimation method using the semiconductor device 100 in which the peak detection circuit 5 shown in Fig. 4 is arranged.

[0034] 4, the peak detection circuit 5 can be configured, for example, by a detection circuit having a diode 51, a capacitor 52, and a discharge switch 53. The diode 51 is connected between the input node Nx and the node Ny, with the forward direction being from the input node Nx to the node Ny. The capacitor 52 is connected between the node Ny and the node Ns. The potential of the node Ns is also referred to as Vss. The node Ns has the same potential as the reference potential node 90 in FIG. 1B, etc., and the input voltage Vx of the peak detection circuit 5 corresponds to the potential difference of the node Nx with respect to the node Ns, i.e., the potential difference of the control terminal G or the negative terminal S with respect to the reference potential.

[0035] The discharge switch 53 is connected in parallel with the capacitor 52 and is turned on and off in response to a switch control signal 35 from the timing control unit 3. The discharge switch 53 can be configured, for example, by a MOSFET with a small leakage current in order to maintain the potential of the node Ny in the off state.

[0036] As described above, the peak detection circuit 5 is connected so that the voltage across both ends of the current source 11 (terminal voltage) is input thereto. Therefore, when the current control unit 1 is connected in the manner shown in FIG. 2A , the input nodes Nx and Ns of the peak detection circuit 5 are connected directly or indirectly to the negative terminal S of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the negative terminal S of the power semiconductor element 10. On the other hand, when the current control unit 1 is connected in the manner shown in FIG. 2B , the input nodes Nx and Ns of the peak detection circuit 5 are connected directly or indirectly to the control terminal G of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the control terminal G of the power semiconductor element 10.

[0037] In the peak detection circuit 5, when the voltage of the input node Nx is higher than the voltage of the node Ny, the input voltage Vx is transmitted to the node Ny and held by the capacitor 52. On the other hand, when the voltage of the input node Nx is lower than the voltage of the node Ny, the input voltage Vx is not transmitted to the node Ny, and therefore the capacitor 52 holds and outputs the peak value of the voltage transmitted by the diode 51 up to that point.

[0038] In FIG. 4, input node Nx corresponds to an example of a "first node", node Ny corresponds to an example of a "second node", and diode 51 corresponds to an example of a "first diode".

[0039] The voltage detection unit 6 detects the voltage (Vdet) of the capacitor 52, i.e., the output voltage of the peak detection circuit 5, by sampling it. Hereinafter, the voltage of the capacitor 52, which corresponds to the input voltage of the voltage detection unit 6, will also be referred to as the detected voltage Vdet. When the discharge switch 53 is in the on state, the detected voltage Vdet is cleared (Vdet=Vss).

[0040] A temperature estimation method using semiconductor device 100 (FIG. 1A) according to the first embodiment will be described with reference to FIG. 5. In FIG. 5, waveforms up to time t2 show voltage waveforms and signal waveforms during normal switching operation without temperature measurement, and waveforms from time t2 onward show voltage waveforms and signal waveforms when temperature measurement is performed in conjunction with switching operation. First, the operation of semiconductor device 100 during normal switching operation will be described.

[0041] (Operation of the Semiconductor Device Under Normal Conditions) The driver circuit 42 outputs a positive potential Vcc that is greater than the threshold voltage and a potential Vee (usually a negative potential or zero potential) that is less than or equal to the threshold voltage to drive the power semiconductor element 10. Specifically, the driver circuit 42 applies the positive potential Vcc or the negative or zero potential Vee as a gate voltage to the control terminal G of the power semiconductor element 10 based on a driver input signal 411 from the main control unit 41. In this way, the driver circuit 42 transitions the power semiconductor element 10 between an on state and an off state.

[0042] During normal operation, the timing control unit 3 controls the current control switch 12 of the current control unit 1 to be always on. Therefore, when an enhancement type element such as an n-type MOSFET is used in the current control switch 12, a signal of logic high (H) level is always input as the switch control signal 31 of the current control switch 12. When a depletion type element such as a p-type MOSFET is used in the current control switch 12, a signal of logic low (L) level is always input as the switch control signal 31.

[0043] 5, in the case of a turn-on operation, when driver input signal 411 to driver circuit 42 changes from L level to H level at time t0, positive potential Vcc is applied to control terminal G of power semiconductor element 10, causing gate voltage Vgs to rise. Gate voltage Vgs reaches positive potential Vcc at time t0x after a rise period determined by a time constant that depends on the resistance value of resistor element 21 and the capacitance of power semiconductor element 10.

[0044] At this time, the gate current supplied from the driver circuit 42 to the power semiconductor element 10 flows directly to the reference potential node 90 via the current control switch 12. Similarly, the current from the current source 11 also flows to the reference potential node 90 via the current control switch 12 and is not output to the driver circuit 42. Note that during the rising period between time t0 and time t0x, a mirror period in which the gate voltage Vgs is a constant value is observed.

[0045] In the case of a turn-off operation, the driver input signal 411 changes from H level to L level at time t1. As a result, a negative or zero potential Vee is applied to the control terminal G of the power semiconductor device 10, and the gate voltage Vgs drops. As in the case of a turn-on operation, the gate voltage Vgs passes through a falling period and reaches the negative or zero potential Vee at time t1x. As in the case of a turn-on operation, the gate current flows to the reference potential node 90 via the current control switch 12. The current from the current source 11 flows to the reference potential node 90 via the current control switch 12 and is not output to the driver circuit 42. Note that a mirror period is also observed during the falling period from time t1 to t1x.

[0046] (Temperature Measurement During On-Period) Next, the operation of the semiconductor device 100 when measuring temperature will be described. Temperature measurement is performed during a period when the gate voltage is stable, other than the rising and falling periods of the gate voltage. The period when the gate voltage is stable includes a period when the gate voltage is stable at a positive potential Vcc (hereinafter referred to as an "on-period") and a period when the gate voltage is stable at a negative or zero potential Vee (hereinafter referred to as an "off-period").

[0047] First, temperature measurement during the ON period will be described. Referring to Fig. 5, at time t2, which corresponds to the timing of the turn-on command, driver input signal 411 changes from L level to H level. At time t3, which is a certain delay period after time t2, switch control signals 31 and 35 switch from H level to L level. This delay time can be simply set to a time constant determined by the resistance value of resistor element 21 and the element capacitance of power semiconductor element 10, or a time longer than that.

[0048] If this delay time is short, the gate drive current from the driver circuit 42 also affects the voltage detected by the voltage detection unit 6, thereby affecting the accuracy of the temperature measurement. On the other hand, if this delay time is long, the time t4 at which the switch control signal 31 is returned to the H level comes close to the turn-off start time t5. As a result, the gate drive current from the driver circuit 42 also affects the voltage detected by the voltage detection unit 6, thereby affecting the accuracy of the temperature measurement.

[0049] 1B is turned off. As a result, the current from the current source 11 flows to the power semiconductor element 10, not to the reference potential node 90. That is, the current control unit 1 supplies current between the control terminal G and the negative terminal S. During this current supply period, the input voltage Vx to the peak detection circuit 5 is expressed by the following equation (1):

[0050]

[0051] In equation (1), Vx(t-t3) represents the input voltage of the peak detection circuit 5 at time t after time t3. ｇｉｎｔ is the value of the gate resistance (internal gate resistance) present in the power semiconductor element 10. The internal gate resistance is, for example, built in on the power semiconductor element 10 using a material such as polysilicon. Alternatively, the internal gate resistance includes a parasitic resistance due to a gate wiring pattern on the power semiconductor element 10.

[0052] R in formula (1) ｇ represents the resistance of the driver circuit 42 and the resistance element 21, and represents the resistance component other than the resistance caused by the power semiconductor element 10 itself. ｇ is applied to the power semiconductor element 10 by an external resistor, so it is relatively easy to select the resistance value and temperature characteristics. ｄｉｅ represents the capacitance value as viewed from the gate side (in the case of FIG. 2A) or the source side (in the case of FIG. 2B) of the power semiconductor element 10. ｇ represents the supply current from the current source 11.

[0053] In the current control unit 1 (FIG. 1B, etc.), when the current control switch 12 is turned off, the current source 11 starts to inject current into the power semiconductor element 10. As a result, the input voltage Vx according to equation (1) is input to the peak detection circuit 5.

[0054] Specifically, as shown in the first term on the right side of equation (1), a voltage V0=(R ｇ +R ｇｉｎｔ ) I ｇ occurs steadily.

[0055] Furthermore, as shown in the second term on the right side of equation (1), after time t3 when the current control switch 12 is turned off, the input voltage Vx becomes (t−t3)·I as the parasitic capacitance of the power semiconductor element 10 is charged. ｇ / C ｄｉｅ The parasitic capacitance C ｄｉｅ is constant, and the current I ｇ is a constant value, the input voltage Vx of the peak detection circuit 5 increases linearly. As the input voltage Vx increases, the change in the input voltage Vx is transmitted to the capacitor 52 via the node Ny, and therefore, from time t3 onwards, the detected voltage Vdet of the voltage detection unit 6 changes in a manner equivalent to the input voltage Vx (Vdet=Vx).

[0056] At time t4, when the switch control signal 31 is returned from L level to H level, the current control switch 12 in the current control unit 1 is turned on, and the current from the current source 11 begins to flow to the reference potential node 90. At the same time, the charge stored in the parasitic capacitance of the power semiconductor element 10 is also discharged. With the current control switch 12 turned on, the voltage between the terminals of the current source 11 becomes zero, and so at time t4, the input voltage Vx of the peak detection circuit 5 becomes 0.

[0057] On the other hand, since the switch control signal 35 is maintained at the L level, the discharge switch 53 is maintained in the OFF state in the peak detection circuit 5. Therefore, after time t4, the detection voltage Vdet of the voltage detection unit 6 is maintained at the voltage value at time t3.

[0058] At time t4x, when the switch control signal 35 changes from L level to H level, the discharge switch 53 in the peak detection circuit 5 (FIG. 4) is turned on, and the voltage of the capacitor 52 becomes zero. In response to this, the detected voltage Vdet of the voltage detection unit 6 changes to 0. Note that time t4x can also be set to coincide with the turn-off command timing at which the driver input signal 411 changes from H level to L level, as will be described later.

[0059] As a result, in the temperature measurement during the ON period, the following input voltage Vx(t4) is measured as the detected voltage Vdet by the voltage detection unit 6 during the period from time t4 to t4x.

[0060]

[0061] current I ｇ is a constant value, and the time difference from time t3 to t4 (i.e., the length of the current supply period) is constant, the value obtained by subtracting the second term on the right-hand side corresponding to the charging voltage of the parasitic capacitance from Vx(t4), that is, V0=(R ｇ +R ｉｎｔ ) I ｇ is the resistance value (R ｇ +R ｉｎｔ ) Normally, the parasitic capacitance has little temperature dependency, so the charging voltage of the parasitic capacitance can be considered to be a constant value.

[0062] Therefore, the voltage value V1 of the detection voltage Vdet at time t4, the time difference between times t3 and t4, and the known I corresponding to the output current of the current source 11 are used. ｇ Using this, the resistance value (R ｇ +R ｇｉｎｔ ) can be calculated.

[0063] Here, the resistance value R ｇ and R ｇｉｎｔ Each of these has temperature dependency. ｇ , R ｇｉｎｔ If each of these has a linear temperature dependency, the resistance value R at temperature T is ｇ (T) and R ｇｉｎｔ is expressed as R using the temperature coefficient K. ｇ (T) ≒ R ｇ 0.(1+K１ ・T), R ｇｉｎｔ (T)≒Rg ｉｎｔ 0.(1+K ２ ・T).

[0064] Resistance value R other than the internal gate resistor of the power semiconductor element 10 ｇ The temperature dependence of the internal gate resistance R of the power semiconductor element 10 ｇｉｎｔ If the temperature dependence of the resistance value caused by the temperature T is sufficiently smaller than the temperature dependence of the resistance value caused by the temperature T, then ΔR ｇ <ΔR ｇｉｎｔ (K １ <K ２ ), then the resistance value (R ｇ +R ｇｉｎｔ ) represents the temperature dependence of the internal gate resistance of the power semiconductor device 10. ｇ By selecting a resistor element (for example, resistor element 21) externally attached to the power semiconductor element 10 to provide K １ <K ２ It is possible to achieve the following.

[0065] Therefore, the resistance value (R ｇ +R ｇｉｎｔ ) with pre-recorded calibration data showing the relationship between the resistance value and temperature, the estimated temperature of the power semiconductor element 10 can be calculated. For example, such calibration data can be obtained by placing the power module 101 in a thermostatic chamber, and changing the element temperature of the power semiconductor element 10 from the outside, and then calculating the resistance value (R ｇ +R ｇｉｎｔ ) can be obtained by

[0066] Alternatively, if it is difficult to obtain calibration data, the internal gate resistance R ｇｉｎｔ rate of change (temperature coefficient K ２ ) is acquired in advance as information indicating the relationship between the temperature and the resistance value of the power semiconductor element 10, and the calculated resistance value (R ｇ +R ｇｉｎｔ ) and the previously acquired temperature coefficient K ２ (K ２ >K １) can also be used to calculate the temperature of the power semiconductor element 10.

[0067] The output current of the current source 11 (I ｇ ), and the time difference between times t3 and t4 (the length of the current supply period by the current control unit 1) are maintained constant, the detection voltage Vdet is affected by the resistance value (R ｇ +R ｇｉｎｔ ) is included as a variable. ｇ +R ｇｉｎｔ It is also possible to set information indicating the relationship between the temperature and resistance value of the power semiconductor element 10 in advance so that the estimated temperature can be calculated directly from the detected voltage Vdet or V0 extracted from the detected voltage Vdet without going through the calculation of V (V = V ).

[0068] (Temperature Measurement During Off-Time Period) Next, temperature measurement during off-time will be described. In Fig. 5, when the driver input signal 411 changes from H level to L level at time t5, which corresponds to the timing of the turn-off command, the switch control signal 31 switches from H level to L level at time t6, which is a certain delay time after time t5. As described above, this delay time can be simply set to a time constant determined by the resistance value of the resistive element 21 and the element capacitance of the power semiconductor element 10, or a time longer than that.

[0069] At time t6, when the switch control signal 31 changes from H level to L level, the current control switch 12 of the current control unit 1 (FIG. 1B, etc.) is turned off. As a result, the current from the current source 11 flows to the power semiconductor element 10, not to the reference potential node 90. In other words, the current control unit 1 supplies current between the control terminal G and the negative terminal S, and the current supply period is set during the off period.

[0070] When the current control switch 12 is turned off and current injection from the current source 11 to the power semiconductor element 10 begins, the input voltage Vx of the peak detection circuit 5 changes according to the above-mentioned equation (1), except that time t3 in equation (1) is replaced by time t6.

[0071] As a result, in the current supply period provided after time t6, as in the case after time t3 described above, the input voltage Vx of the peak detection circuit 5 and the detected voltage Vdet of the voltage detection unit 6 are the steadily occurring voltage V0=(R ｇ +R ｇｉｎｔ ) I ｇ and (t-t6)·I, which is the charging voltage of the parasitic capacitance of the power semiconductor element 10. ｇ / C ｄｉｅ and increases as the parasitic capacitance is charged over time from time t6. That is, the behavior of the input voltage Vx and the detection voltage Vdet after time t6 is the same as after time t3.

[0072] As in the case of measurement during the on-period, when the switch control signal 31 changes from L level to H level at time t7, the current control switch 12 in the current control unit 1 is turned on, causing the input voltage Vx of the peak detection circuit 5 to become 0. On the other hand, until time t7x when the switch control signal 31 changes from L level to H level, the discharge switch 53 in the peak detection circuit 5 is kept off, and therefore, from time t7 onwards, the detection voltage Vdet of the voltage detection unit 6 is maintained at the voltage value at time t7.

[0073] Therefore, in the OFF period, as in the ON period, the voltage value V2 of the detection voltage Vdet at times t7 to t7x, the time difference between times t6 and t7 (the length of the current supply period), and the known I corresponding to the output current of the current source 11 are ｇ Using this, the resistance value (R ｇ +R ｇｉｎｔ ) can be calculated.

[0074] As described above, the resistance value R other than the internal gate resistance of the power semiconductor element 10 ｇ The temperature dependence of the internal gate resistance R of the power semiconductor element 10 ｇｉｎｔ By designing the semiconductor device 100 so that the temperature dependence of the resistance (R ｇ +R ｇｉｎｔ) with calibration data showing the relationship between the resistance value and the temperature that has been recorded in advance, the estimated temperature of the power semiconductor element 10 can be calculated. Alternatively, as described above, the internal gate resistance value R ｇｉｎｔ Temperature coefficient K ２ (K ２ >K １ ) and the calculated resistance value (R ｇ +R ｇｉｎｔ ) can also be used to calculate the temperature of the power semiconductor element 10.

[0075] As explained in the on-period, the output current (I ｇ ), and the time difference between times t6 and t7 (the length of the current supply period by the current control unit 1) are maintained constant, the resistance value (R ｇ +R ｇｉｎｔ ), it is also possible to directly calculate the estimated temperature from the detected voltage Vdet or V0 extracted from the detected voltage Vdet.

[0076] In the example of FIG. 5, the timing at which the switch control signal 31 transitions from H level to L level (current supply start timing from the current source 11) and the timing at which the switch control signal 35 transitions from H level to L level (corresponding to voltage detection start timing) are aligned, but it is also possible to provide a certain time difference between the two.

[0077] Furthermore, the lengths of the times t3 to t4x and t6 to t7x required for measuring the temperature during the on and off periods (i.e., the length of the current supply period) are obtained by subtracting the length of the period required for the on / off transition of the current control switch 12 and the length of the period required for the on / off transition of the discharge switch 53 from the length of the on or off period during switching, as shown in FIG. 5, and can be, for example, several μs to several hundred μs.

[0078] [Effects of First Embodiment] As described above, in the power module 101 of the embodiment, the current I from the current source 11 flows through the path between the control terminal G and the negative terminal S during the ON period or OFF period of the power semiconductor element 10. ｇThe temperature of the power semiconductor element 10 can be stably estimated by measuring the peak voltage between the control terminal G or the negative terminal S and the reference potential node 90 when the current is injected. The timing of starting the injection of the current can be determined from the rise and fall timing of the driver voltage, or simply determined as a time constant determined by the gate resistance and the element capacitance, or after a delay time set as a longer time has elapsed.

[0079] Modification of the First Embodiment In the modification of the first embodiment, a modification of the configuration of the peak detection circuit 5 will be described.

[0080] 6 is a circuit diagram illustrating the configuration of peak detection circuit 5 according to a modification of embodiment 1. In this modification of embodiment 1, peak detection circuit 5 in semiconductor device 100 of FIG. 1A has the configuration shown in FIG.

[0081] 6, in a peak detection circuit 5 according to a modification of the first embodiment, the discharge switch 53 in the circuit configuration of FIG. 4 is replaced with a resistive element 54. That is, in the modification of the first embodiment, on / off control of the discharge switch 53 is not necessary, and the configuration of the peak detection circuit 5 is simplified.

[0082] FIG. 7 is a timing chart for explaining a temperature estimation method using a semiconductor device according to a modification of the first embodiment.

[0083] 7, in the modification of the first embodiment, the voltage waveform of capacitor 52 in peak detection circuit 5 changes, and therefore the waveform of detection voltage Vdet of voltage detection unit 6 changes from that of the first embodiment (FIG. 5). The other signal waveforms and voltage waveforms in FIG. 7 are the same as those in FIG. 5, and therefore detailed description thereof will not be repeated.

[0084] 7, the capacitor 52 is discharged via the resistive element 54 from time t4 during the on-period and time t7 during the off-period when the current control switch 12 of the current controller 1 is turned off in response to the switch control signal 31. As a result, the detection voltage Vdet gradually decreases in accordance with the RC time constant determined by the capacitance value of the capacitor 52 and the resistance value of the resistive element 54.

[0085] In the modification of the first embodiment, the resistance value (R ｇ +R ｇｉｎｔ The timing of sampling the voltage value for calculating (t4) or (t7) is fixed so that the elapsed time from time t4 or t7 is constant.

[0086] This eliminates the influence of the discharge of the capacitor 52, and the voltage V0=(R ｇ +R ｇｉｎｔ ) I ｇ The voltage detection unit 6 can obtain the voltage values ​​V1 and V2 in the first embodiment (FIG. 5) by sampling the detection voltage Vdet preferably at the same time as or immediately after time t4 or t7.

[0087] As a result, even in the modified example of embodiment 1 in which the configuration of the peak detection circuit 5 is simplified, the temperature of the power semiconductor element 10 can be stably determined during the on-period or off-period of the power semiconductor element 10, as in embodiment 1.

[0088] The RC time constant in the peak detection circuit 5 must be determined so that the capacitor 52 discharges within a period (e.g., half the switching period) determined from the switching period (length of the period from time t0 to t2 in FIG. 7) of the power semiconductor element 10. For example, it is preferable to design the capacitor 52 and the resistor element 54 so that the discharge of the capacitor 52 is completed within a few μs to several hundred μs.

[0089] In contrast, in the peak detection circuit 5 according to the first embodiment, the detection voltage Vdet is maintained constant after times t4 and t7, and therefore it is expected that the voltage detection unit 6 can be configured more inexpensively than the modified example of the first embodiment by using a simple detector with a slow time response speed.

[0090] Second Embodiment In a second embodiment, a further modification of the configuration of the peak detection circuit 5 will be described.

[0091] Fig. 8 is a circuit diagram illustrating a first example configuration of a peak detection circuit according to embodiment 2. As shown in Fig. 8, the peak detection circuit 5 according to the first example configuration of embodiment 2 further includes an operational amplifier 55 in addition to the configuration shown in Fig. 4. The operational amplifier 55 is connected between the input node Nx and the diode 51 (anode).

[0092] The operational amplifier 55 is connected as a voltage follower and transmits the voltage of the input node Nx to the anode of the diode 51. Therefore, the same input voltage Vx as in the first embodiment is input to the diode 51. Therefore, the detection voltage Vdet by the voltage detection unit 6 is also the same as in the first embodiment, and the temperature of the power semiconductor element 10 can be stably determined during the on-period or off-period of the power semiconductor element 10 using the same method as in the first embodiment.

[0093] In the circuit configuration of FIG. 4, a current from the current control unit 1, that is, a supply current (I ｇ ) flows into the capacitor 52 and is used to charge the capacitor 52. Therefore, when the temperature is estimated from the relationship of the above-mentioned equation (1), there is a risk that the accuracy of the temperature estimation will be reduced due to an error in the current flowing through the peak detection circuit 5.

[0094] 8 , by connecting an input stage with a large impedance to the input node Nx, it is possible to prevent the supply current of the current source 11 from flowing to the peak detection circuit 5. In this way, by using an active element with a large input impedance, such as the operational amplifier 55, in the input stage to increase the input impedance of the peak detection circuit 5, it is possible to cause almost all of the supply current from the current source 11 to flow to the power semiconductor element 10. In other words, the operational amplifier 55 corresponds to one embodiment of an "impedance conversion circuit."

[0095] As a result, in a semiconductor device equipped with a peak detection circuit according to the first configuration example of the second embodiment, the error in the temperature calculated according to the relationship of equation (1) can be reduced, thereby improving the accuracy of estimating the temperature of the power semiconductor element 10.

[0096] Fig. 9 is a circuit diagram illustrating a second configuration example of the peak detection circuit according to embodiment 2. As shown in Fig. 9, the peak detection circuit 5 according to the second configuration example of embodiment 2 further includes a diode 56 having the same characteristics as the diode 51, and an operational amplifier 58, in addition to the configuration shown in Fig. 8 (first configuration example).

[0097] Diode 56 is connected in the feedback path of operational amplifier 55, which is connected as a voltage follower, and generates a voltage drop equivalent to that of diode 51. A negative bias voltage (V-) for stably conducting diode 56 may be supplied to the cathode of diode 56 via a resistive element. Diode 56 corresponds to one example of a "second diode."

[0098] With this configuration, it is possible to eliminate the effect of the voltage drop due to the diode 51 and suppress the difference between the voltage at the node Ny and the output voltage of the operational amplifier 55 (i.e., the voltage at the input node Nx). This suppresses the difference between the detected voltage Vdet by the voltage detection unit 6 and the input voltage Vx of the peak detection circuit 5, thereby further improving the accuracy of estimating the temperature of the power semiconductor element 10.

[0099] The operational amplifier 58 is connected between the node Ny and the voltage detection unit 6. The operational amplifier 58 is connected as a voltage follower, and outputs a voltage equivalent to the voltage of the node Ny to the voltage detection unit 6 as the detection voltage Vdet. The arrangement of the operational amplifier 58 reduces the output impedance of the peak detection circuit 5. As a result, it is expected that the voltage detection accuracy of the voltage detection unit 6 will be improved. Furthermore, since it is possible to prevent the potential of the node Ny from changing due to the influence of the voltage detection unit 6, the detection accuracy of the detection voltage Vdet can also be improved from this point of view.

[0100] 8, the operational amplifier 58 can also be added between the node Ny and the voltage detection unit 6. The operational amplifier 58 also corresponds to one example of the "impedance conversion circuit."

[0101] In this way, by using the peak detection circuit according to the second embodiment, the voltage change caused by the temperature change of the power semiconductor element 10 is more clearly and directly reflected in the detected voltage Vdet, thereby further improving the accuracy of estimating the temperature of the power semiconductor element 10. In the configuration examples of Figures 8 and 9, it is also possible to replace the discharge switch 53 with a resistance element 54, as in Figure 6 (variation of the first embodiment).

[0102] Embodiment 3. In embodiment 3, a modified example of the on / off control of the current control switch 12 of the current control unit 1 will be described. In embodiment 1, an example was described in which the current control switch 12 has one off period during each of the on period and the off period, which are periods in which the gate voltage of the power semiconductor element 10 is stable other than the rise and fall periods. However, in embodiment 3, the current control switch 12 has multiple off periods.

[0103] 10 is a timing chart for explaining a temperature estimation method using a semiconductor device according to embodiment 3. In Fig. 10, during an off period of a power semiconductor element 10, an off period of the current control switch 12, i.e., a period during which current is supplied from the current source 11, is provided multiple times.

[0104] 10, temperature measurement is performed during the off period after time t5 when the power semiconductor element 10 is turned off. Specifically, as in FIG. 5, from time t6 to time t7, which is a certain delay period after time t5 corresponding to the turn-off command timing, the switch control signal 31 is set to the L level, providing a current supply period from the current control unit 1. As described in the first embodiment, during this period, current is supplied from the current source 11 to the power semiconductor element 10 via the gate wiring unit 2, and the input voltage Vx of the peak detection circuit 5 increases in accordance with the above-described equation (1).

[0105] At time t7, the switch control signal 31 changes from L level to H level. During the H level period of the switch control signal 31, the current control switch 12 in the current control unit 1 is turned on, so that both ends of the current source 11 have the same potential, and therefore the input voltage Vx=0.

[0106] After time t7, there is again a period from time t8 to time t9 during which the switch control signal 31 is at L level. After the switch control signal 31 changes from L level to H level at time t9, there is again a period from time t10 to time t11 during which the switch control signal 31 is at L level.

[0107] During the L level periods of the switch control signal 31 from time t8 to t9 and from time t10 to t11, the input voltage Vx of the peak detection circuit 5 rises according to the above equation (1), similar to the period from time t6 to t7.

[0108] 10, during the OFF period, there are multiple periods during which the switch control signal 31 is at L level, i.e., periods during which current is supplied from the current control unit 1 due to the current control switch 12 being turned off, from time t6 to t7, from time t8 to t9, from time t10 to t11, ..., from time tk-1 to tk. The duration of each L level period of the switch control signal 31 is set to be the same. Therefore, the behavior (waveform) of the input voltage Vx is the same during each L level period of the switch control signal 31. Therefore, the input voltage Vx at the end of each L level period of the switch control signal 31 is at the same voltage value V2.

[0109] 5, when the diode 51 becomes non-conductive while the discharge switch 53 is off, the voltage at the node Ny actually gradually decreases due to leakage current from the discharge switch 53, etc. Fig. 10 also emphasizes the slight decrease in the detection voltage Vdet due to this effect. For example, after time t7, Vx = 0, and the diode 51 becomes non-conductive, and the detection voltage Vdet gradually decreases from V2.

[0110] Between times t8 and t9, a period in which the switch control signal 31 is at L level is provided, causing the input voltage Vx to rise in the same manner as between times t6 and t7. As a result, around time t7, when the input voltage Vx again becomes higher than the voltage at node Ny (detection voltage Vdet), the diode 51 becomes conductive, allowing the detection voltage Vdet to return to V2.

[0111] As described above, according to the third embodiment, by turning the current control switch 12 on and off multiple times and repeating the current supply period multiple times, it is possible to cancel out the attenuation of the output voltage of the peak detection circuit 5, i.e., the detected voltage Vdet of the voltage detection unit 6. As a result, a simple detector with a slow time response speed can be used for the voltage detection unit 6. Note that this on / off operation of the current control switch 12 can be repeated throughout the period in which the gate voltage of the power semiconductor element 10 is stable other than the rise and fall periods, i.e., throughout the entire off period and on period.

[0112] In addition, in order to simplify the notation, FIG. 10 shows an example in which there is no off period of the current control switch 12 (period of current supply from the current control unit 1) during the on period, and temperature measurement is not performed. However, when temperature measurement is performed during both the on period and the off period, it is possible to provide multiple off periods of the current control switch 12 (period of current supply from the current source 11) during at least one of the temperature measurements.

[0113] Furthermore, in the third embodiment, the response delay of the peak detection circuit 5 can be alleviated by repeatedly turning on and off the current control switch 12 multiple times. In particular, in the peak detection circuit 5 shown in FIG. 6 , the response speed is determined by the RC time constant defined by the capacitor 52 and the resistor element 54, and when the number of pulses of the input voltage Vx is small, there is a risk that the peak value of the input voltage Vx will be higher than the output voltage (detection voltage Vdet) of the peak detection circuit 5. In contrast, by repeatedly turning on and off the current control switch 12 multiple times as in the third embodiment, it is possible to provide a plurality of pulse waveforms as the input voltage Vx, and therefore the peak detection circuit 5 can accurately reflect the peak value of the input voltage Vx in the detection voltage Vdet.

[0114] Note that the length of the off period of the current control switch 12 may not be exactly the same due to the influence of jitter in the controller, etc. If the length of the off period varies, the peak value of the input voltage Vx will include factors of variation other than the temperature of the power semiconductor element 10, which may result in a decrease in the accuracy of the temperature estimation. Even in such a case, as in the third embodiment, by providing an off period of the current control switch 12, i.e., a measurement period of the input voltage Vx, within one off period or on period, it is possible to average out the influence of errors due to jitter. This makes it possible to avoid a decrease in the accuracy of the temperature estimation.

[0115] Fourth Embodiment In a fourth embodiment, an example will be described in which the steady-state thermal resistance or transient thermal resistance of the power semiconductor element 10 is calculated using the estimated temperature calculation value of the power semiconductor element 10 calculated in accordance with the first to third embodiments.

[0116] When calculating the steady-state thermal resistance, the power semiconductor element 10 needs to be in a thermally steady state (thermal equilibrium state). This steady state can be achieved by, for example, passing a constant DC current through the power semiconductor element 10 to generate a constant power loss, as in a power cycle test, which is one of the general reliability tests for power semiconductor elements.

[0117] Alternatively, a pseudo-thermal equilibrium state can be created by continuously switching the power semiconductor elements 10 and controlling the current flowing through the power semiconductor elements 10 to a constant amount. For example, in a configuration in which four power semiconductor elements are used to control the direction of current conduction, such as a full-bridge circuit, or in a configuration in which an inductive load or a resistive load is connected to a half-bridge circuit using two power semiconductor elements, the current of each power semiconductor element can be controlled to a constant amount to create a pseudo-thermal equilibrium state.

[0118] Fig. 11 is a configuration diagram showing an example of a power module according to embodiment 4. As shown in Fig. 11, a power module 103 according to embodiment 4 further includes, in addition to the configuration of the power module 101 or 102 (Figs. 1A and 3) according to embodiment 1, a main current detector 81 for measuring a main current Imt and a main voltage detector 82 for detecting a main voltage (drain-source voltage) Vmt of the power semiconductor element 10. The main current Imt measured by the main current detector 81 and the main voltage Vmt detected by the main voltage detector 82 are input to the main control unit 41. This enables the main control unit 41 to calculate the power loss occurring in the power semiconductor element 10 from the product of the main voltage Vmt and the main current Imt.

[0119] 12 is a timing chart for explaining a method for estimating the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment. The control process shown in FIG. 12 can be executed by the main control unit 41, for example.

[0120] Referring to FIG. 12, the power semiconductor element 10 is switched multiple times until time t5 so as to form the above-described thermal equilibrium state, and then is maintained in the off state after time t5.

[0121] During the off period of the power semiconductor element 10, Vmt is generated, while Imt = 0. Conversely, during the on period of the power semiconductor element 10, Imt is generated, and a finite resistance (on-resistance) occurs in the power semiconductor element 10. Therefore, during the on period, a power loss (conduction loss) of Pls = Vmt · Imt occurs due to the on-resistance. Furthermore, during turn-on and turn-off, there is a period in which Vmt · Imt is not zero, and during this period, a power loss (switching loss) of Pls = Vmt · Imt occurs. These power losses Pls cause the temperature Tj of the power semiconductor element 10 to rise.

[0122] During the period from time t5 onwards, no current flows through the power semiconductor element 10, and therefore the temperature Tj of the power semiconductor element 10 gradually decreases depending on the thermal impedance between the power semiconductor element 10 and a cooler (not shown) and the cooling capacity of the cooler.

[0123] The time constant of the temperature change at this time can be simply estimated from the thermal resistance and heat capacity of the heat dissipation path of the power semiconductor element 10. Generally, the time constant in the vicinity of the power semiconductor element 10 is about several tens (μs) to several hundreds (μs). Generally, this value is close to the switching cycle of the power semiconductor element 10 or is slightly longer than the switching cycle. In the first to third embodiments described so far, it was assumed that the temperature of the power semiconductor element 10 during on / off operation was estimated, so that the temperature change of the power semiconductor element 10 during temperature measurement could be almost ignored.

[0124] In contrast, in the fourth embodiment, the temperature change of the power semiconductor element 10 that has been maintained in the off state for a long period of time is measured using the method described in the third embodiment, thereby measuring the thermal resistance and thermal impedance of the power semiconductor element 10.

[0125] 10, the current control switch 12 is repeatedly turned on and off so that a predetermined fixed length of L level period (i.e., current supply period) is provided multiple times in the switch control signal 31. As described in the first to third embodiments, during each off period of the current control switch 12, the current control unit 1 (current source 11) supplies current to generate the input voltage Vx that reflects the temperature Tj at that time.

[0126] Therefore, by obtaining the peak value of the input voltage Vx from the detection voltage Vdet during each current supply period in which the current control switch 12 is turned off, it is possible to calculate the estimated temperature (estimated value of Tj) of the power semiconductor element 10 at each timing. In the example of Fig. 12, N temperature measurements are performed from the first L level period from time t6 to t7 to the Nth L level period (N: an integer of 2 or more) from time tn-1 to tn.

[0127] Since the power semiconductor element 10 is maintained in the off state after time t5, it is gradually cooled. Therefore, the peak value of the input voltage Vx and the detection voltage Vdet gradually decrease due to the temperature element of the power semiconductor element 10. In order to calculate the decrease in temperature Tj from the decrease in detection voltage Vdet, the peak detection circuit 5 needs to have a response speed that can reflect the decrease in the peak value of the input voltage Vx due to the decrease in temperature of the power semiconductor element 10 in the detection voltage Vdet. Therefore, it is preferable that the response time constant of the peak detection circuit 5 is shorter than the thermal time constant of the power semiconductor element 10.

[0128] 13 is a flowchart illustrating a process for calculating the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment. The series of processes shown in FIG.

[0129] The main control unit 41 executes the processes of steps (hereinafter simply referred to as "S") 110 to S150 while the power semiconductor device 10 is in the above-described thermal equilibrium state. In FIG. 12, the processes of S110 to S150 are executed before time t5.

[0130] In S110, the main control unit 41 acquires the main voltage Vmt (instantaneous value) of the power semiconductor element 10 measured by the main voltage detection unit 82, and in S120, acquires the main current Imt (instantaneous value) of the power semiconductor element 10 measured by the main current detection unit 81. Since the main voltage Vmt acquired in S110 and the main current Imt acquired in S120 are values ​​measured at the same timing, in S130 the main control unit 41 calculates the power loss Pls (instantaneous value) generated in the power semiconductor element 10 from the product of the main voltage Vmt and the main current Imt.

[0131] The main control unit 41 determines NO in S140 until the timing for calculating the thermal resistance arrives. When the main control unit 41 determines NO in S140, the main control unit 41 executes processing in S150 to calculate the power loss Plsc for each switching cycle of the power semiconductor element 10. Specifically, the power loss Plsc for each switching cycle is calculated by integrating the power loss Pls calculated in S130 within each switching cycle. In S150, the integrated value is cleared in response to the end or start of each switching cycle.

[0132] 12, a YES determination is made in S140 at time t5. The processes of S110 to S150 are repeatedly executed until a YES determination is made in S140. Note that in S150, a moving average value of the power loss Plsc for the most recent X cycles (X: a predetermined integer of 2 or more) may also be calculated.

[0133] When S140 is determined as YES, the main control unit 41 proceeds to S160 to start calculating the thermal resistance. In S160, the main control unit 41 determines the power P (W) to be used in calculating the thermal resistance Rth. For example, the power P can be the power loss Plsc in the immediately preceding switching cycle calculated in S150 at the time S140 is determined as YES, or the latest moving average value of the power loss Plsc.

[0134] 12, the main control unit 41 calculates the estimated temperature (estimated value of Tj) of the power semiconductor element 10 from the detected voltage Vdet obtained as the peak value of the input voltage Vx for each L level period (equal length) of the switch control signal 31. Here, it is assumed that a total of N temperature measurements are performed, as described in FIG.

[0135] In S170, the main control unit 41 performs the i-th (i: natural number from 1 to N) temperature measurement and calculates the estimated temperature T(i) from the detected voltage Vdet at that time. In FIG. 12, when i=1, the estimated temperature T(1) of the power semiconductor element 10 from time t6 to t7 is calculated.

[0136] When i≧2, S180 calculates the thermal resistance Rth=ΔT / P using the temperature change ΔT(i)=T(i)−T(1) and the power P determined in S160. In S180, the thermal resistance Rth(i) is calculated for the i-th temperature measurement (i≧2).

[0137] The main control unit 41 determines in S190 whether the number of measurements i has reached a predetermined termination condition (N). Until the measurement termination condition is reached (NO in S190), the thermal resistance Rth(i) calculated in S180 is stored in S195. Therefore, by the time the number of measurements i reaches n and the measurement termination condition is met (YES in S190), (N-1) thermal resistances Rth(2) to Rth(N) have been obtained. Note that the measurement termination condition in S190 may be determined not only by the number of measurements but also by the length of time elapsed since S140 returned a YES determination.

[0138] When the measurement termination condition is met (YES in S190), the main control unit 41 can calculate the thermal impedance Zth of the power semiconductor element 10 including the cooling system by using the thermal resistances (here, Rth(2) to Rth(N)) that have been calculated so far in response to the change over time in the temperature Tj of the power semiconductor element 10. In this way, one embodiment of a "thermal resistance calculation unit" can be configured by the main control unit 41 executing the control process shown in FIG.

[0139] In order to calculate the thermal impedance, it is necessary to determine the measurement termination condition in S190 so as to ensure sufficient cooling time for the power semiconductor element 10. The required cooling time depends on the thermal time constant of the cooling system of the power semiconductor element 10, but is generally on the order of several seconds to several hundred seconds. Although it is difficult to incorporate a cooling time of this order into the normal operation mode of a typical power electronics device, for example, in an inverter system, by utilizing current control that can maintain the power semiconductor element in an off state for a certain period of time or by utilizing the timing of system operation shutdown, it is possible to maintain the power semiconductor element 10 in an off state for a relatively long period of time and perform the calculation process of the thermal impedance shown in FIG. 13 .

[0140] In this way, according to the fourth embodiment, it is possible to calculate the thermal resistance Rth of the power semiconductor element 10 using the temperature estimation method for the power semiconductor element 10 described in the first to third embodiments. Furthermore, if an off period (cooling period) of the power semiconductor element 10 for temperature measurement can be secured, it is possible to calculate the thermal impedance Zth of the power semiconductor element 10 including the cooling system.

[0141] Fifth Embodiment In a fifth embodiment, the power modules 101 to 103 according to the first to fourth embodiments are applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the following will describe a case in which the present disclosure is applied to a three-phase inverter as the fifth embodiment.

[0142] FIG. 14 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0143] The power conversion system shown in Fig. 14 includes a power supply 120, a power conversion device 110, and a load 130. The power supply 120 is a DC power supply and supplies DC power to the power conversion device 110. The power supply 120 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery, or it may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 120 may also be configured from a DC / DC converter that converts DC power output from a DC system into a set power.

[0144] The power conversion device 110 is a three-phase inverter connected between a power source 120 and a load 130, and converts DC power supplied from the power source 120 into AC power and supplies the AC power to the load 130. As shown in Fig. 14 , the power conversion device 110 includes a main conversion circuit 111 that converts DC power into AC power and outputs it, and a control circuit 112 that outputs a control signal to the main conversion circuit 111 to control the main conversion circuit 111.

[0145] The load 130 is a three-phase electric motor driven by AC power supplied from the power conversion device 110. The load 130 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0146] The power conversion device 110 will be described in detail below. The main conversion circuit 111 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power source 120 into AC power, which is supplied to the load 130. The main conversion circuit 111 can have a variety of specific circuit configurations. In this embodiment, the main conversion circuit 111 is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements of the main conversion circuit 111 is the power semiconductor element 10 included in the power module 101 of any of the first to fourth embodiments described above. Two of the six switching elements are connected in series to form upper and lower arms, which constitute a respective phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 111, are connected to the load 130.

[0147] As described in the first to fourth embodiments, the power modules 101 to 103 each include a semiconductor device 100 (not shown) for driving each switching element, and the main conversion circuit 111 is therefore equipped with the semiconductor device 100. The semiconductor device 100 generates drive signals for driving the switching elements of the main conversion circuit 111 and supplies them to the control electrodes of the switching elements of the main conversion circuit 111. Specifically, in accordance with control signals from a control circuit 112 (described later), the semiconductor device 100 outputs to the control electrodes of each switching element a drive signal for turning the switching element on and a drive signal for turning the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0148] The control circuit 112 controls the switching elements of the main conversion circuit 111 so that the desired power is supplied to the load 130. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 111 should be in the on state based on the power to be supplied to the load 130. For example, the main conversion circuit 111 can be controlled by PWM (Pulse Width Modulation) control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 112 then outputs a control command (control signal) to the semiconductor device 100 included in the main conversion circuit 111 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the semiconductor device 100 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0149] In the power conversion device according to this embodiment, the power modules 101 to 103 according to the first to fourth embodiments are applied as the power module 101 constituting the main conversion circuit 111, and therefore the reliability of the power conversion device can be improved based on the temperature measurement results of the power semiconductor elements.

[0150] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when supplying power to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0151] Furthermore, the power conversion device to which the present disclosure is applied is not limited to the case where the load is an electric motor, but can also be used as a power supply device for, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system. Furthermore, the power conversion device to which the present disclosure is applied can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0152] Regarding the multiple embodiments described above, we would like to confirm that it was intended from the beginning of the application to appropriately combine the configurations described in each embodiment, including combinations not mentioned in the specification, within the scope that does not result in inconsistencies or contradictions.

[0153] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0154] 1 Current control section, 2 Gate wiring section, 3 Timing control section, 4 Gate drive section, 5 Peak detection circuit, 6 Voltage detection section, 7 Temperature estimation section, 10 Power semiconductor element, 11 Current source, 12 Current control switch, 20 Pulse current source, 21, 54 Resistance element, 31, 35 Switch control signal, 32 Control information, 41 Main control section, 42 Driver circuit, 51, 56 Diode, 52 Capacitor, 53 Discharge switch, 55, 58 Operational amplifier, 71 Temperature information, 81 Main current detection section, 82 Main voltage detection section, 90 Reference potential node, 100 Semiconductor device, 101 to 103 Power module, 110 Power conversion device, 111 Main conversion circuit, 112 Control circuit, 120 Power supply, 130 Load, 411 Driver input signal, 412 Command, D Positive terminal, G Control terminal, Imt Main current (power semiconductor element), Ns, Nx, Ny nodes, S negative terminal, Vdet detection voltage, Vgs gate voltage, Vmt main voltage (power semiconductor element), Vx input voltage (peak detection circuit).

Claims

1. A semiconductor device that drives and controls a semiconductor element, the semiconductor element has a positive terminal, a negative terminal, and a control terminal to which a drive voltage is applied to control a main current flowing between the positive terminal and the negative terminal; The semiconductor device includes: a driver circuit that transitions the semiconductor element between an on state and an off state by supplying the drive voltage to the control terminal; a current control unit for supplying a pulsed current between the control terminal and the negative terminal; a timing control unit that controls a timing at which the current control unit supplies the current; a peak detection circuit for outputting a peak value of an input voltage, which is a potential difference of the control terminal or the negative terminal with respect to a reference potential, during a current supply period by the current control unit; a voltage detection unit that samples the output voltage of the peak detection circuit; a temperature estimator that calculates an estimated temperature of the semiconductor element based on the voltage detected by the voltage detector; The timing control unit operates the current control unit to provide the current supply period during at least one of an on period after the semiconductor element transitions to the on state and an off period after the semiconductor element transitions to the off state.

2. The peak detection circuit includes: a first diode having an anode connected to a first node electrically connected to the control terminal or the negative terminal; a capacitor connected between a second node connected to the cathode of the first diode and a node that supplies the reference potential; 2. The semiconductor device according to claim 1, further comprising a discharge switch element or a discharge resistor for discharging said capacitor.

3. The peak detection circuit includes:

3. The semiconductor device according to claim 2, further comprising an impedance conversion circuit disposed at least one of between said first node and said anode of said first diode and between said second node and said voltage detection portion.

4. The peak detection circuit includes: the impedance conversion circuit includes an operational amplifier connected in a voltage follower manner between the first node and the anode of the first diode, 4. The semiconductor device according to claim 3, further comprising a second diode connected in a feedback path of said voltage follower connection, said second diode causing a voltage drop equivalent to that of said first diode.

5. 5. The semiconductor device according to claim 1, wherein the timing control section provides the current supply period a plurality of times during at least one of the on-period and the off-period.

6. the timing control unit repeats the current supply period a plurality of times during a thermal resistance measurement period during which the semiconductor element is maintained in an off state; The semiconductor device includes: a main current detection unit that detects the main current of the semiconductor element; a main voltage detection unit that detects a main voltage between the positive terminal and the negative terminal of the semiconductor element; The semiconductor device according to any one of claims 1 to 4, further comprising a thermal resistance calculation unit that calculates a power loss for each switching period that occurs in the semiconductor element before the thermal resistance measurement period, and calculates a thermal resistance of the semiconductor element based on the calculated power loss and an amount of change in the estimated temperature calculated for each of the multiple current supply periods.

7. 5. The semiconductor device according to claim 1, wherein the current control unit is disposed at a position that supplies the current from the negative terminal side of the semiconductor element.

8. 5. The semiconductor device according to claim 1, wherein the current control section is disposed at a position that supplies the current from the control terminal side of the semiconductor element.

9. The pulsed current has a predetermined amplitude; the current supply period is set to have a predetermined time length, The semiconductor device according to any one of claims 1 to 4, wherein the temperature estimation unit calculates the estimated temperature using a resistance value calculated from the detected voltage and the amplitude of the current during the current supply period and information indicating a relationship between a predetermined temperature of the semiconductor element and the resistance value.

10. A main conversion circuit having the semiconductor device according to any one of claims 1 to 4 and a semiconductor element driven and controlled by the semiconductor device, converting input power and outputting the power; a control circuit that outputs a control signal to the main conversion circuit to control power conversion by the main conversion circuit.