Filter device, multilayer substrate, and communication apparatus

Abstract

This filter device has a multilayer substrate, a chip mounted on the multilayer substrate, a first filter of which at least a portion is included in the chip, and a first hybrid coupler connected to the first filter. A portion of the first hybrid coupler is included in the multilayer substrate and another portion of the first hybrid coupler is included in the chip.

Description

Filter device, multilayer substrate and communication device

[0001] The present disclosure relates to a filter device having a filter and a hybrid coupler, a multilayer substrate usable for the filter device, and a communication device including the filter device.

[0002] Filter devices that combine a filter and a hybrid coupler are known (e.g., Patent Documents 1 and 2). Hybrid couplers that use lumped elements are also known (e.g., Patent Documents 3 to 5). Patent Documents 3 to 5 list inductors, capacitors, and resonators as lumped elements that make up a hybrid coupler. A hybrid coupler performs its intended function (distribution, phase adjustment, and / or synthesis of an input signal) at a predetermined operating frequency. Patent Documents 3 to 5 show the relationship between the operating frequency and the inductance and / or capacitance values ​​of the lumped elements in various embodiments of hybrid couplers. The contents of Patent Documents 1 to 5 may be incorporated by reference.

[0003] International Publication No. 2022 / 054896 Japanese Patent Application Laid-Open No. 2022-041537 Japanese Patent Application Laid-Open No. 8-335841 Japanese Patent Application Laid-Open No. 2006-186960 International Publication No. 2019 / 163061

[0004] A filter device according to one aspect of the present disclosure includes a multilayer substrate, a chip mounted on the multilayer substrate, a first filter having at least a portion included in the chip, and a first hybrid coupler having a portion included in the multilayer substrate and another portion included in the chip, the first filter being connected to the first filter.

[0005] A multilayer substrate according to one aspect of the present disclosure includes a first surface, a pad located on the first surface and capable of mounting a chip, and a first circuit constituting a first hybrid coupler. The first circuit includes four inductors connected in series to form an electrical loop, and four ports electrically located between the four inductors. A first port of the four ports is connected to the pad. When the chip is not mounted on the pad, the first port is not connected to a reference potential section.

[0006] A communication device according to one aspect of the present disclosure includes the above-described filter device, an antenna connected to the filter device, and an integrated circuit element connected to the antenna via the filter device.

[0007] Fig. 2 is a perspective view showing the configuration of a filter device according to an embodiment. Fig. 3 is a schematic perspective view showing a portion of the internal configuration of a multilayer substrate of the filter device of Fig. 1. Fig. 4 is a circuit diagram showing the configuration of a portion of the filter device of Fig. 1. Fig. 5 is a schematic plan view showing the configuration of an acoustic wave element included in the filter device of Fig. 1. Fig. 6 is a schematic plan view showing the configuration of a chip included in the filter device of Fig. 1. Fig. 7 is a circuit diagram showing the configuration of the filter device of Fig. 1. Fig. 8 is a block diagram showing the configuration of a communication device according to an embodiment.

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings used in the following description are schematic. Therefore, for example, the dimensional ratios in the drawings do not necessarily correspond to the actual ones. Furthermore, the dimensional ratios may not match between drawings. Certain shapes and / or dimensions may be exaggerated, and details may be omitted. However, the above does not deny that the actual shapes and / or dimensions may be as shown in the drawings, or that features of shapes and / or dimensions may be extracted from the drawings.

[0009] In the present disclosure, when the phase of a signal is "shifted," the phase may be advanced or delayed. However, for convenience, when referring to the above, unless a contradiction arises, "shift" or the like will mean only one of the two terms commonly used for various components and various signals. For example, when it is said that the phase of a second signal is shifted by 90° relative to the phase of a first signal, and the phase of a fourth signal is shifted by 90° relative to the phase of a third signal, the former and latter shifts are both shifts in phase that are advanced by 90°, or both shifts in phase that are delayed by 90°.

[0010] 1 is a perspective view showing an example of the configuration of a filter device 1 according to an embodiment. Note that, although any direction of the filter device 1 may be used as the upper side, in the following description, for convenience, the upper side along the plane of the paper in FIG. 1 (the side on which the chip 5 is located relative to the multilayer substrate 3) may be referred to as the upper side.

[0011] The filter device 1 includes a multilayer substrate 3 and one or more chips 5 (two in the illustrated example) mounted on the multilayer substrate 3. The multilayer substrate 3 has a plurality of external terminals 7. The filter device 1 filters a signal input from one of the plurality of external terminals 7, for example, and outputs the filtered signal from another of the plurality of external terminals 7.

[0012] FIG. 3 is a circuit diagram showing an example of the configuration of a portion of the filter device 1. As shown in FIG.

[0013] As described above, the filter device 1 includes the multilayer substrate 3 and the chip 5. From another perspective, the filter device 1 also includes the first filter 9 and the hybrid 11 connected to the first filter 9.

[0014] The first filter 9 directly contributes to the filtering function of the filter device 1. More specifically, the first filter 9 is a band-pass filter that attenuates input signals having frequencies outside a predetermined passband, thereby outputting signals having frequencies within the passband. The hybrid 11 also contributes to reducing nonlinear distortion occurring in the first filter 9, as will be described in detail later.

[0015] The hybrid 11 is, for example, a lumped-element 90° hybrid coupler. The hybrid 11 includes, for example, four series elements 15 (L1 to L4) connected in series to form a loop 13, and four parallel elements 17 (C1 to C4) connected to the portions between the four series elements 15 (four ports 19A to 19D). The four parallel elements 17 are grounded (connected to a reference potential). In the illustrated example, the four series elements 15 are inductors L1 to L4, and the four parallel elements 17 are four capacitors C1 to C4. In the following description, the inductors L1 to L4 may be referred to simply as "inductor L" without distinction. The capacitors C1 to C4 may be referred to simply as "capacitor C" without distinction. The ports 19A to 19D may be referred to simply as "ports 19" without distinction.

[0016] The first filter 9 is composed of one or more chips 5. In other words, the first filter 9 is included in one or more chips 5. The hybrid 11 is partially composed of the multilayer substrate 3 (included in the multilayer substrate 3), and partially composed of one or more chips 5 (included in one or more chips 5). In the example shown in the figure, the loop 13 (series element 15) is included in the multilayer substrate 3, and the parallel element 17 (more specifically, the capacitor C2) is included in the chip 5.

[0017] This configuration provides the following advantages, for example.

[0018] The hybrid 11 does not function as intended for signals in any frequency band, but rather functions as intended for signals in a specific operating frequency (or a frequency band including that operating frequency; hereinafter, the same applies unless otherwise specified). The operating frequency of the hybrid 11 is determined by the capacitance and inductance of the series element 15 and the parallel element 17.

[0019] The hybrid 11 is also connected to the first filter 9, and is expected to perform an intended function for signals passing through the first filter 9. Therefore, the operating frequency of the hybrid 11 is set according to the pass band of the first filter 9 connected to the hybrid 11.

[0020] From the above, if the entire hybrid 11 were provided on the multilayer substrate 3, the multilayer substrate 3 would have to have different configurations for the first filters 9 (or, from another perspective, the chips 5) having different passbands. In other words, the filter devices 1 having different passbands would have different multilayer substrates 3.

[0021] On the other hand, in the filter device 1 according to the embodiment, a portion of the hybrid 11 is provided on the chip 5. Then, by adjusting the inductance and / or capacitance of the portion (capacitance in the illustrated example), the operating frequency of the hybrid 11 can be made to correspond to the pass band of the first filter 9. Therefore, the configuration of the multilayer substrate 3 can be made common for first filters 9 (chips 5) having mutually different pass bands. As a result, the productivity of the multilayer substrate 3 (or, from another perspective, the filter device 1) is improved.

[0022] The above are the main points of the filter device 1 according to the embodiment. The filter device 1 will be roughly described below in the following order: 1. Overview of the filter device 1 ( FIG. 1 ) 2. Multilayer substrate 3 (excluding hybrid 11) 3. Basic features of the hybrid 11 ( FIG. 3 ) 3.1. Operation of the hybrid 11 3.2. Circuit configuration of the hybrid 11 4. First filter 9 4.1. Overview of the first filter 9 4.2. Example of an acoustic wave resonator ( FIG. 4 ) 4.3. Ladder-type filter ( FIG. 5 ) 5. Chip 5 6. Portion of the hybrid 11 located on the multilayer substrate 3 ( FIG. 2 ) 7. Portion of the hybrid 11 located on the chip 5 ( FIGS. 3 and 5 ) 8. Example of the overall circuit configuration of the filter device 1 ( FIG. 6 ) 8.1. Basic features of the circuit configuration 8.2. Distribution of the filter device 1 to the multilayer substrate 3 and chip 5 9. Communication device including the filter device 1 ( FIG. 7 ) 10. Summary of the embodiment

[0023] (1. Overview of the Filter Device) The filter device 1 shown in FIG. 1 is configured, for example, as a surface-mounted chip-type electronic component. For example, the filter device 1 has layered conductors located on its underside as the aforementioned multiple external terminals 7. The multiple external terminals 7 face pads located on the upper surface of a circuit board (not shown) and are bonded to the pads by a conductive bonding material interposed therebetween. From another perspective, the conductive bonding material is a bump, and the material is, for example, solder (the same applies below). The number, position, shape, dimensions, etc. of the multiple external terminals 7 may be set appropriately depending on the function, etc. of the filter device 1.

[0024] As described above, the filter device 1 includes a multilayer substrate 3 and one or more chips 5. The number, position, shape, and dimensions of the chips 5 may be set as appropriate depending on the functions required of the filter device 1. The filter device 1 may include components other than those shown in the drawings. Examples of such components include a sealant or cover that covers the upper surface of the multilayer substrate 3 from above the chips 5. The filter device 1 as a chip-type electronic component may have any general shape and dimensions. For example, the filter device 1 as a whole is generally thin and rectangular.

[0025] As long as the filter device 1 includes the multilayer substrate 3 and the chip 5, it may have various structures other than those shown in the example (however, for convenience, the illustrated configuration may be assumed in the description of the embodiments). The filter device 1 may be configured as a chip-type electronic component that has only the function of a filter, or may be inseparably combined with an element that has a function other than that of a filter.

[0026] For example, the filter device 1 does not have to be a chip-type electronic component. More specifically, for example, although not particularly shown, in a module having a generally board-like shape including a circuit board, an IC (integrated circuit) mounted on or built-in the circuit board, an antenna mounted on or built-in the circuit board, and the filter device 1, the multilayer substrate 3 may be the circuit board.

[0027] Furthermore, for example, the filter device 1 may have a container-like package that houses the multilayer substrate 3 and the chip 5. An external terminal provided on the package may be electrically connected to a terminal (external terminal 7) of the multilayer substrate 3.

[0028] Furthermore, for example, the filter device 1 as a chip-type electronic component having external terminals 7 on the multilayer substrate 3 is not limited to having layer-shaped external terminals 7 on the bottom surface. For example, the layer-shaped external terminals 7 located on the top surface may be connected to a circuit board (not shown) by bonding wires. Also, for example, pin-shaped external terminals 7 may be bonded to the multilayer substrate 3.

[0029] (2. Multilayer Substrate) The basic structure and materials (configuration excluding the specific conductor patterns and dimensions for configuring the filter device 1) of the multilayer substrate 3 (circuit board) may be similar to the structures and materials of various known printed circuit boards. For example, the multilayer substrate 3 may be a low temperature co-fired ceramic (LTCC) substrate, a high temperature co-fired ceramic (HTCC) substrate, an integrated passive device (IPD) substrate, or an organic substrate.

[0030] An example of an LTCC substrate is one made by adding a glass-based material to alumina, which allows firing at low temperatures (for example, around 900°C). In an LTCC substrate, for example, Cu or Ag may be used as the conductive material. An example of an HTCC substrate is one made by using ceramics mainly composed of alumina or aluminum nitride. In an HTCC substrate, for example, tungsten or molybdenum may be used as the conductive material. An example of an IPD substrate is one made by forming passive elements on a Si substrate. An example of an organic substrate is one made by laminating a prepreg impregnated with resin onto a base material made of glass or the like.

[0031] The multilayer substrate 3 has an insulating base 21 and conductors 23 located inside and / or on the surface of the base 21. As can be understood from the explanation in the previous paragraph, the materials of the base 21 and the conductors 23 are arbitrary. The base 21 may have, for example, a plurality of insulating layers 21a stacked on top of each other. The shape and dimensions of the base 21 are arbitrary. In the illustrated example, the base 21 is a thin rectangular parallelepiped. The conductors 23 may have, for example, a conductor layer (reference numeral omitted) located on the upper or lower surface (main surface) of the insulating layer 21a and via conductors (see FIG. 2; reference numeral omitted) penetrating the insulating layer 21a. The number, position, shape, dimensions, etc. of the conductor layers and via conductors may be set appropriately depending on the functions, etc. required of the multilayer substrate 3.

[0032] 1 illustrates, as examples of conductors 23 (conductor layers), the aforementioned plurality of external terminals 7 and a plurality of pads 25 for mounting the chip 5 on the multilayer substrate 3. As will be understood from the example of the overall circuit configuration of the filter device 1 (FIG. 6) described below, each external terminal 7 and each pad 25 are connected, for example, via wiring and / or elements (not shown in FIG. 1) that the multilayer substrate 3 has. This allows the first filter 9 included in the chip 5 to filter a signal input from one of the external terminals 7 and output the signal to another external terminal 7.

[0033] The pads 25 are, for example, overlapped on the upper surface of the base 21. The pads 25 are, for example, bonded to layered external terminals (not shown) located on the underside of the chip 5, facing each other via a conductive bonding material (not shown) interposed therebetween. This allows the chip 5 to be surface-mounted on the multilayer substrate 3. The number, position, shape, size, etc. of the pads 25 may be appropriately set depending on the number of one or more chips 5 and the number, position, shape, size, etc. of the external terminals of each chip 5. Note that, unlike the illustrated example, the pads 25 may be electrically connected to external terminals provided on the upper surface of the chip 5 by bonding wires.

[0034] (3. Basics of Hybrids) (3.1. Operation of Hybrids) As already mentioned, the hybrid 11 shown in FIG. 3 is a 90° hybrid coupler having four ports 19. As is well known, a 90° hybrid coupler has functions as a distributor, combiner, and 90° phase shifter. Specifically, they are as follows. Unless otherwise specified, signals in the following description are assumed to have frequencies at which the hybrid 11 performs its intended function.

[0035] Ports 19A and 19B on the left side of the drawing are electrically connected to ports 19C and 19D on the right side of the drawing, respectively. "Electrical connection" here means that a signal can flow. Therefore, for example, a signal input to port 19A can be output from ports 19C and 19D.

[0036] For convenience, the description of this embodiment may be based on the positional relationship of the ports 19A to 19D in the diagram showing the hybrid 11. However, the positional relationship of the four ports 19A to 19D on the diagram does not have to match the positional relationship of the four actual ports 19A to 19D.

[0037] A signal input to port 19A on the left side of the drawing is distributed to ports 19C and 19D on the right side of the drawing. The distribution ratio (ratio of the intensities of the two distributed signals) is 1:1. The intensities may be, for example, voltage, current, and / or power. The phases of the two distributed signals are shifted by 90° from each other.

[0038] The phase of the signal before distribution (e.g., the signal input to port 19A) and the phase of one of the two signals after distribution (e.g., the signal output from port 19C) may be the same. Also, unlike the above, the phase of the signal before distribution may be different from the phase of both of the two signals after distribution. However, for convenience, in the description of this embodiment, the phase of the signal before distribution may be described as if it were the same as the phase of one of the two signals after distribution. Specifically, the phase of the signals of ports (e.g., ports 19A and 19C) located at the same vertical position on the page may be described as if they were the same.

[0039] Although the above explanation takes the case where a signal is input to port 19A as an example, the above operation is similar when signals are input to the other ports 19B to 19D. That is, a signal input to one of the two ports located on one side of the paper in the left-right direction is distributed at a distribution ratio of 1:1 and output from the two ports located on the other side of the paper in the left-right direction. At this time, the phases of the two distributed signals are shifted by 90° from each other.

[0040] As mentioned above, when a phase is shifted, for convenience, it refers to either an advance or a delay in phase, common to various components and various signals, etc. In the illustration of the drawings, it is assumed that a signal output from a port (e.g., 19D) located in a different position in the vertical direction from the port to which the signal was input (e.g., 19A) is shifted in phase by 90° with respect to a signal output from a port (e.g., 19C) located in the same vertical direction as the port to which the signal was input (e.g., 19A).

[0041] Since a hybrid operating as described above is called a 90° hybrid, the relationship between the four ports of hybrid 11 can be determined from a description of only some of the ports. For example, assume that port 19D is described as a port from which a signal that is 90° out of phase with respect to the phase of the signal distributed from port 19A to port 19C is distributed from port 19A. From this description, it follows that port 19A and the remaining port 19B are located on the same horizontal side of the paper, with ports 19C and 19D located on the opposite side, and that ports 19A and 19C are located on the same vertical side of the paper, with ports 19B and 19D located on the opposite side. When the relationship between the four ports is described using the signal distributed from port 19A as described above, hybrid 11 does not actually need to be configured in such a way that a signal is input from port 19A.

[0042] When signals are input to ports 19A and 19B on the left side of the drawing, each signal is distributed as described above, and the distributed signals are then combined. For example, the signal input to port 19A is the first signal, and the signal input to port 19B is the second signal. The signals obtained by distributing the first signal to ports 19C and 19D are the third and fourth signals. The fourth signal is 90° out of phase with the third signal. The signals obtained by distributing the second signal to ports 19C and 19D are the fifth and sixth signals. The fifth signal is 90° out of phase with the sixth signal. In this case, a signal obtained by combining the third and fifth signals is output to port 19C, and a signal obtained by combining the fourth and sixth signals is output to port 19D. While the example has been given of signals being input to the two ports 19A and 19B on the left side of the drawing, the same applies to signals being input to the two ports 19C and 19D on the right side of the drawing.

[0043] As described above, for example, there may be a phase difference between the first signal (input to port 19A) and the third signal (distributed to port 19C without phase shifting), and there may be a phase difference between the second signal (input to port 19B) and the sixth signal (distributed to port 19D without phase shifting). In this case, the two phase differences are the same. The two phase differences when the signals are in opposite directions are also the same as the two phase differences.

[0044] (3.2. Hybrid Circuit Configuration) The circuit configuration of the hybrid 11 (basic configuration excluding the specific shape and dimensions of the conductors, etc.) may be in various forms, for example, a known configuration, as long as it can perform the functions described above and is capable of separating a portion (the portion included in the multilayer substrate 3) from another portion (the portion included in the chip 5) that can adjust the operating frequency.

[0045] In the illustrated example, as described above, the hybrid 11 has four series elements 15 forming a loop 13 and four parallel elements 17 grounding four ports 19. As another configuration, for example, each of the four series elements 15 includes two elements, and instead of the parallel element 17 grounding the port, a parallel element 17 grounding the portion between the two elements is provided (for example, see FIG. 8 of Patent Document 4).

[0046] In the hybrid 11 having four series elements 15 forming the loop 13 and four parallel elements 17 grounding the four ports 19, the series elements 15 and the parallel elements 17 can be various electronic elements (e.g., inductors, capacitors, and resonators). In the illustrated example, as described above, the four series elements 15 are four inductors, and the four parallel elements 17 are four capacitors.

[0047] Configurations other than those shown in the drawings include, for example, the following: four series elements 15 are configured as four capacitors, and four parallel elements 17 are configured as four inductors; two series elements 15 are configured as two inductors, the remaining two series elements 15 connecting these two inductors are configured as two capacitors, and four parallel elements 17 are configured as four capacitors; two series elements 15 are configured as two inductors, the remaining two series elements 15 connecting these two inductors are configured as two parallel resonant circuits, and four parallel elements 17 are configured as four capacitors; four series elements 15 are configured as four parallel resonant circuits, and four parallel elements 17 are configured as four capacitors; four series elements 15 are configured as four inductors, and four parallel elements 17 are configured as four series resonant circuits.

[0048] The illustrated example and the various aspects described in the preceding paragraph are disclosed in the above-mentioned Patent Documents 3 to 5. Furthermore, the relationship between the operating frequency and the values ​​of various parameters (e.g., inductors and capacitors) of the series element 15 and the parallel element 17 is also well-known in the art or is described in the above-mentioned Patent Documents 3 to 5. Therefore, not all of the relationships between the parameter values ​​and the operating frequency in the various aspects will be described here.

[0049] In the illustrated example, the inductances of inductors L1 and L3 are the same. The inductances of inductors L2 and L4 are the same. The inductances of inductors L1 and L3 are usually different from the inductances of inductors L2 and L4. Furthermore, the capacitances of capacitors C1 to C4 are the same. If the capacitances of capacitors C1 to C4 are increased, for example, the operating frequency of the hybrid 11 will be lower.

[0050] In the description of the embodiment, for convenience, unless otherwise specified, the description will be made on the assumption that the configuration of the hybrid 11 is the same as that of the example in FIG.

[0051] Each series element 15 may be configured to include two or more elements. Furthermore, some or all of each series element 15 may be shared with some or all of the elements other than the hybrid 11. The same applies to the parallel element 17. In the example of FIG. 3 , as will be described in detail later, the capacitor C2 includes a capacitor C2a dedicated to the hybrid 11 and a parallel resonator 29P of the first filter 9. That is, the parallel resonator 29P of the first filter 9 is shared with the hybrid 11 as part of the capacitor C2.

[0052] (4. First Filter) (4.1. Overview of First Filter) The first filter 9 is, for example, a bandpass filter that passes signals in a predetermined passband, as described above. The passband (center frequency and bandwidth) is arbitrary. For example, the passband may be located in the range of 300 MHz to 10 GHz. The passband may also conform to a predetermined standard. The passband may correspond to one passband defined by the standard, or may include two or more passbands defined by the standard.

[0053] The specific configuration of the first filter 9 may be various, for example, a known configuration. More specifically, the first filter 9 may be, for example, a piezoelectric filter including a piezoelectric element, a dielectric filter utilizing electromagnetic waves in a dielectric, an LC filter combining an inductor and a capacitor, or a combination of two or more of these. The piezoelectric filter may be, for example, an elastic wave filter utilizing elastic waves, or may not utilize elastic waves (for example, one utilizing a piezoelectric vibrator).

[0054] Acoustic wave filters may be configured in various ways as long as they utilize acoustic waves. For example, an acoustic wave filter may excite acoustic waves using interdigital transducer (IDT) electrodes located on the surface of a piezoelectric body, or may excite acoustic waves using electrodes facing each other across a piezoelectric thin film (a film bulk acoustic resonator). Furthermore, for example, an acoustic wave filter may be a ladder filter in which multiple acoustic wave resonators are connected in a ladder configuration, a multimode filter (including a double-mode filter) in which multiple IDT electrodes are arranged in the propagation direction of the acoustic waves, or a transversal filter in which acoustic waves are transmitted and received between two IDT electrodes.

[0055] The elastic wave may be, for example, a surface acoustic wave (SAW), a bulk acoustic wave (BAW), a boundary acoustic wave, or a plate wave, although these elastic waves cannot always be clearly distinguished from each other.

[0056] For convenience, in the description of the embodiment, a ladder filter in which acoustic wave resonators using IDT electrodes are connected in a ladder configuration will be mainly taken as an example of the first filter 9. In the following description, an example of an acoustic wave resonator will first be described with reference to Fig. 4. Next, a ladder filter will be described with reference to Fig. 5.

[0057] (4.2. Examples of Elastic Wave Resonators) FIG. 4 is a plan view schematically showing the configuration of an elastic wave resonator 29 (hereinafter, sometimes simply referred to as "resonator 29").

[0058] Although either direction of the resonator 29 may be considered to be the up or down direction, in the following, for convenience, an orthogonal coordinate system consisting of the D1-axis, D2-axis, and D3-axis will be attached to the drawings, and terms such as the top surface or the bottom surface may be used, with the +D3 side being considered to be the up side. The D1-axis is defined to be parallel to the propagation direction of an elastic wave propagating along the top surface of the piezoelectric body (described later), the D2-axis is defined to be parallel to the top surface of the piezoelectric body and perpendicular to the D1-axis, and the D3-axis is defined to be perpendicular to the top surface of the piezoelectric body.

[0059] The resonator 29 is configured as a so-called one-port acoustic wave resonator. The resonator 29 receives a signal from one of two terminals 28, which are shown schematically on both sides of the drawing, and outputs the signal from the other of the two terminals 28. In this case, the resonator 29 converts the electrical signal into an acoustic wave and the acoustic wave into an electrical signal. The terminals 28 may be considered to be abstract representations of an antenna terminal, a transmitting terminal, a receiving terminal, or a reference potential portion, which will be described later with reference to FIG. 6 .

[0060] The resonator 29 includes, for example, a piezoelectric substrate 31 (at least a part of its upper surface 31 a), an IDT electrode 33 (or, in a broader sense, an excitation electrode) located on the upper surface 31 a, and a pair of reflectors 35 located on both sides of the IDT electrode 33. A plurality of resonators 29 may be formed on one piezoelectric substrate 31. That is, the piezoelectric substrate 31 may be shared by a plurality of resonators 29. In the following description, for the sake of convenience, in order to distinguish between a plurality of resonators 29 sharing the same piezoelectric substrate 31, the combination of the IDT electrode 33 and the pair of reflectors 35 (electrode portion of the resonator 29) may be expressed as if it were the resonator 29 (as if the resonator 29 did not include the piezoelectric substrate 31).

[0061] The piezoelectric substrate 31 has piezoelectricity at least in the region of the upper surface 31a where the resonator 29 is provided. Examples of such piezoelectric substrates 31 include those in which the entire substrate is made of a piezoelectric material. Examples of other types of piezoelectric substrates include so-called bonded substrates. A bonded substrate includes a substrate (piezoelectric substrate) made of a piezoelectric material having an upper surface 31a, and a support substrate bonded to the surface of the piezoelectric substrate opposite the upper surface 31a, with or without an adhesive. The support substrate may or may not have a cavity below the piezoelectric substrate. Examples of other types of piezoelectric substrates 31 include those in which a film made of a piezoelectric material (piezoelectric film) or multiple films including a piezoelectric film are formed on a partial region of the main surface on the +D3 side of the support substrate or on the entire main surface.

[0062] The piezoelectric body 31b constituting at least the region of the piezoelectric substrate 31 where the resonator 29 is provided is made of, for example, a single crystal having piezoelectricity. Examples of materials constituting such a single crystal include lithium tantalate (LiTaO ３ ), lithium niobate (LiNbO ３ ) and quartz (SiO ２ The cut angle, planar shape and various dimensions may be set appropriately.

[0063] The IDT electrode 33 and the reflector 35 are composed of layered conductors provided on the piezoelectric substrate 31. The IDT electrode 33 and the reflector 35 are, for example, composed of the same material and thickness. The layered conductors that compose them are, for example, metal. The metal is, for example, Al or an alloy containing Al as a main component (Al alloy). The Al alloy is, for example, an Al-Cu alloy. The layered conductor may be composed of multiple metal layers. The thickness of the layered conductor is set appropriately depending on the electrical characteristics required of the resonator 29, for example. As an example, the thickness of the layered conductor is 50 nm to 600 nm.

[0064] The IDT electrode 33 has a pair of comb-tooth electrodes 37 (one of which is hatched for ease of visibility). Each comb-tooth electrode 37 has, for example, a bus bar 39, a plurality of electrode fingers 41 extending in parallel from the bus bar 39, and a plurality of dummy electrodes 43 protruding from the bus bar 39 between the plurality of electrode fingers 41. The pair of comb-tooth electrodes 37 is arranged so that the plurality of electrode fingers 41 interdigitate with (intersect with) each other.

[0065] The bus bars 39 are formed, for example, in elongated shapes that have a substantially constant width and extend linearly in the propagation direction of the elastic waves (direction D1). The pair of bus bars 39 face each other in a direction (direction D2) perpendicular to the propagation direction of the elastic waves. Note that the width of the bus bars 39 may vary or they may be inclined with respect to the propagation direction of the elastic waves.

[0066] Each electrode finger 41 is formed, for example, in an elongated shape extending linearly in a direction (direction D2) perpendicular to the propagation direction of the elastic wave with a substantially constant width. Note that the width of the electrode fingers 41 may vary. In each comb-tooth electrode 37, the multiple electrode fingers 41 are arranged in the propagation direction of the elastic wave. Furthermore, the multiple electrode fingers 41 of one comb-tooth electrode 37 and the multiple electrode fingers 41 of the other comb-tooth electrode 37 are basically arranged alternately.

[0067] The pitch p of the electrode fingers 41 (e.g., the center-to-center distance between two adjacent electrode fingers 41) is basically constant within the IDT electrode 33. However, a narrow pitch portion where the pitch p is narrower than most of the other portions or a wide pitch portion where the pitch p is wider than most of the other portions may be provided in a part of the IDT electrode 33. Furthermore, a thinned-out portion where the electrode fingers 41 are essentially thinned out may be provided in a part of the IDT electrode 33.

[0068] In the description of the embodiments, unless otherwise specified, the pitch p refers to the pitch of a portion (most of the plurality of electrode fingers 41) excluding peculiar portions such as the narrow-pitch portion, wide-pitch portion, or thinned-out portion. In addition, if the pitch varies in most of the electrode fingers 41 excluding the peculiar portions, the average value of the pitches of most of the electrode fingers 41 (for example, 80% of the total number selected to minimize the variance) may be used as the value of the pitch p.

[0069] The number of electrode fingers 41 may be set appropriately depending on the electrical characteristics required of the resonator 29. Since Fig. 4 is a schematic diagram, the number of electrode fingers 41 is shown as being smaller than that shown. In reality, more electrode fingers 41 may be arranged than shown. The same applies to the strip electrodes 47 of the reflector 35, which will be described later.

[0070] The lengths of the electrode fingers 41 are, for example, equal to each other. The IDT electrode 33 may be apodized, in which the lengths of the electrode fingers 41 (or, from another perspective, the cross width W) vary depending on the position in the propagation direction. The length and width of the electrode fingers 41 may be set appropriately depending on the required electrical characteristics, etc.

[0071] The dummy electrodes 43 protrude, for example, with a generally constant width in a direction perpendicular to the propagation direction of the acoustic wave. The width is, for example, equal to the width of the electrode fingers 41. The multiple dummy electrodes 43 are arranged at the same pitch as the multiple electrode fingers 41, and the tips of the dummy electrodes 43 of one comb-tooth electrode 37 face the tips of the electrode fingers 41 of the other comb-tooth electrode 37 across a gap. Note that the IDT electrode 33 may not include the dummy electrodes 43.

[0072] The pair of reflectors 35 are located on both sides of the IDT electrode 33 in the propagation direction of the acoustic wave. Each reflector 35 may be, for example, electrically floating or may be applied with a reference potential. Each reflector 35 is formed, for example, in a lattice shape. That is, the reflector 35 includes a pair of bus bars 45 facing each other and a plurality of strip electrodes 47 extending between the pair of bus bars 45. The pitch of the plurality of strip electrodes 47 and the pitch between the adjacent electrode fingers 41 and the strip electrode 47 are basically the same as the pitch of the plurality of electrode fingers 41.

[0073] When a voltage is applied to the pair of comb-tooth electrodes 37, the voltage is applied to the piezoelectric body 31 b by the multiple electrode fingers 41, causing the piezoelectric body 31 b to vibrate. That is, an elastic wave is excited. Of the elastic waves of various wavelengths that propagate in various directions, the elastic waves that propagate in the arrangement direction of the multiple electrode fingers 41 with the pitch p of the multiple electrode fingers 41 being approximately half the wavelength (λ / 2) tend to have large amplitudes because the multiple waves excited by the multiple electrode fingers 41 overlap in phase.

[0074] Furthermore, the elastic waves propagating through the piezoelectric body 31b are converted into electrical signals by the plurality of electrode fingers 41. At this time, similar to when elastic waves are excited, the intensity of the electrical signals converted from the elastic waves propagating in the arrangement direction of the plurality of electrode fingers 41, with the pitch p of the plurality of electrode fingers 41 being approximately half the wavelength (λ / 2), tends to be strong.

[0075] Due to the above-described effects (and other effects not described here), the resonator 29 functions as a resonator having a resonance frequency equal to the frequency of an elastic wave whose pitch p is approximately half the wavelength (λ / 2). The pair of reflectors 35 contributes to confining the elastic wave.

[0076] Although not shown in particular, the resonator 29 may have a protective film (not shown) that covers the upper surface 31a of the piezoelectric substrate 31 from above the IDT electrode 33 and the reflector 35. Such a protective film may be made of, for example, SiO ２The additional film is made of an insulating material such as a metal or the like, and contributes to reducing the likelihood of corrosion of the IDT electrode 33 and the like and / or compensating for changes in characteristics of the resonator 29 due to temperature changes. The resonator 29 may also have an additional film that overlaps the upper or lower surfaces of the IDT electrode 33 and the reflector 35 and has a shape that basically fits within the IDT electrode 33 and the reflector 35 in a planar perspective view. Such an additional film is made of, for example, an insulating material or a metal material that has acoustic properties different from those of the material of the IDT electrode 33 and the like, and contributes to improving the reflection coefficient of the elastic wave.

[0077] (4.3. Ladder-Type Filter) Fig. 5 is a plan view showing a ladder-type filter as an example of the first filter 9. As can be understood from the orthogonal coordinate system D1D2D3, this figure shows the upper surface 31a of the piezoelectric substrate 31 (piezoelectric body 31b), similar to Fig. 4. From another perspective, Fig. 5 may be understood as a schematic diagram of the piezoelectric substrate 31 of the chip 5 as seen in plan from the side of the multilayer substrate 3.

[0078] The first filter 9 outputs signals having frequencies within a predetermined pass band from an output terminal 49O, among signals input to an input terminal 49I. Signals having frequencies outside the pass band are discharged to a GND terminal 49G to which a reference potential is applied. Note that these terminals may be collectively referred to as terminals 49.

[0079] The first filter 9 is configured by connecting a plurality of resonators 29 (29S and 29P) in a ladder configuration. Specifically, the first filter 9 includes a plurality of (one or more) series resonators 29S connected in series between an input terminal 49I and an output terminal 49O, and a plurality of (one or more) parallel resonators 29P (parallel arms) connected in parallel between the series line (series arm 51) and a GND terminal 49G (reference potential portion). Each parallel resonator 29P is connected to either the input terminal 49I side or the output terminal 49O side of any one of the series resonators 29S. Specifically, the plurality of parallel resonators 29P connect electrically different positions in the series arm 51 to the GND terminal 49G.

[0080] Although not specifically shown, the impedance of each resonator 29 is minimized at a resonant frequency and maximized at an anti-resonant frequency. The multiple series resonators 29S have substantially the same resonant frequencies and substantially the same anti-resonant frequencies. The multiple parallel resonators 29P have substantially the same resonant frequencies and substantially the same anti-resonant frequencies. The resonant frequencies of the series resonators 29S and the anti-resonant frequencies of the parallel resonators 29P are substantially the same.

[0081] The above-described connection relationships and the settings of the resonant and anti-resonant frequencies realize a band-pass filter. The center frequency of the pass band is approximately the same as the resonant frequency of the series resonator 29S and the anti-resonant frequency of the parallel resonator 29P. The width of the pass band is slightly narrower than the width from the resonant frequency of the parallel resonator 29P to the anti-resonant frequency of the series resonator 29S.

[0082] The number of series resonators 29S and the number of parallel resonators 29P are arbitrary. Furthermore, the first filter 9 may or may not include a parallel resonator 29P connected closer to the input terminal 49I than the series resonator 29S electrically closest to the input terminal 49I (in the illustrated example). Similarly, the first filter 9 may or may not include a parallel resonator 29P connected closer to the output terminal 49O than the series resonator 29S electrically closest to the output terminal 49O (in the illustrated example).

[0083] Although not particularly shown, each series resonator 29S may be divided into two or more resonators. For example, each series resonator 29S may have a plurality of resonators 29 connected in series with each other. Similarly, each parallel resonator 29P may be divided into two or more resonators. The specific positions of the series resonators 29S and the parallel resonators 29P on the upper surface 31a of the piezoelectric body 31b, the shape and dimensions of each resonator 29, etc. may be set appropriately depending on the characteristics required of the first filter 9. Furthermore, the first filter 9 may have a configuration other than the resonators 29. For example, the first filter 9 may have an inductor or a capacitor connected in series or parallel to the resonator 29.

[0084] (5. Chip) The chip 5 may be configured, for example, mostly by the piezoelectric substrate 31. Specifically, for example, the chip 5 may have the piezoelectric substrate 31 and a relatively thin layer overlapping the surface of the piezoelectric substrate 31. Examples of the relatively thin layer include a conductive layer (such as the IDT electrode 33) overlapping the upper surface 31a of the piezoelectric substrate 31, and a protective film (not shown) covering most of the upper surface 31a from above the conductive layer. Note that the protective film does not cover the terminals (49I, 49O, and 49G). The chip 5 may also have a layer covering the side or lower surface of the piezoelectric substrate 31.

[0085] The chip 5 having the configuration described in the previous paragraph is mounted on the multilayer substrate 3, for example, with its top surface 31a facing the top surface of the multilayer substrate 3 (the upper surface in FIG. 1 ). At this time, the terminals 49 of the chip 5 and the pads 25 of the multilayer substrate 3 face each other and are joined by a conductive bonding material (not shown) interposed between them. A space is formed between the chip 5 and the multilayer substrate 3 (or, from another perspective, above the resonator 29) with a height roughly corresponding to the thickness of the bonding material bonding the terminals 49 and the pads 25.

[0086] Furthermore, in addition to the above configuration, the chip 5 may have, for example, a box-shaped insulating cover (not shown) that covers the upper surface 31a of the piezoelectric substrate 31. This cover defines a space above the resonator 29. The chip 5 is, for example, located above the terminal 49 and has a pillar-shaped terminal that penetrates the cover. The chip 5 is mounted on the multilayer substrate 3 with the upper surface of the cover facing the upper surface of the multilayer substrate 3 (the upper surface in FIG. 1 ). At this time, the upper surfaces of the pillar-shaped terminals and the pads 25 of the multilayer substrate 3 face each other and are joined by a conductive bonding material (not shown) interposed therebetween.

[0087] 5 , one chip 5 may include one first filter 9. Also, one chip 5 may include only a part of one first filter 9. For example, a plurality of series resonators 29S and a plurality of parallel resonators 29P that configure the same first filter 9 may be provided on separate chips 5. Also, one chip 5 may include two or more first filters 9. The number of terminals 49 included in one chip 5 may be set appropriately depending on the differences in configuration as described above.

[0088] 2 is a perspective view showing a portion of the hybrid 11 located on the multilayer substrate 3. In this figure, the outline of the multilayer substrate 3 is shown by a dotted line, and the conductors that form part of the hybrid 11 are shown by a solid line.

[0089] The portion of the hybrid 11 located on the multilayer substrate 3 may be selected arbitrarily. In the example of Fig. 2, the multilayer substrate 3 has four series elements 15 (more specifically, four inductors L). In other words, the multilayer substrate 3 does not have four parallel elements 17 (more specifically, four capacitors C).

[0090] Unlike the illustrated example, the multilayer substrate 3 may have, for example, one to three of the four series elements 15 (or, conversely, it does not have to have one to three series elements 15). Also, for example, the multilayer substrate 3 may have one to four of the four parallel elements 17, as long as it does not have all of the hybrids 11. In the multilayer substrate 3, the combination of the number of series elements 15 and the number of parallel elements 17 is also arbitrary.

[0091] Also, unlike the illustrated example, the multilayer substrate 3 may have part of one series element 15 and / or part of one parallel element 17. For example, the capacitance required for the capacitor C1 may be realized by the combined capacitance of the capacitance of the capacitor provided on the multilayer substrate 3 and the capacitance of the capacitor provided on the chip 5. Then, adjustment according to the operating frequency may be realized by, for example, the capacitance of the capacitor provided on the chip 5.

[0092] The specific configuration of the series element 15 and / or the parallel element 17 included in the multilayer substrate 3 (in other words, built into the multilayer substrate 3) is arbitrary. For example, the series element 15 and / or the parallel element 17 may be built into the multilayer substrate 3, may be a chip embedded in the multilayer substrate 3, or may be a combination of both. More specifically, examples of elements built into the multilayer substrate 3 include elements configured by a conductor layer (reference numeral omitted) overlapping the insulating layer 21 a ( FIG. 1 ) and / or a via conductor (reference numeral omitted) penetrating the insulating layer 21 a.

[0093] In the description of the embodiments, unless otherwise specified, the elements (15, 17, etc.) included in the multilayer substrate 3 refer to, for example, elements that cannot be separated from the multilayer substrate 3 without destroying the multilayer substrate 3. Therefore, for example, elements (e.g., chips) mounted on the surface of the multilayer substrate 3 with a conductive adhesive material are not included in the elements included in the multilayer substrate 3. Furthermore, the elements included in the multilayer substrate 3 may be located entirely inside the multilayer substrate 3, or may be partially exposed to the outside of the multilayer substrate 3.

[0094] When the inductor and / or capacitor are built into the multilayer substrate 3, the specific configuration of the inductor and / or capacitor is also arbitrary. For example, the inductor may be formed of a conductor extending in a spiral shape, a layered conductor extending in a spiral shape, or a layered conductor extending in a meandering shape. The capacitor may be formed of two layered conductors (parallel plates) facing each other via the insulating layer 21a, or may be formed of layered conductors (parallel plates) in the same layer facing each other on the surface of the insulating layer 21a, or may be formed of a pair of comb-shaped electrodes (see IDT electrode 33) located on the surface of the insulating layer 21a. From another perspective, the inductor and / or capacitor may be three-dimensional or two-dimensional.

[0095] In the example of Fig. 2, the inductors L1 to L4 are built into the multilayer substrate 3. Specifically, they are formed into a three-dimensional coil shape with the axial direction being the stacking direction of the multiple insulating layers 21a (Fig. 1) in the multilayer substrate 3. More specifically, although not specifically labeled, the inductors have multiple conductor layers that extend between the multiple insulating layers 21a over less than one turn (half a turn in the illustrated example), and multiple via conductors that penetrate the multiple insulating layers 21a and connect the multiple conductor layers together. Note that, unlike the illustrated example, the three-dimensional coil-shaped inductors L1 to L4 built into the multilayer substrate 3 may be configured with conductor layers and via conductors with the axial direction being along the insulating layers 21a.

[0096] The portions between the four inductors L are ports 19. For convenience, in Fig. 2, the four via conductors extending upward from the four layered wirings (reference numerals omitted) that connect the four inductors L in series are denoted by the reference numerals 19A to 19D. However, from an electrical point of view (ignoring the inductance of the wiring, etc.), not only the above-mentioned four via conductors but also any positions of the above-mentioned four layered wirings or conductors (not shown) connected to the upper ends of the via conductors may be considered as ports 19A to 19D.

[0097] (7. Portion of Hybrid Located on Chip) The portion of the hybrid 11 located on the chip 5 may be selected arbitrarily. Explanation of examples of this arbitrarily selected portion is the reverse of the explanation of the above-mentioned example of the portion of the hybrid 11 selected to be located on the multilayer substrate 3, and will be omitted. For convenience, in explaining the embodiments, an example in which the capacitors C1 to C4 serving as the parallel elements 17 of the hybrid 11 are located on the chip 5 will be mainly taken as an example, and explanations will be given assuming such an example without special mention.

[0098] The specific configuration of the series element 15 and / or the parallel element 17 included in the chip 5 is arbitrary. For example, the series element 15 and / or the parallel element 17 may be built into or embedded in the substrate (e.g., the piezoelectric substrate 31) included in the chip 5, as in the case where the series element 15 and / or the parallel element 17 are provided on the multilayer substrate 3. Also, unlike the case of the multilayer substrate 3, the elements (15 and / or 17) may be chips mounted on the surface of the substrate (e.g., the piezoelectric substrate 31) included in the chip 5. Furthermore, in an embodiment where the chip 5 has a cover covering the piezoelectric substrate 31 as described above, the elements (15 and / or 17) may be formed by conductors (conductor layers and / or through conductors) located on the surface and / or inside of the cover. The elements (15 and / or 17) may also be realized by a combination of the various configurations described above. In any case, the series element 15 and / or the parallel element 17 included in the chip 5 are electrically connected to the rest of the hybrid 11 when the chip 5 is mounted on the multilayer substrate 3.

[0099] When the inductor and / or capacitor are built into the piezoelectric substrate 31 or the cover covering the piezoelectric substrate 31, the specific configuration of the inductor and / or capacitor is arbitrary, similar to when the inductor and / or capacitor are built into the multilayer substrate 3. For example, the inductor may be spiral, vortex, or meander-shaped, and the capacitor may be two-layered parallel plates, parallel plates in one layer, or a pair of comb-teeth electrodes.

[0100] 5, the capacitor C2 serving as the parallel element 17 is formed of a conductor located on the upper surface of the piezoelectric substrate 31 (piezoelectric body 31b). Specifically, the capacitor C2 includes a capacitor C2a and a capacitor C2b.

[0101] In the description of FIG. 5, it is assumed that, among the multiple terminals 49, the output terminal 49O is the terminal that is directly connected (without passing through other filters or other hybrids) to the portion of the hybrid 11 that is located on the multilayer substrate 3 (loop 13). That is, the output terminal 49O is directly connected to one of ports 19A to 19D. For convenience, it is assumed here that the output terminal 49O is connected to port 19B, following FIG. 3. The capacitor C2 is connected closer to the output terminal 49O than the series resonator 29S that is located closest to the output terminal 49O (or, from another perspective, port 19B). As a result, the capacitor C2 functions as a parallel element 17 that constitutes the hybrid 11.

[0102] Furthermore, since both capacitors C2a and C2b are connected closer to the output terminal 49O than the series resonator 29S, which is located closest to the output terminal 49O, the combined capacitance of both capacitors becomes the capacitance of the parallel element 17 (capacitor C2). More specifically, since capacitors C2a and C2b are connected in parallel between the output terminal 49O (port 19B) and the GND terminal 49G, the sum of the capacitances of capacitors C2a and C2b becomes the capacitance of capacitor C2.

[0103] 5, the connection position of capacitor C2a to the series arm 51 is closer to the output terminal 49O than the connection position of capacitor C2b to the series arm 51 (illustrated example). However, unlike the illustrated example, the former position may be the same as the latter position, or may be farther from the output terminal 49O. Also, for example, a wire extending from the series arm 51 may branch and extend to capacitors C2a and C2b.

[0104] 5, the capacitors C2a and C2b are connected separately to the same GND terminal 49G. Unlike the illustrated example, the wiring extending from the capacitors C2a and C2b may join and extend to the GND terminal 49G. Alternatively, the capacitors C2a and C2b may be connected to different GND terminals 49G.

[0105] 5, the capacitor C2a is configured with a pair of comb-shaped electrodes (reference numerals omitted) similar to the IDT electrode 33. However, because the capacitor C2a does not utilize acoustic waves, the arrangement direction of the multiple electrode fingers does not have to be parallel to the propagation direction of the acoustic waves (direction D1). In the illustrated example, the arrangement direction of the multiple electrode fingers in the capacitor C2a is perpendicular to the propagation direction of the acoustic waves. Note that, just to be clear, the arrangement direction of the multiple electrode fingers in the capacitor C2a may be parallel to the propagation direction of the acoustic waves or may be inclined at an angle of less than 90°.

[0106] Furthermore, since the capacitor C2a does not utilize acoustic waves, unlike the IDT electrode 33 of the resonator 29, reflectors do not need to be provided on both sides of the pair of comb-shaped electrodes (as shown in the illustrated example). However, unlike the illustrated example, one or two reflectors may be provided adjacent to the capacitor C2a to reduce the likelihood that the acoustic waves generated by the capacitor C2a will have unintended effects on the resonator 29, etc. Furthermore, the capacitor C2a does not need to have a dummy electrode 43, and the pitch of the electrode fingers may be set arbitrarily. For example, the pitch of the capacitor C2a may be smaller than the pitch of the acoustic wave resonator.

[0107] The pair of comb-shaped electrodes of the capacitor C2a are made of the same material and have the same thickness as the IDT electrode 33 of the resonator 29. However, the materials and thicknesses of the two electrodes may be different.

[0108] The capacitor C2b is formed by the IDT electrode 33 of the parallel resonator 29P. That is, the parallel resonator 29P, which is connected closer to the output terminal 49O than the series resonator 29S, which is closest to the output terminal 49O, is shared by the capacitor C2b.

[0109] Unlike the illustrated example, capacitor C2 may be composed only of capacitor C2a that is not shared by the first filter 9, or conversely, may be composed only of capacitor C2b that is shared by the first filter 9.

[0110] (8. Example of Overall Circuit Configuration of Filter Device 1) (8.1. Basic Items of Circuit Configuration) The overall circuit configuration of the filter device 1 having the above-described first filter 9 and hybrid 11 (excluding items related to the structure such as the parallel element 17 being provided on the chip 5) may be various, and may be the same as a known one, for example. An example of the overall circuit configuration of the filter device 1 is shown below.

[0111] FIG. 6 is a schematic diagram showing an example of the overall circuit configuration of the filter device 1. As shown in FIG.

[0112] 6 is configured as a branching filter (more specifically, a duplexer). The filter device 1 has, for example, a transmission path 2T that filters a transmission signal from a transmission terminal 7T and outputs the filtered signal to an antenna terminal 7A, and a reception path 2R that filters a reception signal from the antenna terminal 7A and outputs the filtered signal to a reception terminal 7R. The transmission terminal 7T, the reception terminal 7R, and the antenna terminal 7A are each an example of the external terminal 7 shown in FIG. 1.

[0113] The transmission path 2T has a transmission filter system 12 that is directly responsible for filtering the transmission signal. The transmission filter system 12 includes transmission filters 9TA and 9TB (sometimes simply referred to as transmission filter 9T without distinguishing between the two). The reception path 2R has a reception filter system 14 that is directly responsible for filtering the reception signal. The reception filter system 14 includes a reception filter 9R. The transmission filter 9T and reception filter 9R are each an example of the first filter 9. The transmission filter system 12 (transmission filter 9T) corresponds to the transmission band. The reception filter system 14 (reception filter 9R) corresponds to the reception band. In other words, the passbands of the transmission filter 9T and reception filter 9R are different from each other (they do not overlap).

[0114] The filter device 1 also includes a first hybrid 11A and a second hybrid 11B. The first hybrid 11A and the second hybrid 11B are each an example of a hybrid 11. The first hybrid 11A is interposed between the antenna terminal 7A, the transmit filters 9TA and 9TB, and the receive filter 9R. The second hybrid 11B is interposed between the transmit terminal 7T, the transmit filters 9TA and 9TB, and the termination resistor 61. Between the first hybrid 11A and the second hybrid 11B, a signal path passing through the transmit filter 9TA and a signal path passing through the transmit filter 9TB are configured.

[0115] The first hybrid 11A and the second hybrid 11B divide, adjust the phase, and / or combine the transmit signal and / or the receive signal. During this process, for example, nonlinear distortions generated in the transmit filter 9T and / or the receive filter 9R are divided, the divided nonlinear distortions are made to be in opposite phases, and then the opposite-phase nonlinear distortions are combined and cancel each other out. In other words, the nonlinear distortion is reduced. Meanwhile, the filter device 1 basically maintains the strength of the transmit signal and the receive signal.

[0116] The specific connection relationships in the above-described circuit configuration and the principle of the above-described effects are explained in Patent Document 1. Therefore, only the main points of the circuit configuration of the illustrated example will be briefly described below.

[0117] The transmit filters 9TA and 9TB correspond to the same pass band (transmission band). That is, the pass bands of both filters are substantially and / or design-wise identical. The transmit filters 9TA and 9TB have the same or similar configurations and substantially or design-wise identical characteristics. However, the transmit filters 9TA and 9TB may be fine-tuned so that the pass bands and / or characteristics are slightly different.

[0118] In the first hybrid 11A, a port 19A is connected to the antenna terminal 7A, a port 19B is connected to the receiving filter 9R, a port 19C is connected to the transmitting filter 9TA, and a port 19D is connected to the transmitting filter 9TB.

[0119] In the second hybrid 11B, a port 19A is connected to a transmission filter 9TA. A port 19B is connected to a transmission filter 9TB. A port 19C is connected to a termination resistor 61. A port 19D is connected to a transmission terminal 7T.

[0120] From another perspective, the transmit filter system 12 is connected to the antenna terminal 7A via the first hybrid 11A and to the transmit terminal 7T via the second hybrid 11B. The receive filter system 14 is connected to the antenna terminal 7A via the first hybrid 11A and is directly connected to the receive terminal 7R.

[0121] When a signal (e.g., a transmission signal) is input from the outside to the transmission terminal 7T, the second hybrid 11B distributes two signals, each with a phase difference of 90°, to the transmission filters 9TA and 9TB. The two distributed signals pass through the transmission filters 9TA and 9TB and are then input to the first hybrid 11A. The two signals input to the first hybrid 11A are converted into in-phase signals and output to the antenna terminal 7A.

[0122] On the other hand, the two signals input to the first hybrid 11A are (ideally) not output to the receive filter 9R. This is because the two signals are out of phase when they travel to port 19B and cancel each other out. In the above explanation, the transmit signal was used as an example, but nonlinear distortions occurring in the transmit filter 9T also cancel each other out in a similar manner.

[0123] When a signal (e.g., a received signal) is input from the antenna to the antenna terminal 7A, the first hybrid 11A distributes two signals, each with a phase difference of 90°, to the transmit filters 9TA and 9TB. The two distributed signals are reflected by the transmit filters 9TA and 9TB and returned to the first hybrid 11A. The two signals returned to the first hybrid 11A are then converted into in-phase signals and output to the receive filter 9R.

[0124] The two signals returned to the first hybrid 11A are not (ideally) output to the antenna terminal 7A, and no insertion loss occurs due to the first hybrid 11A, because the two signals are in opposite phases when directed to the port 19A and cancel each other out.

[0125] As described above, the signal input to the antenna terminal 7A is reflected by the transmission filter system 12 and output to the reception filter 9R. In the present disclosure, even in this configuration, the reception filter 9R is expressed as being connected to the antenna terminal 7A via the first hybrid 11A.

[0126] The termination resistor 61 has, for example, a predetermined resistance value and connects the second hybrid 11B to the reference potential section. This reduces, for example, reflection of signals flowing from the ports 19A and / or 19B to the port 19C. Although not shown, the filter device 1 may have a matching circuit for impedance matching at an appropriate position.

[0127] Although not specifically shown, the following are other examples of the overall circuit configuration of the filter device 1. Since the specific configuration and effects of each of the following examples are explained in Patent Document 1, only the main points will be described here.

[0128] For example, in the example of Fig. 6, the configuration of the transmitting side and the receiving side may be reversed. That is, the two terminals shown as the receiving terminal 7R and the transmitting terminal 7T in Fig. 6 may be the transmitting terminal 7T and the receiving terminal 7R, the filter shown as the receiving filter 9R in Fig. 6 may be the transmitting filter 9T, and the two filters shown as the two transmitting filters 9T in Fig. 6 may be the two receiving filters 9R.

[0129] In this case, when a signal (e.g., a received signal) is input from the antenna to the antenna terminal 7A, the signals are phase-shifted by 90° by the first hybrid 11A and distributed to the two receiving filters 9R. After passing through the two receiving filters 9R, the distributed signals are made into in-phase signals by the second hybrid 11B and output to the receiving terminal 7R.

[0130] 6 may be combined with the above-described example (not shown). Specifically, a new termination resistor is connected to port 19B of the first hybrid 11A. Two second hybrids 11B are also provided. Ports 19C and 19D of one second hybrid 11B connect ports 19C and 19D of the first hybrid 11A to the transmission terminal 7T and termination resistor 61 via two transmission filters 9T, as in the example of FIG. 6. Ports 19C and 19D of the other second hybrid 11B connect ports 19C and 19D of the first hybrid 11A to the reception terminal 7R and termination resistor 61 via two reception filters 9R, as in the above-described example (not shown).

[0131] In the illustrated example, the first filter 9 receives an unbalanced signal and outputs an unbalanced signal. An unbalanced signal can be, for example, a signal whose signal level changes relative to a reference potential. However, the first filter 9 may also receive a balanced signal and / or output a balanced signal. A balanced signal can be, for example, two signals whose phases are opposite to each other.

[0132] (8.2. Distribution of filter device to multilayer substrate and chip) The lower part of Figure 6 also indicates whether the components of the filter device 1 are located on the multilayer substrate 3 or the chip 5, as indicated by the symbols for the multilayer substrate 3 and the chip 5.

[0133] Although the reference numeral for the multilayer substrate 3 is shown in multiple positions, as can be understood from the above description, there is only one multilayer substrate 3. However, unlike the description in Fig. 6 , the filter device 1 shown in Fig. 1 may constitute only a part of the circuit configuration shown in Fig. 6 . In other words, unlike the description here, there may be two or more multilayer substrates 3.

[0134] As can be understood from the above description, the number of chips 5 is arbitrary. For example, only one chip 5 may be provided corresponding to all the first filters 9, one chip 5 may be provided for each first filter 9, one chip 5 may be provided corresponding to each of the transmit filter system 12 and the receive filter system 14 (two chips 5 in total), or one first filter 9 may be distributed across two or more chips 5.

[0135] The chip 5 includes, for example, at least a portion of the first filter 9. Therefore, the range marked with the symbol of chip 5 and not including the first filter 9 (the rightmost chip 5 in FIG. 6 ) does not mean a chip that does not include the first filter 9, but refers to any of the chips 5 that include the first filter 9, and merely does not include the first filter 9 for the sake of illustration in FIG. 6 . However, unlike the description here, there may be chips 5 that do not include the first filter 9.

[0136] 6 , in a configuration in which the filter device 1 includes two or more hybrids 11, the technical feature of providing a portion of the hybrid 11 on the chip 5 may be applied to any of the hybrids 11. In the illustrated example, the technical feature of providing a portion of the hybrid 11 on the chip 5 is applied to both the first hybrid 11A and the second hybrid 11B (or, from another perspective, to all of the hybrids 11 included in the filter device 1).

[0137] 6 , the four ports 19 of each hybrid 11 are connected directly to the external terminal 7 (without going through the first filter 9 or another hybrid 11) or to first filters 9 with different functions. The parallel elements 17 (e.g., capacitors) that are partly or entirely provided on the chip 5 may be connected to any of the various ports described above. From another perspective, the technical feature of providing part or all of the parallel elements 17 on the chip 5 may be applied to any number of the four ports 19. In the illustrated example, the above feature is applied to all of the ports 19.

[0138] The parallel element 17 connected to the port 19 (e.g., ports 19B-19C of the first hybrid 11A) directly connected to the first filter 9 may be connected to a terminal 49 for connecting the first filter 9 to the multilayer substrate 3 (port 19 from another perspective), as illustrated in FIG. 5 . The parallel element 17 connected to the port 19 (e.g., port 19A of the first hybrid 11A) directly connected to the external terminal 7 may be connected to a terminal 49 provided for the parallel element 17. More specifically, although not specifically illustrated, the chip 5 may have, in addition to the first filter 9, a terminal 49 connected to the port 19, a terminal 49 connecting to the external terminal 7, and a wiring connecting the two. The parallel element 17 may then connect the above wiring to a GND terminal 49G.

[0139] Unlike the illustrated example, the parallel element 17 connected to the port 19 directly connected to the external terminal 7 may be provided outside the filter device 1. For example, the parallel element 17 may be provided on a circuit board (not shown) on which the filter device 1 is mounted, and may connect the external terminal 7 to a reference potential section of the circuit board (not shown). Note that it is not impossible to provide any of the parallel elements 17 connected to the port 19 directly connected to the first filter 9 outside the filter device 1.

[0140] The four parallel elements 17 (capacitors C1 to C4) constituting one hybrid 11 may be provided on the same chip 5 or on different chips 5. For example, in a mode in which one chip 5 is provided for each first filter 9, the capacitor C2 of the first hybrid 11A may be provided on the chip 5 having the receive filter 9R, the capacitor C4 of the first hybrid 11A may be provided on the chip 5 having the transmit filter 9TA, and the capacitor C3 of the first hybrid 11A may be provided on the chip 5 having the transmit filter 9TB.

[0141] In the illustrated example, the termination resistor 61 is provided on the chip 5. However, the termination resistor 61 may also be provided on the multilayer substrate 3. The reference potential portion to which the parallel element 17 is connected may be any of various conductors on the multilayer substrate 3, various conductors on the chip 5, or various conductors on a circuit board (not shown) on which the filter device 1 is mounted, as long as it is assumed that a reference potential is applied to those conductors. Furthermore, the term "reference potential portion" may refer to all of the various conductors listed above, or may refer to any of the various conductors, unless otherwise specified or unless a contradiction arises.

[0142] (9. Communication Device Including Filter Device) Fig. 7 is a block diagram showing the main parts of a communication device 151 as an example of use of the filter device 1. The communication device 151 has a module 171 and a housing 173 that houses the module 171. The module 171 performs wireless communication using radio waves and includes the filter device 1. Here, only the transmit filter system 12 and the receive filter system 14 of the filter device 1 are shown schematically.

[0143] In module 171, a transmission information signal TIS containing information to be transmitted is modulated and frequency-raised (converted into a high-frequency signal having a carrier frequency) by an RF-IC (Radio Frequency Integrated Circuit) 153 (an example of an integrated circuit element) to generate a transmission signal TS. Unwanted components outside the transmission passband are removed from the transmission signal TS by a bandpass filter 155, amplified by an amplifier 157, and input to filter device 1 (transmission terminal 7T). The filter device 1 (transmission filter system 12) then removes unwanted components outside the transmission passband from the input transmission signal TS and outputs the removed transmission signal TS from antenna terminal 7A to antenna 159. The antenna 159 converts the input electrical signal (transmission signal TS) into a radio signal (radio wave) and transmits it.

[0144] Furthermore, in module 171, a radio signal (radio wave) received by antenna 159 is converted by antenna 159 into an electrical signal (received signal RS) and input to filter device 1 (antenna terminal 7A). Filter device 1 (receive filter system 14) removes unnecessary components outside the receive passband from the input received signal RS and outputs the signal from receive terminal 7R to amplifier 161. The output received signal RS is amplified by amplifier 161, and unnecessary components outside the receive passband are removed by bandpass filter 163. The received signal RS is then frequency-downshifted and demodulated by RF-IC 153 to generate received information signal RIS.

[0145] The transmit information signal TIS and the receive information signal RIS may be low-frequency signals (baseband signals) containing appropriate information, such as analog audio signals or digitized audio signals. The passband of the radio signal may be set as appropriate. The modulation method may be phase modulation, amplitude modulation, frequency modulation, or a combination of two or more of these. Although the direct conversion method is illustrated, other appropriate circuit methods may be used, such as a double superheterodyne method. Furthermore, FIG. 7 shows only the essential parts, and low-pass filters, isolators, etc. may be added at appropriate positions, and the positions of amplifiers, etc. may be changed.

[0146] In the module 171, the components from the RF-IC 153 to the antenna 159 are mounted on or built into the same circuit board, for example. As a result, the filter device 1 is combined with other components to form a module. Note that the filter device 1 may be included in the communication apparatus 151 without being modularized. Furthermore, the components exemplified as components of the module 171 may be located outside the module or may not be housed in the housing 173. For example, the antenna 159 may be exposed to the outside of the housing 173.

[0147] (10. Summary of the embodiment) As described above, the filter device 1 includes the multilayer substrate 3, the chip 5 mounted on the multilayer substrate 3, the first filter 9 at least a part of which is included in the chip 5, and the first hybrid coupler (hybrid 11) connected to the first filter 9. The hybrid 11 has a part (e.g., loop 13) included in the multilayer substrate 3 and another part (e.g., one or more parallel elements 17) included in the chip 5.

[0148] In this case, for example, as described at the beginning of the description of the embodiment, the operating frequency can be adjusted by the chip 5 so that the hybrid 11 has an operating frequency corresponding to the pass band of the first filter 9 included in the chip 5. As a result, the multilayer substrate 3 can be made common for different pass bands (different chips 5), thereby improving productivity. Also, for example, depending on the configuration of the multilayer substrate 3, the filter device 1 can be made smaller by configuring the capacitor C using the piezoelectric element 31b of the chip 5, which has a higher dielectric constant than the multilayer substrate 3.

[0149] The first hybrid coupler (hybrid 11) may have four series elements 15 connected in series to each other to electrically form a loop 13, four ports 19 electrically located between the four series elements 15, and four parallel elements 17 connecting the four ports 19 to a reference potential portion (e.g., a GND terminal 49G). A first parallel element (any of the parallel elements 17) of the four parallel elements 17 may have an intra-chip element included in the chip 5 (in this embodiment, the entire first parallel element).

[0150] In this case, for example, as described below, it becomes easier to provide a portion of the hybrid 11 on the chip 5. Furthermore, while the four series elements 15 electrically form the loop 13, the four parallel elements 17 electrically branch off from the loop 13 separately from one another. Therefore, when structurally separating a portion of the hybrid 11, separating the parallel elements 17 tends to result in a simpler structure than separating the series elements 15.

[0151] The in-chip element of the first parallel element (any of the parallel elements 17) of the four parallel elements 17 may have a first capacitor (in the embodiment, a capacitor C (any of C1 to C4) of the first parallel element as a whole).

[0152] In this case, for example, a hybrid 11 configured with four inductors L and four capacitors C as illustrated in Fig. 3 etc. can be used. In addition, for example, as already described, there is an effect that the piezoelectric body 31b of the chip 5, which has a higher dielectric constant than the multilayer substrate 3, can be used as the capacitor C.

[0153] The first filter 9 may include an acoustic wave filter (in this embodiment, the entire first filter 9 is an acoustic wave filter). The chip 5 may include a piezoelectric body 31b and an excitation electrode (an IDT electrode 33). The IDT electrode 33 may be located on the piezoelectric body 31b to form an acoustic wave filter. The first capacitor (capacitor C provided on the chip 5) may be located on the piezoelectric body 31b.

[0154] In this case, for example, as already mentioned, the piezoelectric element 31b of the chip 5, which has a higher dielectric constant than the multilayer substrate 3, can be used as the capacitor C. Since the piezoelectric element 31b is already present for the acoustic wave filter, the likelihood of the filter device 1 becoming larger due to the use of a piezoelectric element as the capacitor C is reduced.

[0155] In a configuration in which the first filter 9 has an acoustic wave filter, the first port (e.g., any one of ports 19B to 19D of the first hybrid 11A in FIG. 6 ) to which the first parallel element (parallel element 17 having an in-chip element provided on the chip 5) of the four ports 19 is connected may be connected to the acoustic wave filter without going through another filter or another hybrid coupler.

[0156] In this case, for example, the first port to which the on-chip element is connected is a port that is intended to be connected to a terminal 49 (input terminal 49I or output terminal 49O) of the chip 5 that has the acoustic wave filter. Therefore, when the on-chip element is connected to the terminal 49 that is connected to the first port, the on-chip element is connected to the first port. That is, unlike when the first port is connected to the external terminal 7 (for example, port 19A of the first hybrid 11A in FIG. 6 ), there is no need to provide a dedicated terminal 49 (a new terminal 49 separate from the terminal 49 for the acoustic wave filter) for connecting the first port and the on-chip element.

[0157] The first filter 9 (acoustic wave filter) may include a plurality of series resonators 29S and a plurality of parallel resonators 29P. The plurality of series resonators 29S may be connected in series. The plurality of parallel resonators 29P may be connected in parallel between a series arm 51 including the plurality of series resonators 29S and a reference potential section (GND terminal 49G). One end of the series arm 51 may be connected to a first port (any of ports 19) of the hybrid 11 to which a first capacitor (capacitor C located on the chip 5) is connected. The plurality of parallel resonators 29P may include a first parallel resonator (parallel resonator 29P) electrically connected closer to the first port than the series resonator 29S located closest to the first port. The first parallel resonator may be shared by at least a portion of the first capacitor (e.g., capacitor C2b in FIG. 5 ).

[0158] In this case, for example, the parallel resonator 29P is shared with the capacitor C, thereby making it possible to reduce the size of the filter device 1.

[0159] The first capacitor (e.g., capacitor C2 in FIG. 5) may include a capacitor shared by the parallel resonator 29P, as well as a second capacitor (e.g., capacitor C2a in FIG. 5) included in the chip 5 and not shared by the parallel resonator 29P of the acoustic wave filter.

[0160] In this case, for example, the parallel resonator 29P can be used in common as part of the capacitor C (capacitor C2b) as described above to achieve miniaturization, while the capacitance of the capacitor C can be easily adjusted by the capacitor C2a.

[0161] The first port of the four ports 19 to which the first parallel element is connected (e.g., port 19A of the first hybrid 11A in Figure 6) may be connected to the external terminal 7 of the filter device 1 (e.g., antenna terminal 7A in Figure 6) without going through the first filter 9 or other filters.

[0162] In other words, a portion of the parallel element 17 that is directly connected to the external terminal may be provided on the chip 5. In this case, the hybrid 11 is completed within the filter device 1, which makes it easier to handle, compared to an embodiment in which the parallel element 17 is provided externally (for example, on a circuit board (not shown) on which the filter device 1 is mounted).

[0163] The four parallel elements 17 may be four capacitors C1 to C4 having the same capacitance.

[0164] In this case, for example, a hybrid 11 having four inductors L1 to L4 and four capacitors C1 to C4 can be used, as shown in Fig. 3. Furthermore, since the capacitances of the capacitors C1 to C4 can be adjusted uniformly, the operating frequency of the hybrid 11 can be easily adjusted.

[0165] As illustrated in FIG. 6 , the filter device 1 may include a first 90° hybrid coupler (first hybrid 11A), a second 90° hybrid coupler (second hybrid 11B), a first filter system (transmit filter system 12), and a second filter system (receive filter system 14). The first 90° hybrid coupler may be connected to a common terminal (antenna terminal 7A). The second 90° hybrid coupler may be connected to a first terminal (transmit terminal 7T). The first filter system may be connected to the common terminal via the first 90° hybrid coupler and to the first terminal via the second 90° hybrid coupler, and may pass signals in a first passband (transmit band). The second filter system may be connected to the common terminal via the first 90° hybrid coupler and to a second terminal (receive terminal 7R), and may pass signals in a second passband (receive band) different from the first passband. The transmit filter system 12 may include a second filter and a third filter (transmit filters 9TA and 9TB) that pass signals in the first passband. The second filter and the third filter may be connected to the first 90° hybrid and the second 90° hybrid in such a manner that, when a signal is input to one of the common terminal and the first terminal, signals out of phase with each other by 90° are distributed to the second filter and the third filter, and the distributed signals are output as in-phase signals to the other of the common terminal and the first terminal. The first 90° hybrid coupler or the second 90° hybrid coupler may be the first hybrid coupler (the hybrid 11, a portion of which is provided on the chip 5). The second filter, the third filter, or the second filter system may include the first filter 9 (a filter included in the chip 5 on which a portion of the hybrid 11 is provided). That is, at least a portion of at least one of the second filter, the third filter, and the second filter system may be provided on the chip 5 on which a portion of the hybrid 11 is provided.

[0166] In the above configuration, for example, as already described, nonlinear distortion can be reduced in the process of dividing and combining signals.

[0167] From another perspective, the multilayer substrate 3 may have a first surface (top surface), a pad 25, and a first circuit (e.g., loop 13). The pad 25 may be located on the top surface of the multilayer substrate 3 and may be capable of mounting a chip 5. The first circuit may constitute a first hybrid coupler (hybrid 11). The first circuit may also have four inductors L connected in series to each other to electrically form the loop 13, and four ports 19 electrically located between the four inductors L. A first port of the four ports 19 (e.g., port 19B in FIG. 3 ) may be connected to the pad 25. When the chip 5 is not mounted on the pad 25, the first port may be disconnected from a reference potential portion (e.g., a terminal of the external terminal 7 to which a reference potential is applied, and the pad 25 that applies a reference potential to the chip 5). In other words, when the chip 5 is mounted, the first port may be connected to the reference potential portion via the parallel element 17 of the chip 5.

[0168] Such a multilayer substrate 3 can be used for a filter device 1 in which the hybrid 11 is configured by mounting the above-mentioned chip 5 on the multilayer substrate 3. Note that the multilayer substrate 3 may be distributed in a state in which the chip 5 is not mounted.

[0169] From another perspective, the communication device 151 may have a filter device 1, an antenna 159 connected to the filter device 1, and an integrated circuit element (RF-IC 153) connected to the antenna 159 via the filter device 1.

[0170] As described above, for example, the filter device 1 can improve productivity, which in turn improves productivity of the communication apparatus 151 including the filter device 1.

[0171] In the above embodiment, the hybrid 11, the first hybrid 11A, and the second hybrid 11B are each an example of a first hybrid coupler. The first filter 9, the transmit filters 9TA and 9TB, and the receive filter 9R are each an example of a first filter and an example of an acoustic wave filter. The capacitors C1 to C4 are each an example of a first parallel element, an example of an on-chip element, and an example of a first capacitor. The GND terminal 49G is an example of a reference potential section. The IDT electrode 33 is an example of an excitation electrode. The ports 19A to 19D are each an example of a first port. The capacitor C2b in FIG. 3 is an example of a second capacitor that is not shared by the parallel resonators. The antenna terminal 7A is an example of a common terminal. The transmit terminal 7T is an example of a first terminal. The first hybrid 11A is an example of a first 90-degree hybrid coupler. The second hybrid 11B is an example of a second 90-degree hybrid coupler. The transmit filter system 12 is an example of a first filter system. The receiving filter system 14 is an example of a second filter system. The transmitting filters 9TA and 9TB are examples of a second filter and a third filter. The loop 13 is an example of a first circuit. The RF-IC 153 is an example of an integrated circuit element.

[0172] The technology according to the present disclosure is not limited to the above-described embodiment and may be implemented in various modes.

[0173] In the description of the embodiments, for convenience, the advantages of being able to adjust the operating frequency of the hybrid coupler by using a portion of the hybrid coupler provided on the chip and being able to share a multilayer substrate for various chips (the advantage of improving productivity) have been mainly mentioned. However, the technology according to the present disclosure does not necessarily have to be implemented in a manner that achieves such advantages. Even in this case, advantages can be achieved, such as being able to use a piezoelectric material with a high dielectric constant on the chip as a capacitor for the hybrid coupler.

[0174] The filter device is not limited to a duplexer. For example, the filter device may have two receive paths with different passbands as the first filter system and the second filter system, or may have two transmit paths with different passbands. The filter device may have a filter system in addition to the first filter system and the second filter system. For example, the filter device may be a triplexer having three filter systems or a quadplexer having four filter systems. The filter device may also have only one first filter (i.e., a filter).

[0175] The hybrid coupler is not limited to a 90° hybrid coupler, but may be a 180° hybrid coupler. A filter device that combines a 180° hybrid coupler and a filter is described in, for example, Patent Document 2.

[0176] 1...filter device, 3...multilayer substrate, 5...chip, 9...first filter, 11...hybrid (first hybrid coupler).

Claims

1. A multilayer board; A chip mounted on the multilayer substrate; a first filter at least partially contained within the chip; a first hybrid coupler, a portion of which is included in the multilayer substrate and another portion of which is included in the chip, the first hybrid coupler being connected to the first filter; Possesses Filter device.

2. The first hybrid coupler comprises: Four series elements connected in series to each other to form an electrical loop; four ports each electrically located between the four series elements; four parallel elements connecting the four ports and a reference potential portion; A first parallel element of the four parallel elements includes an on-chip element included on the chip. The filter device of claim 1 .

3. The on-chip component includes a first capacitor. The filter device of claim 2 .

4. the first filter includes an acoustic wave filter, The chip comprises: A piezoelectric body; an excitation electrode of the acoustic wave filter located on the piezoelectric body; The first capacitor is located on the piezoelectric body. The filter device according to claim 3 .

5. the first filter includes an acoustic wave filter, A first port, among the four ports, to which the first parallel element is connected, is connected to the acoustic wave filter without passing through any other filter or any other hybrid coupler. The filter device of claim 2 .

6. the first filter includes an acoustic wave filter, a first port, among the four ports, to which the first parallel element is connected, is connected to the acoustic wave filter without passing through any other filter or any other hybrid coupler; The acoustic wave filter includes: A plurality of series resonators connected in series with each other; a plurality of parallel resonators connected in parallel to each other between a series arm including the plurality of series resonators and the reference potential portion, the first port is connected to one end of the series arm, the plurality of parallel resonators include a first parallel resonator connected closer to the first port than a series resonator electrically located closest to the first port, The first parallel resonator is shared by at least a part of the first capacitor. The filter device according to claim 3 .

7. The first capacitor includes a second capacitor that is included in the chip and is not shared by a parallel resonator of the acoustic wave filter. The filter device of claim 6.

8. A first port, among the four ports, to which the first parallel element is connected, is connected to an external terminal of the filter device without passing through the first filter or another filter. The filter device of claim 2 .

9. The four parallel elements are four capacitors having the same capacitance. The filter device of claim 2 .

10. a first 90° hybrid coupler connected to the common terminal; a second 90° hybrid coupler connected to the first terminal; a first filter system connected to the common terminal via the first 90° hybrid coupler and to the first terminal via the second 90° hybrid coupler, the first filter system passing signals in a first passband; a second filter system connected to the common terminal via the first 90° hybrid coupler and to a second terminal, the second filter system passing a signal of a second pass band different from the first pass band; It has the first filter system includes a second filter and a third filter each passing a signal in the first passband; the second filter and the third filter are connected to the first 90° hybrid coupler and the second 90° hybrid coupler in a connection relationship in which, when a signal is input to one of the common terminal and the first terminal, signals having a phase difference of 90° with respect to each other are distributed to the second filter and the third filter, and the distributed signals are output as in-phase signals to the other of the common terminal and the first terminal; the first 90° hybrid coupler or the second 90° hybrid coupler is the first hybrid coupler, The second filter, the third filter, or the second filter system includes the first filter. The filter device of claim 1 .

11. The first page and a pad located on the first surface and capable of mounting a chip; a first circuit constituting a first hybrid coupler; It has The first circuit is Four inductors connected in series to each other to form an electrical loop; and four ports electrically located between the four inductors, respectively; a first port of the four ports is connected to the pad; When the chip is not mounted on the pad, the first port is not connected to a reference potential portion. Multilayer board.

12. A filter device according to any one of claims 1 to 10, an antenna connected to the filter device; an integrated circuit element connected to the antenna via the filter device; A communication device having the above configuration.