Bandgap reference circuit, and semiconductor device

Abstract

A bandgap reference circuit (20) comprises: a diode characteristic element group (22); a dynamic element matching circuit (23) which repeatedly performs an operation to select, from the diode characteristic element group (22), a first diode characteristic element group (22a) configured by connecting in parallel M diode characteristic elements, and a second diode characteristic element group (22b) configured by connecting in parallel N (≥M) diode characteristic elements, within a fixed period, while changing a combination of selected diode characteristic elements; a reference voltage generating circuit (30) for generating a reference voltage (VBG) on the basis of a difference between current densities of currents flowing through the first diode characteristic element group (22a) and the second diode characteristic element group (22b); and a second-order temperature coefficient adjusting circuit (37) for adjusting a second-order temperature coefficient of the generated reference voltage (VBG).

Description

Bandgap reference circuit and semiconductor device

[0001] The present disclosure relates to a bandgap reference circuit that generates a reference voltage and a semiconductor device that includes the bandgap reference circuit.

[0002] Conventionally, as a bandgap reference circuit that generates a reference voltage with excellent temperature characteristics, a reference voltage generation circuit has been proposed that includes a reference voltage generation circuit element that generates a reference voltage based on the difference between voltages applied to a first diode characteristic element and a second diode characteristic element that has a current density different from that of the first diode characteristic element, a first adjustment circuit element that adjusts the linear temperature coefficient of the reference voltage, and a second adjustment circuit element that adjusts the quadratic temperature coefficient of the reference voltage (see, for example, Patent Document 1).

[0003] Patent No. 5842164

[0004] However, while the technology of Patent Document 1 improves the temperature characteristics of the generated reference voltage, there is a problem in that characteristic variations occur among a plurality of manufactured reference voltage generating circuits depending on characteristic variations of the first diode characteristic element and the second diode characteristic element used. Note that, unless otherwise specified, characteristic variations refer to variations in characteristics among individual devices, and are also called manufacturing variations.

[0005] Therefore, an object of the present disclosure is to provide a bandgap reference circuit with reduced characteristic variations and a semiconductor device including such a bandgap reference circuit.

[0006] In order to achieve the above object, a bandgap reference circuit according to one aspect of the present disclosure includes: a diode-characteristic element group including a plurality of diode-characteristic elements; a dynamic element matching circuit that selects, from the diode-characteristic element group, a first diode-characteristic element group including M diode-characteristic elements connected in parallel, where M is an integer greater than or equal to 1, and a second diode-characteristic element group including N diode-characteristic elements connected in parallel, where N is an integer greater than 2, and repeats this operation within a constant period while changing the combination of the M diode-characteristic elements and the N diode-characteristic elements to be selected; a reference voltage generation circuit that generates a reference voltage based on a difference between a current density of a current flowing through the first diode-characteristic element group and a current density of a current flowing through the second diode-characteristic element group; and a secondary temperature coefficient adjustment circuit that adjusts a secondary temperature coefficient of the reference voltage generated by the reference voltage generation circuit.

[0007] In order to achieve the above object, a semiconductor device according to one embodiment of the present disclosure includes the bandgap reference circuit and a time-discrete filter that receives the reference voltage output from the bandgap reference circuit, wherein the dynamic element matching circuit repeats the operation in synchronization with a clock signal, and the time-discrete filter performs time-discrete filtering in synchronization with the clock signal.

[0008] The present disclosure provides a bandgap reference circuit with reduced characteristic variations and a semiconductor device including such a bandgap reference circuit.

[0009] FIG. 1 is a circuit block diagram showing the configuration of a semiconductor device including a bandgap reference circuit according to an embodiment. FIG. 2 is a block diagram showing the functions of the dynamic element matching circuit shown in FIG. 1. FIG. 3 is a diagram showing a group of diode-characteristic elements and a group of switches shown in FIG. 1. FIG. 4 is a timing chart showing an example of operation of the dynamic element matching circuit shown in FIG. 3. FIG. 5 is a diagram explaining the transition of the selection state shown in FIG. 4. FIG. 6A is a diagram showing a group of diode-characteristic elements and a group of switches according to a modified example. FIG. 6B is a timing chart showing an example of operation of the dynamic element matching circuit according to the modified example shown in FIG. 6A. FIG. 6C is a diagram explaining the transition of the selection state shown in FIG. 6B. FIG. 6D is a diagram explaining the transition of the selection state according to a reference example. FIG. 7 is a diagram showing the results of a simulation comparing the amount of fluctuation (noise) in the reference voltage between the modified example shown in FIG. 6C and the reference example shown in FIG. 6D. FIG. 8 is a circuit diagram showing an example of the configuration of a switch selection circuit realizing a dynamic element matching circuit according to a modified example incorporating randomness. FIG. 9A is a timing chart showing the operation of the switch selection circuit shown in FIG. 8. FIG. 9B is a diagram showing diode-characteristic elements selected as the first diode-characteristic element group by the switch selection circuit shown in FIG. 8 . FIG. 10 is a diagram illustrating the effect of the operation of the dynamic element matching circuit according to the modified example incorporating randomness shown in FIG. 8 . FIG. 11 is a diagram illustrating an example configuration of a switch selection circuit realizing a dynamic element matching circuit according to the modified example incorporating ΔΣ modulation. FIG. 12 is a diagram showing the layout of a diode-characteristic element group on a substrate according to the modified example. FIG. 13 is a circuit block diagram showing the configuration of a semiconductor device according to the modified example in which a bipolar transistor included in a secondary temperature coefficient adjustment circuit is included in the diode-characteristic element group and is subjected to dynamic element matching. FIG. 14 is a circuit diagram showing a detailed configuration of the dynamic element matching circuit group in FIG. 13 . FIG. 15 is a circuit diagram showing a specific example configuration of the first switch circuit and the second switch circuit in FIG. 1 . FIG. 16A is a circuit diagram showing a specific example configuration of the time-discrete filter in FIG. 1 .Fig. 16B is a timing chart showing the operation of the time-discrete filter shown in Fig. 16A. Fig. 17A is a circuit block diagram showing the configuration of a semiconductor device according to a modified example including an averaging filter as an analog signal processing circuit in place of the time-discrete filter, AD converter, and averaging filter in the embodiment. Fig. 17B is a circuit diagram showing a detailed configuration of the averaging filter shown in Fig. 17A. Fig. 17C is a diagram showing an example of one cycle in which the averaging filter shown in Fig. 17A performs averaging processing.

[0010] Hereinafter, embodiments and variations thereof of the present disclosure will be described in detail with reference to the drawings. The embodiments and variations thereof described below each represent a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement and connection configurations, signal waveforms, timing, and the like shown in the following embodiments and variations are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "A and B are connected" means that A and B are electrically connected, and includes not only the case where A and B are directly connected, but also the case where A and B are indirectly connected with another circuit element sandwiched between A and B.

[0011] 1 is a circuit block diagram showing the configuration of a semiconductor device 10 including a bandgap reference circuit 20 according to an embodiment. The semiconductor device 10 includes the bandgap reference circuit 20 that generates a reference voltage VBG, a time-discrete filter 40 that performs time-discrete filtering on the generated reference voltage VBG to output a reference voltage VBG2, an AD converter 41 that converts the output reference voltage VBG2 into a digital signal, and an averaging filter 42 that averages the output digital signal.

[0012] The bandgap reference circuit 20 includes a timing generation circuit 21 , a diode characteristic element group 22 , a dynamic element matching circuit 23 , a reference voltage generation circuit 30 , a first-order temperature coefficient adjustment circuit 36 ​​, and a second-order temperature coefficient adjustment circuit 37 .

[0013] Based on a clock input from outside, the timing generation circuit 21 generates a chopping clock 1 to be supplied to the first switch circuit 32, a chopping clock 2 to be supplied to the second switch circuit 34, a filter clock to be supplied to the time-discrete filter 40, and a DEM control clock to be supplied to the dynamic element matching circuit 23.

[0014] The diode-characteristic element group 22 is composed of a plurality of diode-characteristic elements, each having one end (cathode) connected in common (here, ground). A diode-characteristic element is an element having diode characteristics functionally composed of an anode and a cathode, such as a diode or an NPN bipolar transistor with its collector and base connected. In this embodiment, the base-emitter voltage of an NPN bipolar transistor with its collector and base connected is used as the bandgap voltage.

[0015] The dynamic element matching circuit 23 is composed of a switch group 25 consisting of a plurality of switches that connect the anode portions of the plurality of diode characteristic elements that make up the diode characteristic element group 22 to a connection point V1 for generating a reference voltage V1 or a connection point V3 for generating a reference voltage V3, and a switch selection circuit 24 that outputs a DEM control signal that controls the on / off of each switch that makes up the switch group 25 in accordance with a DEM control clock from the timing generation circuit 21.

[0016] As shown in the functional block diagram of the dynamic element matching circuit 23 in FIG. 2 , functionally, the dynamic element matching circuit 23 selects, from the diode characteristic element group 22, a first diode characteristic element group 22a configured with parallel connections of M diode characteristic elements, where M is an integer equal to or greater than 1, and a second diode characteristic element group 22b configured with parallel connections of N diode characteristic elements, where N is an integer equal to or greater than M, and repeats this operation within a constant period while changing the combination of the selected M diode characteristic elements and N diode characteristic elements.

[0017] The reference voltage generating circuit 30 is a circuit that generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22 a and the current density of the current flowing through the second diode characteristic element group 22 b (in other words, the difference between the averaged diode characteristic voltages (i.e., bandgap voltages)), and has a first current source 31 a, a second current source 31 b, a first switch circuit 32, a first resistor element 33 a, a second resistor element 33 b, a second switch circuit 34, and a differential amplifier 35.

[0018] The first current source 31a and the second current source 31b are both variable current sources that have one end connected to the power supply voltage VDD and output currents of the same magnitude according to the output voltage Vo of the differential amplifier 35. The first current source 31a and the second current source 31b output currents of magnitudes adjusted in a direction that applies negative feedback to the differential amplifier 35.

[0019] The first switch circuit 32 is a circuit that periodically switches the current source that supplies current to the first diode characteristic element group 22 a and the current source that supplies current to the second diode characteristic element group 22 b between the first current source 31 a and the second current source 31 b in response to a chopping clock 1 from the timing generation circuit 21.

[0020] The first resistor element 33a and the second resistor element 33b have the same resistance value, and are respectively a current limiting element inserted in a path (hereinafter, this path is also referred to as the “first path”) through which current flows to the first diode characteristic element group 22a via the switch group 25, and a current limiting element inserted in a path (hereinafter, this path is also referred to as the “second path”) through which current flows to the second diode characteristic element group 22b via the switch group 25 and the primary temperature coefficient adjustment circuit 36.

[0021] The differential amplifier 35 has a non-inverting input terminal (first input terminal) and an inverting input terminal (second input terminal) to which a voltage V1 dependent on the current density of the current flowing through the first diode characteristic element group 22a (i.e., a first voltage at a connection point V1 between the first resistor element 33a and the switch group 25) and a voltage V2 dependent on the current density of the current flowing through the second diode characteristic element group 22b (i.e., a second voltage at a connection point V2 between the second resistor element 33b and the primary temperature coefficient adjustment circuit 36) are input via the second switch circuit 34, and amplifies the difference between the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal to output the output voltage Vo. In response to a chopping clock 2 from the timing generation circuit 21, the differential amplifier 35 switches the connection mode of the internal circuit 35a in synchronization with the switching operation of the second switch circuit 34 so that the same amplification operation is performed whether the non-inverting input terminal and the inverting input terminal are functionally swapped or not.

[0022] The second switch circuit 34 is a switch circuit that periodically switches the voltage input to the non-inverting input terminal of the differential amplifier 35 and the voltage input to the inverting input terminal of the differential amplifier 35 between voltage V1 and voltage V2 in response to chopping clock 2 from the timing generation circuit 21.

[0023] The primary temperature coefficient adjustment circuit 36 ​​is a variable resistance element connected in series with the second resistance element 33b, and is adjusted to a resistance value that brings the primary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30 closer to zero.

[0024] The secondary temperature coefficient adjustment circuit 37 is a circuit that adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30, and is composed of two bipolar transistors 37b and 37c connected in series between the power supply voltage VDD and ground, and a current mirror circuit 37a that receives the base current of the bipolar transistor 37b (i.e., 1) as an input and outputs a variable current having a current ratio of 1:k to the connection point V2. The current ratio 1:k of the current mirror circuit 37a is adjusted to a value that brings the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30 closer to zero.

[0025] Next, the operation of the semiconductor device 10 according to this embodiment configured as above will be described.

[0026] First, the overall operation will be described.

[0027] In the first path including the connection point V1, the current output from the first current source 31a or the second current source 31b flows through the first resistor element 33a via the first switch circuit 32, and further flows through the first diode characteristic element group 22a which is composed of a parallel connection of M diode characteristic elements selected by the switch group 25 of the dynamic element matching circuit 23.

[0028] On the other hand, in the second path including the connection point V2, the current output from the second current source 31b or the first current source 31a flows through the second resistor element 33b and the primary temperature coefficient adjustment circuit 36 ​​via the first switch circuit 32, and further flows through the second diode characteristic element group 22b composed of N diode characteristic elements connected in parallel and selected by the switch group 25 of the dynamic element matching circuit 23. Current flows in and out of the connection point V2 to and from the secondary temperature coefficient adjustment circuit 37.

[0029] Here, the voltage V1 at the connection point V1 is the averaged diode characteristic voltage of the first diode characteristic element group 22a, while the voltage V2 at the connection point V2 is the voltage obtained by adding the voltage drop in the primary temperature coefficient adjustment circuit 36 ​​to the averaged diode characteristic voltage of the second diode characteristic element group 22b (the third voltage at the connection point V3).

[0030] Such voltages V1 and V2 are input to the differential amplifier 35 via the second switch circuit 34, and the output voltage Vo from the differential amplifier 35 is negatively fed back to adjust the output currents of the first current source 31a and the second current source 31b.

[0031] The voltage at the connection point between the first switch circuit 32 and the second resistor element 33b is output from the reference voltage generating circuit 30 as a reference voltage VBG and input to the time-discrete filter 40, where voltage fluctuations (noise) caused by the switching operations of the dynamic element matching circuit 23, the first switch circuit 32, and the second switch circuit 34 are suppressed, and the voltage is input to the AD converter 41 as a reference voltage VBG2.

[0032] In the AD converter 41, the reference voltage VBG2 is converted into a digital signal, and the digital signal is subjected to digital signal processing such as moving average in the averaging filter 42, where it is averaged.

[0033] Next, the significance of the primary temperature coefficient adjustment circuit 36 ​​will be explained.

[0034] In the reference voltage generating circuit 30, the magnitudes of the currents output by the first current source 31 a and the second current source 31 b are equal, the resistance values ​​of the first resistor element 33 a and the second resistor element 33 b are equal, and the negative feedback of the differential amplifier 35 causes an imaginary short between the non-inverting input terminal and the inverting input terminal, so that the voltages V1 and V2 are equal, and further, the voltage obtained by adding the voltage drop across the second resistor element 33 b to the voltage V2 becomes the reference voltage VBG. Therefore, the first-order differential component dVBG / dT of the reference voltage VBG with respect to the temperature T is expressed by the following equation 1.

[0035] dVBG / dT=dVf2 / dT+(k / q)・(ln(n)・(R2+R3) / R3) (Formula 1)

[0036] Here, Vf2 is the forward voltage of the second diode characteristic element group 22b, k is Boltzmann's constant, q is elementary charge, ln represents the natural logarithm, n is the current density ratio (here, N / M) between the first diode characteristic element group 22a and the second diode characteristic element group 22b, R2 is the resistance value of the second resistor element 33b, and R3 is the resistance value of the primary temperature coefficient adjustment circuit 36.

[0037] Therefore, by adjusting the resistance value R3 of the primary temperature coefficient adjustment circuit 36 ​​so that the value of the above equation 1 becomes zero, the primary temperature coefficient of the reference voltage VBG can be made zero. For example, when n = 8, R2 = 90 kΩ, and dVf2 / dT = -1.8 mV / °C, the resistance value R3 of the primary temperature coefficient adjustment circuit 36 ​​is 10 kΩ. Note that k / q = 86.17 μV.

[0038] Next, the significance of the secondary temperature coefficient adjustment circuit 37 will be described.

[0039] When the bandgap voltage VBG0 generated by the second diode characteristic element group 22b for generating the reference voltage VBG is expanded with respect to temperature T as VBG0(T), the second derivative with respect to t=ΔT / T0 is obtained as follows: ２ VBG0(t) / dt ２ = 2 a2. Note that the third-order terms and above are ignored because they are negligible within the expected temperature range. Here, T0 is the reference temperature, ΔT is the temperature difference between temperature T and the reference temperature T0, and a2 is the constant of the second-order term in the above series expansion.

[0040] The reference voltage generating circuit 30 outputs a reference voltage VBG(t) in which the quadratic temperature coefficient is cancelled by adding the adjustment current Ic(t) from the quadratic temperature coefficient adjustment circuit 37 to the bandgap voltage VBG0(t). In other words, since VBG(t) can be expressed as VBG0(t)=VBG0(t)-R2·Ic(t), the second-order derivative d ２ VBG(t) / dt ２ is expressed as the following equation 2.

[0041] d ２ VBG(t) / dt ２ =2・a2−R2・d ２ Ic(t) / dt ２ (Formula 2)

[0042] Therefore, by adjusting the adjustment current Ic(t) output from the secondary temperature coefficient adjustment circuit 37 so that the above equation 2 becomes zero when t = 0, that is, when the temperature T is the reference temperature T0 (for example, 27°C = 300K), the secondary temperature coefficient of the reference voltage VBG can be made zero.

[0043] Specifically, when the adjustment current Ic(t) is a current expressed as Ic(t) = C exp(-t) using a constant C, the quadratic temperature coefficient of the reference voltage VBG can be set to zero by setting the adjustment current Ic(t) to satisfy Ic(t) = 2 a2 / (R2 C). Alternatively, the adjustment current Ic(t) may be a current expressed as Ic(t) = C / t using a constant C.

[0044] Next, an example of the operation of the dynamic element matching circuit 23 will be described.

[0045] 3 is a diagram showing the diode characteristic element group 22 and the switch group 25 in FIG. 1. The diode characteristic element group 22 is composed of eight NPN bipolar transistors, each of which has a collector connected to a base, as diode characteristic elements Q1 to Q8, each of which is a power of two (eight in this example). One end (cathode) of each of the eight diode characteristic elements Q1 to Q8 is connected in common (ground in this example).

[0046] The switch group 25 is composed of switches S1 to S8 for connecting the other ends (anodes; collectors and bases of NPN bipolar transistors) of the eight diode-characteristic elements Q1 to Q8 to a connection point V1, and switches T1 to T8 for connecting the other ends to a connection point V3. In the switch group 25, the on / off of the switches S1 to S8 is controlled by control signals S1 to S8 included in the DEM control signal from the switch selection circuit 24, and the on / off of the switches T1 to T8 is controlled by control signals T1 to T8 included in the DEM control signal. As a result, the diode-characteristic element group 22 is divided into a first diode-characteristic element group 22a composed of M diode-characteristic elements connected in parallel, and a second diode-characteristic element group 22b composed of N diode-characteristic elements connected in parallel.

[0047] Furthermore, since the diode characteristic element group 22 is composed of a power-of-two number of diode characteristic elements Q1 to Q8, the frequency divider circuit of the dynamic element matching circuit 23 (particularly, the switch selection circuit 24 that outputs a DEM control signal to the switch group 25) for selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b in the diode characteristic element group 22 can be simplified, and averaging in the time-discrete filter 40, the AD converter 41, and the averaging filter 42 can be facilitated.

[0048] 4 is a timing chart showing an example of operation of the dynamic element matching circuit 23 shown in FIG. In this diagram, "CLK" indicates the clock input to the timing generation circuit 21 in FIG. 1, "S1" to "S8" indicate control signals S1 to S8 that drive the switches S1 to S8, "T1" to "T8" indicate control signals T1 to T8 that drive the switches T1 to T8, a "first diode characteristic element group" indicates diode characteristic elements selected as the first diode characteristic element group 22a, and a "second diode characteristic element group" indicates diode characteristic elements selected as the second diode characteristic element group 22b. In "S1" to "S8" and "T1" to "T8," an H level indicates that the corresponding switch is on, and an L level indicates that the corresponding switch is off.

[0049] As shown in the figure, the on / off of the switches S1 to S8 and T1 to T8 that constitute the switch group 25 is controlled by the control signals S1 to S8 and T1 to T8, so that at the first CLK, the diode-characteristic element Q1 is selected as the first diode-characteristic element group 22a, and the seven diode-characteristic elements Q2 to Q8 other than the diode-characteristic element Q1 are selected as the second diode-characteristic element group 22b; at the second CLK, the diode-characteristic element Q2 is selected as the first diode-characteristic element group 22a, and the seven diode-characteristic elements Q1 and Q3 to Q8 other than the diode-characteristic element Q2 are selected as the second diode-characteristic element group 22b; and similarly, at the eighth CLK, the diode-characteristic element Q8 is selected as the first diode-characteristic element group 22a, and the seven diode-characteristic elements Q1 to Q7 other than the diode-characteristic element Q8 are selected as the second diode-characteristic element group 22b, and the same selection state is repeated for eight CLKs, one cycle of which is one selection state.

[0050] Fig. 5 is a diagram illustrating the transition of the selection state shown in Fig. 4. Fig. 5(a) shows the arrangement positions of the eight diode characteristic elements Q1 to Q8 constituting the diode characteristic element group 22 on the substrate 26 of the semiconductor device 10. Fig. 5(b) shows the transition of the selection state of the diode characteristic elements Q1 to Q8 shown in Fig. 4.

[0051] As can be seen from (b) of FIG. 5, the state transitions are repeated starting from "State 1" in which the diode-characteristic element Q1 is selected as the first diode-characteristic element group 22a and the seven diode-characteristic elements Q2 to Q8 other than the diode-characteristic element Q1 are selected as the second diode-characteristic element group 22b, passing through "State 2," "State 3," ..., and ending at "State 8" in which the diode-characteristic element Q8 is selected as the first diode-characteristic element group 22a and the seven diode-characteristic elements Q1 to Q7 other than the diode-characteristic element Q8 are selected as the second diode-characteristic element group 22b.

[0052] As described above, according to this operation example, the one diode-characteristic element selected as the first diode-characteristic element group 22a and the seven diode-characteristic elements selected as the second diode-characteristic element group 22b are alternated for each clock by the dynamic element matching circuit 23. In either selection state, the number M of diode-characteristic elements selected as the first diode-characteristic element group 22a and the number N of diode-characteristic elements selected as the second diode-characteristic element group 22b are constant (i.e., always 1 and 7, respectively). Furthermore, the number of times each of the diode-characteristic elements Q1 to Q8 is selected as the first diode-characteristic element group 22a and the second diode-characteristic element group 22b in one cycle is the same (1 and 7, respectively).

[0053] This suppresses fluctuations in the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b due to manufacturing variations in the diode characteristic elements Q1 to Q8 and corrects them at regular intervals, thereby suppressing variations between semiconductor devices 10 in the reference voltage VBG generated based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b.

[0054] Furthermore, since temperature-dependent characteristic fluctuations of the first diode characteristic element group 22 a and the second diode characteristic element group 22 b are also suppressed, the adjustment range of the current ratio 1:k provided to the current mirror circuit 37 a included in the secondary temperature coefficient adjustment circuit 37 can be narrowed, or adjustment of the secondary temperature coefficient is no longer necessary. As a result, the circuit size of the secondary temperature coefficient adjustment circuit 37 can be reduced, or the secondary temperature coefficient adjustment circuit 37 can be eliminated altogether, thereby reducing the circuit area of ​​the bandgap reference circuit 20.

[0055] Next, an example of the configuration and operation of a dynamic element matching circuit according to a modified example of this embodiment will be described.

[0056] 6A is a diagram showing a diode-characteristic element group 27 and a switch group 25a according to a modified example. This figure corresponds to FIG. 3 in the embodiment, but in this modified example, the diode-characteristic element group 27 is composed of 16 diode-characteristic elements Q1 to Q16. Furthermore, the switch group 25a is composed of switches S1 to S16 for connecting to the node V1 and switches T1 to T16 for connecting to the node V3, corresponding to the 16 diode-characteristic elements Q1 to Q16.

[0057] Fig. 6B is a timing chart showing an example of operation of the dynamic element matching circuit according to the modified example shown in Fig. 6A. This figure corresponds to Fig. 4 in the embodiment, but in this modified example, the first diode characteristic element group 22a is composed of two diode characteristic elements selected from the 16 diode characteristic elements Q1 to Q16, and the second diode characteristic element group 22b is composed of 14 diode characteristic elements other than the two selected diode characteristic elements.

[0058] 6C is a diagram illustrating the transition of the selection state shown in FIG. 6B. (a) of FIG. 6C is a graph illustrating the base-emitter voltage VBE (vertical axis) of the 16 diode-characteristic elements Q1 to Q16 constituting the diode-characteristic element group 27, depending on their layout on the substrate 26 of the semiconductor device 10 and their placement positions in the X-axis direction (the placement positions in the direction from Q1 to Q4, horizontal axis). (b) of FIG. 6C illustrates the transition of the selection state of the diode-characteristic elements Q1 to Q16 shown in FIG. 6B.

[0059] 6C(a), in this modification, the 16 diode-characteristic elements Q1 to Q16 are formed in a 4×4 rectangular arrangement on the substrate 26. Furthermore, as shown in the graph of FIG. 6C(a), the base-emitter voltage VBE of each diode-characteristic element increases in the direction from left to right in the layout of FIG. 6C(a), depending on the manufacturing process of the semiconductor device 10, etc.

[0060] As can be seen from this figure, in this modification, the positions on the substrate 26 of the two diode-characteristic elements selected as the first diode-characteristic element group 22a are point-symmetric in both selection states. For example, the positions on the substrate 26 of the diode-characteristic elements Q1 and Q13 selected in state 1 are point-symmetric, and the positions on the substrate 26 of the diode-characteristic elements Q2 and Q14 selected in state 2 are point-symmetric.

[0061] Similarly, the positions on the substrate 26 of the 14 diode characteristic elements selected as the second diode characteristic element group 22b are point symmetric in any selected state.

[0062] In this way, when the diode characteristic elements constituting the diode characteristic element group 27 have characteristic dependence on their placement positions, according to the operation example of this modified example, regardless of the selection state, both the first diode characteristic element group 22a and the second diode characteristic element group 22b are composed of diode characteristic elements that are placed in point-symmetric positions, so that the amount of fluctuation in the reference voltage VBG generated in each selection state is suppressed and noise associated with voltage fluctuations between selection states is reduced.

[0063] Fig. 6D is a diagram illustrating transitions in the selection state according to a reference example. Fig. 6D (a) is the same as Fig. 6C (a). Fig. 6D (b) differs from Fig. 6C (b) in that the positions on the substrate 26 of the two diode characteristic elements selected as the first diode characteristic element group 22a and the fourteen diode characteristic elements selected as the second diode characteristic element group 22b are not point-symmetric in any of the selection states.

[0064] In such a reference example, the generated reference voltage VBG varies for each selection state depending on the placement positions on the substrate 26 of the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b, resulting in voltage fluctuations between selection states and generating noise.

[0065] Fig. 7 is a diagram showing the results of a simulation comparing the amount of fluctuation (noise) in the reference voltage VBG between the modified example shown in Fig. 6C and the reference example shown in Fig. 6D. This figure shows the time waveform (Fig. 7(a)) and spectrum (Fig. 7(b)) of the amount of fluctuation (noise) in the reference voltage VBG when one cycle (period) in the selected state is set to 160 μs, assuming the arrangement positions of the diode-characteristic elements Q1 to Q16 and the variations in the base-emitter voltage VBE as shown in Fig. 6C(a) and Fig. 6D(a).

[0066] In (a) and (b) of Figures 7, the solid lines represent a case in which the first diode characteristic element group 22a and the second diode characteristic element group 22b are composed of diode characteristic elements that are positioned symmetrically with respect to a point, as in the modified example shown in Figure 6C, and the dashed lines represent a case in which the first diode characteristic element group 22a and the second diode characteristic element group 22b are composed of diode characteristic elements that are not positioned symmetrically with respect to a point, as in the reference example shown in Figure 6D.

[0067] As can be seen from FIG. 7B, in the case of the reference example, a noise spectrum having multiple peaks including a peak that is maximum at 12.5 kHz is observed, whereas in the case of the modified example, almost no noise is observed.

[0068] From the above, it can be seen that by selecting the first diode characteristic element group 22a and the second diode characteristic element group 22b to be composed of diode characteristic elements that are positioned point-symmetrically on the substrate 26, fluctuations (noise) in the reference voltage VBG that occur between selection states can be suppressed.

[0069] Next, as an example of the operation of the dynamic element matching circuit 23, an example in which randomness is introduced when selecting diode characteristic elements for the first diode characteristic element group 22a and the second diode characteristic element group 22b will be described.

[0070] 8 is a circuit diagram showing an example of the configuration of a switch selection circuit 24a that realizes a dynamic element matching circuit according to a modified example incorporating randomness. The switch selection circuit 24a controls the switch group 25 so that one diode-characteristic element selected randomly from eight diode-characteristic elements Q1 to Q8 is selected as the first diode-characteristic element group 22a, and the remaining seven diode-characteristic elements are selected as the second diode-characteristic element group 22b. The selection state is defined as State 1, and transitions from State 1 to State 8 constitute one cycle. The selection state is randomly changed to control the switch group 25 so that eight cycles of the selection state are repeated.

[0071] The switch selection circuit 24a is composed of a shift register 50 configured by eight sets of two-input selectors and flip-flops (FFs) connected to the outputs of the two-input selectors, connected in series; a counter 51 that outputs a selection control signal to each selector; a pseudo-random number sequence generator 52 that provides a pseudo-random number (P / N code) to one of the selectors; and an inverter 53 that inverts the 8-bit output (control signals S1 to S8) from the shift register 50 and outputs it as control signals T1 to T8.

[0072] Fig. 9A is a timing chart showing the operation of the switch selection circuit 24a shown in Fig. 8. In this diagram, "CLK" is the DEM control clock in Fig. 8, "CNT" is the output signal of the counter 51, "SEL[1:8]" is the selection control signal (8 bits) output by the pseudo-random number sequence generator 52, and "S1" to "S8" are control signals S1 to S8 output from the eight flip-flops that make up the shift register 50. This diagram shows the timing of eight cycles (cycles 1 to 8), with one cycle consisting of transitions from state 1 to state 8.

[0073] In this figure, as shown by the signal waveform of "CNT," the counter 51 outputs an H level in state 1 and an L level in other states. Also, as shown by "SEL[1:8]," the pseudo-random number sequence generator 52 outputs a selection control signal in which one bit out of eight bits is randomly set to an H level every cycle.

[0074] As a result, in each cycle, as indicated by the control signals "S1" to "S8," in state 1, the shift register 50 selects signals SEL1 to SEL8 from the two input signals, and as a result, determines and outputs the start position of one cycle determined by the pseudo-random sequence generator 52, and from state 2 onwards, selects and outputs the output of the previous flip-flop from the two input signals, thereby transitioning through the remaining seven states in order.

[0075] 9B is a diagram showing the diode characteristic elements selected as the first diode characteristic element group 22a by the switch selection circuit 24a shown in FIG. The diagram shows the diode characteristic elements selected as the first diode characteristic element group 22a for cycles 1 to 8, which transition from state 1 to state 8. Note that in each state, the diode characteristic elements selected as the second diode characteristic element group 22b are seven diode characteristic elements excluding the diode characteristic elements selected as the first diode characteristic element group 22a.

[0076] As shown in this figure, in each cycle, the diode characteristic element selected as the first diode characteristic element group 22a is diode characteristic element Q1 in cycle 1, and in cycles 2 to 8, the diode characteristic elements are diode characteristic elements Q7, Q3, Q2, Q8, Q5, Q6, and Q4 selected randomly from among the diode characteristic elements excluding the diode characteristic elements already selected.

[0077] FIG. 10 illustrates the effect of the operation of the dynamic element matching circuit according to the modified example incorporating randomness shown in FIG. 8 . (a) of FIG. 10 is a graph showing the base-emitter voltage VBE (vertical axis) of the eight diode-characteristic elements Q1 to Q8 constituting the diode-characteristic element group 22, depending on their layout positions on the substrate 26 (layout) and their positions in the X-axis direction (horizontal axis). (b) of FIG. 10 is a graph showing the results of a simulation comparing the fluctuation (noise) of the reference voltage VBG between the state transitions of the dynamic element matching circuit according to the embodiment not incorporating randomness shown in FIG. 5 and the state transitions of the dynamic element matching circuit according to the modified example incorporating randomness shown in FIG. 9B . Similar to the simulation results shown in FIG. 7 , the spectrum of the fluctuation (noise) of the reference voltage VBG when one cycle (period) of the selected state is set to 160 μs is shown here. In (b) of Figure 10, the dashed line shows the spectrum during state transition by the dynamic element matching circuit of the embodiment shown in Figure 5 that does not incorporate randomness, and the solid line shows the spectrum during state transition by the dynamic element matching circuit of the modified embodiment that incorporates randomness as shown in Figure 9B.

[0078] As can be seen from FIG. 10(b), in the state transition without incorporating randomness, a large noise peak is observed at 6.25 kHz, whereas in the state transition with incorporating randomness, the intensity of the noise peak is kept small.

[0079] From the above, it can be seen that the dynamic element matching circuit according to the modified example suppresses fluctuations (noise) in the reference voltage VBG that occur between selection states by selecting and combining the diode characteristic elements that make up the first diode characteristic element group 22a and the second diode characteristic element group 22b with randomness.

[0080] Next, as another example of the operation of the dynamic element matching circuit 23, an example in which ΔΣ modulation is adopted when selecting diode characteristic elements for the first diode characteristic element group 22a and the second diode characteristic element group 22b will be described.

[0081] Fig. 11 is a diagram illustrating an example of the configuration of a switch selection circuit 24b that realizes a dynamic element matching circuit according to a modified example that incorporates ΔΣ modulation. Fig. 11(a) is a diagram in which "VBE fluctuation amount (expressed with the center at 0)" has been added to Fig. 10(a). Fig. 11(b) is a circuit diagram showing an example of the configuration of the switch selection circuit 24b.

[0082] As shown in FIG. 11(a), in this example, the target value of the base-emitter voltage VBE corresponds to the center position of the diode characteristic elements Q1 to Q8 in the X-axis direction.

[0083] As shown in FIG. 11B, the switch selection circuit 24 b includes a target value setting circuit 54 , a ΔΣ modulator 55 , a Y-axis selection circuit 56 , a selector 57 , and an inverter 58 .

[0084] The target value setting circuit 54 holds a target value (here, the placement position "0" in the X-axis direction) and outputs it to the ΔΣ modulator 55 to set it. The ΔΣ modulator 55 targets the target value (0) provided by the target value setting circuit 54 and performs ΔΣ modulation in accordance with the DEM control clock to select one of four positions in the X-axis direction (-2, -1, 1, 2) and repeatedly outputs the selected position to the selector 57. The Y-axis selection circuit 56 sequentially selects two placement positions (top row, bottom row) of the diode-characteristic elements Q1 to Q8 in the Y-axis direction and outputs the selected position to the selector 57. The selector 57 selects one diode-characteristic element determined by the outputs from the ΔΣ modulator 55 and the Y-axis selection circuit 56 and outputs control signals S1 to S8 to the switch group 25. The inverter 58 inverts the control signals S1 to S8 from the selector 57 and outputs the resulting control signals T1 to T8 to the switch group 25.

[0085] The switch selection circuit 24b operates in accordance with ΔΣ modulation, so that the frequency of selection of the diode-characteristic element is high at the two positions (−1, 1) in the X-axis direction and low at the two positions (−2, 2), reducing the amount of fluctuation caused by state switching. As a result, noise can be suppressed more effectively than with cyclic selection operation.

[0086] A dynamic element matching circuit having such a switch selection circuit 24b selects the first diode characteristic element group 22a and the second diode characteristic element group 22b in repeated selection of a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b such that the M diode characteristic elements constituting the first diode characteristic element group 22a are swapped in accordance with ΔΣ modulation and the N diode characteristic elements constituting the second diode characteristic element group 22b are swapped in accordance with ΔΣ modulation.

[0087] Therefore, the dynamic element matching circuit according to the modified example incorporating such ΔΣ modulation suppresses fluctuations (noise) in the reference voltage VBG that occur between selection states, just like the dynamic element matching circuit according to the modified example incorporating the above-mentioned randomness.

[0088] Next, another example of the layout of the diode characteristic element group 28 on the substrate 26 will be described.

[0089] 12 is a diagram showing the layout of the diode characteristic element group 28 according to the modified example on the substrate 26. In this diagram, 16 white rectangles located in the center indicate diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b, and 20 hatched rectangles located on the periphery indicate dummy diode characteristic elements that are not selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0090] In other words, in this modified example, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b based on the diode characteristic elements excluding the diode characteristic elements located on the periphery of the diode characteristic element group 28 when viewed in a plan view of the substrate 26.

[0091] In general, diode-characteristic elements located on the periphery of the diode-characteristic element group 28 have greater characteristic variations due to factors such as the density of impurity diffusion during the semiconductor manufacturing process, compared to diode-characteristic elements located in the center. Therefore, according to this modification, the first diode-characteristic element group 22a and the second diode-characteristic element group 22b are configured after excluding diode-characteristic elements with large characteristic variations, and therefore characteristic variations of the selected first diode-characteristic element group 22a and the second diode-characteristic element group 22b are suppressed compared to the normal case in which no non-selected diode-characteristic elements are provided on the periphery.

[0092] Next, an example will be described in which the diode characteristic element group 22 includes the bipolar transistors 37b and 37c included in the secondary temperature coefficient adjustment circuit 37 and is subjected to dynamic element matching.

[0093] 13 is a circuit block diagram showing the configuration of a semiconductor device 10a according to a modified example in which bipolar transistors (i.e., diode characteristic elements) included in a secondary temperature coefficient adjustment circuit are included in the diode characteristic element group as targets of dynamic element matching. The semiconductor device 10a includes a dynamic element matching circuit group 23a instead of the switch group 25 and the diode characteristic element group 22 in the semiconductor device 10 shown in FIG.

[0094] The dynamic element matching circuit group 23a has connection points V1, V2, V3, VDD, and V4 as connection points with the reference voltage generating circuit 30. The connection points V1, V2, V3, and VDD are the same as those shown in FIG. 1. The connection point V4 corresponds to the input terminal IN of the current mirror circuit 37a.

[0095] Fig. 14 is a circuit diagram showing a detailed configuration of the dynamic element matching circuit group 23a in Fig. 13. The dynamic element matching circuit group 23a is composed of ten bipolar transistors Q1 to Q10 and nine switches S20 to S23 and S25 to S29 provided for each of the bipolar transistors Q1 to Q10.

[0096] In this modified example, the DEM control signal from the switch selection circuit 24 allows each of the ten bipolar transistors Q1 to Q10 to be selected as the first diode characteristic element group 22a, as the second diode characteristic element group 22b, or as a bipolar transistor (i.e., a diode characteristic element) included in the secondary temperature coefficient adjustment circuit 37.

[0097] For example, when the bipolar transistor Q1 is selected as the first diode characteristic element group 22a, among the switches S20 to S23 and S25 to S29, only the switches S20, S27 and S29 are turned on, and the other switches are turned off.

[0098] Furthermore, when the bipolar transistor Q1 is selected as the second diode characteristic element group 22b, among the switches S20 to S23 and S252 to S29, only the switches S21, S27 and S29 are turned on, and the other switches are turned off.

[0099] Furthermore, when the bipolar transistor Q1 is selected as the bipolar transistor 37b included in the secondary temperature coefficient adjustment circuit 37, among the switches S20 to S23 and S25 to S29, only the switches S22, S25 and S28 are turned on, and the other switches are turned off.

[0100] Furthermore, when the bipolar transistor Q1 is selected as the bipolar transistor 37c included in the secondary temperature coefficient adjustment circuit 37, among the switches S20 to S23 and S25 to S29, only the switches S23, S26 and S29 are turned on, and the other switches are turned off.

[0101] As described above, in this modified example, the dynamic element matching circuit group 23a selects at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37 from the diode characteristic element group (bipolar transistors Q1 to Q10), in addition to the first diode characteristic element group 22a and the second diode characteristic element group 22b, and repeats this operation within a constant period while changing the combination of the selected M diode characteristic elements, the N diode characteristic elements, and the at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37.

[0102] As a result, not only the diode characteristic element group 22 but also the bipolar transistors 37b and 37c included in the secondary temperature coefficient adjustment circuit 37 are subject to dynamic element matching, so that the adjusted current Ic(t) output from the secondary temperature coefficient adjustment circuit 37 is averaged, the adjustment range of the current ratio 1:k that the current mirror circuit 37a of the secondary temperature coefficient adjustment circuit 37 must have is narrower, and the circuit scale of the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0103] Next, a specific configuration example of the first switch circuit 32 and the second switch circuit 34 included in the semiconductor device 10 according to the embodiment will be described.

[0104] Fig. 15 is a circuit diagram showing a specific example of the configuration of the first switch circuit 32 and the second switch circuit 34 in Fig. 1. The first switch circuit 32 (second switch circuit 34) has two input terminals IN1 and IN2 and two output terminals OUT1 and OUT2, and is composed of four switches 32a to 32d each configured by connecting an N-channel MOS transistor and a P-channel MOS transistor in parallel, and a logic circuit 32e that generates control signals SEL1 and XSEL1 (an inverted signal of SEL1) to be supplied to the gates of the N-channel MOS transistor and the P-channel MOS transistor based on a chopping clock 1 (2) input from the timing generation circuit 21.

[0105] When the control signals SEL1 and XSEL1 are at active levels (e.g., H level and L level, respectively), the input terminals IN1 and IN2 are connected straight to the output terminals OUT1 and OUT2, respectively, while when the control signals SEL1 and XSEL1 are at negative levels (e.g., L level and H level, respectively), the input terminals IN1 and IN2 are cross-connected to the output terminals OUT2 and OUT1, respectively.

[0106] Therefore, the first switch circuit 32 continues to alternately switch between straight and cross connections between the first current source 31 a and the second current source 31 b and the first resistor element 33 a and the second resistor element 33 b based on the chopping clock 1 input from the timing generation circuit 21. As a result, the current source supplying current to the first diode characteristic element group 22 a and the current source supplying current to the second diode characteristic element group 22 b are periodically switched between the first current source 31 a and the second current source 31 b.

[0107] This averages out the variations in output current due to manufacturing variations in the circuit components that make up the first current source 31 a and the second current source 31 b, and reduces the adjustment range in the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37, thereby enabling the circuit scale of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37 to be reduced.

[0108] Similarly, the second switch circuit 34 continues to alternately switch between straight and cross connections between the connection points V1 and V2 and the non-inverting input terminal and inverting input terminal of the differential amplifier 35, based on the chopping clock 2 input from the timing generation circuit 21. Note that the internal circuit 35a of the differential amplifier 35 also switches the connection mode in response to the chopping clock 2 from the timing generation circuit 21, in synchronization with the switching operation of the second switch circuit 34, so that the same amplification operation is performed whether the non-inverting input terminal and the inverting input terminal are functionally swapped or not.

[0109] As a result, the voltage input to the non-inverting input terminal and the voltage input to the inverting input terminal of the differential amplifier 35 are periodically switched between a first voltage that depends on the current density of the current flowing through the first diode characteristic element group 22a and a second voltage that depends on the current density of the current flowing through the second diode characteristic element group 22b.

[0110] This averages out characteristic variations such as offset voltage due to manufacturing variations in the circuit components that make up the differential amplifier 35, and reduces the adjustment range in the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37, thereby enabling the circuit scale of the primary temperature coefficient adjustment circuit 36 ​​and the secondary temperature coefficient adjustment circuit 37 to be reduced.

[0111] Next, a specific configuration example of the discrete time filter 40 included in the semiconductor device 10 according to the embodiment will be described.

[0112] Fig. 16A is a circuit diagram showing a specific example of the configuration of the time-discrete filter 40 in Fig. 1. The time-discrete filter 40 is a filter that smoothes the reference voltage VBG generated by the reference voltage generation circuit 30 and outputs it as a reference voltage VBG2, and is composed of a logic circuit 40a, a switch 40b, and a capacitor 40c.

[0113] The logic circuit 40a outputs a drive signal SW to the switch 40b in synchronization with the filter clock from the timing generation circuit 21, thereby driving the switch 40b to turn on and off. As a result, of the reference voltage VBG input to the switch 40b, only the voltage during the time when the voltage is stable passes through, is smoothed by the capacitor 40c, and is output as the reference voltage VBG2.

[0114] 16B is a timing chart showing the operation of the time-discrete filter 40 shown in Fig. 16A. In this figure, "CLK" indicates the filter clock in Fig. 16A, "S1" to "S8" indicate the control signals S1 to S8 that drive the switches S1 to S8, "chopping clock 1" and "chopping clock 2" indicate the chopping clocks 1 and 2 output by the timing generation circuit 21, respectively, "VBG" indicates the reference voltage VBG generated by the reference voltage generation circuit 30, "SW" indicates the drive signal SW output by the logic circuit 40a of the time-discrete filter 40, and "VBG2" indicates the reference voltage VBG2 output from the time-discrete filter 40.

[0115] 16B, noise occurs in the reference voltage "VBG" due to the on / off of the switches S1 to S8 by the control signals S1 to S8, but the noise is suppressed as shown in the reference voltage "VBG2" by the time discretization (on / off by "SW") by the switch 40b of the time-discrete filter 40 and the capacitor 40c. This makes it possible to shorten the stabilization wait time for the signal to be taken in by the AD converter 41 at the subsequent stage.

[0116] Next, a semiconductor device 10b according to a modification will be described, which includes an averaging filter as an analog signal processing circuit in place of the time-discrete filter 40, AD converter 41, and averaging filter 42 in the embodiment.

[0117] 17A is a circuit block diagram showing the configuration of a semiconductor device 10b according to a modified example, which includes an averaging filter 43 as an analog signal processing circuit in place of the time-discrete filter 40, the AD converter 41, and the averaging filter 42 of the embodiment. The semiconductor device 10b includes an averaging filter 43 as an analog signal processing circuit in place of the time-discrete filter 40, the AD converter 41, and the averaging filter 42 of the semiconductor device 10 shown in FIG.

[0118] Fig. 17B is a circuit diagram showing a detailed configuration of the averaging filter 43 shown in Fig. 17A. The averaging filter 43 is a filter that smoothes the reference voltage VBG generated by the reference voltage generating circuit 30 and outputs it as a reference voltage VBG3, and is composed of a logic circuit 43a, capacitors 43b and 43c, an operational amplifier 43d, and switches 44a to 44e.

[0119] The logic circuit 43a controls the on / off of the switches 44a to 44e in synchronization with the filter clock from the timing generation circuit 21. Specifically, the logic circuit 43a controls the on / off of the switches 44a to 44d so that a state in which the switches 44a and 44c are on and the other switches are off, and a state in which the switches 44b and 44d are on and the other switches are off, are alternately switched on and off. The switch 44e performs a reset operation (i.e., short-circuits and opens) once per dynamic element matching cycle (a cycle in which the diode-characteristic elements Q1 to Q8 are selected).

[0120] As a result, the reference voltage VBG input to the switch 44a is subjected to alternating sampling and integration, undergoes signal processing equivalent to the processing by the time-discrete filter 40, AD converter 41, and averaging filter 42 in the embodiment, and is output as a time-averaged reference voltage VBG3.

[0121] 17C is a diagram showing an example of one cycle in which the averaging filter 43 shown in FIG. 17A performs averaging processing. This diagram shows three examples ((a) to (c)) of combinations of the logic levels of the chopping clocks 1 and 2 output from the timing generation circuit 21 and the diode-characteristic elements selected as part of the first diode-characteristic element group 22a in one cycle in which the averaging filter 43 performs averaging processing.

[0122] In the combination example (a), in one cycle in which the averaging filter 43 performs averaging processing, chopping clock 1 is used for one cycle, chopping clock 2 is used for two cycles, and the cycle in which diode characteristic elements Q1 to Q8 are selected as the first diode characteristic element group 22a is repeated for four cycles.

[0123] In the combination example (b), in one cycle in which the averaging filter 43 performs the averaging process, the chopping clock 1 is repeated for one cycle, the chopping clock 2 is repeated for 16 cycles, and the diode characteristic elements Q1 to Q8 are selected as the first diode characteristic element group 22a for two cycles.

[0124] In the combination example (c), in one cycle in which the averaging filter 43 performs the averaging process, the chopping clock 1 is repeated for 8 cycles, the chopping clock 2 is repeated for 16 cycles, and the diode characteristic elements Q1 to Q8 are selected as the first diode characteristic element group 22a for one cycle.

[0125] In any of the combination examples, the chopping clock 1, the chopping clock 2, and the cycle for selecting the diode-characteristic elements Q1 to Q8 as the first diode-characteristic element group 22a are synchronized, and one period for the averaging process performed by the averaging filter 43 is the least common multiple of the period of the chopping clock 1, the period of the chopping clock 2, and the period for the repetition of the selection of the first diode-characteristic element group 22a and the second diode-characteristic element group 22b by the dynamic element matching circuit 23.

[0126] Therefore, the reference voltage VBG3 output from the averaging filter 43 is averaged for all combinations of the chopping clock 1, the chopping clock 2, and the operation of the dynamic element matching circuit 23, thereby efficiently suppressing variations in elements and circuits (diode characteristic elements, resistive elements, differential amplifiers).

[0127] Note that Figure 17C is an example of one cycle in which the averaging filter 43 shown in Figure 17A performs averaging processing, but instead, it may be an example of one cycle in which the averaging filter 42 shown in Figure 1 performs averaging processing.

[0128] As described above, the bandgap reference circuit 20 according to the above embodiment includes: a diode characteristic element group 22 including a plurality of diode characteristic elements; a dynamic element matching circuit 23 that selects, from the diode characteristic element group 22, a first diode characteristic element group 22a including M diode characteristic elements connected in parallel, where M is an integer equal to or greater than 1, and a second diode characteristic element group 22b including N diode characteristic elements connected in parallel, where N is an integer equal to or greater than M, and repeats this operation within a constant period while changing the combination of the M diode characteristic elements and the N diode characteristic elements to be selected; a reference voltage generation circuit 30 that generates a reference voltage VBG based on the difference between the current density of the current flowing through the first diode characteristic element group 22a and the current density of the current flowing through the second diode characteristic element group 22b; and a secondary temperature coefficient adjustment circuit 37 that adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30.

[0129] As a result, the dynamic element matching circuit 23 generates the reference voltage VBG while switching between the M diode characteristic elements constituting the first diode characteristic element group 22a and the N diode characteristic elements constituting the second diode characteristic element group 22b, thereby averaging the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b, thereby realizing a bandgap reference circuit with reduced characteristic variations. As a result, the adjustment range of the secondary temperature coefficient adjustment circuit 37 can be narrowed, and the circuit size of the secondary temperature coefficient adjustment circuit 37 can be reduced.

[0130] The bandgap reference circuit 20 further includes a first-order temperature coefficient adjustment circuit 36 ​​that adjusts the first-order temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30. This suppresses the first-order temperature coefficient of the generated reference voltage VBG.

[0131] Furthermore, the sum of M and N is a power of 2. This simplifies the digital circuit that generates the combinations of M diode-characteristic elements and N diode-characteristic elements selected by the dynamic element matching circuit 23.

[0132] Furthermore, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b so that the ratio of M to N is the same in each repetition. This suppresses changes in the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b compared to when the ratio of M to N changes, and suppresses noise generated when switching the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0133] Furthermore, the dynamic element matching circuit 23 selects the first diode characteristic element group 22 a and the second diode characteristic element group 22 b such that the number of times that each of the selected diode characteristic elements is selected as the first diode characteristic element group 22 a and the second diode characteristic element group 22 b within a certain period is the same. As a result, the number of times that each of the diode characteristic elements constituting the diode characteristic element group 22 is selected as the first diode characteristic element group 22 a and the second diode characteristic element group 22 b is the same, changes in the characteristics of the first diode characteristic element group 22 a and the second diode characteristic element group 22 b are suppressed, and noise generated when switching the diode characteristic elements constituting the first diode characteristic element group 22 a and the second diode characteristic element group 22 b is suppressed.

[0134] The diode characteristic element group 22 is arranged on a substrate, and the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b so that the arrangement positions of the M diode characteristic elements on the substrate are point-symmetrical and the arrangement positions of the N diode characteristic elements on the substrate are point-symmetrical in a plan view of the substrate. This reduces the dependency of the first diode characteristic element group 22a and the second diode characteristic element group 22b on their arrangement positions, even if the diode characteristic elements constituting the diode characteristic element group 22 have characteristic variations depending on their arrangement positions.

[0135] In the above modification, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b such that, in repeatedly selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b, the M diode characteristic elements constituting the first diode characteristic element group 22a are randomly interchanged and the N diode characteristic elements constituting the second diode characteristic element group 22b are randomly interchanged. This randomly interchanges the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b, thereby suppressing noise generated when switching the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0136] In the above modification, the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b such that, in repeatedly selecting a combination of the first diode characteristic element group 22a and the second diode characteristic element group 22b, the M diode characteristic elements constituting the first diode characteristic element group 22a are swapped in accordance with the ΔΣ modulation and the N diode characteristic elements constituting the second diode characteristic element group 22b are swapped in accordance with the ΔΣ modulation. As a result, the diode characteristic elements selected as the first diode characteristic element group 22a and the second diode characteristic element group 22b are swapped in accordance with the ΔΣ modulation, and noise generated when switching the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b is suppressed.

[0137] In the above modification, the diode characteristic element group 22 is disposed on a substrate, and the dynamic element matching circuit 23 selects the first diode characteristic element group 22a and the second diode characteristic element group 22b from diode characteristic elements excluding diode characteristic elements located on the periphery of the diode characteristic element group 22 in a plan view of the substrate. As a result, the first diode characteristic element group 22a and the second diode characteristic element group 22b are configured after excluding diode characteristic elements with large characteristic variations, and therefore characteristic variations of the selected first diode characteristic element group 22a and second diode characteristic element group 22b are suppressed compared to a normal case in which no unselected diode characteristic elements are provided on the periphery.

[0138] Furthermore, in the above-described modified example, the dynamic element matching circuit group 23a performs an operation of selecting, from the diode characteristic element group (bipolar transistors Q1 to Q10), in addition to the first diode characteristic element group 22a and the second diode characteristic element group 22b, at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37, repeatedly within a certain period while changing the combination of the selected M diode characteristic elements, the N diode characteristic elements, and the at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37. As a result, the at least one diode characteristic element that functions as the secondary temperature coefficient adjustment circuit 37 is also included in the dynamic element matching, so that characteristic variations of the diode characteristic elements that constitute the secondary temperature coefficient adjustment circuit 37 are suppressed and the adjustment range of the secondary temperature coefficient adjustment circuit 37 can be narrowed, thereby enabling the circuit size of the secondary temperature coefficient adjustment circuit 37 to be reduced.

[0139] Furthermore, the bandgap reference circuit 20 according to the embodiment includes a first current source 31 a and a second current source 31 b, a first diode characteristic element receiving a current from one of the first current source 31 a and the second current source 31 b, a second diode characteristic element receiving a current from the other of the first current source 31 a and the second current source 31 b and through which a current with a different current density than that of the first diode characteristic element flows, a reference voltage generation circuit 30 generating a reference voltage VBG based on the difference in current densities, a primary temperature coefficient adjustment circuit 36 ​​adjusting a primary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30, a secondary temperature coefficient adjustment circuit 37 adjusting a secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30, and a first switch circuit 32 periodically switching between the first current source 31 a and the second current source 31 b as the current source supplying a current to the first diode characteristic element and the current source supplying a current to the second diode characteristic element.

[0140] This suppresses variations in the characteristics of the bandgap reference circuit due to differences in characteristics between the first current source 31a and the second current source 31b.

[0141] The bandgap reference circuit 20 according to the embodiment includes a first current source 31 a and a second current source 31 b, a first diode characteristic element that receives a supply of current from one of the first current source 31 a and the second current source 31 b, a second diode characteristic element that receives a supply of current from the other of the first current source 31 a and the second current source 31 b and through which a current of a different current density than that of the first diode characteristic element flows, a reference voltage generation circuit 30 that generates a reference voltage VBG based on the difference in current densities, and a linear temperature coefficient adjustment circuit that adjusts the linear temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30. The reference voltage generating circuit 30 includes an adjustment circuit 36 ​​and a secondary temperature coefficient adjustment circuit 37 that adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generating circuit 30. The reference voltage generating circuit 30 includes a differential amplifier 35 having a first input terminal and a second input terminal to which a first voltage that depends on the current density of a current flowing through a first diode characteristic element and a second voltage that depends on the current density of a current flowing through a second diode characteristic element are input, and a second switch circuit 34 that periodically switches the voltage input to the first input terminal and the voltage input to the second input terminal between the first voltage and the second voltage.

[0142] This suppresses variations in the characteristics of the bandgap reference circuit due to variations in the characteristics of the circuit components that make up the differential amplifier 35.

[0143] The bandgap reference circuit 20 further includes a dynamic element matching circuit 23 that selects, as the first diode characteristic element, a first diode characteristic element group 22a configured of M diode characteristic elements connected in parallel, where M is an integer greater than or equal to 1, from a diode characteristic element group 22 configured of a plurality of diode characteristic elements, and selects, as the second diode characteristic element, a second diode characteristic element group 22b configured of N diode characteristic elements connected in parallel, where N is an integer greater than or equal to 1, from the diode characteristic element group 22, and repeats this operation within a constant period while changing the combination of the selected M diode characteristic elements and N diode characteristic elements.

[0144] This averages the characteristics of the first diode characteristic element group 22a and the second diode characteristic element group 22b, and suppresses noise that occurs when switching the diode characteristic elements that make up the first diode characteristic element group 22a and the second diode characteristic element group 22b.

[0145] Furthermore, the semiconductor device 10 according to the above embodiment includes the bandgap reference circuit 20 and the time-discrete filter 40 that receives the reference voltage VBG output from the bandgap reference circuit 20, the dynamic element matching circuit 23 repeatedly operates in synchronization with a clock signal, and the time-discrete filter 40 performs time-discrete filtering in synchronization with the clock signal. This suppresses noise generation due to switching operations in the dynamic element matching circuit 23, the first switch circuit 32, and the second switch circuit 34.

[0146] Furthermore, the semiconductor device 10b according to the above modification includes the bandgap reference circuit 20 and an averaging filter 43 that receives the reference voltage VBG output from the bandgap reference circuit 20, the dynamic element matching circuit 23 repeatedly operates in synchronization with a clock signal, and the averaging filter 43 performs averaging filtering in synchronization with the clock signal, thereby suppressing noise that occurs when the diode characteristic elements constituting the first diode characteristic element group 22a and the second diode characteristic element group 22b are switched.

[0147] Furthermore, the semiconductor device 10 according to the above embodiment includes the bandgap reference circuit 20 and an AD converter 41 that receives the reference voltage VBG output from the bandgap reference circuit 20, the dynamic element matching circuit 23 repeatedly operates in synchronization with a clock signal, and the AD converter 41 converts the reference voltage VBG into a digital signal in synchronization with the clock signal. This shifts the switching timing in the dynamic element matching circuit 23 from the sampling timing in the AD converter 41, thereby suppressing output errors from the AD converter 41.

[0148] Furthermore, the semiconductor device 10b according to the above modification includes a first current source 31a and a second current source 31b, a diode characteristic element group 22 configured from a plurality of diode characteristic elements, a first diode characteristic element group 22a configured from the diode characteristic element group 22 in which M diode characteristic elements, where M is an integer greater than or equal to 1, are connected in parallel and receive current from one of the first current source 31a and the second current source 31b, and a second diode characteristic element group 22a configured from the diode characteristic element group 22 in which M diode characteristic elements, where N is an integer greater than 2, are connected in parallel and receive current from the other of the first current source 31a and the second current source 31b. a dynamic element matching circuit that periodically selects a second diode characteristic element group that receives a current, while changing the combination of M diode characteristic elements and N diode characteristic elements to be selected; a first switch circuit that periodically switches between a first current source and a second current source; and a current source that periodically switches between a first current source and a second current source. a differential amplifier 35 having a first input terminal and a second input terminal to which a first voltage dependent on the current density of the current flowing through the first diode characteristic element group 22a and a second voltage dependent on the current density of the current flowing through the second diode characteristic element group 22b are input; and a second voltage generator 36 having a first input terminal and a second input terminal to which a first voltage dependent on the current density of the current flowing through the first diode characteristic element group 22a and a second voltage dependent on the current density of the current flowing through the second diode characteristic element group 22b are input. The system includes a reference voltage generation circuit 30 including a switch circuit 34, a secondary temperature coefficient adjustment circuit 37 that adjusts the secondary temperature coefficient of the reference voltage VBG generated by the reference voltage generation circuit 30, and an averaging filter 43 that receives the reference voltage VBG output from the reference voltage generation circuit 30, and the averaging filter 43 averages the reference voltage VBG at a period that is the least common multiple of a fixed period in the operation selected by the dynamic element matching circuit 23, the period in the operation of the first switch circuit 32, and the period in the operation of the second switch circuit 34.

[0149] As a result, the reference voltage VBG is averaged by the averaging filter 43 for each fixed period in the selection operation by the dynamic element matching circuit 23, each period in the operation of the first switch circuit 32, and each period in the operation of the second switch circuit 34, thereby efficiently suppressing noise in the reference voltage VBG.

[0150] While the bandgap reference circuit and semiconductor device according to the present disclosure have been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and modifications, and other forms constructed by combining some of the components of the embodiments and modifications, are also included within the scope of the present disclosure.

[0151] For example, although the bandgap reference circuit 20 according to the above embodiment includes the primary temperature coefficient adjustment circuit 36, the first switch circuit 32, and the second switch circuit 34, these are not necessarily required for the bandgap reference circuit. By including the dynamic element matching circuit 23, a bandgap reference circuit can be realized that has a unique effect not seen in the past of suppressing characteristic variations.

[0152] Furthermore, the bandgap reference circuit 20 according to the above embodiment includes the timing generation circuit 21, the first current source 31 a, and the second current source 31 b, but these components are not necessarily required. These components may be provided outside the bandgap reference circuit 20, and a circuit configuration may be used by these components.

[0153] Furthermore, the first switch circuit 32 and the second switch circuit 34 included in the bandgap reference circuit 20 according to the above embodiment do not necessarily require the dynamic element matching circuit 23 and the diode characteristic element group 22. They may be provided with a first diode characteristic element and a second diode characteristic element through which a current with a different current density from that of the first diode characteristic element flows, instead of the dynamic element matching circuit 23 and the diode characteristic element group 22. In this case, the first diode characteristic element and the second diode characteristic element may be a single diode characteristic element or may be configured by two or more diode characteristic elements connected in parallel.

[0154] The bandgap reference circuit and semiconductor device according to the present disclosure can be used as a bandgap reference circuit and semiconductor device with reduced characteristic variations, for example, as a reference voltage generation circuit used in an AD converter or voltage measuring instrument that requires high precision and high stability.

[0155] 10, 10a, 10b Semiconductor device 20 Bandgap reference circuit 21 Timing generation circuit 22, 27, 28 Diode characteristic element group 22a First diode characteristic element group 22b Second diode characteristic element group 23 Dynamic element matching circuit 23a Dynamic element matching circuit group 24, 24a, 24b Switch selection circuit 25, 25a Switch group 26 Substrate 30 Reference voltage generation circuit 31a First current source 31b Second current source 32 First switch circuit 32a to 32d Switch 32e Logic circuit 33a First resistor element 33b Second resistor element 34 Second switch circuit 35 Differential amplifier 35a Internal circuit 36 ​​Primary temperature coefficient adjustment circuit 37 Secondary temperature coefficient adjustment circuit 37a Current mirror circuit 37b, 37c Bipolar transistor 40 Time discrete filter 40a, 43a Logic circuit 40b, 44a to 44e Switch 40c, 43b, 43c Capacitor 41 AD converter 42, 43 Averaging filter 43d Operational amplifier 50 Shift register 51 Counter 52 Pseudo-random number sequence generator 53, 58 Inverter 54 Target value setting circuit 55 ΔΣ modulator 56 Y-axis selection circuit 57 Selector Q1 to Q16 Diode characteristic element (bipolar transistor) S1 to S16, S20 to S23, S25 to S29, T1 to T16 Switch

Claims

1. a diode characteristic element group including a plurality of diode characteristic elements; a dynamic element matching circuit that selects, from the diode characteristic element group, a first diode characteristic element group configured with M of the diode characteristic elements connected in parallel, where M is an integer equal to or greater than 1, and a second diode characteristic element group configured with N of the diode characteristic elements connected in parallel, where N is an integer equal to or greater than M, and repeats this operation within a constant period while changing the combination of the M of the diode characteristic elements and the N of the diode characteristic elements to be selected; a reference voltage generating circuit that generates a reference voltage based on a difference between a current density of a current flowing through the first diode characteristic element group and a current density of a current flowing through the second diode characteristic element group; a second-order temperature coefficient adjustment circuit for adjusting a second-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit, Bandgap reference circuit.

2. The reference voltage generating circuit further includes a first-order temperature coefficient adjustment circuit for adjusting a first-order temperature coefficient of the reference voltage generated by the reference voltage generating circuit.

2. The bandgap reference circuit of claim 1.

3. The sum of M and N is a power of 2.

3. A bandgap reference circuit according to claim 1 or 2.

4. the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group such that the ratio of M to N is the same value in each of the repetitions.

3. A bandgap reference circuit as claimed in claim 1 or 2.

5. the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group such that the number of times each of the selected diode characteristic elements is selected as the first diode characteristic element group and the second diode characteristic element group within the fixed period is the same.

3. A bandgap reference circuit as claimed in claim 1 or 2.

6. the diode characteristic element group is disposed on a substrate; the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group such that, in a plan view of the substrate, the M diode characteristic elements are arranged at point-symmetric positions on the substrate, and the N diode characteristic elements are arranged at point-symmetric positions on the substrate.

3. A bandgap reference circuit as claimed in claim 1 or 2.

7. the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group such that the M diode characteristic elements are randomly replaced and the N diode characteristic elements are randomly replaced in the repetition.

3. A bandgap reference circuit as claimed in claim 1 or 2.

8. the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group such that the M diode characteristic elements are replaced in accordance with ΔΣ modulation and the N diode characteristic elements are replaced in accordance with ΔΣ modulation during the repetition.

3. A bandgap reference circuit as claimed in claim 1 or 2.

9. the diode characteristic element group is disposed on a substrate; the dynamic element matching circuit selects the first diode characteristic element group and the second diode characteristic element group from among diode characteristic elements excluding diode characteristic elements located on a periphery of the diode characteristic element group in a plan view of the substrate.

3. A bandgap reference circuit as claimed in claim 1 or 2.

10. the dynamic element matching circuit repeats an operation of selecting, from the diode characteristic element group, in addition to the first diode characteristic element group and the second diode characteristic element group, at least one diode characteristic element functioning as the secondary temperature coefficient adjustment circuit, while changing a combination of the selected M diode characteristic elements, the N diode characteristic elements, and the at least one diode characteristic element functioning as the secondary temperature coefficient adjustment circuit, within a constant period.

3. A bandgap reference circuit as claimed in claim 1 or 2.

11. a first current source and a second current source; a first diode characteristic element receiving a current from one of the first current source and the second current source; a second diode characteristic element that is supplied with a current from the other of the first current source and the second current source and through which a current having a different current density flows than that of the first diode characteristic element; a reference voltage generating circuit that generates a reference voltage based on the difference in current density; a first-order temperature coefficient adjustment circuit for adjusting a first-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit; a second-order temperature coefficient adjustment circuit for adjusting a second-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit; a first switch circuit that periodically switches a current source that supplies a current to the first diode characteristic element and a current source that supplies a current to the second diode characteristic element between the first current source and the second current source. Bandgap reference circuit.

12. a first current source and a second current source; a first diode characteristic element receiving a current from one of the first current source and the second current source; a second diode characteristic element that is supplied with a current from the other of the first current source and the second current source and through which a current having a different current density flows than that of the first diode characteristic element; a reference voltage generating circuit that generates a reference voltage based on the difference in current density; a first-order temperature coefficient adjustment circuit for adjusting a first-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit; a second-order temperature coefficient adjustment circuit for adjusting a second-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit, The reference voltage generating circuit includes: a differential amplifier having a first input terminal and a second input terminal to which a first voltage dependent on a current density of a current flowing through the first diode characteristic element and a second voltage dependent on a current density of a current flowing through the second diode characteristic element are input; a second switch circuit that periodically switches a voltage input to the first input terminal and a voltage input to the second input terminal between the first voltage and the second voltage; Bandgap reference circuit.

13. The present invention further includes a dynamic element matching circuit that performs, within a constant period, an operation of selecting, as the first diode characteristic element, a first diode characteristic element group configured with a parallel connection of M diode characteristic elements, where M is an integer equal to or greater than 1, from a diode characteristic element group configured with a plurality of diode characteristic elements, and selecting, as the second diode characteristic element, a second diode characteristic element group configured with a parallel connection of N diode characteristic elements, where N is an integer equal to or greater than 1, from the diode characteristic element group, while changing a combination of the selected M diode characteristic elements and the selected N diode characteristic elements.

13. A bandgap reference circuit according to claim 11 or 12.

14. A bandgap reference circuit according to claim 13; a time-discrete filter that receives the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit repeats the above operation in synchronization with a clock signal; the time-discrete filter performs a time-discrete filtering process in synchronization with the clock signal; Semiconductor device.

15. A bandgap reference circuit according to claim 13; an averaging filter that receives the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit repeats the above operation in synchronization with a clock signal; the averaging filter performs averaging filtering in synchronization with the clock signal; Semiconductor device.

16. A bandgap reference circuit according to claim 13; an AD converter that receives the reference voltage output from the bandgap reference circuit; The dynamic element matching circuit repeats the above operation in synchronization with a clock signal; The AD converter converts the reference voltage into a digital signal in synchronization with the clock signal. Semiconductor device.

17. a first current source and a second current source; a diode characteristic element group including a plurality of diode characteristic elements; a dynamic element matching circuit that selects from the diode characteristic element group a first diode characteristic element group that is composed of M of the diode characteristic elements connected in parallel, where M is an integer equal to or greater than 1, and that receives a current from one of the first current source and the second current source, and a second diode characteristic element group that is composed of N of the diode characteristic elements connected in parallel, where N is an integer equal to or greater than M, and that receives a current from the other of the first current source and the second current source, while changing a combination of the M of the diode characteristic elements and the N of the diode characteristic elements to be selected, within a constant period; a first switch circuit that periodically switches a current source that supplies a current to the first diode characteristic element group and a current source that supplies a current to the second diode characteristic element group between the first current source and the second current source; a reference voltage generating circuit that generates a reference voltage based on a difference between a current density of a current flowing through the first diode characteristic element group and a current density of a current flowing through the second diode characteristic element group, the reference voltage generating circuit including: a differential amplifier having a first input terminal and a second input terminal to which a first voltage dependent on a current density of a current flowing through the first diode characteristic element group and a second voltage dependent on a current density of a current flowing through the second diode characteristic element group are input; and a second switch circuit that periodically switches the voltage input to the first input terminal and the voltage input to the second input terminal between the first voltage and the second voltage; a second-order temperature coefficient adjustment circuit for adjusting a second-order temperature coefficient of the reference voltage generated by the reference voltage generation circuit; an averaging filter that receives the reference voltage output from the reference voltage generating circuit; the averaging filter averages the reference voltage with a period that is the least common multiple of the constant period in the selection operation by the dynamic element matching circuit, the period in the operation of the first switch circuit, and the period in the operation of the second switch circuit. Semiconductor device.