Ceramic electronic component, circuit board, electronic device, and method for manufacturing ceramic electronic component

Abstract

To suppress damage to an element body due to stress applied via an external electrode, a ceramic electronic component according to one aspect comprises: a ceramic in an external shape having a first surface; an internal conductor provided in the ceramic by sandwiching a portion of the ceramic; an external electrode provided on the first surface and connected to the internal conductor; and a first surface portion of the ceramic which is located on the first surface side and contains a first element for improving the sinterability of the ceramic higher in concentration than that in the portion of the ceramic sandwiched by the internal conductor.

Description

Ceramic electronic component, circuit board, electronic device, and method for manufacturing ceramic electronic component

[0001] The present invention relates to a ceramic electronic component, a circuit board, an electronic device, and a method for manufacturing a ceramic electronic component.

[0002] In order to reduce the mounting area and height of ceramic electronic components, there are methods in which an external electrode is provided only on one surface of the ceramic electronic component that will be the mounting surface, or an external electrode is provided that extends to a second surface adjacent to the one surface (Patent Documents 1 and 2).

[0003] Japanese Patent No. 6816817 Japanese Patent Application Laid-Open No. 2015-201612

[0004] However, when external electrodes are provided on only one surface of a ceramic electronic component that serves as a mounting surface, or on two surfaces including a second surface adjacent to the mounting surface, the element body is prone to damage due to stress acting via the external electrodes after the ceramic electronic component is mounted. Therefore, an object of the present invention is to prevent damage to the element body due to stress acting via the external electrodes.

[0005] In order to solve the above problem, a ceramic electronic component according to one embodiment of the present invention comprises a ceramic having an outer shape with a first surface, an internal conductor disposed within the ceramic sandwiching a portion of the ceramic, an external electrode disposed on the first surface and connected to the internal conductor, and a first surface portion of the ceramic located on the first surface side, the first surface portion containing a first element that improves the sinterability of the ceramic at a concentration higher than the concentration in the portion of the ceramic sandwiched between the internal conductors.

[0006] In a ceramic electronic component according to another aspect of the present invention, the first element is one or more elements selected from Ni, Mn, Sn, Mg, Ba, Zn, Si, B, Al, Cu, Li, Ca, Zr, In, and Ti. The first element is a component different from a main component of the ceramic material. In a ceramic electronic component according to another aspect of the present invention, the first surface portion contains the first element at a concentration of 0.4 at. % or more.

[0007] A ceramic electronic component according to a preferred embodiment of the present invention further includes an outer surface portion located on a surface other than the first surface in the outer shape, the outer surface portion having a concentration of the first element that is 0.87 to 1.21 times the concentration of the first element in the first surface portion.

[0008] In a ceramic electronic component according to another aspect of the present invention, the internal conductor is made of a material containing the first element, and the first surface portion contains a second element different from the first element that promotes diffusion of the first element. In a ceramic electronic component according to another aspect of the present invention, the second element is at least one of Sn and Fe.

[0009] In addition, in a ceramic electronic component according to one aspect of the present invention, the external electrodes are made of multiple layers including a conductive resin layer.A circuit board according to one aspect of the present invention includes any of the ceramic electronic components described above and a substrate on which the ceramic electronic component is mounted via solder.

[0010] An electronic device according to one aspect of the present invention includes the circuit board described above. A method for manufacturing a ceramic electronic component according to one aspect of the present invention includes the steps of: forming a ceramic having an outer shape with a first surface; forming internal conductors within the ceramic to sandwich a portion of the ceramic; forming external electrodes on the first surface and connected to the internal conductors; and forming a first surface portion of the ceramic located on the first surface side, the first surface portion containing a first element that improves the sinterability of the ceramic at a higher concentration than the concentration in the portion of the ceramic sandwiched between the internal conductors.

[0011] According to a method for manufacturing a ceramic electronic component of one aspect of the present invention, the step of forming the first surface portion includes forming the first surface portion from a material to which the first element is added at a concentration higher than the concentration in a portion sandwiched between the internal conductors. Also, according to a method for manufacturing a ceramic electronic component of one aspect of the present invention, the step of forming the internal conductor includes forming the internal conductor from a material containing the first element, and the step of forming the first surface portion includes forming the first surface portion from a material containing a second element that promotes diffusion of the first element, and firing the ceramic causes the first element to diffuse from the internal conductor into the first surface portion.

[0012] According to the present invention, damage to the element body due to stress applied via the external electrodes can be suppressed.

[0013] 1 is a perspective view showing an example of the configuration of a capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1; FIG. 3 is a cross-sectional view taken along line B-B in FIG. 1; FIG. 4 is a flowchart showing an example of a method for manufacturing a capacitor according to the first embodiment; FIG. 5 is a view showing a coating step in the method for manufacturing a capacitor; FIG. 6 is a view showing a printing step in the method for manufacturing a capacitor; FIG. 7 is a view showing a pattern of an electrode layer; FIG. 8 is a first view showing a molding step in the method for manufacturing a capacitor; FIG. 9 is a second view showing a molding step in the method for manufacturing a capacitor; FIG. 10 is a view showing a pressure bonding step in the method for manufacturing a capacitor; FIG. 11 is a view showing a cutting step in the method for manufacturing a capacitor; FIG. 12 is a first view showing a margin attachment step in the method for manufacturing a capacitor; FIG. 13 is a second view showing the margin attachment step in the method for manufacturing a capacitor; FIG. 14 is a view showing an element body obtained in the binder removal step; FIG. 15 is a cross-sectional view showing the configuration of a circuit board on which a capacitor according to the first embodiment is mounted; FIG. 16 is a table showing test results in examples; FIG. 17 is a perspective view showing the configuration of a ceramic electronic component according to a second embodiment.

[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all of the combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be modified or changed as appropriate depending on the specifications of the device to which the present invention is applied and various conditions (such as usage conditions and usage environment).

[0015] The technical scope of the present invention is defined by the claims and is not limited by the following individual embodiments. The drawings used in the following description may differ in scale and shape from the actual structure to make each configuration easier to understand. Components shown in the drawings described earlier may be referenced as appropriate in the description of the drawings that follow.

[0016] 1 to 3 are diagrams showing an example of the configuration of a capacitor according to one embodiment of the present invention. Fig. 1 shows a perspective view with a portion in cross section, Fig. 2 shows a cross section taken along line A-A in Fig. 1, and Fig. 3 shows a cross section taken along line B-B in Fig. 1. In this embodiment, a capacitor 1 is used as an example of an electronic component.

[0017] Capacitor 1 is a so-called multilayer ceramic capacitor. Capacitor 1 is mounted on a mounting substrate and is used to remove noise from a semiconductor chip mounted on the mounting substrate. Capacitor 1 includes an element body 2 and external electrodes 6A and 6B. Element body 2, which includes an internal conductor and ceramic, includes a laminate 2A, cover layers 5A and 5B, and margin layers 5C, 5D, 5E, and 5F as part of the ceramic.

[0018] In this specification, unless otherwise understood in the context, directions are described based on the "DL axis" direction, "DW axis" direction, and "DH axis" direction in FIG. 1 , and are referred to as the "length" direction, "width" direction, and "height" direction, respectively. The shapes of the element body 2 and the laminate 2A are preferably approximately rectangular parallelepiped for purposes such as ease of manufacturing and improved packaging density. The corners of the element body 2 may be chamfered along the ridges of the element body 2. The element body 2 has a first surface M1 and a second surface M2 facing away from each other, and the first surface M1 is the mounting surface that faces the substrate when the capacitor 1 is mounted on the substrate. The first surface M1 may be referred to as the bottom surface of the element body 2, and the second surface M2 may be referred to as the top surface of the element body 2.

[0019] The laminate 2A includes internal electrode layers 3A and 3B, which are an example of internal conductors, and a dielectric layer 4, which is a part of ceramic. The internal electrode layers 3A and 3B and the dielectric layer 4 are layers extending in the width direction DW and the height direction DH. The laminate 2A has a structure in which the internal electrode layers 3A and 3B and the dielectric layer 4 are alternately stacked in the length direction DL. Focusing on the internal electrode layers 3A and 3B, two types of internal electrode layers 3A and 3B are stacked alternately. Note that, although FIGS. 1 to 3 show an example in which a total of 10 internal electrode layers 3A and 3B are stacked, the number of stacked internal electrode layers 3A and 3B is not particularly limited.

[0020] The cover layers 5A and 5B are provided on both ends of the laminate 2A in the stacking direction (length direction DL). The margin layers 5C, 5D, 5E, and 5F are provided on each of the four sides of the laminate 2A perpendicular to the stacking direction (length direction DL). In other words, the laminate 2A is sandwiched between the cover layers 5A and 5B and surrounded by the margin layers 5C, 5D, 5E, and 5F.

[0021] However, among the margin layers 5C, 5D, 5E, and 5F, the margin layer 5E located on the first surface M1 side of the element body 2 is provided in a location corresponding to a part of the first surface M1, and the internal electrode layers 3A and 3B are drawn to the first surface M1 in locations where the margin layer 5E is not provided. That is, each of the internal electrode layers 3A and 3B is provided with drawn portions RA and RB located on the first surface M1 side of the element body 2.

[0022] The external electrodes 6A, 6B are positioned in parallel on the first surface M1 while being separated from each other in the width direction DW. The spacing between the external electrodes 6A, 6B in the width direction DW is, for example, 110 μm or more. The internal electrode layers 3A, 3B are connected to the external electrodes 6A, 6B on the first surface M1. Specifically, one internal electrode layer 3A of the two types of internal electrode layers 3A, 3B is connected to one external electrode 6A of the two external electrodes 6A, 6B via a lead portion RA. The other internal electrode layer 3B is connected to the other external electrode 6B via a lead portion RB.

[0023] By arranging the external electrodes 6A, 6B on the first surface M1 of the element body 2, the external electrodes 6A, 6B are prevented from protruding in the height direction DH or from overhanging in the width direction DW and length direction DL. This reduces the mounting area of ​​the capacitor 1 while reducing the height of the capacitor 1. Furthermore, it becomes possible to mount the capacitor 1 using LSC (Land-Side Capacitor) mounting, improving the mounting density. The external electrodes 6A, 6B may be arranged on two surfaces, including a second surface adjacent to the first surface M1 of the element body 2. When the external electrodes 6A, 6B are arranged on two surfaces of the element body 2, the mounting strength of the capacitor 1 is improved compared to when the external electrodes 6A, 6B are arranged on only one surface.

[0024] Each of the external electrodes 6A, 6B includes an underlayer 7 formed on the first surface M1 of the element body 2 and a plating layer 9 laminated on the underlayer 7. The underlayers 7 are formed on the first surface M1 of the element body 2 in parallel along the length direction DL while being separated from each other in the width direction DW. The conductive material of the underlayer 7 is mainly composed of a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn, for example.

[0025] The underlayer 7 may contain a common material mixed with a metal. The common material, when mixed in the form of islands in the underlayer 7, can reduce the difference in thermal expansion coefficient between the element body 2 and the underlayer 7 and relieve stress on the underlayer 7. The common material is, for example, a ceramic component that is the main component of the dielectric layer 4. The underlayer 7 may also contain a glass component. When the glass component is mixed into the underlayer 7, it can densify the underlayer 7. The glass component is, for example, an oxide of Ba, Sr, Ca, Zn, Al, Si, or B (boron).

[0026] The base layer 7 may be composed of a sintered body of a coating film containing a dielectric material. This ensures adhesion between the element body 2 and the base layer 7 while increasing the thickness of the base layer 7, thereby ensuring the strength of each external electrode 6A, 6B and electrical continuity with the internal electrode layers 3A, 3B. The base layer 7 may be a conductive resin layer. If the base layer 7 is a conductive resin layer, stress acting on the external electrodes 6A, 6B is dispersed via the solder, suppressing damage to the element body 2 due to stress.

[0027] The plating layer 9 is continuously formed for each external electrode 6A, 6B so as to cover the base layer 7. At this time, the plating layer 9 is electrically connected to the internal electrode layers 3A, 3B via the base layer 7. The plating layer 9 is also electrically connected to the terminals of the mounting board via solder. The material of the plating layer 9 is, for example, a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn. The plating layer 9 may be a plating layer of a single metal component, or may be a plurality of plating layers of different metal components.

[0028] The plating layer 9 has a three-layer structure, for example, of a Cu plating layer formed on the underlayer 7, a Ni plating layer formed on the Cu plating layer, and a Sn plating layer formed on the Ni plating layer. The Cu plating layer can improve the adhesion of the plating layer 9 to the underlayer 7. The Ni plating layer can improve the heat resistance of the external electrodes 6A, 6B during soldering. The Sn plating layer can improve the wettability of the plating layer 9 with solder.

[0029] The thickness of each of the internal electrode layers 3A, 3B and the dielectric layer 4 in the stacking direction is, for example, within a range of 0.05 μm to 5 μm, e.g., 0.3 μm. The material of the internal electrode layers 3A, 3B is mainly composed of a highly conductive metal, and may be, for example, a metal or alloy containing at least one selected from Cu, Fe, Zn, Al, Ni, Pt, Pd, Ag, Au, and Sn.

[0030] The material of the dielectric layer 4 may be, for example, primarily composed of a ceramic material having a perovskite structure. The primary component may be present at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 may be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, and calcium zirconate titanate.

[0031] The cover layers 5A, 5B and margin layers 5C to 5F are mainly made of a ceramic material, for example, which may be the same as the ceramic material of the dielectric layer 4.

[0032] Of the margin layers 5C to 5F, the margin layer 5E located on the first surface M1 side contains an element (first element) that improves the sinterability of the ceramic. The first element is, for example, one or more elements selected from Ni, Mn, Sn, Mg, Ba, Zn, Si, B, Al, Cu, Li, Ca, Zr, In, and Ti. The concentration of the first element is higher in the margin layer 5E than in the dielectric layer 4.

[0033] After mounting, damage to the element body 2 due to stress applied via the external electrodes of the capacitor 1 is likely to occur on the first surface M1 side. By including the first element in the margin layer 5E located on the first surface M1 side at a concentration higher than the concentration in the dielectric layer 4, densification is promoted and damage to the element body 2 is suppressed. In particular, when the first element is Ni, it is desirable for it to be included in the margin layer 5E on the first surface M1 side at a concentration of 0.4 at. % or more.

[0034] The first element may be added in advance to the material for forming the margin layer 5E, or may be contained in the material for the internal electrode layers 3A and 3B and diffused into the margin layer 5E. When the first element diffuses from the internal electrode layers 3A and 3B into the margin layer 5E, it is preferable that the margin layer 5E contain an element (second element) that promotes the diffusion of the first element. The second element is, for example, at least one of Sn and Fe.

[0035] Of the margin layers 5C to 5F, it is desirable that the margin layer 5F located on the second surface M2 side also contains the first element. It is desirable that the concentration of the first element in the margin layer 5E on the first surface M1 side be 0.87 times or more and 1.21 times or less than the concentration of the first element in the margin layer 5F on the second surface M2 side. By including the first element in the margin layer 5F on the second surface M2 side at this ratio, the difference in color between the margin layer 5E on the first surface M1 side and the margin layer 5F on the second surface M2 side is suppressed, reducing the number of defective judgments during visual inspection. In particular, when the first element is Ni, it is desirable that it be included in the margin layer 5F on the second surface M2 side at a concentration of 0.5 at. % or less. If a large amount of the first element is added, the margin layer 5F becomes too hard, which may make the chip more susceptible to cracking or chipping during plating. For example, in the case of the capacitor 1 according to the first embodiment, the exposed area of ​​the element body 2 that is not covered by the external electrodes 6A, 6B is larger than in conventional capacitors, and therefore cracks and chips are more likely to occur due to stress applied to the external electrodes 6A, 6B. For this reason, it is particularly desirable in the structure of the capacitor 1 according to the first embodiment, for example, to densify the margin layer 5F to an extent that damage due to stress applied to the external electrodes 6A, 6B can be suppressed by adjusting the concentration of the first element in the margin layer 5F as described above.

[0036] Fig. 4 is a flowchart showing an example of a method for manufacturing a capacitor according to the first embodiment. Figs. 5 to 14 are diagrams showing an example of a method for manufacturing a capacitor according to the first embodiment. Figs. 5, 6, 10, 11, and 14 show cross-sectional views, Fig. 7 shows a plan view, and Figs. 8 and 9 show perspective views. Figs. 12(A) and 13(A) show plan views, and Figs. 12(B) and 13(B) show perspective views. For convenience of illustration, the number of layers of the internal electrodes is not shown accurately.

[0037] In the blending step (S1) of FIG. 4 , an organic solvent and an organic binder serving as a dispersant and a molding aid are added to a dielectric material powder, which is then pulverized and mixed to produce a mud-like slurry. The dielectric material powder may include, for example, ceramic powder. The dielectric material powder may also include an additive. The additive may be, for example, an oxide or glass of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder may be, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent may be, for example, ethanol or toluene.

[0038] Next, in the coating step (S2) of Fig. 4, as shown in Fig. 5, a slurry containing ceramic powder is applied in the form of a sheet onto a carrier film and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry is applied using a doctor blade method, a die coater method, a gravure coater method, or the like.

[0039] Next, in the printing step (S3) of Fig. 4, the conductive paste for internal electrodes is applied to the green sheet 24 in a predetermined pattern, as shown in Fig. 6, to form a precursor of the electrode-containing layer 23. At this time, as shown in Fig. 7, the precursor of the electrode-containing layer 23 is formed with precursors of the electrode portions 23a in the predetermined pattern and precursors of the margin portions 23b in a pattern opposite to the predetermined pattern (i.e., a pattern that complements the predetermined pattern to form a continuous electrode-containing layer 23). The precursor of the electrode-containing layer 23 is formed with precursors of the electrode portions 23a and precursors of the margin portions 23b in a continuous pattern that corresponds to a plurality of element bodies 2 that will be cut along cut lines CL in a later step.

[0040] The conductive paste for the internal electrodes of the electrode portion 23a contains powder of the metal used as the material for the internal electrode layers 3A, 3B. For example, if the metal used as the material for the internal electrode layers 3A, 3B is Ni, the conductive paste for the internal electrodes contains Ni powder. The conductive paste for the internal electrodes also contains a binder, a solvent, and, if necessary, an auxiliary. The conductive paste for the internal electrodes may contain, as a co-material, the ceramic material that is the main component of the dielectric layer 4. The conductive paste for the internal electrodes is applied by screen printing, inkjet printing, gravure printing, or the like.

[0041] The margin portion 23b is a portion where a slurry similar to the slurry for the green sheet 24 is applied and dried. However, the slurry for the margin portion 23b contains at least one of a first element and a second element. If the slurry for the margin portion 23b contains the first element but not the second element, the concentration of the first element in the slurry for the margin portion 23b is higher than the concentration of the first element in the green sheet 24. If the slurry for the margin portion 23b contains the second element, the internal electrode conductive paste for the electrode portion 23a contains the first element. Furthermore, the slurry for the margin portion 23b contains a second element in an amount sufficient to sufficiently promote diffusion of the first element so that the concentration of the first element in the margin portion 23b is higher than the concentration in the green sheet 24.

[0042] Next, in the molding step (S4) of Fig. 4, a plurality of green sheets 24 are stacked with the positions of the electrode portions 23a and the margin portions 23b alternately shifted, as shown in Fig. 8. Furthermore, in the molding step, green sheets 24 on which the electrode-containing layers 23 are formed and green sheets 25 for outer layers on which the electrode-containing layers 23 are not formed are stacked to form a laminated block, as shown in Fig. 9. Note that although Figs. 8 and 9 show a portion corresponding to one element body 2, in reality, a continuous pattern corresponding to a plurality of element bodies 2 is formed.

[0043] Next, in the pressure-bonding step (S5) of Fig. 4, the laminated block is pressed to pressure-bond the electrode layer 23 and the green sheets 24 and 25 as shown in Fig. 10. As a method for pressing the laminated block, for example, a method in which the laminated block is sandwiched between resin films and isostatically pressed is used.

[0044] Next, in the cutting step (S6) of Fig. 4, the pressed laminated block is cut along cut lines CL and singulated into rectangular parallelepiped block pieces 2B, as shown in Fig. 11. Each singulated block piece 2B corresponds to a combination of the laminate 2A, the cover layers 5A and 5B, and the margin layer 5E on the first surface M1 side. The cut lines CL shown in Fig. 11 are located at the same positions as the cut lines CL shown in Fig. 7. For example, a method such as blade dicing is used to cut the laminated block.

[0045] Next, in the margin attachment step (S7) of Fig. 4, a margin green sheet 26 is attached to the individual block pieces 2B as shown in Fig. 12 or 13. Plan views are shown in Fig. 12(A) and Fig. 13(A), and perspective views are shown in Fig. 12(B) and Fig. 13(B). The margin green sheet 26 is attached to three sides of the block piece 2B, for example, by three-side attachment as shown in Fig. 12 or by roll attachment as shown in Fig. 13.

[0046] In the three-side pasting shown in Fig. 12, a margin green sheet 26 cut to the size of each side is pasted onto the block piece 2B. In the roll pasting shown in Fig. 13, the margin green sheet 26 is pasted so as to wrap around the block piece 2B from one corner 27A through three sides to the other corner 27B. The margin green sheet 26 is then cut at the location of the other corner 27B.

[0047] The material of the margin green sheet 26 may be, for example, the same material as that of the green sheet 24 for the dielectric layer 4 or the margin portion 23b. Next, in the binder removal step (S8) of Fig. 4, the binder contained in the block piece 2B to which the margin green sheet 26 is attached is removed by heating. In the binder removal step, for example, N ２The element body is heated in the atmosphere. By the binder removal step, an element body 2 having margin layers 5C to 5F is obtained as shown in FIG.

[0048] Next, in the base coating step (S9) of FIG. 4 , a conductive paste for the base layer is applied to the first surface M1 of the element body 2 and dried. The conductive paste for the base layer is applied by, for example, a dipping method. The conductive paste for the base layer contains a powder or filler of the metal used as the conductive material for the base layer 7. For example, if the metal used as the conductive material for the base layer 7 is Cu, the conductive paste for the base layer contains Cu powder or filler. The conductive paste for the base layer may also contain, for example, a glass component as a co-material. The conductive paste for the base layer also contains a binder and a solvent.

[0049] 4, the element body coated with the conductive paste for the base layer is fired to integrate the internal electrode layers 3A, 3B with the dielectric layer 4, and also to integrate the base layer 7 with the element body 2. The element body and the conductive paste for the base layer are fired, for example, in a firing furnace at 1000 to 1400°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A, 3B, firing is performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B.

[0050] 4 , a Cu layer, a Ni layer, and a Sn layer are sequentially formed by plating on the underlayer 7 to form a plating layer 9, thereby obtaining the capacitor 1. In the plating step, for example, the element body 2 on which the underlayer 7 has been formed is placed in a barrel together with a plating solution, and the barrel is rotated and an electric current is applied to form the plating layer 9.

[0051] 15 is a cross-sectional view showing the configuration of a circuit board on which the capacitor according to the first embodiment is mounted. The circuit board 10 includes a first substrate 41 and a second substrate 45. The circuit board 10 is included in a variety of electronic devices. Examples of electronic devices that include the circuit board 10 include automotive electrical components, servers, board computers, and various other electronic devices.

[0052] Land electrodes 42A, 42B, 44A, and 44B are formed on the back surface of the first substrate 41. The capacitor 1 is connected to the land electrodes 42A and 42B for mounting the capacitor via solder layers 43A and 43B attached to the plating layers 9 of the external electrodes 6A and 6B, respectively. Solder balls 47A and 47B, for example, are formed on the other land electrodes 44A and 44B on the back surface of the first substrate 41.

[0053] For example, a semiconductor chip (not shown) is mounted on the front surface side of the first substrate 41. This semiconductor chip may be a microprocessor, a semiconductor memory, an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit).

[0054] By mounting capacitor 1 on the back surface side of first substrate 41, capacitor 1 is disposed on the back surface side of the semiconductor chip mounted on the front surface side of first substrate 41. This makes it possible to mount capacitor 1 in close proximity to the semiconductor chip mounted on the front surface side of first substrate 41, effectively eliminating noise applied to the semiconductor chip.

[0055] Land electrodes 46A and 46B are formed on the back surface of the second substrate 45. The first and second substrates 41 and 45 are connected to each other via solder balls 47A and 47B. The second substrate 45 is used, for example, as a motherboard on which the first substrate 41 is mounted. A constant distance is maintained between the first and second substrates 41 and 45 via the solder balls 47A and 47B. Furthermore, a resin 48 that seals the capacitor 1 is filled between the first and second substrates 41 and 45. This resin 48 may be, for example, an epoxy resin. After the first and second substrates 41 and 45 are connected to each other via the solder balls 47A and 47B, the resin 48 may be injected between the substrates 41 and 45 and cured. The resin 48 covers the capacitor 1, the solder layers 43A and 43B, and the solder balls 47A and 47B, and is in close contact with the top surface of the element body 2.

[0056] Arranging the external electrodes 6A, 6B on the first surface M1 of the element body 2 prevents the external electrodes 6A, 6B from protruding in the height direction DH and prevents the solder layers 43A, 43B from wetting up onto the capacitor 1, thereby reducing the height of the mounted capacitor 1. This allows the capacitor 1 to be accommodated in the gap between the substrates 41, 45 connected to each other via the solder balls 47A, 47B, achieving LSC mounting. The external electrodes 6A, 6B may be arranged on two surfaces, including the second surface adjacent to the first surface M1 of the element body 2, which improves the mounting strength of the capacitor 1 compared to arrangement on only one surface.

[0057] Furthermore, even if stress is concentrated on the element body 2 through the external electrodes 6A, 6B after the capacitor 1 is mounted, damage to the element body 2 is suppressed by promoting the density of the margin layer 5E on the first surface M1 side of the element body 2.

[0058] EXAMPLES Examples in which specific values ​​are applied to the capacitor 1 of the above-described embodiment will be described below.

[0059] Fig. 16 is a table showing test results for the examples. Fig. 16 shows test results for three comparative examples and six examples. In the comparative examples and examples shown in Fig. 16, Ni is used as an example of the first element, and Ni is contained in the internal electrode layers 3A and 3B.

[0060] 16, the amount of Ni added in the margin layer 5E on the first surface side of the element body 2 is described as "addition amount A," and the amount of Ni added in the margin layer 5F on the second surface side of the element body 2 is described as "addition amount B." Also, the amount of Ni diffused in the margin layer 5E on the first surface side is described as "diffusion amount A," the amount of Ni diffused in the margin layer 5F on the second surface side is described as "diffusion amount B," and the amount of Ni diffused in the dielectric layer 4 is described as "diffusion amount C." The ratio of the diffusion amount A to the diffusion amount B is described as the "A / B ratio."

[0061] Here, the diffusion amount means the total amount of Ni, including Ni diffused from the internal electrode layers 3A and 3B and added Ni. The added amount and diffusion amount are expressed as the concentration of Ni atoms relative to all atoms in at. %.

[0062] 16 also shows an evaluation of crack occurrence in a strength test in which distortion after mounting is assumed (post-mount crack evaluation), an evaluation of crack occurrence in plating using bulk (plating crack evaluation), and an evaluation of defects in appearance inspection (appearance defect evaluation). These evaluations are indicated by the symbols "x", "o", and "◎", with an occurrence rate of 0% being evaluated as "◎", an occurrence rate of less than 5% being evaluated as "o", and an occurrence rate of 5% or more being evaluated as "x".

[0063] In all three comparative examples, the additive amount A is "0", the diffusion amount A is the concentration of only Ni diffused from the internal electrode layers 3A and 3B, and the diffusion amount A in the three comparative examples is approximately the same value as the diffusion amount C. Therefore, in all three comparative examples, the density of the margin layer 5E on the first surface side is low, and the post-mount crack evaluation is "x".

[0064] In Comparative Example 1, the additive amount B is also "0", and the diffusion amount B is also approximately the same value as the diffusion amount C, so the "A / B ratio" is "1.09". Therefore, the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side is small, and the appearance defect evaluation is "◎". In addition, the crack evaluation during plating is also "◎".

[0065] In Comparative Example 2, the additive amount B was "0.2" and the "A / B ratio" was "0.87." As a result, the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side was suppressed, and the appearance was evaluated as "good." In Comparative Example 3, the additive amount B was "0.4" and the "A / B ratio" was "0.67." As a result, the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side was large, and the appearance was evaluated as "poor."

[0066] On the other hand, in Example 1, the additive amount A is "0.2" and the additive amount B is "0", so that the diffusion amount A is greater than the diffusion amount C by 0.1 at. % or more, and the diffusion amount B is not significantly different from the diffusion amount C. As a result, the crack evaluation after mounting was "◎", and the crack evaluation during plating was also "◎". In Example 1, the "A / B ratio" was "1.41", so there was a large difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side, and the appearance defect evaluation was "×".

[0067] In Example 2, the additive amount A is "0.6" and the additive amount B is "0.4", so that the diffusion amount A is nearly double the diffusion amount C, and the diffusion amount B is also greater than the diffusion amount C by 0.1 at. % or more. As a result, the crack evaluation after mounting was "◎", and the crack evaluation during plating was "◯". Since the "A / B ratio" of Example 2 is "1.38", which is close to Example 1, the appearance defect evaluation was "×", as in Example 1.

[0068] In Example 3, the additive amount A is "0.2" and the additive amount B is also "0.2", the diffusion amount A is greater than the diffusion amount C by 0.1 at. % or more, and the diffusion amount B is greater than the diffusion amount C by 0.07 at. % or more. As a result, the crack evaluation after mounting was "◎", and the crack evaluation during plating was "◯". The "A / B ratio" in Example 3 was "1.07", and the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side was small, so the appearance defect evaluation was "◎".

[0069] In Example 4, the additive amount A is "0.2" and the additive amount B is "0.4", so that the diffusion amount A is greater than the diffusion amount C by nearly 0.1 at. %, and the diffusion amount B is greater than the diffusion amount C by nearly 0.15 at. %. As a result, the crack evaluation after mounting was "A", and the crack evaluation during plating was "Good". The "A / B ratio" in Example 4 was "0.90", which suppressed the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side, and the appearance defect evaluation was "Good".

[0070] In Example 5, the additive amount A is "0.4" and the additive amount B is "0.2", so that the diffusion amount A is greater than the diffusion amount C by 0.15 at. % or more, and the diffusion amount B is greater than the diffusion amount C by nearly 0.07 at. %. As a result, the crack evaluation after mounting was "◎", and the crack evaluation during plating was "◯". The "A / B ratio" in Example 5 was "1.21", and the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side was suppressed, so the appearance defect evaluation was "◯".

[0071] In Example 6, the additive amount A is "0.4" and the additive amount B is "0.4", the diffusion amount A is greater than the diffusion amount C by 0.15 at. % or more, and the diffusion amount B is greater than the diffusion amount C by nearly 0.15 at. %. As a result, the crack evaluation after mounting was "◎", and the crack evaluation during plating was "◯". The "A / B ratio" in Example 6 was "1.06", and the difference in color between the margin layer 5E on the first surface side and the margin layer 5F on the second surface side was small, so the appearance defect evaluation was "◎".

[0072] 16, it was confirmed that the crack evaluation after mounting was significantly improved when the diffusion amount A was larger than the diffusion amount C. In particular, when the first element was Ni, it was confirmed that a significant effect was obtained when the diffusion amount A was 0.4 at. % or more. Furthermore, it was confirmed that the difference in color tone was suppressed when the "A / B ratio" was "0.87" or more and "1.21" or less.

[0073] Second Embodiment FIG. 17 is a perspective view showing the configuration of a ceramic electronic component according to a second embodiment. FIG. 17 shows a chip inductor as an example of a ceramic electronic component. The chip inductor 31 includes an element body 32 and external electrodes 36A and 36B. The element body 32 includes a coil pattern 33, which is an example of an internal conductor, and a magnetic body 34, which is an example of a ceramic. The element body 32 has, for example, a substantially rectangular parallelepiped shape. The corners of the element body 32 may be chamfered along the ridges of the element body 32. The element body 32 has a first surface M11 and a second surface M12 that face back to back.

[0074] The coil pattern 33 is covered with a magnetic body 34, and the spirally wound coil pattern 33 is insulated from the other portions by the magnetic body 34. Both ends of the coil pattern 33 are drawn out from the magnetic body 34 on the first surface M11 side of the element body 32 and connected to external electrodes 36A and 36B.

[0075] The material of the coil pattern 33 is selected from metals such as Cu, Fe, Zn, Al, Sn, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or may be an alloy containing these metals. The material of the magnetic body 34 is, for example, ferrite. The external electrodes 36A, 36B are located on the first surface M11 side of the element body 32 and are separated from each other. The external electrodes 36A, 36B are arranged on the first surface M11 along the length direction DL and spaced apart in the width direction DW.

[0076] The first surface M11 of the magnetic body 34 contains the first element, and the concentration of the first element at the first surface M11 is higher than the concentration of the first element in the magnetic body 34 located between the coil patterns 33. As a result, the sinterability of the magnetic body 34 at the first surface M11 is improved, and the density is increased, which suppresses damage to the element body 32 due to stress applied to the chip inductor 31 via the external electrodes 36A, 36B after mounting.

[0077] In the above-described embodiments, a multilayer ceramic capacitor and a chip inductor are exemplified as ceramic electronic components, but the ceramic electronic component of the present invention may be a chip resistor, a sensor chip, etc. In addition, in the above-described embodiments, a ceramic electronic component having two external electrodes is exemplified, but the ceramic electronic component of the present invention may be one having three or more external electrodes.

[0078] REFERENCE SIGNS LIST 1 capacitor, 2 element body, 2A laminate, 3A, 3B internal electrode layer, 4 dielectric layer, 5A, 5B cover layer, 5C, 5D, 5E, 5F margin layer, 6A, 6B external electrode, 7 underlayer, 9 plating layer, 31 chip inductor, 32 element body, 33 coil pattern, 34 magnetic body, 36A, 36B external electrode

Claims

1. a shaped ceramic having a first surface; an internal conductor provided within the ceramic across a portion of the ceramic and having an extension portion located on the first surface side; an external electrode provided on the first surface and connected to the internal conductor via the lead portion at the first surface; a first surface portion of the ceramic, the first element being included in the ceramic at a concentration higher than a concentration of a portion of the ceramic sandwiched between the internal conductors, the first surface portion being provided at a portion of the ceramic corresponding to a part of the first surface, the first surface portion being located at a portion of the first surface where the drawn portion is not provided; A ceramic electronic component comprising:

2. 2. The ceramic electronic component according to claim 1, wherein the first element is one or more elements selected from the group consisting of Ni, Mn, Sn, Mg, Ba, Zn, Si, B, Al, Cu, Li, Ca, Zr, In and Ti.

3. 2. The ceramic electronic component according to claim 1, wherein the first surface portion contains the first element at a concentration of 0.4 at. % or more.

4. 2. The ceramic electronic component according to claim 1, wherein the concentration of the first element in the first surface portion is 0.87 times or more and 1.21 times or less than the concentration of the first element in an outer surface portion located at a surface other than the first surface in the outer shape.

5. 5. The ceramic electronic component according to claim 4, wherein the outer surface portion contains the first element at a concentration of less than 0.5 at. %.

6. the internal conductor is made of a material containing the first element, The ceramic electronic component according to claim 1 , wherein the first surface portion contains a second element that promotes diffusion of the first element.

7. 7. The ceramic electronic component according to claim 6, wherein the second element is at least one of Sn and Fe.

8. 2. The ceramic electronic component according to claim 1, wherein the external electrodes are made of a plurality of layers including a conductive resin layer.

9. A ceramic electronic component according to any one of claims 1 to 8, a substrate on which the ceramic electronic component is mounted via solder at the portion of the external electrode provided on the first surface; A circuit board comprising:

10. An electronic device comprising the circuit board according to claim 9.

11. forming a shaped ceramic having a first surface; forming an internal conductor disposed within the ceramic across a portion of the ceramic and having an extension portion located on the first surface side; forming an external electrode provided on the first surface and connected to the internal conductor via the lead portion at the first surface; forming a first surface portion of the ceramic, the first element being contained in the ceramic at a concentration higher than a concentration in a portion of the ceramic sandwiched between the internal conductors, the first surface portion being provided at a portion of the ceramic where the drawn portion is not provided on the first surface side; 2. A method for producing a ceramic electronic component comprising the steps of:

12. 12. The method for manufacturing a ceramic electronic component according to claim 11, wherein the step of forming the first surface portion comprises forming the first surface portion from a material to which the first element is added at a concentration higher than a concentration in a portion sandwiched between the internal conductors.

13. The step of forming the internal conductor includes forming the internal conductor from a material containing the first element, 12. The method for manufacturing a ceramic electronic component according to claim 11, characterized in that the step of forming the first surface portion includes forming the first surface portion from a material containing a second element that promotes diffusion of the first element, and sintering the ceramic to diffuse the first element from the internal conductor into the first surface portion.

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