DC / DC converter and semiconductor device

Abstract

This DC / DC converter comprises: a pair of first terminals; a pair of second terminals; a primary side circuit; a secondary side circuit; a first capacitor; and a second capacitor. The primary side circuit comprises a first semiconductor switching element and a first reactor. The secondary side circuit comprises: at least one of a diode and a second semiconductor switching element; and a second reactor. The primary side circuit is provided between: the pair of first terminals; and the first capacitor and the second capacitor. The secondary side circuit is provided between: the first capacitor and the second capacitor; and the pair of second terminals.

Description

DC / DC converters and semiconductor devices

[0001] The invention disclosed herein relates to a DC / DC converter and a semiconductor device including the DC / DC converter.

[0002] A gate driver circuit (see, for example, Patent Document 1) drives a semiconductor switching element. Conventionally, an isolated DC / DC converter including a transformer is used as a power supply circuit that supplies DC power to the gate driver circuit.

[0003] Japanese Patent Application Laid-Open No. 2019-140432

[0004] Generally, a transformer is larger than other circuit components, and therefore the area of ​​a power supply circuit equipped with a transformer tends to be large.

[0005] Furthermore, there is a strong demand for miniaturization of inverters installed in EVs (electric vehicles). Therefore, miniaturization of semiconductor modules, which are components of inverters installed in EVs, is being actively promoted. As a result, the area of ​​a power supply circuit including a transformer becomes relatively large in a semiconductor module.

[0006] Furthermore, the efficiency of a power supply circuit equipped with a transformer decreases due to iron loss that occurs in the transformer.

[0007] The DC / DC converter disclosed in this specification includes a pair of first terminals configured to receive a first DC power, a pair of second terminals configured to output a second DC power, a primary side circuit, a secondary side circuit, a first capacitor, and a second capacitor. The primary side circuit includes a first semiconductor switching element and a first reactor. The secondary side circuit includes at least one of a diode and a second semiconductor switching element, and a second reactor. The primary side circuit is provided between the pair of first terminals and the first and second capacitors. The secondary side circuit is provided between the first and second capacitors and the pair of second terminals.

[0008] The semiconductor device disclosed herein comprises a semiconductor module and the above-described DC / DC converter configured to supply power to the semiconductor module.

[0009] According to the invention disclosed in this specification, a small-sized and highly efficient DC / DC converter can be realized.

[0010] FIG. 1 is a diagram illustrating a DC / DC converter according to an embodiment. FIG. 2 is a diagram illustrating a DC / DC converter according to a first example. FIG. 3 is a diagram illustrating the operation of the DC / DC converter according to the first example when the first semiconductor switching element is on. FIG. 4 is a diagram illustrating the operation of the DC / DC converter according to the first example when the first semiconductor switching element is off. FIG. 5 is a diagram illustrating voltages and currents at various components of the DC / DC converter according to the first example. FIG. 6 is a diagram illustrating a DC / DC converter according to a second example. FIG. 7 is a diagram illustrating the operation of the DC / DC converter according to the second example when the first semiconductor switching element is on. FIG. 8 is a diagram illustrating the operation of the DC / DC converter according to the second example when the first semiconductor switching element is off. FIG. 9 is a diagram illustrating voltages and currents at various components of the DC / DC converter according to the second example. FIG. 10 is a diagram illustrating a DC / DC converter according to a third example. FIG. 11 is a diagram illustrating the operation of the DC / DC converter according to the third example when the first semiconductor switching element is on. FIG. 12 is a diagram for explaining the operation of the DC / DC converter according to the third embodiment when the first semiconductor switching element is off. FIG. 13 is a diagram illustrating voltages and currents at various components of the DC / DC converter according to the third embodiment. FIG. 14 is a diagram illustrating a DC / DC converter according to a fourth embodiment. FIG. 15 is a diagram illustrating a first example of a control unit. FIG. 16 is a diagram illustrating voltages at various components of the DC / DC converter when the first example of a control unit is applied. FIG. 17 is a diagram illustrating a second example of a control unit. FIG. 18 is a diagram illustrating voltages at various components of the DC / DC converter when the second example of a control unit is applied. FIG. 19 is a diagram illustrating a third example of a control unit. FIG. 20 is a diagram illustrating voltages at various components of the DC / DC converter when the third example of a control unit is applied. FIG. 21 is a diagram illustrating a fourth example of a control unit. FIG. 22 is a diagram illustrating a semiconductor device. FIG. 23 is a plan view of a semiconductor module. FIG. 24 is a front view of the semiconductor module shown in FIG. 23. FIG. 25 is a partially enlarged view of FIG. 23. FIG. 26 is a partially enlarged view of FIG. 24. 27A is a partially enlarged cross-sectional view of the first wiring substrate shown in FIG. 26. FIG.27B is a partially enlarged cross-sectional view of the first wiring substrate shown in FIG. 26, showing a configuration different from that shown in FIG. 5A. FIG. 28 is a partially enlarged cross-sectional view of the interconnection shown in FIG. 26. FIG. 29 is a block diagram of a circuit provided on the first wiring substrate shown in FIG. 26. FIG. 30 is a perspective view of one of the multiple semiconductor devices constituting the semiconductor module shown in FIG. 23. FIG. 31 is a plan view of the semiconductor device shown in FIG. 30. FIG. 32 is a plan view corresponding to FIG. 31, seen through the sealing resin. FIG. 33 is a partially enlarged view of FIG. 32. FIG. 34 is a plan view corresponding to FIG. 31, seen through the first conductive member and omitting the sealing resin and second conductive member. FIG. 35 is a right side view of the semiconductor device shown in FIG. 23. FIG. 36 is a bottom view of the semiconductor device shown in FIG. 23. FIG. 37 is a cross-sectional view taken along line XV-XV in FIG. 32. FIG. 38 is a cross-sectional view taken along line XVI-XVI in FIG. 32. Fig. 39 is a partial enlarged view of the first element and its periphery shown in Fig. 38. Fig. 40 is a partial enlarged view of the second element and its periphery shown in Fig. 38. Fig. 41 is a cross-sectional view taken along line XIX-XIX in Fig. 32. Fig. 42 is a cross-sectional view taken along line XX-XX in Fig. 32.

[0011] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a field effect transistor whose gate structure is composed of at least three layers: a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value, an insulating layer, and a P-type, N-type, or intrinsic semiconductor layer. In other words, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0012] 1 is a diagram showing a DC / DC converter according to an embodiment of the present invention, the DC / DC converter CNV1 includes a pair of first terminals T1A and T1B, a pair of second terminals T2A and T2B, a primary circuit 1, a secondary circuit 2, a first capacitor C1, and a second capacitor C2.

[0013] The pair of first terminals T1A and T1B are configured to receive first DC power. For example, as shown in Fig. 1, a positive electrode of a DC power supply PS1 that outputs the first DC power is connected to the first terminal T1A, and a negative electrode of the DC power supply PS1 is connected to the first terminal T1B.

[0014] The pair of second terminals T2A and T2B is configured to output second DC power. For example, as shown in FIG. 1 , a first end of a load LD1 is connected to the second terminal T2A, and a second end of a load LD2 is connected to the second terminal T2B. The pair of second terminals T2A and T2B outputs the second DC power to the load LD1.

[0015] The primary circuit 1 includes a first semiconductor switching element (not shown in FIG. 1 ) and a first reactor (not shown in FIG. 1 ). The secondary circuit 2 includes at least one of a diode (not shown in FIG. 1 ) and a second semiconductor switching element (not shown in FIG. 1 ), and a second reactor (not shown in FIG. 1 ).

[0016] The primary circuit 1 is provided between a pair of first terminals T1A and T1B and a first capacitor C1 and a second capacitor C2. The secondary circuit 2 is provided between the first capacitor C1 and the second capacitor C2 and a pair of second terminals T2A and T2B. The first capacitor C1 and the second capacitor C2 insulate the primary circuit 1 from the secondary circuit 2.

[0017] A first end of the output capacitor C3 is connected to the second terminal T2 A. A second end of the output capacitor C3 is connected to the second terminal T2 B. The output capacitor C3 suppresses ripples in the DC voltage supplied to the load LD1.

[0018] The DC / DC converter CNV1 is configured to include a first capacitor C1 and a second capacitor C2 as insulating elements. Generally, a capacitor is smaller than a transformer. Therefore, the DC / DC converter CNV1 can be made smaller than a DC / DC converter that includes a transformer.

[0019] Furthermore, since the DC / DC converter CNV1 does not include a transformer, there is no decrease in efficiency due to iron loss that occurs in a transformer, and therefore the DC / DC converter CNV1 can be made more efficient than a DC / DC converter that includes a transformer.

[0020] In the case where the DC / DC converter CNV1 is configured such that, when the first semiconductor switching element is on, power is transmitted from the primary side circuit 1 to the load LD1 via the charges in the first capacitor C1 and the second capacitor C2 (for example, the configuration shown in FIG. 6 described below), when the first semiconductor switching element is on, a current flows through the path of the second reactor, the first capacitor C1, and the second capacitor C2, and a series resonant circuit is formed by the first capacitor C1, the second capacitor C2, and the second reactor.

[0021] During a quarter of the resonant period in the series resonant circuit, the voltages of the first capacitor C1 and the second capacitor C2 increase.

[0022] Consider the case where the ¼ period of the series resonant circuit is equal to or shorter than the on-time of the first semiconductor switching element (the time corresponding to the duty of the first semiconductor switching element). In this case, the voltages of the first capacitor C1 and the second capacitor C2 rise to the DC voltage applied to the pair of first terminals T1A and T1B, and power cannot be supplied from the primary circuit 1 to the secondary circuit 2.

[0023] The phenomenon in which power cannot be supplied from the primary circuit 1 to the secondary circuit 2 regardless of the on-time of the first semiconductor switching element acts in the same way as when the on-time (duty) of the first semiconductor switching element is shortened, resulting in a decrease in the DC voltage output from the pair of second terminals T2A and T2B.

[0024] Therefore, in order to prevent a drop in the DC voltage output from the pair of second terminals T2A and T2B, in the DC / DC converter CNV1, it is desirable that 1 / 4 of the resonant period in the above-mentioned series resonant circuit be longer than the on time of the first semiconductor switching element.

[0025] On the other hand, in the case where the DC / DC converter CNV1 is configured such that, when the first semiconductor switching element is off, power is transmitted from the primary side circuit 1 to the load LD1 via the charges in the first capacitor C1 and the second capacitor C2 (for example, the configurations shown in FIGS. 3 and 10 described below), when the first semiconductor switching element is off, a current flows through the path of the first reactor, the first capacitor C1, and the second capacitor C2, and power is transmitted to the load. At this time, the first capacitor C1, the second capacitor C2, and the first reactor form a series resonant circuit.

[0026] Here, if the time during which the first semiconductor switching element is off becomes long, the polarity of the current in the series resonant circuit formed by the first capacitor C1, the second capacitor C2 and the first reactor will be reversed, and power will no longer be able to be supplied from the primary side circuit 1 to the secondary side circuit 2.

[0027] In a series resonant circuit, the current in the resonant circuit reaches a maximum value of reverse polarity in ¾ of the resonant period, so if the time during which the first semiconductor switching element is off exceeds ¾ of the resonant period, the polarity of the current in the series resonant circuit formed by the first capacitor C1, the second capacitor C2, and the first reactor will be reversed, and power will no longer be able to be supplied from the primary side circuit 1 to the secondary side circuit 2, resulting in a decrease in the DC voltage output from the pair of second terminals T2A and T2B. For the above reasons, it is desirable that ¾ of the resonant period in the series resonant circuit formed by the first capacitor C1, the second capacitor C2, and the first reactor be longer than the time during which the first semiconductor switching element is off.

[0028] Generally, in order to reduce the cost of circuit components, components are commonly used, and therefore the first reactor and the second reactor have the same inductance value.

[0029] In other words, the resonant frequency of the series resonant circuit formed by the first capacitor C1, the second capacitor C2, and the second reactor when the first semiconductor switching element is on is equal to the resonant frequency of the series resonant circuit formed by the first capacitor C1, the second capacitor C2, and the first reactor when the first semiconductor switching element is off. Therefore, it is desirable that the ¼ period of the resonant frequency of the series resonant circuit formed by the first capacitor C1, the second capacitor C2, and the second reactor be longer than the on time of the first semiconductor switching element.

[0030] <First Example of DC / DC Converter> Fig. 2 is a diagram showing a DC / DC converter according to Example 1. A DC / DC converter CNV1A is a first example of the DC / DC converter CNV1.

[0031] In this embodiment, the primary circuit 1 includes a first semiconductor switching element Q1, which is an N-channel MOS field effect transistor, and a first reactor L1.

[0032] In this embodiment, the secondary circuit 2 includes a diode D1 and a second reactor L2.

[0033] A first end of the first reactor L1 and a first end (drain) of the first semiconductor switching element Q1 are connected to a first end of the second reactor L2 and an anode of the diode D1 via a first capacitor C1. A second end of the first reactor L1 is connected to the first terminal T1A.

[0034] A second terminal (source) of the first semiconductor switching element Q1 is connected to a second terminal of the second reactor L2 via a second capacitor C2 and also to the first terminal T1B.

[0035] The cathode of the diode D1 is connected to the second terminal T2A and the first terminal of the output capacitor C3. The second terminal of the second reactor L2 is also connected to the second terminal T2B and the second terminal of the output capacitor C3.

[0036] Next, the operation of the DC / DC converter CNV1A will be described.

[0037] FIG. 3 is a diagram for explaining the operation of the DC / DC converter CNV1A when the first semiconductor switching element Q1 is on.

[0038] The amount of change ΔIL1_on in the current IL1 flowing through the first reactor L1 is expressed by the following formula (1). In the formula, V1 is the voltage supplied from the DC power supply PS1 to the pair of first terminals T1A and T1B. Also, L1 in the formula is the inductance value of the first reactor L1. Also, Ton in the formula is the on time of the first semiconductor switching element Q1. ΔIL1_on=(V1 / L1)×Ton (1)

[0039] The amount of change ΔIL2_on in the current IL2 flowing through the second reactor L2 is expressed by the following equation (2). In the equation, VC1 is the voltage of the first capacitor C1, VC2 is the voltage of the second capacitor C2, and L2 is the inductance value of the second reactor L2. ΔIL2_on=[(VC1+VC2) / L2]×Ton (2)

[0040] FIG. 4 is a diagram for explaining the operation of the DC / DC converter CNV1A when the first semiconductor switching element Q1 is off.

[0041] Even when the first semiconductor switching element Q1 is turned off, the polarity of the current IL1 flowing through the first reactor L1 does not change due to the action of the first reactor L1. Therefore, the amount of change ΔIL1_off in the current IL1 flowing through the first reactor L1 is expressed by the following equation (3). Note that V2 in the equation is the voltage supplied to the load LD1 from the pair of second terminals T2A and T2B. Also, Toff in the equation is the off time of the first semiconductor switching element Q1. ΔIL1_off=[(V1-VC1-VC2-V2) / L1]×Toff (3)

[0042] The amount of change ΔIL2_off in the current IL2 flowing through the second reactor L2 is expressed by the following equation (4): ΔIL2_off=(−V2 / L2)×Toff (4)

[0043] The total amount of change in the current IL2 flowing through the second reactor L2 during one switching period of the first semiconductor switching element Q1 is zero. Therefore, the following equation (5) is derived. In the equation, d is the on-time of the first semiconductor switching element Q1 divided by the switching period of the first semiconductor switching element Q1. [(VC1+VC2) / L2]×Ton+(−V2 / L2)×Toff=0 VC1+VC2=V2×[(1−d) / d] (5)

[0044] Considering the first reactor L1 in the same way and further taking into account the above equation (5), the following equation (6) is derived: (V1 / L1)×Ton+[(V1−VC1−VC2−V2) / L1]×Toff=0 V2=V1×[d / (1−d)] (6)

[0045] As can be seen from the above equation (6), the voltage V2 can be made to approach the target value by controlling the on-time of the first semiconductor switching element Q1 and thus the duty d of the first semiconductor switching element Q1.

[0046] From the above equations (5) and (6), VC1 + VC2 = V1 holds. Furthermore, considering that components are generally standardized to reduce circuit component costs, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are the same. Therefore, VC1 = VC2 holds, and so VC1 = V1 / 2 and VC2 = V1 / 2.

[0047] In the following calculations, a combined capacitance C of the capacitance C1 of the first capacitor C1 and the capacitance C2 of the second capacitor C2 is used. The combined capacitance C is expressed by the following formula: C=C1×C2 / (C1+C2)

[0048] Considering that the sum of the change in the voltage VC1 of the first capacitor C1 and the change in the voltage VC2 of the second capacitor C2 becomes zero during one switching period of the first semiconductor switching element Q1, the following equation (7) holds: −IL2×Ton / C+IL1×Toff / C=0 IL2=IL1×[(1−d) / d] (7)

[0049] The current Iin input from the pair of first terminals T1A and T1B is equal to the output power Pout divided by the voltage V1. The current Iin is equal to the average value of the current IL1 flowing through the first reactor L1.

[0050] From the above, the average value of the current IL2 flowing through the second reactor L2 is derived from the above equation (7) as follows: IL2=Pout / V2=Iout

[0051] When the first semiconductor switching element Q1 is off, the first capacitor C1 and the second capacitor C2 are charged by the current IL1 flowing through the first reactor L1, and the voltage VC of the combined capacitance C rises. The rise ΔVC at this time can be calculated as follows: ΔVC = (1 / C) ∫ (IL1) dt ΔVC ≈ Iin × Toff / C

[0052] The voltage VC of the combined capacitance C varies by ±ΔVC / 2 around the voltage V1. Therefore, the maximum value VCp of the voltage VC of the combined capacitance C can be calculated as follows: VCp=V1+ΔVC / 2

[0053] When the first semiconductor switching element Q1 is off, a voltage of V1+VC is applied to the first semiconductor switching element Q1, so the maximum value of the voltage applied to the first semiconductor switching element Q1 is V1+ΔVC / 2.

[0054] As a result of the above, the withstand voltage of the first semiconductor switching element Q1 should be equal to or greater than the sum of the voltage V1 applied to the pair of first terminals T1A and T1B, the maximum voltage of the first capacitor C1, and the maximum voltage of the second capacitor C2.

[0055] 5 is a diagram showing voltages and currents at various parts of the DC / DC converter CNV1A. The voltage VG in the diagram is a gate signal supplied to the control terminal (gate) of the first semiconductor switching element Q1. The voltage VDS in the diagram is a voltage generated between the first terminal (drain) and the second terminal (source) of the first semiconductor switching element Q1.

[0056] <Second Example of DC / DC Converter> Fig. 6 is a diagram showing a DC / DC converter according to a second example. DC / DC converter CNV1B is a second example of the DC / DC converter CNV1. In the second example, the same parts and voltages of the same parts as in the first example are designated by the same reference numerals and symbols.

[0057] In this embodiment, the primary circuit 1 includes a first semiconductor switching element Q1, which is an N-channel MOS field effect transistor, and a first reactor L1.

[0058] In this embodiment, the secondary circuit 2 includes a diode D1 and a second reactor L2.

[0059] A first end (source) of the first semiconductor switching element Q1 and a first end of the first reactor L1 are connected to the cathode of the diode D1 and the first end of the second reactor L2 via a first capacitor C1. A second end (drain) of the first semiconductor switching element Q1 is connected to the first terminal T1A.

[0060] The second end of the first reactor L1 is connected to the anode of the diode D1 via the second capacitor C2 and also to the first terminal T1B.

[0061] A second end of the second reactor L2 is connected to the second terminal T2A and the first end of the output capacitor C3. An anode of the diode D1 is also connected to the second terminal T2B and the second end of the output capacitor C3.

[0062] Next, the operation of the DC / DC converter CNV1B will be described.

[0063] FIG. 7 is a diagram for explaining the operation of the DC / DC converter CNV1B when the first semiconductor switching element Q1 is on.

[0064] The amount of change ΔIL1_on in the current IL1 flowing through the first reactor L1 is expressed by the following equation (11): ΔIL1_on=(V1 / L1)×Ton (11)

[0065] The amount of change ΔIL2_on in the current IL2 flowing through the second reactor L2 is expressed by the following equation (12): ΔIL2_on=[(V1−VC1−VC2−V2) / L2]×Ton (12)

[0066] FIG. 8 is a diagram for explaining the operation of the DC / DC converter CNV1B when the first semiconductor switching element Q1 is off.

[0067] Even when the first semiconductor switching element Q1 is turned off, the polarity of the current IL1 flowing through the first reactor L1 does not change due to the action of the first reactor L1. Therefore, the amount of change ΔIL1_off in the current IL1 flowing through the first reactor L1 is expressed by the following equation (13): ΔIL1_off=[(−VC1−VC2) / L1]×Toff (13)

[0068] The amount of change ΔIL2_off in the current IL2 flowing through the second reactor L2 is expressed by the following equation (14): ΔIL2_off=(−V2 / L2)×Toff (14)

[0069] The total amount of change in the current IL1 flowing through the first reactor L1 during one switching period of the first semiconductor switching element Q1 is zero. Therefore, the following equation (15) is derived: (V1 / L1)×Ton+[(−VC1−VC2) / L1]×Toff=0 VC1+VC2=V1×[d / (1−d)] (15)

[0070] Considering the second reactor L2 in the same manner and further taking into account the above equation (15), the following equation (16) is derived: [(V1-VC1-VC2-V2) / L2]×Ton+(-V2 / L2)×Toff=0 V2=V1×[d / (1-d)] (16)

[0071] As can be seen from the above equation (16), the voltage V2 can be made to approach the target value by controlling the on-time of the first semiconductor switching element Q1 and thus the duty d of the first semiconductor switching element Q1.

[0072] From the above equations (15) and (16), VC1 + VC2 = -V2 holds. Furthermore, considering that components are generally standardized to reduce circuit component costs, the capacitance of the first capacitor C1 and the capacitance of the second capacitor C2 are the same. Therefore, VC1 = VC2 holds, and so VC1 = V2 / 2 and VC2 = V2 / 2.

[0073] In the following calculations, a combined capacitance C of the capacitance C1 of the first capacitor C1 and the capacitance C2 of the second capacitor C2 is used. The combined capacitance C is expressed by the following formula: C=C1×C2 / (C1+C2)

[0074] Considering that the sum of the change in the voltage VC1 of the first capacitor C1 and the change in the voltage VC2 of the second capacitor C2 becomes zero during one switching period of the first semiconductor switching element Q1, the following equation (17) holds: IL2×Ton / C+(−IL1)×Toff / C=0 IL2=IL1×[(1−d) / d] (17)

[0075] The current Iin input from the pair of first terminals T1A and T1B is equal to the output power Pout divided by the voltage V1. The current Iin is equal to the average value of the current IL1 flowing through the first reactor L1.

[0076] From the above, the current IL2 flowing through the second reactor L2 is derived from the above equation (17) as follows: IL2=Pout / V2=Iout

[0077] When the first semiconductor switching element Q1 is off, the first capacitor C1 and the second capacitor C2 are charged by the current IL2 flowing through the second reactor L2, and the voltage VC of the combined capacitance C rises. The amount of rise at this time can be calculated as follows: ΔVC=(1 / C)∫(IL2)dt ΔVC≈Iout×Toff / C

[0078] The voltage VC of the combined capacitance C varies by ±ΔVC / 2 around the voltage V2. Therefore, the maximum value VCp of the voltage VC of the combined capacitance C can be calculated as follows: VCp=V2+ΔVC / 2

[0079] When the first semiconductor switching element Q1 is off, the combined capacitance C is discharged, and the voltage VC of the combined capacitance C decreases by ΔVC / 2. Therefore, when the first semiconductor switching element Q1 is off, the maximum value of the voltage applied to the first semiconductor switching element Q1 is V1.

[0080] FIG. 9 is a diagram showing voltages and currents at various points in the DC / DC converter CNV1B.

[0081] <Third Example of DC / DC Converter> Fig. 10 is a diagram showing a DC / DC converter according to a third example. The DC / DC converter CNV1C is a third example of the DC / DC converter CNV1. In the third example, the same parts and voltages of the same parts as in the first example are designated by the same reference numerals and symbols.

[0082] In this embodiment, the primary circuit 1 includes a first semiconductor switching element Q1, which is an N-channel MOS field effect transistor, and a first reactor L1.

[0083] In this embodiment, the secondary circuit 2 includes a diode D1 and a second reactor L2.

[0084] A first end of the first reactor L1 and a first end (drain) of the first semiconductor switching element Q1 are connected to the anode of the diode D1 and the first end of the second reactor L2 via a first capacitor C1. A second end (source) of the first semiconductor switching element Q1 is connected to the cathode of the diode D1 via a second capacitor C2. The second end (source) of the first semiconductor switching element Q1 is also connected to the first terminal T1B.

[0085] A second end of the second reactor L2 is connected to the second terminal T2A and the first end of the output capacitor C3. A cathode of the diode D1 is also connected to the second terminal T2B and the second end of the output capacitor C3.

[0086] Next, the operation of the DC / DC converter CNV1C will be described.

[0087] FIG. 11 is a diagram for explaining the operation of the DC / DC converter CNV1C when the first semiconductor switching element Q1 is on.

[0088] FIG. 12 is a diagram for explaining the operation of the DC / DC converter CNV1C when the first semiconductor switching element Q1 is off.

[0089] As in the first and second embodiments, the capacitance of the first capacitor C1 is the same as the capacitance of the second capacitor C2, so that VC1=VC2.

[0090] In the following calculations, a combined capacitance C of the capacitance C1 of the first capacitor C1 and the capacitance C2 of the second capacitor C2 is used. The combined capacitance C is expressed by the following formula: C=C1×C2 / (C1+C2)

[0091] When the first semiconductor switching element Q1 is on, the change amount ΔVC_on of the voltage VC of the combined capacitance C is expressed by the following equation (21): ΔVC_on=−(1 / C)∫(IL2)dt (21)

[0092] When the first semiconductor switching element Q1 is off, the change amount ΔVC_off of the voltage VC of the combined capacitance C is expressed by the following equation (22): ΔVC_off=(1 / C)∫(IL1)dt (22)

[0093] The current Iin input from the pair of first terminals T1A and T1B is equal to the output power Pout divided by the voltage V1. The current Iin is equal to the average value of the current IL1 flowing through the first reactor L1.

[0094] On the other hand, the current Iout output from the pair of second terminals T2A and T2B is equal to the output power Pout divided by the voltage V2. The current Iout is equal to the average value of the current IL2 flowing through the second reactor L2.

[0095] From the above, the above equations (21) and (22) become the following equations (23) and (24): ΔVC_on=−Iout×Ton / C (23) ΔVC_off=Iin××Toff / C (24)

[0096] Considering that the total amount of change in the voltage VC of the combined capacitance C becomes zero during one switching period of the first semiconductor switching element Q1, the following equation (25) holds: Iout=-Iin×[(1-d) / d] (25)

[0097] Here, since the input power P1 and the output power P2 are equal, V1×Iin=V2×Iout holds, and when this relationship is substituted into the above equation (25), the following equation (26) is derived: V2=−V1×[d / (1−d)] (26)

[0098] As can be seen from the above equation (26), the voltage V2 can be made to approach the target value by controlling the on-time of the first semiconductor switching element Q1 and thus the duty d of the first semiconductor switching element Q1. Note that the voltages V2 and V1 have opposite polarities.

[0099] Because voltage V2 has the opposite polarity to voltage V1, voltage VC of composite capacitance C is V1+V2. Therefore, when first semiconductor switching element Q1 is off, the maximum value of the voltage applied to first semiconductor switching element Q1 is V1+V2+ΔVC_off / 2.

[0100] FIG. 13 is a diagram showing voltages and currents at various points in the DC / DC converter CNV1C.

[0101] <Fourth Example of DC / DC Converter> Fig. 14 is a diagram showing a DC / DC converter according to Example 4. A DC / DC converter CNV1D is a fourth example of the DC / DC converter CNV1.

[0102] The DC / DC converter CNV1D has a configuration in which the diode D1 in the DC / DC converter CNV1A is replaced with a second semiconductor switching element Q2. The second semiconductor switching element Q2 is an N-channel field effect transistor.

[0103] Therefore, when transmitting power from the primary side circuit 1 to the secondary side circuit 2, the operation of the DC / DC converter CNV1D is the same as that of the first embodiment. Also, when transmitting power from the secondary side circuit 2 to the primary side circuit 1, the operation of the DC / DC converter CNV1D is the same as that of the second embodiment. In other words, the DC / DC converter CNV1D is capable of transmitting power in both directions.

[0104] <First Example of Control Unit> Fig. 15 is a diagram showing a first example of the control unit CNT1. Fig. 15 is a schematic diagram showing the main parts of the first example of the control unit CNT1. Fig. 16 is a diagram showing the voltages of each part of the DC / DC converter CNV1 when the first example of the control unit CNT1 is applied. The first example of the control unit CNT1 can be applied to, for example, the DC / DC converter CNV1A or the DC / DC converter CNV1D.

[0105] The control unit CNT1 is provided in the DC / DC converter CNV1 and controls the first semiconductor switching element Q1. If the DC / DC converter CNV1 includes a second semiconductor switching element Q2, the control unit CNT1 also controls the second semiconductor switching element Q2.

[0106] The control unit CNT1 shown in FIG. 15 includes a duty calculation unit OP1, a comparator COMP1, a delay circuit DLY1, an AND gate AN1, and a gate signal generation unit GNR1.

[0107] The detected value of the voltage V1 is supplied to the duty calculation unit OP1 and the non-inverting input terminal of the comparator COMP1. The detected value of the voltage V1 may be the value of the voltage V1 itself or a divided value of the voltage V1.

[0108] The comparator COMP1 compares the detected value of the voltage V1 with a constant potential to determine whether the DC / DC converter CNV1 is powered on, that is, whether the voltage V1 has risen to or above a predetermined value.

[0109] The output (enable signal EN) of the comparator COMP1 is supplied to an AND gate AN1 via a delay circuit DLY1.

[0110] The duty calculation unit OP1 calculates a duty command value DUTY for the first semiconductor switching element Q1 based on the detected value of the voltage V1 and the target value of the voltage V2. The duty calculation unit OP1 supplies the duty command value DUTY to the AND gate AN1.

[0111] A duty command value DUTY*, which is the logical product of the enable signal EN and the duty command value DUTY, is supplied to a gate signal generation unit GNR1, which generates a gate signal VG having a duty corresponding to the duty command value DUTY*.

[0112] As a result, the control unit CNT1 shown in FIG. 15 stops the switching operation of the first semiconductor switching element Q1 for a predetermined time immediately after the DC / DC converter CNV1 is started, and maintains the first semiconductor switching element Q1 in an off state.

[0113] The predetermined time is the delay time provided by the delay circuit DLY1, and is the time from the power-on timing TM1 to the switching operation start timing TM2 of the first semiconductor switching element Q1 shown in FIG.

[0114] During the period from timing TM1 to timing TM2, a resonant circuit is formed by the primary circuit 1, the secondary circuit 2, the first capacitor C1, and the second capacitor C2, and the output capacitor C3 is charged by the resonant circuit, thereby achieving a soft start of the DC / DC converter CNV1 and suppressing the inrush current.

[0115] <Second Example of Control Unit> Fig. 17 is a diagram showing a second example of the control unit CNT1. Fig. 17 is a schematic diagram showing the main parts of the second example of the control unit CNT1. Fig. 18 is a diagram showing the voltages of each part of the DC / DC converter CNV1 when the second example of the control unit CNT1 is applied. The second example of the control unit CNT1 can be applied to, for example, the DC / DC converter CNV1B.

[0116] The control unit CNT1 shown in FIG. 17 includes a duty calculation unit OP1, a comparator COMP1, a delay circuit DLY1, an AND gate AN1, an inverter INV1, an OR gate OR1, and a gate signal generation unit GNR1.

[0117] The detected value of the voltage V1 is supplied to the duty calculation unit OP1 and the non-inverting input terminal of the comparator COMP1. The detected value of the voltage V1 may be the value of the voltage V1 itself or a divided value of the voltage V1.

[0118] The comparator COMP1 compares the detected value of the voltage V1 with a constant potential to determine whether the DC / DC converter CNV1 is powered on, that is, whether the voltage V1 has risen to or above a predetermined value.

[0119] The output (enable signal EN) of the comparator COMP1 is supplied to an AND gate AN1 and an inverter INV1 via a delay circuit DLY1.

[0120] The duty calculation unit OP1 calculates a duty command value DUTY for the first semiconductor switching element Q1 based on the detected value of the voltage V1 and the target value of the voltage V2. The duty calculation unit OP1 supplies the duty command value DUTY to the AND gate AN1.

[0121] A duty command value DUTY*, which is the logical product of the enable signal EN and the duty command value DUTY, is supplied to an OR gate OR1. An inverter INV1 supplies an inverted signal of the enable signal EN to the OR gate OR1. The output of the OR gate OR1 is supplied to a gate signal generation unit GNR1. The gate signal generation unit GNR1 generates a gate signal VG having a duty corresponding to the duty command value DUTY*.

[0122] As a result, the control unit CNT1 shown in FIG. 17 stops the switching operation of the first semiconductor switching element Q1 for a predetermined time immediately after the DC / DC converter CNV1 is started, and maintains the first semiconductor switching element Q1 in an on state.

[0123] The predetermined time is the delay time provided by the delay circuit DLY1, and is the time from the power-on timing TM1 to the switching operation start timing TM2 of the first semiconductor switching element Q1 shown in FIG.

[0124] During the period from timing TM1 to timing TM2, a resonant circuit is formed by the primary circuit 1, the secondary circuit 2, the first capacitor C1, and the second capacitor C2, and the output capacitor C3 is charged by the resonant circuit, thereby achieving a soft start of the DC / DC converter CNV1 and suppressing the inrush current.

[0125] <Third Example of Control Unit> Fig. 19 is a diagram showing a third example of the control unit CNT1. Fig. 19 is a schematic diagram showing the main parts of the third example of the control unit CNT1. Fig. 20 is a diagram showing the voltages of each part of the DC / DC converter CNV1 when the third example of the control unit CNT1 is applied. The third example of the control unit CNT1 can be applied to, for example, any of the DC / DC converters CNV1A to CNV1D.

[0126] The control unit CNT1 shown in FIG. 19 includes a duty calculation unit OP1, a multiplier MAC1, a ramp voltage generation unit RAMP1, and a gate signal generation unit GNR1.

[0127] The detected value of the voltage V1 is supplied to the duty calculation unit OP1 and the non-inverting input terminal of the comparator COMP1. The detected value of the voltage V1 may be the value of the voltage V1 itself or a divided value of the voltage V1.

[0128] The duty calculation unit OP1 calculates a duty command value DUTY for the first semiconductor switching element Q1 based on the detected value of the voltage V1 and the target value of the voltage V2, and supplies the duty command value DUTY to the multiplier MAC1.

[0129] The ramp voltage generating unit RAMP1 generates a ramp voltage and supplies it to the multiplier MAC1.

[0130] The multiplier MAC1 supplies a duty command value DUTY*, which is the result of multiplying the duty command value DUTY by the lamp voltage, to the gate signal generator GNR1, which generates a gate signal VG having a duty corresponding to the duty command value DUTY*.

[0131] As a result, the control unit CNT1 shown in FIG. 19 increases the duty of the first semiconductor switching element Q1 for a predetermined time immediately after the start-up of the DC / DC converter CNV1.

[0132] The predetermined time is the time from the power-on timing TM1 to the timing TM2 at which the ramp-like increase of the duty command value DUTY* stops, as shown in FIG.

[0133] Since the duty of the first semiconductor switching element Q1 increases in a ramp manner, a soft start of the DC / DC converter CNV1 is achieved and inrush current is suppressed.

[0134] <Fourth Example of Control Unit> Fig. 21 is a diagram showing a fourth example of the control unit CNT1. Fig. 21 is a schematic diagram showing a main part of the fourth example of the control unit CNT1. The fourth example of the control unit CNT1 can be applied to, for example, any of the DC / DC converters CNV1A to CNV1D.

[0135] The control unit CNT1 shown in FIG. 21 includes a duty calculation unit OP1, a secondary current calculation unit OP2, a Vf calculation unit OP3, and a gate signal generation unit GNR1.

[0136] The above description of the operation of the DC / DC converter CNV1 is based on the assumption of an ideal state with no loss. However, when a current flows through the diode D1, a forward voltage drop Vf occurs. Therefore, unless the effect of the forward voltage drop Vf is compensated for, the voltage V2 will decrease from the target value by the amount of the forward voltage drop Vf.

[0137] The control unit CNT1 shown in FIG. 21 compensates for the influence of the forward voltage drop Vf.

[0138] The secondary-side current calculation unit OP2 calculates (estimates) the current flowing through the diode D1 based on the current ISW flowing through the first semiconductor switching element Q1 detected by a current detection unit provided in the DC / DC converter CNV1. The secondary-side current calculation unit OP2 calculates the current flowing through the diode D1 using the above-mentioned formula for calculating the current IL2 flowing through the second reactor L2.

[0139] The Vf calculation unit OP3 uses the calculation result of the secondary current calculation unit OP2, i.e., based on the current flowing through the diode D1 estimated by the secondary current calculation unit OP2, to calculate the forward voltage drop Vf occurring across the diode D1. The Vf calculation unit OP3 stores in advance an approximation formula that indicates the current-voltage characteristics of the diode D1.

[0140] The adder ADD1 supplies the corrected target value V2*, which is the result of adding the target value of the voltage V2 and the forward voltage drop Vf calculated by the Vf calculation unit OP3, to the duty calculation unit OP1.

[0141] The duty calculation unit OP1 calculates a duty command value DUTY* for the first semiconductor switching element Q1 based on the detected value of the voltage V1 and the corrected target value V2*. The duty calculation unit OP1 supplies the duty command value DUTY* to the gate signal generation unit GNR1. The gate signal generation unit GNR1 generates a gate signal VG having a duty corresponding to the duty command value DUTY*.

[0142] <Semiconductor Device> The DC / DC converter CNV1 is mounted on a semiconductor device 3, as shown in FIG. 22 . The semiconductor device 3 is, for example, an inverter device that supplies three-phase AC power to a three-phase motor. The semiconductor device 3 of the configuration example shown in FIG. 22 includes the DC / DC converter CNV1 and a semiconductor module A10. The semiconductor module A10 includes a plurality of semiconductor devices (power modules) B10, a plurality of first wiring boards 71, a second wiring board 72, a heat sink 70 (not shown in FIG. 22 ), a plurality of interconnection wires 73 (not shown in FIG. 22 ), a plurality of mounting members 74 (not shown in FIG. 22 ), a plurality of support members 75 (not shown in FIG. 22 ), and a plurality of positioning pins 76 (not shown in FIG. 22 ).

[0143] The DC / DC converter CNV1 is configured to supply power to the second wiring board 72. The gate driver 83 (see FIG. 29 described later) provided on the first wiring board 71 is configured to receive power supplied from the DC / DC converter CNV1 via the second wiring board 72. As will be described later, the gate driver 83 may be provided on the second wiring board 72 instead of the first wiring board 71. Furthermore, since power is supplied from the DC / DC converter CNV1 to the second wiring board 72, the DC / DC converter CNV1 may be provided on the second wiring board 72.

[0144] 23 to 42, the semiconductor module A10 will be described. For convenience, the semiconductor module A10 will be described after first describing the plurality of semiconductor devices B10 that constitute the semiconductor module A10.

[0145] In the description of the semiconductor module A10, for convenience, the direction in which a first signal terminal 161 of a semiconductor device B10 (described later) extends is referred to as the "first direction z." The direction perpendicular to the first direction z is referred to as the "second direction x." The direction perpendicular to both the first direction z and the second direction x is referred to as the "third direction y."

[0146] (Semiconductor Device B10) The multiple semiconductor devices B10 constituting the semiconductor module A10 will be described with reference to FIGS. 30 to 42. All of the multiple semiconductor devices B10 are identical. Therefore, the description of the multiple semiconductor devices B10 will focus on one of the semiconductor devices B10. The semiconductor device B10 includes a support 11, a first conductive layer 121, a second conductive layer 122, a first input terminal 13, an output terminal 14, a second input terminal 15, a first signal terminal 161, a second signal terminal 162, multiple semiconductor elements 21, a first conductive member 31, a second conductive member 32, and a sealing resin 50. The semiconductor device B10 further includes a third signal terminal 171, a fourth signal terminal 172, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, a seventh signal terminal 19, a pair of thermistors 22, and a pair of control wirings 60. For ease of understanding, FIGS. 32 and 33 show the sealing resin 50 in a see-through manner. 32, the transmitted sealing resin 50 is indicated by an imaginary line (two-dot chain line). In FIG. 34, for ease of understanding, the first conductive member 31 is transmitted, and the second conductive member 32 and the sealing resin 50 are not shown.

[0147] The semiconductor device B10 converts a DC power supply voltage applied to the first input terminal 13 and the second input terminal 15 into AC power using the semiconductor element 21. The converted AC power is input from the output terminal 14 to a power supply target such as a motor.

[0148] As shown in FIGS. 38 to 40 , the support 11 is located on the opposite side of the semiconductor elements 21 in the first direction z, with the first conductive layer 121 and the second conductive layer 122 sandwiched therebetween. The support 11 supports the first conductive layer 121 and the second conductive layer 122. In the semiconductor device B10, the support 11 is made of a DBC (Direct Bonded Copper) substrate. As shown in FIGS. 38 to 40 , the support 11 includes an insulating layer 111, an intermediate layer 112, and a heat dissipation layer 113. The support 11 is covered with a sealing resin 50 except for a portion of the heat dissipation layer 113.

[0149] As shown in FIGS. 38 to 40 , the insulating layer 111 includes a portion interposed between the intermediate layer 112 and the heat dissipation layer 113 in the first direction z. The insulating layer 111 is made of a material with relatively high thermal conductivity. The insulating layer 111 is made of ceramics containing aluminum nitride (AlN), for example. The insulating layer 111 may be made of an insulating resin sheet instead of ceramics. The thickness of the insulating layer 111 is thinner than the thickness of each of the first conductive layer 121 and the second conductive layer 122.

[0150] 38 to 40 , the intermediate layer 112 is located between the insulating layer 111 and the first and second conductive layers 121 and 122 in the first direction z. The intermediate layer 112 includes a pair of regions spaced apart from each other in the second direction x. The composition of the intermediate layer 112 includes copper (Cu). As shown in FIG. 34 , the intermediate layer 112 is surrounded by the periphery of the insulating layer 111 when viewed along the first direction z.

[0151] As shown in Figures 38 to 40, the heat dissipation layer 113 is located on the opposite side of the intermediate layer 112 in the first direction z, with the insulating layer 111 sandwiched therebetween. As shown in Figure 36, the heat dissipation layer 113 is exposed from the sealing resin 50. A heat sink 70, which will be described later, is bonded to the heat dissipation layer 113. The heat dissipation layer 113 contains copper. The thickness of the heat dissipation layer 113 is greater than the thickness of the insulating layer 111. When viewed along the first direction z, the heat dissipation layer 113 is surrounded by the periphery of the insulating layer 111.

[0152] As shown in FIGS. 38 to 40 , the first conductive layer 121 and the second conductive layer 122 are bonded to the support 11. The first conductive layer 121 and the second conductive layer 122 contain copper. The first conductive layer 121 and the second conductive layer 122 are spaced apart from each other in the second direction x. As shown in FIGS. 37 and 38 , the first conductive layer 121 has a first main surface 121A and a first back surface 121B facing opposite sides in the first direction z. The first main surface 121A faces the plurality of semiconductor elements 21. As shown in FIG. 39 , the first back surface 121B is bonded to one of a pair of regions of the intermediate layer 112 via a first adhesive layer 123. The first adhesive layer 123 is, for example, a brazing material containing silver (Ag) in its composition. 37 and 38 , the second conductive layer 122 has a second main surface 122A and a second back surface 122B that face opposite each other in the first direction z. The second main surface 122A faces the same side as the first main surface 121A in the first direction z. As shown in Fig. 40 , the second back surface 122B is bonded to the other of the pair of regions of the intermediate layer 112 via a first adhesive layer 123.

[0153] As shown in FIGS. 34 and 38 , each of the multiple semiconductor elements 21 is mounted on either the first conductive layer 121 or the second conductive layer 122. The semiconductor element 21 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the semiconductor element 21 may be a switching element such as an insulated gate bipolar transistor (IGBT), or a diode. In the description of the semiconductor device B10, the semiconductor element 21 is an n-channel MOSFET with a vertical structure. The semiconductor element 21 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0154] 34 , in the semiconductor device B10, the multiple semiconductor elements 21 include multiple first elements 21A and multiple second elements 21B. The structure of each of the multiple second elements 21B is the same as the structure of each of the multiple first elements 21A. The multiple first elements 21A are mounted on a first main surface 121A of a first conductive layer 121. The multiple first elements 21A are arranged along the third direction y. The multiple second elements 21B are mounted on a second main surface 122A of a second conductive layer 122. The multiple second elements 21B are arranged along the third direction y.

[0155] As shown in FIGS. 34, 39 and 40, the plurality of semiconductor elements 21 have a first electrode 211, a second electrode 212, a third electrode 213 and a fourth electrode 214.

[0156] 39 and 40 , the first electrode 211 faces either the first conductive layer 121 or the second conductive layer 122. A current corresponding to the power before being converted by the semiconductor element 21 flows through the first electrode 211. In other words, the first electrode 211 corresponds to the drain electrode of the semiconductor element 21.

[0157] 39 and 40 , the second electrode 212 is located on the opposite side to the first electrode 211 in the first direction z. A current corresponding to the power converted by the semiconductor element 21 flows through the second electrode 212. In other words, the second electrode 212 corresponds to the source electrode of the semiconductor element 21.

[0158] 39 and 40 , the third electrode 213 is located on the same side as the second electrode 212 in the first direction z. A gate voltage for driving the semiconductor element 21 is applied to the third electrode 213. That is, the third electrode 213 corresponds to the gate electrode of the semiconductor element 21. As shown in FIG. 12 , the area of ​​the third electrode 213 is smaller than the area of ​​the second electrode 212 when viewed along the first direction z.

[0159] 34 , the fourth electrode 214 is located on the same side as the second electrode 212 in the first direction z, and is located next to the third electrode 213 in the third direction y. The potential of the fourth electrode 214 is equal to the potential of the second electrode 212.

[0160] As shown in FIGS. 39 and 40 , the conductive bonding layer 23 is interposed between either the first conductive layer 121 or the second conductive layer 122 and the first electrode 211 of one of the multiple semiconductor elements 21. The conductive bonding layer 23 is, for example, solder. Alternatively, the conductive bonding layer 23 may include a sintered body of metal particles. The first electrodes 211 of the multiple first elements 21A are conductively bonded to the first main surface 121A of the first conductive layer 121 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple first elements 21A are electrically connected to the first conductive layer 121. The first electrodes 211 of the multiple second elements 21B are conductively bonded to the second main surface 122A of the second conductive layer 122 via the conductive bonding layer 23. As a result, the first electrodes 211 of the multiple second elements 21B are electrically connected to the second conductive layer 122.

[0161] As shown in FIGS. 32 and 38 , the first input terminal 13 is located on the opposite side of the second conductive layer 122 in the second direction x, with the first conductive layer 121 sandwiched therebetween, and is connected to the first conductive layer 121. This allows the first input terminal 13 to be electrically connected to the first electrodes 211 of the multiple first elements 21A via the first conductive layer 121. The first input terminal 13 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The first input terminal 13 extends from the first conductive layer 121 in the second direction x. The first input terminal 13 has a covering portion 13A and an exposed portion 13B. As shown in FIG. 38 , the covering portion 13A is connected to the first conductive layer 121 and is covered with a sealing resin 50. The covering portion 13A is flush with the first main surface 121A of the first conductive layer 121. The exposed portion 13B extends from the covered portion 13A in the second direction x and is exposed from the sealing resin 50. The thickness of the first input terminal 13 is thinner than the thickness of the first conductive layer 121.

[0162] As shown in FIGS. 32 and 37 , the output terminal 14 is located on the opposite side of the first conductive layer 121 in the second direction x, sandwiching the second conductive layer 122 therebetween, and is connected to the second conductive layer 122. This allows the output terminal 14 to be electrically connected to the first electrodes 211 of the plurality of second elements 21B via the second conductive layer 122. AC power converted by the semiconductor elements 21 is output from the output terminal 14. In the semiconductor device B10, the output terminal 14 includes a pair of regions spaced apart from each other in the third direction y. Alternatively, the output terminal 14 may have a single configuration without a pair of regions. The output terminal 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIG. 37 , the covering portion 14A is connected to the second conductive layer 122 and covered with a sealing resin 50. The covering portion 14A is flush with the second main surface 122A of the second conductive layer 122. The exposed portion 14B extends from the covered portion 14A in the second direction x and is exposed from the sealing resin 50. The thickness of the output terminal 14 is thinner than the thickness of the second conductive layer 122.

[0163] As shown in FIGS. 32 and 37 , the second input terminal 15 is located on the same side as the first input terminal 13 with respect to the first conductive layer 121 and the second conductive layer 122 in the second direction x, but is located away from the first conductive layer 121 and the second conductive layer 122. The second input terminal 15 is electrically connected to the second electrodes 212 of the plurality of second elements 21B. The second input terminal 15 is an N terminal (negative electrode) to which a DC power supply voltage to be converted is applied. The second input terminal 15 includes a pair of regions located away from each other in the third direction y. The first input terminal 13 is located between the pair of regions in the third direction y. The second input terminal 15 has a covering portion 15A and an exposed portion 15B. As shown in FIG. 37 , the covering portion 15A is located away from the first conductive layer 121 and is covered with a sealing resin 50. The exposed portion 15B extends from the covered portion 15A in the second direction x and is exposed from the sealing resin 50.

[0164] The pair of control wirings 60 constitute part of the conductive paths between the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, and the pair of sixth signal terminals 182, and the plurality of semiconductor elements 21. As shown in FIGS. 32 to 34 , the pair of control wirings 60 includes a first wiring 601 and a second wiring 602. In the second direction x, the first wiring 601 is located between the plurality of first elements 21A and the first input terminal 13 and the second input terminal 15. The first wiring 601 is bonded to the first main surface 121A of the first conductive layer 121. The first wiring 601 also constitutes part of the conductive path between the seventh signal terminal 19 and the first conductive layer 121. In the second direction x, the second wiring 602 is located between the plurality of second elements 21B and the output terminal 14. The second wiring 602 is joined to the second main surface 122A of the second conductive layer 122. As shown in Figures 39 and 40 , the pair of control wirings 60 has an insulating layer 61, multiple wiring layers 62, a metal layer 63, and multiple sleeves 64. The pair of control wirings 60 is covered with sealing resin 50 except for a portion of each of the multiple sleeves 64.

[0165] 39 and 40 , the insulating layer 61 includes a portion interposed between the plurality of wiring layers 62 and the metal layer 63 in the first direction z. The insulating layer 61 is made of, for example, ceramics. The insulating layer 61 may be made of an insulating resin sheet instead of ceramics.

[0166] 39 and 40 , the multiple wiring layers 62 are located on one side of the insulating layer 61 in the first direction z. The multiple wiring layers 62 contain copper. As shown in Fig. 34 , the multiple wiring layers 62 include a first wiring layer 621, a second wiring layer 622, a pair of third wiring layers 623, a fourth wiring layer 624, and a fifth wiring layer 625. The pair of third wiring layers 623 are adjacent to each other in the third direction y.

[0167] 39 and 40 , the metal layer 63 is located on the opposite side of the multiple wiring layers 62 in the first direction z, with the insulating layer 61 sandwiched therebetween. The metal layer 63 contains copper. The metal layer 63 of the first wiring 601 is bonded to the first main surface 121A of the first conductive layer 121 by a second adhesive layer 68. The metal layer 63 of the second wiring 602 is bonded to the second main surface 122A of the second conductive layer 122 by the second adhesive layer 68. The second adhesive layer 68 is made of a material that may or may not be conductive. The second adhesive layer 68 is, for example, solder.

[0168] As shown in Figures 39 and 40 , each of the multiple sleeves 64 is bonded to one of the multiple wiring layers 62 by a third adhesive layer 69. The multiple sleeves 64 are made of a conductive material such as metal. Each of the multiple sleeves 64 has a cylindrical shape extending along the first direction z. One end of the multiple sleeves 64 is conductively bonded to one of the multiple wiring layers 62. As shown in Figures 31 and 38 , an end surface 641 corresponding to the other end of the multiple sleeves 64 is exposed from the top surface 51 of the sealing resin 50, which will be described later. The third adhesive layer 69 is conductive. The third adhesive layer 69 is, for example, solder.

[0169] As shown in FIG. 33 , one of the pair of thermistors 22 is conductively joined to a pair of third wiring layers 623 of the first wiring 601. As shown in FIG. 33 , the other of the pair of thermistors 22 is conductively joined to a pair of third wiring layers 623 of the second wiring 602. The pair of thermistors 22 are, for example, NTC (Negative Temperature Coefficient) thermistors. NTC thermistors have the characteristic of gradually decreasing resistance as temperature increases. The pair of thermistors 22 are used as temperature detection sensors for the semiconductor device B10.

[0170] As shown in Fig. 30 , the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, the pair of sixth signal terminals 182, and the seventh signal terminal 19 are made of metal pins extending in the first direction z. These terminals protrude from the top surface 51 of the sealing resin 50, which will be described later. Furthermore, these terminals are individually press-fitted into the multiple sleeves 64 of the pair of control wires 60. As a result, each of these terminals is supported by one of the multiple sleeves 64 and is electrically connected to one of the multiple wiring layers 62.

[0171] 34 and 39 , the first signal terminal 161 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the first wiring layer 621 of the first wire 601. As a result, the first signal terminal 161 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the first wire 601. Furthermore, the first signal terminal 161 is electrically connected to the third electrodes 213 of the multiple first elements 21A. A gate voltage for driving the multiple first elements 21A is applied to the first signal terminal 161.

[0172] 34 and 40 , the second signal terminal 162 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the first wiring layer 621 of the second wire 602. As a result, the second signal terminal 162 is supported by the sleeve 64 and is electrically connected to the first wiring layer 621 of the second wire 602. Furthermore, the second signal terminal 162 is electrically connected to the third electrodes 213 of the multiple second elements 21B. A gate voltage for driving the multiple second elements 21B is applied to the second signal terminal 162.

[0173] As shown in Fig. 31 , the third signal terminal 171 is located next to the first signal terminal 161 in the third direction y. As shown in Fig. 34 , the third signal terminal 171 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the second wiring layer 622 of the first wire 601. As a result, the third signal terminal 171 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the first wire 601. Furthermore, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple first elements 21A is applied to the third signal terminal 171.

[0174] As shown in FIG. 31 , the fourth signal terminal 172 is located next to the second signal terminal 162 in the third direction y. As shown in FIG. 34 , the fourth signal terminal 172 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the second wiring layer 622 of the second wire 602. As a result, the fourth signal terminal 172 is supported by the sleeve 64 and is electrically connected to the second wiring layer 622 of the second wire 602. Furthermore, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. A voltage corresponding to the maximum current among the currents flowing through the fourth electrodes 214 of the multiple second elements 21B is applied to the fourth signal terminal 172.

[0175] As shown in FIG. 31 , the pair of fifth signal terminals 181 are located on the opposite side of the third signal terminal 171 in the third direction y, with the first signal terminal 161 sandwiched therebetween. The pair of fifth signal terminals 181 are adjacent to each other in the third direction y. As shown in FIG. 34 , the pair of fifth signal terminals 181 are individually press-fitted into a pair of sleeves 64, among the multiple sleeves 64 of the pair of control wires 60, that are joined to the pair of third wiring layers 623 of the first wire 601. As a result, the pair of fifth signal terminals 181 are supported by the pair of sleeves 64 and are electrically connected to the pair of third wiring layers 623 of the first wire 601. Furthermore, the pair of fifth signal terminals 181 are electrically connected to the thermistor 22, among the pair of thermistors 22, that is electrically connected to the pair of third wiring layers 623 of the first wire 601.

[0176] As shown in FIG. 31 , the pair of sixth signal terminals 182 are located on the opposite side of the fourth signal terminal 172 in the third direction y, with the second signal terminal 162 sandwiched therebetween. The pair of sixth signal terminals 182 are adjacent to each other in the third direction y. As shown in FIG. 34 , the pair of sixth signal terminals 182 are individually press-fitted into a pair of sleeves 64, among the multiple sleeves 64 of the pair of control wires 60, that are joined to the pair of third wiring layers 623 of the second wire 602. As a result, the pair of sixth signal terminals 182 are supported by the pair of sleeves 64 and are electrically connected to the pair of third wiring layers 623 of the second wire 602. Furthermore, the pair of sixth signal terminals 182 are electrically connected to the thermistor 22, among the pair of thermistors 22, that is electrically connected to the pair of third wiring layers 623 of the second wire 602.

[0177] As shown in Fig. 31 , the seventh signal terminal 19 is located on the opposite side of the first signal terminal 161 in the third direction y, with the third signal terminal 171 sandwiched therebetween. As shown in Fig. 34 , the seventh signal terminal 19 is press-fitted into one of the multiple sleeves 64 of the pair of control wires 60 that is joined to the fifth wiring layer 625 of the first wire 601. As a result, the seventh signal terminal 19 is supported by the sleeve 64 and is electrically connected to the fifth wiring layer 625 of the first wire 601. Furthermore, the seventh signal terminal 19 is electrically connected to the first conductive layer 121. A voltage equivalent to the DC power input to the first input terminal 13 and the second input terminal 15 is applied to the seventh signal terminal 19.

[0178] As shown in FIG. 34 , the multiple first wires 41 are conductively bonded to the third electrodes 213 of the multiple first elements 21A and the fourth wiring layer 624 of the first wiring 601. As shown in FIG. 34 , the multiple third wires 43 are conductively bonded to the fourth wiring layer 624 of the first wiring 601 and the first wiring layer 621 of the first wiring 601. This allows the first signal terminal 161 to be electrically connected to the third electrodes 213 of the multiple first elements 21A. The composition of the multiple first wires 41 and the multiple third wires 43 includes gold (Au). Alternatively, the composition of the multiple first wires 41 and the multiple third wires 43 may include copper or aluminum.

[0179] 34, the plurality of first wires 41 are conductively joined to the third electrodes 213 of the plurality of second elements 21B and the fourth wiring layer 624 of the second wiring 602. Furthermore, the plurality of third wires 43 are conductively joined to the fourth wiring layer 624 of the second wiring 602 and the first wiring layer 621 of the second wiring 602. As a result, the second signal terminal 162 is electrically connected to the third electrodes 213 of the plurality of second elements 21B.

[0180] As shown in FIG. 34 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple first elements 21A and the second wiring layer 622 of the first wiring 601. As a result, the third signal terminal 171 is electrically connected to the fourth electrodes 214 of the multiple first elements 21A. Furthermore, as shown in FIG. 34 , the multiple second wires 42 are conductively bonded to the fourth electrodes 214 of the multiple second elements 21B and the second wiring layer 622 of the second wiring 602. As a result, the fourth signal terminal 172 is electrically connected to the fourth electrodes 214 of the multiple second elements 21B. The composition of the multiple second wires 42 includes gold. Alternatively, the composition of the multiple second wires 42 may include copper or aluminum.

[0181] 34 , the fourth wire 44 is conductively bonded to the fifth wiring layer 625 of the first wiring 601 and the first main surface 121A of the first conductive layer 121. This allows the seventh signal terminal 19 to be electrically connected to the first conductive layer 121. The composition of the fourth wire 44 includes gold. Alternatively, the composition of the fourth wire 44 may include copper or aluminum.

[0182] As shown in Figures 34 and 39, the first conductive member 31 is conductively bonded to the second electrodes 212 of the multiple first elements 21A and the second main surface 122A of the second conductive layer 122. This allows the second electrodes 212 of the multiple first elements 21A to be electrically connected to the second conductive layer 122. The first conductive member 31 contains copper. The first conductive member 31 is a metal clip. As shown in Figure 34, the first conductive member 31 has a main body 311, multiple first joint portions 312, multiple first connecting portions 313, second joint portions 314, and second connecting portions 315.

[0183] The main body portion 311 forms a main portion of the first conductive member 31. As shown in Fig. 34 , the main body portion 311 extends in the third direction y. As shown in Fig. 38 , the main body portion 311 straddles between the first conductive layer 121 and the second conductive layer 122.

[0184] 39 , the multiple first bonding portions 312 are individually bonded to the second electrodes 212 of the multiple first elements 21A. Each of the multiple first bonding portions 312 faces the second electrode 212 of one of the multiple first elements 21A.

[0185] 34 , the multiple first coupling portions 313 are connected to the main body portion 311 and the multiple first bonding portions 312. The multiple first coupling portions 313 are spaced apart from one another in the third direction y. As shown in FIG. 38 , when viewed in the third direction y, the multiple first coupling portions 313 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they extend from the multiple first bonding portions 312 toward the main body portion 311.

[0186] 34 and 38 , the second bonding portion 314 is bonded to the second main surface 122A of the second conductive layer 122. The second bonding portion 314 faces the second main surface 122A. The second bonding portion 314 extends in the third direction y. The dimension of the second bonding portion 314 in the third direction y is equal to the dimension of the main body portion 311 in the third direction y.

[0187] 34 and 38 , the second connecting portion 315 is connected to the main body portion 311 and the second bonding portion 314. When viewed along the third direction y, the second connecting portion 315 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it extends from the second bonding portion 314 toward the main body portion 311. The dimension of the second connecting portion 315 in the third direction y is equal to the dimension of the main body portion 311 in the third direction y.

[0188] 38, 39, and 40, the semiconductor device B10 further includes a first conductive bonding layer 33. The first conductive bonding layer 33 is interposed between the second electrodes 212 of the plurality of first elements 21A and the plurality of first bonding portions 312. The first conductive bonding layer 33 conductively bonds the second electrodes 212 of the plurality of first elements 21A to the plurality of first bonding portions 312. The first conductive bonding layer 33 is, for example, solder. Alternatively, the first conductive bonding layer 33 may include a sintered body of metal particles.

[0189] 38 , the semiconductor device B10 further includes a second conductive bonding layer 34. The second conductive bonding layer 34 is interposed between the second main surface 122A of the second conductive layer 122 and the second bonding portion 314. The second conductive bonding layer 34 conductively bonds the second main surface 122A and the second bonding portion 314. The second conductive bonding layer 34 is, for example, solder. Alternatively, the second conductive bonding layer 34 may include a sintered body of metal particles.

[0190] As shown in FIGS. 22 and 40 , the second conductive member 32 is conductively joined to the second electrodes 212 of the plurality of second elements 21B and the covering portion 15A of the second input terminal 15. This electrically connects the second electrodes 212 of the plurality of second elements 21B to the second input terminal 15. The second conductive member 32 contains copper. The second conductive member 32 is a metal clip. As shown in FIG. 33 , the second conductive member 32 has a pair of main body portions 321, a plurality of third joint portions 322, a plurality of third connecting portions 323, a pair of fourth joint portions 324, a pair of fourth connecting portions 325, a plurality of intermediate portions 326, and a plurality of cross beam portions 327.

[0191] As shown in Fig. 33 , the pair of main bodies 321 are spaced apart from each other in the third direction y. The pair of main bodies 321 extend in the second direction x. As shown in Fig. 37 , the pair of main bodies 321 are arranged parallel to the first main surface 121A of the first conductive layer 121 and the second main surface 122A of the second conductive layer 122. The pair of main bodies 321 are located farther from the first main surface 121A and the second main surface 122A than the main body 311 of the first conductive member 31.

[0192] 33 , the intermediate portions 326 are spaced apart from one another in the third direction y and are located between the pair of main body portions 321 in the third direction y. The intermediate portions 326 extend in the second direction x. The dimension of each of the intermediate portions 326 in the second direction x is smaller than the dimension of each of the pair of main body portions 321 in the second direction x.

[0193] 40 , the multiple third joints 322 are individually joined to the second electrodes 212 of the multiple second elements 21B. Each of the multiple third joints 322 faces the second electrode 212 of one of the multiple second elements 21B.

[0194] 33 and 41 , the multiple third connecting portions 323 are connected to both sides of the multiple third joint portions 322 in the third direction y. Furthermore, the multiple third connecting portions 323 are connected to either the pair of main body portions 321 or the multiple intermediate portions 326. When viewed along the second direction x, each of the multiple third connecting portions 323 is inclined in a direction away from the second main surface 122A of the second conductive layer 122 as it moves from either one of the multiple third joint portions 322 to either the pair of main body portions 321 or the multiple intermediate portions 326.

[0195] 33 and 37, the pair of fourth joint portions 324 are joined to the covering portion 15A of the second input terminal 15. The pair of fourth joint portions 324 face the covering portion 15A.

[0196] 33 and 37 , the pair of fourth connecting portions 325 are connected to the pair of main body portions 321 and the pair of fourth joint portions 324. When viewed in the third direction y, the pair of fourth connecting portions 325 are inclined in a direction away from the first main surface 121A of the first conductive layer 121 as they extend from the pair of fourth joint portions 324 toward the pair of main body portions 321.

[0197] As shown in FIGS. 33 and 42 , the multiple cross beam portions 327 are arranged along the third direction y. As viewed along the first direction z, the multiple cross beam portions 327 include regions that individually overlap the multiple first joint portions 312 of the first conductive member 31. Of the multiple cross beam portions 327, the cross beam portion 327 located at the center in the third direction y is connected to the multiple intermediate portions 326 on both sides in the third direction y. Of the multiple cross beam portions 327, the remaining two cross beam portions 327 are connected to one of the pair of main body portions 321 and one of the multiple intermediate portions 326 on both sides in the third direction y. As viewed along the second direction x, the multiple cross beam portions 327 are convex in the first direction z toward the first main surface 121A of the first conductive layer 121.

[0198] 38, 40, and 41, the semiconductor device B10 further includes a third conductive bonding layer 35. The third conductive bonding layer 35 is interposed between the second electrodes 212 of the plurality of second elements 21B and the plurality of third bonding portions 322. The third conductive bonding layer 35 conductively bonds the second electrodes 212 of the plurality of second elements 21B to the plurality of third bonding portions 322. The third conductive bonding layer 35 is, for example, solder. Alternatively, the third conductive bonding layer 35 may include a sintered body of metal particles.

[0199] 37 , the semiconductor device B10 further includes a fourth conductive bonding layer 36. The fourth conductive bonding layer 36 is interposed between the covering portion 15A of the second input terminal 15 and the pair of fourth joint portions 324. The fourth conductive bonding layer 36 conductively bonds the covering portion 15A and the pair of fourth joint portions 324. The fourth conductive bonding layer 36 is, for example, solder. Alternatively, the fourth conductive bonding layer 36 may include a sintered body of metal particles.

[0200] As shown in FIGS. 37, 38, 41, and 42, the sealing resin 50 covers the first conductive layer 121, the second conductive layer 122, the plurality of semiconductor elements 21, the first conductive members 31, and the second conductive members 32. The sealing resin 50 also covers a portion of each of the support 11, the first input terminal 13, the output terminal 14, and the second input terminal 15. The sealing resin 50 has electrical insulation properties. The sealing resin 50 is made of a material containing, for example, black epoxy resin. As shown in FIGS. 31 and 35 to 38, the sealing resin 50 has a top surface 51, a bottom surface 52, a pair of first side surfaces 53, a pair of second side surfaces 54, and a pair of recesses 55.

[0201] 37 and 38 , top surface 51 faces the same side in first direction z as first main surface 121A of first conductive layer 121. As shown in Fig. 37 and 38 , bottom surface 52 faces the opposite side in first direction z from top surface 51. As shown in Fig. 36 , heat dissipation layer 113 of support body 11 is exposed from bottom surface 52.

[0202] 31 and 35 , the pair of first side surfaces 53 are spaced apart from each other in the second direction x. The pair of first side surfaces 53 face the second direction x and extend in the third direction y. The pair of first side surfaces 53 are connected to the top surface 51. An exposed portion 13B of the first input terminal 13 and an exposed portion 15B of the second input terminal 15 are exposed from one of the pair of first side surfaces 53. An exposed portion 14B of the output terminal 14 is exposed from the other of the pair of first side surfaces 53.

[0203] 31 and 36 , the pair of second side surfaces 54 are spaced apart from each other in the third direction y. The pair of second side surfaces 54 face opposite each other in the third direction y and extend in the second direction x. The pair of second side surfaces 54 are connected to the top surface 51 and the bottom surface 52.

[0204] 31 and 36 , the pair of recesses 55 are recessed in the second direction x from the first side surfaces 53 on which the exposed portion 13B of the first input terminal 13 and the exposed portion 15B of the second input terminal 15 are exposed. The pair of recesses 55 extend from the top surface 51 to the bottom surface 52 in the first direction z. The pair of recesses 55 are located on both sides of the first input terminal 13 in the third direction y.

[0205] 23 to 29, the semiconductor module A10 will be described. The semiconductor module A10 includes the aforementioned semiconductor devices B10, a heat sink 70, a plurality of first wiring boards 71, a second wiring board 72, a plurality of interconnection wires 73, a plurality of mounting members 74, a plurality of support members 75, and a plurality of positioning pins 76. The semiconductor module A10 is used, for example, in an inverter for driving a three-phase AC motor.

[0206] As shown in Figures 23 and 24, the heat sink 70 supports the multiple semiconductor devices B10. The heat sink 70 is located on the opposite side of the multiple semiconductor devices B10 from the first signal terminals 161 and second signal terminals 162 with respect to the multiple semiconductor elements 21 of the multiple semiconductor devices B10 (see Figures 24 and 42). Therefore, the heat sink 70 faces the heat dissipation layers 113 of the multiple semiconductor devices B10. The heat sink 70 is made of a material containing aluminum, for example. The multiple semiconductor devices B10 are arranged on the heat sink 70 along the third direction y.

[0207] As shown in FIG. 25 , the multiple first wiring boards 71 ​​are individually electrically connected to the first signal terminal 161, the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, a pair of fifth signal terminals 181, a pair of sixth signal terminals 182, and the seventh signal terminal 19 of the multiple semiconductor devices B10. As shown in FIG. 26 , each of the multiple first wiring boards 71 ​​faces the top surface 51 of the sealing resin 50 of one of the multiple semiconductor devices B10. The multiple first wiring boards 71 ​​are located on the opposite side of the heat sink 70 from the multiple semiconductor elements 21 of the multiple semiconductor devices B10 (see FIGS. 24 and 42 ). When viewed along the first direction z, the multiple first wiring boards 71 ​​individually overlap the sealing resin 50 of the multiple semiconductor devices B10.

[0208] 27A , each of the multiple first wiring boards 71 ​​has a board 711, main wiring 712, back wiring 713, and internal wiring 714. The board 711 has multiple through holes 711A that penetrate in the first direction z. The main wiring 712 is arranged on one side of the board 711 in the first direction z and faces the second wiring board 72. The back wiring 713 is arranged on the other side of the board 711 in the first direction z. The internal wiring 714 is arranged in the multiple through holes 711A. The internal wiring 714 is connected to the main wiring 712 and the back wiring 713. The main wiring 712 forms a path for mutual conduction between the internal wiring 714, a circuit provided on one of the multiple first wiring boards 71, and one of the multiple interconnection wirings 73 that is conductive to that circuit.

[0209] 27A , each of the first signal terminals 161 of the multiple semiconductor devices B10 has a base 161A and a bulge 161B. One side of the base 161A in the first direction z is press-fitted into one of the multiple sleeves 64 of the multiple semiconductor devices B10. The bulge 161B is provided on the other side of the base 161A in the first direction z. The bulge 161B bulges in a direction perpendicular to the first direction z.

[0210] 27A , each of the first signal terminals 161 of the multiple semiconductor devices B10 is press-fitted into one of the multiple through holes 711A of the multiple first wiring substrates 71. As a result, the internal wiring 714 arranged in one of the multiple through holes 711A is pressure-contacted with the bulging portion 161B of the first signal terminal 161. Therefore, by being press-fitted into one of the multiple first wiring substrates 71 in the first direction z, each of the first signal terminals 161 of the multiple semiconductor devices B10 is electrically connected to that first wiring substrate 71. Each of the second signal terminal 162, the third signal terminal 171, the fourth signal terminal 172, the pair of fifth signal terminals 181, the pair of sixth signal terminals 182, and the seventh signal terminal 19 of the multiple semiconductor devices B10 also has a configuration similar to the base portion 161A and the bulging portion 161B of the first signal terminal 161. As a result, these signal terminals are also press-fitted into any of the plurality of first wiring boards 71 ​​in the first direction z and are electrically connected to that first wiring board 71 .

[0211] 27B shows a different configuration of the first signal terminals 161 of the multiple semiconductor devices B10 from that shown in FIG. The first signal terminals 161 have a seat 161C in addition to a base 161A and a bulge 161B. When the first signal terminal 161 is press-fitted into one of the multiple through-holes 711A of the multiple first wiring substrates 71, the internal wiring 714 arranged in the through-hole 711A is pressed against the bulge 161B, and the seat 161C comes into contact with the back wiring 713.

[0212] As shown in FIG. 29, each of the plurality of first wiring substrates 71 is provided with a pair of first protection circuits 81, a pair of second protection circuits 82, a pair of gate drivers 83, and a pair of gate resistors 84.

[0213] One of the pair of first protection circuits 81 is electrically connected to the first signal terminal 161 and the third signal terminal 171 of the semiconductor device B10. The other of the pair of first protection circuits 81 is electrically connected to the second signal terminal 162 and the fourth signal terminal 172. The pair of first protection circuits 81 suppresses application of an overvoltage to the third electrodes 23 of the multiple semiconductor elements 21 of the semiconductor device B10. The pair of first protection circuits 81 generally includes a snubber circuit.

[0214] One of the pair of second protection circuits 82 is electrically connected to the first signal terminal 161 and the seventh signal terminal 19 of the semiconductor device B10. The other of the pair of second protection circuits 82 is electrically connected to the second signal terminal 162 and a second driver 83B, which will be described later. The pair of second protection circuits 82 suppresses surge voltages from being applied to the multiple semiconductor elements 21 of the semiconductor device B10. The pair of second protection circuits 82 generally includes a clamp circuit.

[0215] The pair of gate drivers 83 includes a first driver 83A and a second driver 83B. The first driver 83A is electrically connected to one first protection circuit 81 and one second protection circuit 82, and drives the plurality of first elements 21A of the semiconductor device B10. The second driver 83B is electrically connected to the other first protection circuit 81 and the other second protection circuit 82, and drives the plurality of second elements 21B of the semiconductor device B10. One of the pair of gate resistors 84 is provided in the conductive path between the first driver 83A and the first signal terminal 161. The other of the pair of gate resistors 84 is provided in the conductive path between the second driver 83B and the second signal terminal 162.

[0216] In the semiconductor module A10, at least a pair of first protection circuits 81 is provided on each of the multiple first wiring substrates 71. Therefore, the pair of second protection circuits 82, the pair of gate drivers 83, and the pair of gate resistors 84 may be provided on the second wiring substrate 72.

[0217] As shown in FIG. 24 , the second wiring board 72 is electrically connected to the plurality of first wiring boards 71 ​​via a plurality of interconnections 73. As shown in FIG. 23 , the second wiring board 72 extends in the third direction y. The second wiring board 72 is provided with circuits that drive and control the plurality of semiconductor devices B10, such as a controller for controlling the pair of gate drivers 83, but that are not provided on the plurality of first wiring boards 71. Furthermore, the second wiring board 72 is provided with an overheat protection circuit that is electrically connected to the pair of thermistors 22 of the plurality of semiconductor devices B10. The second wiring board 72 is located on the opposite side of the heat sink 70 in the first direction z, with the plurality of first wiring boards 71 ​​sandwiched therebetween. When viewed in the first direction z, the second wiring board 72 overlaps the plurality of first wiring boards 71.

[0218] As shown in FIG. 24 , the multiple interconnection wires 73 electrically connect the multiple first wiring boards 71 ​​and the second wiring board 72. In the semiconductor module A10, the multiple interconnection wires 73 have a first connection portion 731 and a second connection portion 732. As shown in FIG. 25 , the first connection portion 731 is electrically connected to one of the multiple first wiring boards 71. As shown in FIGS. 25 and 26 , the first connection portion 731 includes multiple connection pins 731A. The multiple connection pins 731A extend in the first direction z. As shown in FIG. 26 , the second connection portion 732 is electrically connected to the second wiring board 72 and faces the first connection portion 731. As shown in FIG. 28 , the second connection portion 732 has a housing portion 732A and multiple connection holes 732B. The multiple connection pins 731A are individually inserted into the multiple connection holes 732B. As a result, the first connecting portion 731 is electrically connected to the second connecting portion 732 .

[0219] 28 , the housing portion 732A of the second connection portion 732 can be displaced relative to the multiple connection pins 731A in a direction perpendicular to the first direction z. This allows the second connection portion 732 to be displaced relative to the first connection portion 731 in a direction perpendicular to the first direction z. Therefore, the multiple communication wires 73 are configured to be displaceable in a direction perpendicular to the first direction z. The configuration of such multiple communication wires 73 can be applied to known connector configurations disclosed in Japanese Patent Application Laid-Open Nos. 2018-113163, 2018-63886, and 2017-139101, for example.

[0220] As shown in FIGS. 23 and 24 , the multiple mounting members 74 are used to fasten the multiple semiconductor devices B10 to the heat sink 70. The multiple mounting members 74 are conductors containing metal. The multiple mounting members 74 individually contact the top surfaces 51 of the sealing resin 50 of the multiple semiconductor devices B10 and individually straddle the top surfaces 51 of the sealing resin 50 of the multiple semiconductor devices B10. The multiple mounting members 74 are, for example, leaf springs. Each of the multiple mounting members 74 is located between the first signal terminal 161 and the second signal terminal 162 of any of the multiple semiconductor devices B10 in the second direction x. The multiple mounting members 74 are located between the heat sink 70 and the multiple first wiring boards 71 ​​in the first direction z.

[0221] 24 , the plurality of support members 75 are positioned between the heat sink 70 and the plurality of first wiring boards 71 ​​in the first direction z. The plurality of first wiring boards 71 ​​are supported by the plurality of support members 75. The plurality of support members 75 are columnar. As shown in FIG. 25 , when viewed along the first direction z, the plurality of support members 75 are positioned away from the top surfaces 51 of the sealing resin 50 of the plurality of semiconductor devices B10.

[0222] 24 , the positioning pins 76 are positioned between the heat sink 70 and the second wiring board 72 in the first direction z. The positioning pins 76 are arranged along the third direction y. Each of the positioning pins 76 is positioned between two of the multiple semiconductor devices B10 that are adjacent to each other in the third direction y. The positioning pins 76 are used to determine the position of the second wiring board 72 relative to the heat sink 70 and to support the second wiring board 72.

[0223] <Others> Various modifications can be made to the embodiments of the present disclosure as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of embodiments of the present disclosure, and the meanings of the terms in the present disclosure and each constituent element are not limited to those described in the above-described embodiments.

[0224] <Supplementary Note> Supplementary notes are provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0225] A DC / DC converter (CNV1, CNV1A to CNV1D) of the present disclosure includes a pair of first terminals (T1A, T1B) configured to receive a first DC power, a pair of second terminals (T2A, T2B) configured to output a second DC power, a primary side circuit (1), a secondary side circuit (2), a first capacitor (C1), and a second capacitor (C2), the primary side circuit includes a first semiconductor switching element (Q1) and a first reactor (L1), the secondary side circuit includes at least one of a diode (D1) and a second semiconductor switching element (Q2), and a second reactor (L2), the primary side circuit is provided between the pair of first terminals and the first capacitor and the second capacitor, and the secondary side circuit is provided between the first capacitor and the second capacitor and the pair of second terminals (first configuration).

[0226] The DC / DC converter having the first configuration may be configured (second configuration) such that ¼ of the resonance period of a series resonance circuit formed by the second reactor, the first capacitor, and the second capacitor is longer than the on-time of the first semiconductor switching element.

[0227] In the DC / DC converter having the first or second configuration, the secondary-side circuit may include the diode, a first end of the first reactor and a first end of the first semiconductor switching element are connected to a first end of the second reactor and an anode of the diode via the first capacitor, a second end of the first semiconductor switching element is connected to a second end of the second reactor via the second capacitor, one of the pair of first terminals is connected to the second end of the first reactor, the other of the pair of first terminals is connected to the second end of the first semiconductor switching element, one of the pair of second terminals is connected to the cathode of the diode, and the other of the pair of second terminals is connected to the second end of the second reactor (third configuration).

[0228] In the DC / DC converter having the first or second configuration, the secondary-side circuit may include the diode, a first end of the first semiconductor switching element and a first end of the first reactor connected to the cathode of the diode and the first end of the second reactor via the first capacitor, a second end of the first reactor connected to the anode of the diode via the second capacitor, one of the pair of first terminals connected to the second end of the first semiconductor switching element, the other of the pair of first terminals connected to the second end of the first reactor, one of the pair of second terminals connected to the second end of the second reactor, and the other of the pair of second terminals connected to the anode of the diode (a fourth configuration).

[0229] In the DC / DC converter having the first or second configuration, the secondary-side circuit may include the diode, a first end of the first reactor and a first end of the first semiconductor switching element are connected to an anode of the diode and a first end of the second reactor via the first capacitor, a second end of the first semiconductor switching element is connected to a cathode of the diode via the second capacitor, one of the pair of first terminals is connected to a second end of the first reactor, the other of the pair of first terminals is connected to a second end of the first semiconductor switching element, one of the pair of second terminals is connected to a second end of the second reactor, and the other of the pair of second terminals is connected to the cathode of the diode (a fifth configuration).

[0230] In the DC / DC converter having the first or second configuration, the secondary-side circuit may include the second semiconductor switching element, a first end of the first reactor and a first end of the first semiconductor switching element are connected to a first end of the second reactor and a first end of the second semiconductor switching element via the first capacitor, a second end of the first semiconductor switching element is connected to a second end of the second reactor via the second capacitor, one of the pair of first terminals is connected to the second end of the first reactor, the other of the pair of first terminals is connected to the second end of the first semiconductor switching element, one of the pair of second terminals is connected to the second end of the second semiconductor switching element, and the other of the pair of second terminals is connected to the second end of the second reactor (sixth configuration).

[0231] The DC / DC converter having any of the first to sixth configurations may further include a control unit (CNV1), and the control unit may be configured to stop the switching operation of the first semiconductor switching element for a predetermined period of time immediately after starting the DC / DC converter (seventh configuration).

[0232] The DC / DC converter having any of the first to sixth configurations may further include a control unit (CNV1), wherein the control unit is configured to control the duty of the first semiconductor switching element so that the voltage output from the pair of second terminals becomes a target value, and the control unit is configured to increase the duty in a ramp-like manner immediately after startup of the DC / DC converter (eighth configuration).

[0233] The DC / DC converter having any of the first to eighth configurations may further include a control unit (CNV1), wherein the secondary-side circuit includes the diode, and the control unit is configured to estimate a current flowing through the diode based on a current flowing through the first semiconductor switching element, calculate a forward voltage drop across the diode based on the estimated current flowing through the diode, and control the duty of the first semiconductor switching element using a sum of the calculated forward voltage drop across the diode and a target value for a voltage output from the pair of second terminals (ninth configuration).

[0234] In the DC / DC converter having any of the first to ninth configurations described above, the withstand voltage of the first semiconductor switching element may be equal to or greater than the sum of the input voltage applied to the pair of first terminals, the maximum voltage of the first capacitor, and the maximum voltage of the second capacitor (tenth configuration).

[0235] The semiconductor device (3) of the present disclosure includes a power module and a DC / DC converter having any one of the first to tenth configurations described above, and the DC / DC converter is configured to supply power for driving and controlling the power module (eleventh configuration).

[0236] In the semiconductor device of the eleventh configuration, the semiconductor module includes a plurality of semiconductor devices (B10), each of which includes a semiconductor element and a signal terminal (161) extending in a first direction and conducting to the semiconductor element; and a heat sink (70) located on the opposite side of the semiconductor element in the first direction from the side on which the signal terminal is located, and supporting the plurality of semiconductor devices. The semiconductor device may be configured to include a plurality of first wiring boards (71) located on the opposite side of the semiconductor element in the first direction from the side on which the heat sink is located, and which individually conduct to the signal terminals of the plurality of semiconductor devices, and a second wiring board (72) which conducts to the plurality of first wiring boards, wherein the plurality of first wiring boards are provided with a first protection circuit (81) which prevents overvoltage from being applied to the semiconductor element, and the signal terminal of any of the plurality of semiconductor devices is press-fitted into any of the plurality of first wiring boards in the first direction, and further include a plurality of connecting wires (73) which connect the plurality of first wiring boards and the second wiring board, and wherein the plurality of connecting wires are displaceable in a direction perpendicular to the first direction (twelfth configuration).

[0237] 1 Primary side circuit 2 Secondary side circuit 3 Semiconductor device ADD1 Adder AN1 AND gate C1 First capacitor C2 Second capacitor C3 Output capacitor CNT1 Control unit CNV1, CNV1A to CNV1D DC / DC converter COMP1 Comparator D1 Diode DLY1 Delay circuit GNR1 Gate signal generation unit L1 First reactor L2 Second reactor LD1 Load MAC1 Multiplier PS1 DC power supply OP1 Duty calculation unit OP2 Secondary side current calculation unit OP3 Vf calculation unit OR1 OR gate Q1 First semiconductor switching element Q2 Second semiconductor switching element RAMP1 Ramp voltage generation unit T1A, T1B First terminal T2A, T2B Second terminal A10 Semiconductor module B10, B20, B30 Semiconductor device 11 Support 111 Insulating layer 112 Intermediate layer 113 Heat dissipation layer 121 First support layer 121A First main surface 121B First back surface 122 Second support layer 122A Second main surface 122B Second support layer 123 First adhesive layer 13 First input terminal 13A Covered portion 13B Exposed portion 14 Output terminal 14A Covered portion 14B Exposed portion 15 Second input terminal 15A Covered portion 15B Exposed portion 161 First signal terminal 161A Base portion 161B Bulging portion 161C Seat portion 162 Second signal terminal 171 Third signal terminal 172 Fourth signal terminal 181 Fifth signal terminal 182 Sixth signal terminal 19 Seventh signal terminal 21 Semiconductor element 21A First element 21B Second element 211 First electrode 212 Second electrode 213 Third electrode 214 Fourth electrode 22 Thermistor 23 Conductive bonding layer 31 First conductive member 311 Main body 312 First bonding portion 313 First connecting portion 314 Second bonding portion315 Second connecting portion 32 Second conductive member 321 Main body portion 322 Third bonding portion 323 Third connecting portion 324 Fourth bonding portion 325 Fourth connecting portion 326 Middle portion 327 Cross beam portion 33 First conductive bonding layer 34 Second conductive bonding layer 35 Third conductive bonding layer 36 Fourth conductive bonding layer 41 First wire 42 Second wire 43 Third wire 44 Fourth wire 50 Sealing resin 51 Top surface 52 Bottom surface 53 First side surface 54 Second side surface 55 Recess 56 Pedestal portion 561 Support surface 562 Mounting hole 60 Control wiring 601 First wiring 602 Second wiring 61 Insulating layer 62 Wiring layer 621 First wiring layer 622 Second wiring layer 623 Third wiring layer 624 Fourth wiring layer 625 Fifth wiring layer 63 Metal layer 64 Sleeve 641 End face 65 Support pin 651 Seat surface 66 Base layer 68 Second adhesive layer 69 Third adhesive layer 70 Heat sink 71 First wiring board 711 Board 711A Through hole 712 Main wiring 713 Back wiring 714 Internal wiring 72 Second wiring board 73 Interconnecting wiring 731 First connection part 731A Connection pin 731B Housing part 732 Second connection part 732A Housing part 732B Connection hole 74 Mounting member 75 Support member 76 Positioning pin 77 Fastening member 78 Cover 78A Inner surface 78B Outer surface 781 Main part 782 Beam part 81 First protection circuit 82 Second protection circuit 83 Gate driver 83A First driver 83B Second driver 84 Gate resistor z First direction x Second direction y Third direction

Claims

1. a pair of first terminals configured to receive a first DC power; a pair of second terminals configured to output a second DC power; A primary side circuit; A secondary circuit; A first capacitor; A second capacitor; Equipped with The primary side circuit includes a first semiconductor switching element and a first reactor, the secondary side circuit includes at least one of a diode or a second semiconductor switching element, and a second reactor; the primary side circuit is provided between the pair of first terminals, and the first capacitor and the second capacitor; The secondary side circuit is provided between the first capacitor, the second capacitor and the pair of second terminals.

2. 2. The DC / DC converter according to claim 1, wherein ¼ of a resonance period of a series resonance circuit formed by said second reactor, said first capacitor, and said second capacitor is longer than an ON time of said first semiconductor switching element.

3. the secondary side circuit includes the diode, a first end of the first reactor and a first end of the first semiconductor switching element are connected to a first end of the second reactor and an anode of the diode via the first capacitor; a second end of the first semiconductor switching element is connected to a second end of the second reactor via the second capacitor; one of the pair of first terminals is connected to the second end of the first reactor, and the other of the pair of first terminals is connected to the second end of the first semiconductor switching element; 2 . The DC / DC converter according to claim 1 , wherein one of the pair of second terminals is connected to the cathode of the diode, and the other of the pair of second terminals is connected to the second end of the second reactor.

4. the secondary side circuit includes the diode, a first end of the first semiconductor switching element and a first end of the first reactor are connected to a cathode of the diode and a first end of the second reactor via the first capacitor; a second end of the first reactor is connected to the anode of the diode via the second capacitor; one of the pair of first terminals is connected to the second end of the first semiconductor switching element, and the other of the pair of first terminals is connected to the second end of the first reactor; 2 . The DC / DC converter according to claim 1 , wherein one of the pair of second terminals is connected to the second end of the second reactor, and the other of the pair of second terminals is connected to the anode of the diode.

5. the secondary side circuit includes the diode, a first end of the first reactor and a first end of the first semiconductor switching element are connected to the anode of the diode and the first end of the second reactor via the first capacitor; a second end of the first semiconductor switching element is connected to the cathode of the diode via the second capacitor; one of the pair of first terminals is connected to the second end of the first reactor, and the other of the pair of first terminals is connected to the second end of the first semiconductor switching element; 2 . The DC / DC converter according to claim 1 , wherein one of the pair of second terminals is connected to the second end of the second reactor, and the other of the pair of second terminals is connected to the cathode of the diode.

6. the secondary side circuit includes the second semiconductor switching element, a first end of the first reactor and a first end of the first semiconductor switching element are connected to a first end of the second reactor and a first end of the second semiconductor switching element via the first capacitor; a second end of the first semiconductor switching element is connected to a second end of the second reactor via the second capacitor; one of the pair of first terminals is connected to the second end of the first reactor, and the other of the pair of first terminals is connected to the second end of the first semiconductor switching element; 2. The DC / DC converter according to claim 1, wherein one of the pair of second terminals is connected to the second end of the second semiconductor switching element, and the other of the pair of second terminals is connected to the second end of the second reactor.

7. A control unit is further provided.

2. The DC / DC converter according to claim 1, wherein the control unit is configured to stop a switching operation of the first semiconductor switching element for a predetermined time immediately after start-up of the DC / DC converter.

8. A control unit is further provided. the control unit is configured to control a duty of the first semiconductor switching element so that a voltage output from the pair of second terminals becomes a target value; 2. The DC / DC converter according to claim 1, wherein the control unit is configured to increase the duty in a ramp manner immediately after start-up of the DC / DC converter.

9. A control unit is further provided. the secondary side circuit includes the diode, The control unit is estimating a current flowing through the diode based on a current flowing through the first semiconductor switching element; Calculating a forward drop voltage generated in the diode based on the estimated current flowing through the diode; 2. The DC / DC converter according to claim 1, configured to control a duty of the first semiconductor switching element using a sum of the calculated forward drop voltage generated in the diode and a target value of a voltage output from the pair of second terminals.

10. 2. The DC / DC converter according to claim 1, wherein the withstand voltage of the first semiconductor switching element is equal to or greater than a sum of an input voltage applied to the pair of first terminals, a maximum voltage of the first capacitor, and a maximum voltage of the second capacitor.

11. A power module and a DC / DC converter according to any one of claims 1 to 10, The DC / DC converter is configured to supply power for driving and controlling the power module.

12. The semiconductor module includes: A plurality of semiconductor devices, each of which includes a semiconductor element and a signal terminal extending in a first direction and electrically connected to the semiconductor element; a heat sink located on an opposite side to a side on which the signal terminals are located with respect to the semiconductor element in the first direction and supporting the plurality of semiconductor devices; a plurality of first wiring boards located on an opposite side of the semiconductor element from a side on which the heat sink is located in the first direction, and each of the first wiring boards is electrically connected to the signal terminals of the plurality of semiconductor devices; a second wiring board electrically connected to the plurality of first wiring boards, a first protection circuit that suppresses application of an overvoltage to the semiconductor element is provided on the first wiring substrate; the signal terminal of any one of the plurality of semiconductor devices is press-fitted into any one of the plurality of first wiring substrates in the first direction, a plurality of interconnections for electrically connecting the plurality of first wiring boards and the second wiring board; The semiconductor device of claim 11 , wherein the plurality of interconnects are displaceable in a direction perpendicular to the first direction.