Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor (1) in which the occurrence of dielectric breakdown is further suppressed. The multilayer ceramic capacitor (1) comprises: a laminate (2) including a plurality of dielectric layers (4) and a plurality of internal electrode layers (10) stacked on one another; and external electrodes (20) provided on a first end surface (62a) and a second end surface (62b). The internal electrode layers (10) comprise first internal electrode layers (10a) and second internal electrode layers (10b), the first internal electrode layers (10a) being led to the first end surface (62a), and the second internal electrode layers (10b) being led to the second end surface (62b). The external electrodes (20) include a first external electrode (20a) connected to the first internal electrode layers (10a) and a second external electrode (20b) connected to the second internal electrode layers (10b). A region that is disposed on the first end surface (62a) side and in which the first internal electrode layers (10a) do not overlap each other in the stacking direction (T), and a region that is disposed on the second end surface (62b) side and in which the second internal electrode layers (10b) do not overlap each other in the stacking direction (T) are defined as L gap regions (51). The L gap regions (51) comprise Si segregation layers (14).

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] As multilayer ceramic capacitors become smaller and their capacitance increases, they are more susceptible to dielectric breakdown. Patent Document 1 describes a technique for suppressing this dielectric breakdown by forming at least a portion of the region near the edge of the internal electrode of the dielectric layer from a dielectric ceramic having a higher withstand voltage than other regions.

[0003] Japanese Patent Application Publication No. 11-317321

[0004] In order to further miniaturize and increase capacitance, the thickness of the dielectric layers of multilayer ceramic capacitors has become thinner. As the thickness of the dielectric layers decreases, the insulation resistance value decreases. In particular, in the region where internal electrodes connected to the same external electrode overlap on the end face side of the laminate, the internal electrodes are structurally prone to bending. This causes the thickness of the dielectric layers to decrease locally, making dielectric breakdown more likely to occur. Therefore, an object of the present invention is to provide a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed.

[0005] a first end surface and a second end surface that face each other in a length direction that is perpendicular to the stacking direction and the width direction; and external electrodes provided on the first end surface and the second end surface, wherein the internal electrode layers include first internal electrode layers and second internal electrode layers, and the first internal electrode layers are extended to the first end surface and the second internal electrode layers are extended to the second end surface. The external electrodes include a first external electrode connected to the first internal electrode layers and a second external electrode connected to the second internal electrode layers. An area that is arranged on the first end surface side and where the first internal electrode layers do not overlap with each other in the stacking direction, and an area that is arranged on the second end surface side and where the second internal electrode layers do not overlap with each other in the stacking direction are defined as an L-gap area, and the L-gap area includes a Si segregation layer.

[0006] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the occurrence of dielectric breakdown is further suppressed.

[0007] 1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view taken along line II in FIG. 1; FIG. 3 is a cross-sectional view taken along line II-II in FIG. 1; FIG. 4 is a view showing a portion of an LT cross section of the multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 5 is a view showing a portion of a WT cross section of the multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 6 is a view showing a portion of a WT cross section of another configuration of the multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 7 is a plan view of a ceramic green sheet according to an embodiment of the present invention; FIG. 8 is a plan view of a ceramic green sheet according to an embodiment of the present invention; FIG. 9 is a view showing an LT cross section of laminated ceramic green sheets; FIG. 10 is a view showing the results of a high-temperature load reliability test; and FIG. 11 is a view showing the results of a dielectric constant and a mean time to failure.

[0008] Hereinafter, an embodiment of a multilayer ceramic capacitor 1 of the present invention will be described with reference to the accompanying drawings.

[0009] (External Shape of Multilayer Ceramic Capacitor) The external appearance of a multilayer ceramic capacitor 1 will be outlined with reference to Fig. 1. Fig. 1 is a perspective view showing a multilayer ceramic capacitor 1 according to this embodiment. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20.

[0010] (Definition of Directions) The drawings appropriately show the L direction, W direction, and T direction. The L direction is the length direction L of the multilayer ceramic capacitor 1. The W direction is the width direction W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. Therefore, the cross section shown in FIG. 2 is called an LT cross section, and the cross section shown in FIG. 3 is called a WT cross section. The length direction L, width direction W, and stacking direction T do not necessarily have to be orthogonal to each other. The length direction L, width direction W, and stacking direction T may intersect each other.

[0011] (External Shape of Laminate) The laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has two main surfaces 61, two end surfaces 62, and two side surfaces 63. The main surface 61 is a surface facing the stacking direction T. The end surfaces 62 are surfaces facing the length direction L. The side surfaces 63 are surfaces facing the width direction W. One of the two main surfaces 61 is a first main surface 61a, and the other is a second main surface 61b. One of the two end surfaces 62 is a first end surface 62a, and the other is a second end surface 62b. One of the two side surfaces 63 is a first side surface 63a, and the other is a second side surface 63b. The second main surface 61b and the first side surface 63a are shown in FIG. 1.

[0012] It is preferable that the ridges and corners of the laminate 2 are rounded. A ridge is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect. The size of the laminate 2 is not particularly limited.

[0013] (Structure of the Laminate) The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2.

[0014] (Internal Structure of Laminate (LT Cross Section)) The internal structure of the laminate 2 will be described with reference to FIG. 2. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 taken along line II. FIG. 2 shows the LT cross section of the multilayer ceramic capacitor 1. The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked on top of each other in the stacking direction T.

[0015] (Inner layer portion and outer layer portion) The laminate 2 is divided into an inner layer portion 53 and two outer layer portions 54 in the stacking direction T. The outer layer portion 54 includes a first outer layer portion 54a and a second outer layer portion 54b. The first outer layer portion 54a and the second outer layer portion 54b are located at positions sandwiching the inner layer portion 53 in the stacking direction T.

[0016] A plurality of dielectric layers 4 and a plurality of internal electrode layers 10 are arranged in the internal layer portion 53. In the internal layer portion 53, the plurality of internal electrode layers 10 face each other with the dielectric layer 4 interposed therebetween. Therefore, a capacitance is formed in the internal layer portion 53. Therefore, the internal layer portion 53 is a portion of the laminate 2 that essentially functions as a capacitor. For this reason, the internal layer portion 53 is also called an effective portion.

[0017] The first outer layer portion 54a is a portion of the outer layer portion 54 located on the side of the first main surface 61a of the laminate 2. The second outer layer portion 54b is a portion of the outer layer portion 54 located on the side of the second main surface 61b of the laminate 2. Specifically, the first outer layer portion 54a is a portion between the first main surface 61a and an internal electrode layer 10 of the multiple internal electrode layers 10 that is closest to the first main surface 61a. The second outer layer portion 54b is a portion between the second main surface 61b and an internal electrode layer 10 of the multiple internal electrode layers 10 that is closest to the second main surface 61b. No internal electrode layer 10 is arranged in the first outer layer portion 54a and the second outer layer portion 54b. The remaining dielectric layers 4 of the multiple dielectric layers 4, excluding the dielectric layer 4 for the internal layer portion 53, are arranged in the first outer layer portion 54a and the second outer layer portion 54b. The first outer layer portion 54 a and the second outer layer portion 54 b function as protective layers for the inner layer portion 53 .

[0018] (Dielectric Layer) The dielectric layer 4 can be classified into a dielectric layer 4 arranged in the inner layer portion 53 and a dielectric layer 4 arranged in the outer layer portion 54. The dielectric layer 4 arranged in the inner layer portion 53 is referred to as an inner dielectric layer 4a. The dielectric layer 4 arranged in the outer layer portion 54 is referred to as an outer dielectric layer 4b.

[0019] (Number of Dielectric Layers) The number of dielectric layers 4 stacked in the laminate 2 can be, for example, 5 to 2000.

[0020] (Material of Dielectric Layer) The material of the dielectric layer 4 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , CaZrO ３It is possible to use a dielectric ceramic made of the above-mentioned main components. It is also possible to use a material in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to these main components.

[0021] (Thickness of Dielectric Layer) The thickness of the dielectric layer 4 can be set to, for example, 0.3 μm or more and 0.6 μm or less.

[0022] (Internal electrode layers) The internal electrode layers 10 can be classified into first internal electrode layers 10a and second internal electrode layers 10b. The first internal electrode layer 10a is an internal electrode layer 10 connected to the first external electrode 20a. The second internal electrode layer 10b is an internal electrode layer 10 connected to the second external electrode 20b. The first internal electrode layer 10a extends from the first end face 62a toward the second end face 62b. The second internal electrode layer 10b extends from the second end face 62b toward the first end face 62a.

[0023] (Facing portion and lead-out portion) The first internal electrode layer 10a and the second internal electrode layer 10b each have a facing electrode portion 11 and a lead-out electrode portion 12. The facing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The lead-out electrode portion 12 is a portion of the internal electrode layer 10 that is led out from the facing electrode portion 11 to the first end face 62a or the second end face 62b of the laminate 2.

[0024] The opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a. The lead electrode portion 12 of the first internal electrode layer 10a is referred to as the first lead electrode portion 12a. The first lead electrode portion 12a is a portion that is led out from the first opposing electrode portion 11a to the first end face 62a of the laminate 2.

[0025] Similarly, the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b. The lead electrode portion 12 of the second internal electrode layer 10b is referred to as the second lead electrode portion 12b. The second lead electrode portion 12b is a portion that is led out from the second opposing electrode portion 11b to the second end face 62b of the laminate 2.

[0026] (Number of Internal Electrode Layers) The number of the internal electrode layers 10 can be, for example, 10 to 2000. The number of the internal electrode layers 10 includes the number of the first internal electrode layers 10a and the number of the second internal electrode layers 10b.

[0027] (Thickness of Internal Electrode Layer) The thickness of the internal electrode layer 10 can be, for example, 0.1 μm or more and 5.0 μm or less, preferably 0.2 μm or more and 2.0 μm or less. When the thickness of the internal electrode layer 10 is 0.5 μm or more, a plating film is likely to grow when the metal layer of the external electrode 20 is formed by plating.

[0028] (Material of the internal electrode layer) The material of the internal electrode layer 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the internal electrode layer 10 may contain dielectric particles of the same composition as the ceramic contained in the dielectric layer 4.

[0029] (Electrode Opposing Portion) The following describes the division of the laminate 2 in the longitudinal direction L. The laminate 2 can be divided into an electrode opposing portion 50 and an L gap (L gap region) 51 in the longitudinal direction L. The electrode opposing portion 50 in the division in the longitudinal direction L is referred to as an L opposing portion 50a. The L gap 51 includes a first L gap 51a and a second L gap 51b.

[0030] The L opposing portion 50a corresponds to a portion where the first internal electrode layer 10a and the second internal electrode layer 10b oppose each other in the stacking direction T. A capacitance is formed in the L opposing portion 50a. For this reason, the L opposing portion 50a is also called an effective portion.

[0031] (L Gaps) The L gaps 51 are portions in the length direction L of the laminate 2 where the first internal electrode layers 10a and the second internal electrode layers 10b do not face each other in the stacking direction T. Of the L gaps 51, the first L gap 51a is between the L opposing portion 50a and the first end face 62a. The second L gap 51b is between the L opposing portion 50a and the second end face 62b.

[0032] In the first L gap 51a, the first internal electrode layer 10a is arranged but the second internal electrode layer 10b is not arranged in the stacking direction T. In the second L gap 51b, the second internal electrode layer 10b is arranged but the first internal electrode layer 10a is not arranged in the stacking direction T.

[0033] The first L gap 51a functions as an extension to the first end surface 62a of the first opposing electrode portion 11a, and the second L gap 51b functions as an extension to the second end surface 62b of the second opposing electrode portion 11b.

[0034] The length of the L gap 51 in the longitudinal direction L can be, for example, 10% to 30% of the length of the laminate 2 in the longitudinal direction L. Furthermore, the length of the L gap 51 in the longitudinal direction L can be, for example, 5 μm to 30 μm.

[0035] (External Electrodes) The external electrodes 20 include a first external electrode 20a and a second external electrode 20b. (First External Electrode) The first external electrode 20a is an external electrode 20 arranged on a first end surface 62a of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a. (Second External Electrode) The second external electrode 20b is an external electrode 20 arranged on a second end surface 62b of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0036] (External Electrode on Each Surface) The external electrode 20 extends from one end surface 62 to parts of the two main surfaces 61 and to parts of the two side surfaces 63 .

[0037] (Layer Structure of External Electrode) The layer structure of the external electrode 20 will be described with reference to FIG. 2 . The external electrode 20 includes a base electrode layer 21 and a plating layer 23. The plating layer 23 includes an inner plating layer 24 and a top plating layer 25. These layers are arranged in the following order from the end surface 62 of the laminate 2: base electrode layer 21, inner plating layer 24, top plating layer 25. More specifically, the first external electrode 20a includes a first base electrode layer 21a and a first plating layer 23a. The first plating layer 23a further includes a first inner plating layer 24a and a first top plating layer 25a. Similarly, the second external electrode 20b includes a second base electrode layer 21b and a second plating layer 23b. The second plating layer 23b further includes a second inner plating layer 24b and a second top plating layer 25b.

[0038] (Base Electrode Layer) The first base electrode layer 21a is disposed on and covers the first end face 62a of the laminate 2. The first base electrode layer 21a extends from the first end face 62a to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.

[0039] Similarly, the second base electrode layer 21b is disposed on and covers the second end face 62b of the laminate 2. The second base electrode layer 21b extends from the second end face 62b to a portion of the first main surface 61a, a portion of the second main surface 61b, a portion of the first side surface 63a, and a portion of the second side surface 63b.

[0040] (Baking Layer) The first base electrode layer 21a and the second base electrode layer 21b are configured as baking layers. The baking layer contains a glass component and a metal. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baking layer may be a multi-layered layer.

[0041] (Plating Layer) The plating layer 23 on the base electrode layer 21 will be described. As described above, in this embodiment, the plating layer 23 includes the inner plating layer 24 and the top plating layer 25. When the plating layer 23 is a two-layer structure, it is preferable that the plating layers are, from bottom to top, a Ni plating layer and a Sn plating layer. That is, the inner plating layer 24 is a Ni plating layer, and the top plating layer 25 is a Sn plating layer.

[0042] The Ni plating layer can prevent the base electrode layer 21 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer can improve the wettability of the solder when mounting the multilayer ceramic capacitor 1, facilitating mounting. Therefore, by using an Sn plating layer as the top plating layer 25, the wettability of the solder to the external electrode 20 can be improved. The thickness of each plating layer is preferably 3 μm or more and 9 μm or less.

[0043] (Internal Structure of Laminate (WT Cross Section)) The internal structure of the laminate 2 will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 shown in FIG. 1 taken along line II-II. The laminate 2 is divided into an electrode opposing portion 50 and a W gap 52 in the width direction W. The electrode opposing portion 50 in the section in the width direction W is referred to as a W opposing portion 50b. The W gap 52 includes a first W gap 52a and a second W gap 52b.

[0044] The W opposing portion 50b is a portion where the internal electrode layers 10 oppose each other in the stacking direction T. The W gap 52 is a portion in the width direction W where neither the first internal electrode layer 10a nor the second internal electrode layer 10b is arranged in the stacking direction T.

[0045] Of the W gaps 52, the first W gap 52a is between the W opposing portion 50b and the first side surface 63a in the width direction W of the laminate 2. The second W gap 52b is between the W opposing portion 50b and the second side surface 63b.

[0046] The first W gap 52a and the second W gap 52b are arranged to sandwich the W opposing portion 50b. The first W gap 52a and the second W gap 52b function as protective layers for the internal electrode layer 10.

[0047] The length of the W gap 52 in the width direction W can be, for example, 20% to 30% of the length of the width direction W of the laminate 2. Furthermore, the length of the W gap 52 in the width direction W can be, for example, 5 μm to 50 μm.

[0048] (Size of Multilayer Ceramic Capacitor) The size of the multilayer ceramic capacitor 1 is not particularly limited. The size of the multilayer ceramic capacitor 1 can be, for example, as follows: The dimension L in the length direction L of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension L. The L dimension is preferably 0.25 mm or more and 1.0 mm or less. The dimension T in the stacking direction T of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension T. The T dimension is preferably 0.125 mm or more and 0.5 mm or less. The dimension W in the width direction W of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, is defined as dimension W. The W dimension is preferably 0.125 mm or more and 0.5 mm or less. The lengths of each portion of the laminate 2 and the external electrodes 20 can be measured using a micrometer or an optical microscope.

[0049] (Terminal Configuration) In the present embodiment, the multilayer ceramic capacitor 1 has been described as a two-terminal multilayer ceramic capacitor by way of example. However, the multilayer ceramic capacitor 1 is not limited to being a two-terminal multilayer ceramic capacitor, and may be a multi-terminal multilayer ceramic capacitor having three or more terminals.

[0050] (Si Segregation Layer) The multilayer ceramic capacitor 1 of this embodiment includes a Si segregation layer 14 in the L gap 51. The Si segregation layer 14 refers to a Si layer formed on the surface of the internal electrode layer 10 or the like.

[0051] The Si segregation layer 14 will be described with reference to Fig. 4. Fig. 4 is a diagram showing a portion of the LT cross section of the multilayer ceramic capacitor 1 of this embodiment. Fig. 4 corresponds to an enlarged view of the region R1 indicated by the dashed line in Fig. 2. Fig. 4 shows the first L gap 51a and its vicinity.

[0052] In and near the first L gap 51a, a Si segregation layer 14 is formed on the surface of the internal electrode layer 10. (First Internal Electrode Layer) For the first internal electrode layer 10a, the Si segregation layer 14 is formed on the entire surface of the first lead electrode portion 12a and on at least a part of the surface of the first opposing electrode portion 11a. The at least a part of the first opposing electrode portion 11a corresponds to a portion of the first opposing electrode portion 11a that is close to the first L gap 51a.

[0053] (Second Internal Electrode Layer) For the second internal electrode layer 10b, a Si segregation layer 14 is formed on at least a part of the surface of the second opposing electrode portion 11b. The at least a part of the second opposing electrode portion 11b corresponds to a part of the second opposing electrode portion 11b that is close to the first L gap 51a.

[0054] With respect to the first internal electrode layer 10a and the second internal electrode layer 10b, the portion close to the first L gap 51a refers to a portion, for example, approximately 50 μm from the boundary between the first L gap 51a and the L opposing portion 50a in the direction of the L opposing portion 50a.

[0055] The end of the internal electrode layer 10 is referred to as an electrode end 10e. The end of the internal electrode layer 10 means an end surface parallel to the stacking direction T of the internal electrode layer 10. Fig. 4 shows the electrode end 10e of the second internal electrode layer 10b. In the configuration shown in Fig. 4, a Si segregation layer 14 is formed over the entire electrode end 10e in the direction parallel to the stacking direction T.

[0056] As described above, the Si segregation layer 14 is formed not only on the surface parallel to the length direction L of the internal electrode layer 10 but also on the surface at the electrode end 10e parallel to the stacking direction T. In this way, the Si segregation layer 14 is formed on the surface of the internal electrode layer 10 in the first L gap 51a and its vicinity.

[0057] 4, a floating island electrode 13 having a floating island shape is formed in the first L gap 51a. A Si segregation layer 14 is also formed on the surface of this floating island electrode 13. The floating island electrode 13 can be formed intentionally when forming the internal electrode layer 10. Alternatively, it may be formed unintentionally when forming the internal electrode layer 10.

[0058] (Second L Gap) The Si segregation layer 14 has been described above using the first L gap 51a as an example. However, the second L gap 51b has a similar configuration. That is, the second lead electrode 12b and the first opposing electrode 11a in the second L gap 51b also have the same Si segregation layer 14 as the first lead electrode 12a and the second opposing electrode 11b in the first L gap 51a.

[0059] (Electrode Ends in Width Direction) The electrode ends 10e in the width direction W of the internal electrode layers 10 will be described with reference to Fig. 5. Fig. 5 is a diagram showing a part of the WT cross section of the multilayer ceramic capacitor 1 according to an embodiment of the present invention. Note that Fig. 5 is a schematic diagram. Therefore, the number of patterns and the like may not match those in other drawings.

[0060] As shown in FIG. 5 , the Si segregation layer 14 is also formed in the electrode end portion 10e in the width direction W. Specifically, the Si segregation layer 14 is also formed in the electrode end portion 10e in the width direction W over the entire area in a direction parallel to the stacking direction T. The Si segregation layer 14 is also formed on the surface parallel to the width direction W of the internal electrode layer 10. However, the Si segregation layer 14 is not formed so as to cover the entire surface parallel to the width direction W. The Si segregation layer 14 is formed on a surface parallel to the width direction W at a predetermined distance from the electrode end portion 10e. In FIG. 5 , this predetermined distance is indicated by distance d1. Distance d1 can be, for example, 1 μm or more and 50 μm or less.

[0061] (Another Configuration of Si Segregation Layer) FIG. 6 is a diagram showing another configuration of the region R2 in FIG. 5 . The configuration shown in FIG. 5 and the configuration shown in FIG. 6 differ in the position where the Si segregation layer 14 is formed on the surface of the internal electrode layer 10. In the configuration shown in FIG. 5 , as shown in the region R2, the Si segregation layer 14 is formed over the entire electrode end 10e of the internal electrode layer 10 in the stacking direction T. In contrast, in the configuration example shown in FIG. 6 , the Si segregation layer 14 is not formed over the entire electrode end 10e in the stacking direction T. The Si segregation layer 14 is formed at both ends of the electrode end 10e in the stacking direction T. On the other hand, the Si segregation layer 14 is not formed in the central portion of the electrode end 10e in the stacking direction T. Therefore, the internal electrode layer 10 is exposed from the central portion of the electrode end 10e in the stacking direction T.

[0062] As shown in FIGS. 5 and 6 , the Si segregation layer 14 may be formed over the entire electrode end portion 10e of the internal electrode layer 10 in the width direction W in the stacking direction T, or may be formed over a part of the stacking direction T.

[0063] (Thickness of Si-segregation layer) The thickness of the Si-segregation layer 14 can be, for example, 0.01 μm or more and 0.30 μm or less. The thickness of the Si-segregation layer 14 can be determined by exposing a cross section of the laminate 2, distinguishing between the dielectric particles and the Si-segregation layer using a scanning electron microscope (SEM), and further performing elemental analysis of the surface using energy dispersive X-ray analysis (EDX).

[0064] (Manufacturing Method of Multilayer Ceramic Capacitor) A manufacturing method of the multilayer ceramic capacitor 1 will be described with reference to Fig. 7 etc. (Manufacturing of Laminated Block) Ceramic green sheets 30, electrode paste 31 for the internal electrode layers 10, and step paste 32 for the step layers 5 are prepared.

[0065] (Step Layer) First, the step layer 5 will be described. It is preferable that the difference in length in the stacking direction T of the laminate 2 be small between the electrode opposing portion 50 and the L gap 51. However, in the inner layer portion 53, the lengths in the stacking direction T tend to differ between the electrode opposing portion 50 and the L gap 51. The dielectric layers 4 and the internal electrode layers 10 are stacked in the electrode opposing portion 50. In contrast, the dielectric layers 4 and only the internal electrode layers 10 connected to one external electrode 20 are stacked in the L gap 51. Therefore, the lengths in the stacking direction T tend to differ between the electrode opposing portion 50 and the L gap 51.

[0066] Therefore, in order to reduce the difference in length between the L gap 51 and the electrode opposing portion 50 in the stacking direction T, an additional dielectric layer 4 is disposed in the L gap 51. This additional dielectric layer 4 is referred to as a step layer 5. The step layer 5 preferably has the same components as the dielectric layer 4. However, the components of the dielectric layer 4 are not limited to these.

[0067] The step layer 5 is shown in Fig. 4. As shown in Fig. 4, the step layer 5 is disposed in the first L gap 51a between two first opposing electrode portions 11a that face each other in the stacking direction T. The step layer 5 compensates for the thickness of the second internal electrode layer 10b, thereby making it possible to reduce the difference in length in the stacking direction T between the first L gap 51a and the L opposing portion 50a.

[0068] In this embodiment, a Si component is blended into the step paste 32. This Si component will later form the Si segregation layer 14. Adding the Si component to the step paste 32 is an example of a method for forming the Si segregation layer 14.

[0069] (Application of Paste) An overview of lamination of ceramic green sheets 30 when forming the step layer 5 will be described. The pattern shapes of the electrode paste 31 and step paste 32 will be described later. First, the electrode paste 31 and step paste 32 are applied to the ceramic green sheet 30 in a desired pattern. The application of each paste to the ceramic green sheet 30 can be performed by a method such as screen printing or gravure printing. The electrode paste 31 and step paste 32 are printed in a predetermined pattern on the ceramic green sheet 30 by any printing method. In this way, a ceramic green sheet 30 for the inner layer portion 53 on which the paste is printed is obtained.

[0070] (Lamination) A predetermined number of ceramic green sheets 30 on which the pattern of the internal electrode layer 10 is not printed are laminated. This creates a portion corresponding to the outer layer portion 54. On top of this, ceramic green sheets 30 for the inner layer portion 53 on which paste has been applied are sequentially laminated. This creates a portion corresponding to the inner layer portion 53. Furthermore, on top of that, a predetermined number of ceramic green sheets 30 for the other outer layer portion 54 are laminated. This creates a laminated sheet. The laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to create a laminated block.

[0071] (Pattern) FIG. 7 is a plan view of a ceramic green sheet 30 to which the electrode paste 31 and the step paste 32 are applied. FIG. 7 is a view of the ceramic green sheet 30 as viewed from the stacking direction T. 701 and 702 in FIG. 7 each represent one ceramic green sheet 30. A laminated sheet can be obtained by stacking these ceramic green sheets 30. In the example shown in FIG. 7, ten electrode patterns are formed on the ceramic green sheet 30 using the electrode paste 31. The electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between two electrode patterns aligned in the length direction L. The electrode paste 31 and the step paste 32 are applied in the same pattern to the two ceramic green sheets 30 shown in 701 and 702 in FIG. 7.

[0072] (Lamination) When laminating two ceramic green sheets 30 shown in 701 and 702 in Fig. 7, they are stacked with a shift in the length direction L. The shift distance is indicated by a distance d2 in Fig. 7. By stacking two ceramic green sheets 30 with a shift, it is possible to easily fabricate a multilayer ceramic capacitor 1 in which a Si segregation layer 14 is formed in both the first L gap 51a and the second L gap 51b. This will be described later.

[0073] (Fabrication of laminated chips) The laminated block is cut to a predetermined size to cut out laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0074] (Firing) Next, the laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the ceramic layers 4 and the internal electrode layers 10, but is preferably 900°C or higher and 1400°C or lower.

[0075] (External Electrode) Next, the external electrode 20 is formed. (Base Electrode Layer) A conductive paste that will become the base electrode layer 21 is applied to the two end faces 62 of the laminate 2 to form the base electrode layer 21. To form a baked layer, a conductive paste containing a glass component and a metal is applied by a method such as dipping. Then, a baking process is performed to form the base electrode layer 21. The baking temperature is preferably 500°C or higher and 900°C or lower. The baking time is preferably 30 minutes or higher and 2 hours or lower. The baking atmosphere is, for example, H ２ O and H ２ Preferably, the atmosphere is a reducing atmosphere containing

[0076] Next, a plating layer 23 is formed on the surface of the base electrode layer 21. In this embodiment, a Ni plating layer is formed on the baked layer. This Ni plating layer becomes the inner plating layer 24. Next, a Sn plating layer is formed on the Ni plating layer. This Sn plating layer becomes the top plating layer 25. The Ni plating layer and the Sn plating layer are formed sequentially by, for example, barrel plating. In this manner, the multilayer ceramic capacitor 1 is obtained.

[0077] (Lamination and Cutting) Lamination and cutting in the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described in more detail with reference to FIGS. 8 and 9 . FIG. 8 is a plan view of a ceramic green sheet 30 to which an electrode paste 31 and a step paste 32 are applied. The shapes of the patterns of the electrode paste 31 and the step paste 32 applied to the ceramic green sheet 30 are different between FIGS. 7 and 8 . In the configuration shown in FIG. 7 , the electrode patterns are arranged in two columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between two electrode patterns aligned in the length direction L. In contrast, in the configuration shown in FIG. 8 , the electrode patterns are arranged in four columns in the length direction L and five rows in the width direction W. The step paste 32 is applied between the first and second electrode patterns and between the third and fourth electrode patterns among the four electrode patterns aligned in the length direction L. In this way, the electrode paste 31 and the step paste 32 can be applied to the ceramic green sheet 30 in a variety of patterns depending on the type of multilayer ceramic capacitor 1 to be manufactured.

[0078] (Stacking) The ceramic green sheet 30 designated by 801 in Fig. 8 is the first ceramic green sheet 30a. The ceramic green sheet 30 designated by 802 in Fig. 8 is the second ceramic green sheet 30b. The first ceramic green sheet 30a and the second ceramic green sheet 30b are stacked with a shift, similar to the configuration shown in Fig. 7. Specifically, they are stacked with a shift of a distance d2 in the longitudinal direction L.

[0079] (Cutting) Cutting of the laminated ceramic green sheets 30 will be described with reference to FIG. 9. FIGS. 9(a) and 9(b) are views showing the LT cross section of the laminated ceramic green sheets 30. To simplify the configuration, FIGS. 9(a) and 9(b) illustrate an example in which only two ceramic green sheets 30 are stacked. In the following description, this laminate of two ceramic green sheets 30 will be referred to as a laminate 40. Lines L1 and L2 shown in FIG. 9(a) indicate cutting lines. These lines L1 and L2 correspond to lines L1 and L2 shown in FIG. 8. FIG. 9(a) shows the laminate 40 before cutting. FIG. 9(b) shows the laminate 40 after cutting along lines L1 and L2.

[0080] 9( a), the first ceramic green sheet 30a and the second ceramic green sheet 30b in the laminate 40 are stacked with a shift in the length direction L. Therefore, the end 31b in the length direction L of the pattern of the electrode paste 31 on the second ceramic green sheet 30b is aligned in the length direction L with the center 32a in the length direction L of the pattern of the step paste 32 on the first ceramic green sheet 30a. In other words, the end 31b of the pattern of the electrode paste 31 and the center 32a of the pattern of the step paste 32 are both located on the line L1.

[0081] (Line L2) Similarly, the central portion 32b in the longitudinal direction L of the pattern of the step paste 32 on the second ceramic green sheet 30b is aligned with the end portion 31a in the longitudinal direction L of the pattern of the electrode paste 31 on the first ceramic green sheet 30a in the longitudinal direction L. That is, the central portion 32b of the pattern of the step paste 32 and the end portion 31a of the pattern of the electrode paste 31 are both located on the line L2.

[0082] 9B shows the laminate 40 after cutting. The laminate 40 cut along the lines L1 and L2 has a step layer 5 formed in the L gap 51. This is because the ceramic green sheets 30 are stacked with a shift so that the pattern applied to the first ceramic green sheet 30a and the pattern applied to the second ceramic green sheet 30b have the positional relationship described above.

[0083] (Cut surface) The cut surface created by cutting along line L1 is referred to as first cut surface 41. The cut surface created by cutting along line L2 is referred to as second cut surface 42. First cut surface 41 corresponds to first end surface 62a of laminate 2. Second cut surface 42 corresponds to second end surface 62b of laminate 2. Here, "corresponding" means a portion of laminate 2 that corresponds when laminate 40 is fired to become laminate 2.

[0084] Exposed from a first cut surface 41 of the laminate 40, in this order in the stacking direction T, are the first green sheet 30a corresponding to the inner dielectric layer 4a, the step paste 32 corresponding to the step layer 5, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the electrode paste 31 corresponding to the first internal electrode layer 10a. Similarly, exposed from a second cut surface 42 of the laminate 40, in this order in the stacking direction T, are the first green sheet 30a corresponding to the inner dielectric layer 4a, the electrode paste 31 corresponding to the second internal electrode layer 10b, the second green sheet 30b corresponding to the inner dielectric layer 4a, and the step paste 32 corresponding to the step layer 5. In the length direction L, the portions where the step paste 32 is arranged become the first L gap 51a and the second L gap 51b, respectively.

[0085] (Formation of Si segregation layer) As described above, the step paste 32 contains a Si component for forming the Si segregation layer 14. This Si component migrates within the step paste 32 and adheres to the internal electrode layers 10. The Si component is a liquid phase component. Therefore, the Si component can move across the dielectric material and approach the internal electrode layers. Specifically, the Si component adheres to the surface of the extraction electrode portion 12 and at least a part of the end and surface of the counter electrode portion 11. The Si component adhered to each internal electrode layer 10 forms the Si segregation layer 14.

[0086] (Other Methods for Forming Si Segregation Layer) The method for forming the Si segregation layer 14 is not limited to the method of blending the Si component into the step paste 32 described above. Another method for forming the Si segregation layer 14 is to apply the Si component to the L gap 51. In this method, the Si component is applied by printing or the like to an application pattern of the electrode paste 31 corresponding to the portion where the Si segregation layer 14 is desired to be formed. Another method for forming the Si segregation layer 14 is to impregnate the WT end face of the laminated chip before firing, i.e., the face corresponding to the end face 62 of the laminate 2, with the Si component.

[0087] (Effect of Si Segregation Layer) The multilayer ceramic capacitor 1 of this embodiment is provided with the Si segregation layer 14 in the L gap 51. This can improve the reliability of the multilayer ceramic capacitor 1. This is because the Si segregation layer 14 has high IR (insulation resistance).

[0088] The evaluation results of the characteristics of the multilayer ceramic capacitor 1 are shown below. (High-Temperature Load Reliability Test) The results of the high-temperature load reliability test are described with reference to FIG. 10 . FIG. 10 shows the results of the high-temperature load reliability test for the comparative example and examples. The high-temperature load reliability test was conducted as follows. 100 samples were prepared for each of the comparative example and examples 1 to 8. The samples were mounted on glass epoxy substrates using eutectic solder. The thickness of the dielectric layer in the samples was 0.5 μm. First, the initial insulation resistance value of each sample was measured. Next, the glass epoxy substrate was placed in a high-temperature chamber, and a voltage of 6.3 V was applied to each sample in an environment of 150°C. The insulation resistance value was then measured after 200 hours and 500 hours. The initial insulation resistance value was compared with the insulation resistance value after aging, and a decrease of one order of magnitude or more in insulation resistance value was determined to be defective. As shown in FIG. 10 , no defects occurred in the samples with the Si segregation layer after 200 hours. Moreover, even after 500 hours, the number of defects was kept to 5 or less.

[0089] In particular, in Examples 2 to 6 in which the thickness of the Si segregation layer was 0.03 μm or more and 0.15 μm or less, no defects occurred even after 500 hours had elapsed, in addition to after 200 hours had elapsed.

[0090] (Dielectric Constant and Mean Time to Failure) The evaluation results of the dielectric constant and mean time to failure will be described with reference to FIG. 11. FIG. 11 is a diagram showing the evaluation results of the dielectric constant and mean time to failure for the comparative example and the example. The thickness of the dielectric layer in the samples was set to four types, ranging from 0.3 μm to 0.6 μm. By varying the thickness of the dielectric layer, samples with different element thicknesses were produced. In addition, the thickness of the Si segregation layer was set to 0.07 μm and 0.08 μm.

[0091] Si has a low dielectric constant. Therefore, a decrease in the dielectric constant was observed in the sample in which the Si segregation layer was formed. Furthermore, an improvement in the mean time to failure (MTTF) was observed in the sample in which the Si segregation layer was formed.

[0092] In particular, in Examples B and C in which the thickness of the dielectric layer was 0.4 μm or more and 0.5 μm or less, a significant improvement in MTTF was observed.

[0093] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0094] <1> A laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface opposing each other in a lamination direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the lamination direction and the width direction; and external electrodes provided on the first end surface and the second end surface, the internal electrode layers including first internal electrode layers and second internal electrode layers, the first internal electrode layers being drawn out to the first end surface, and the second internal electrode layers being drawn out to the second end surface, the external electrodes including a first external electrode connected to the first internal electrode layers and a second external electrode connected to the second internal electrode layers, an L-gap region being an area arranged on the first end surface side where the first internal electrode layers do not overlap each other in the lamination direction, and an area arranged on the second end surface side where the second internal electrode layers do not overlap each other in the lamination direction, The multilayer ceramic capacitor, wherein the L gap region includes a Si segregation layer.

[0095] <2> The multilayer ceramic capacitor according to <1>, wherein the thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less.

[0096] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein the Si segregation layer is present at the end in the width direction of the first internal electrode layer and at the end in the width direction of the second internal electrode.

[0097] <4> The multilayer ceramic capacitor according to any one of <1> to <3>, wherein the thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less.

[0098] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 4 Dielectric layer 5 Step layer 10 Internal electrode layer 11 Counter electrode portion 12 Lead electrode portion 13 Floating island electrode 14 Si segregation layer 20 External electrode 21 Base electrode layer 23 Plating layer 24 Inner plating layer 25 Surface plating layer 30 Ceramic green sheet 31 Electrode paste 32 Step paste 40 Laminate 41 First cut surface 42 Second cut surface 50 Electrode counter portion 51 L gap (L gap region) 52 W gap 53 Inner layer portion 54 Outer layer portion 61 Main surface 62 End surface 63 Side surface R1 Region R2 Region T Stacking direction L Length direction W Width direction

Claims

1. The dielectric layer includes a plurality of dielectric layers and a plurality of internal electrode layers that are stacked together, a laminate including a first main surface and a second main surface opposed to each other in a stacking direction, a first side surface and a second side surface opposed to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposed to each other in a length direction perpendicular to the stacking direction and the width direction; external electrodes provided on the first end surface and the second end surface; Equipped with the internal electrode layer includes a first internal electrode layer and a second internal electrode layer, the first internal electrode layer is extended to the first end face, the second internal electrode layer is extended to the second end face, the external electrodes include a first external electrode connected to the first internal electrode layer and a second external electrode connected to the second internal electrode layer; an L-gap region is a region disposed on the first end face side, in which the first internal electrode layers do not overlap with each other in the stacking direction, and an L-gap region is a region disposed on the second end face side, in which the second internal electrode layers do not overlap with each other in the stacking direction, the L gap region comprises a Si segregation layer; The thickness of the Si segregation layer is 0.03 μm or more and 0.15 μm or less, A floating island electrode having a floating island shape is formed in the L gap region, the Si segregation layer is formed on a surface of the floating island electrode, Multilayer ceramic capacitor.

2. the Si segregation layer is present at an end portion in the width direction of the first internal electrode layer and an end portion in the width direction of the second internal electrode layer; The multilayer ceramic capacitor according to claim 1 .

3. The thickness of the dielectric layer is 0.4 μm or more and 0.5 μm or less.

3. The multilayer ceramic capacitor according to claim 1.