Method for manufacturing semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, the method including: a step for preparing a semiconductor package and a motherboard, the semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate, the motherboard being provided with a plurality of metal pads and solder paste disposed at a plurality of locations on a part of the metal pads, and disposing the semiconductor package and the motherboard so that the plurality of solder balls and the plurality of metal pads face each other; and a step for heating the semiconductor package and the motherboard to form electrical connections between the plurality of solder balls and the plurality of metal pads, wherein the disposing step involves preparing the motherboard so that the solder paste is not placed on the metal pads disposed in at least a portion of a peripheral-end side and disposing the semiconductor package and the motherboard via a spacer therebetween.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] In recent years, electronic devices such as computers have become larger due to the increased speed and capacity of the signals they use. Semiconductor packages used in these electronic devices have also become more highly integrated and functional.

[0003] A semiconductor package is configured by mounting a semiconductor chip made of an inorganic compound such as silicon on an organic substrate containing resin, etc. The semiconductor package is electrically connected to a motherboard or the like via solder or the like.

[0004] In semiconductor packages, warpage can occur due to stress caused by the difference in the linear expansion coefficient between the semiconductor chip and the organic substrate. Warpage of semiconductor packages increases as the package becomes larger, and can cause problems with connection when mounted on a motherboard, etc.

[0005] One method of mounting a semiconductor package on a motherboard that addresses warpage of the semiconductor package is to provide a spacer between the semiconductor package and the motherboard in advance (see, for example, Non-Patent Document 1).

[0006] Furthermore, there is a method of changing the amount of solder paste applied to the motherboard side in accordance with the warpage shape of the semiconductor package (see, for example, Patent Document 1). Specifically, Patent Document 1 describes printing soldering material on a printed wiring board such as a motherboard on multiple pads that connect to solder balls of electronic components so that the amount of soldering material decreases from the center toward the outside.

[0007] JP 2009-76812 A

[0008] Fletcher (Cheng Piao) Tung et al., Challenges of Large Body FCBGA on Board Level Assembly and Reliability, 2018 IEEE 68th Electronic Components and Technology Conference

[0009] In recent years, semiconductors used in computers, servers, etc. have become more multifunctional, and as a result, the package substrates on which semiconductor chips are mounted and the semiconductor packages have become larger. Furthermore, as the semiconductor packages become larger, the amount of warpage and mass of the entire semiconductor package formed by connecting the semiconductor chip to the package substrate are increasing.

[0010] Furthermore, through investigations by the present inventors, it has been found that connection between the semiconductor package and the motherboard may become difficult when spacers are provided at the edges of the semiconductor package to prevent contact between the solder balls, as described in Non-Patent Document 1. The reason for this is that the gap between the semiconductor package and the motherboard widens at the melting temperature of the solder balls in the center of the semiconductor package in a plan view, making connection failure between the two more likely to occur.

[0011] On the other hand, it was found that when solder paste is added to the connection point on the motherboard side and the motherboard and semiconductor package are connected by reflow, a short circuit is more likely to occur due to the phenomenon (also known as bridging) in which solder balls located at the edge of the semiconductor package come into contact with adjacent solder balls.

[0012] The tendency for poor connections to occur at the edges and center of the semiconductor package and motherboard as described above leads to a decrease in yield and increases the manufacturing cost of semiconductor devices. Furthermore, when applying solder paste to the connection points on the motherboard so that the amount of solder paste decreases from the center to the outside of the motherboard, as in Patent Document 1, it is necessary to vary the amount of solder paste applied depending on the position on the motherboard. This complicates the process of applying the solder paste, resulting in a problem of low manufacturing efficiency for semiconductor devices.

[0013] The present disclosure has been made in consideration of the above-described conventional circumstances, and aims to provide a method for manufacturing a semiconductor device that can reduce connection defects at the edges and center of a semiconductor package and a motherboard and that is excellent in manufacturing efficiency. The present disclosure aims to provide a semiconductor device in which connection defects at the edges and center of a semiconductor package and a motherboard are reduced.

[0014] Specific means for achieving the above object are as follows: <1> A method for manufacturing a semiconductor device, comprising the steps of preparing a package substrate, a semiconductor package having a plurality of solder balls on one surface of the package substrate, and a motherboard having a plurality of metal pads and a plurality of solder pastes arranged on some of the plurality of metal pads, and arranging the semiconductor package and the motherboard so that the plurality of solder balls face the plurality of metal pads, and heating the semiconductor package and the motherboard to electrically join the plurality of solder balls and the plurality of metal pads, wherein in the arranging step, the motherboard is prepared such that the solder paste is not arranged on at least some of the metal pads arranged on the peripheral edge side, and the semiconductor package and the motherboard are arranged via a spacer. <2> For the plurality of solder pastes, the volume of the solder paste per metal pad is independently 0.01 mm ３ ~0.03mm ３<3> The method for manufacturing a semiconductor device according to <1>, wherein the volume of solder paste per metal pad relative to the maximum volume of solder paste per metal pad is independently 80% or more for the plurality of solder pastes. <4> The method for manufacturing a semiconductor device according to any one of <1> to <3>, wherein the plurality of solder pastes are formed on some of the plurality of metal pads by screen printing. <5> The method for manufacturing a semiconductor device according to any one of <1> to <4>, wherein the height of the spacer in a cross-sectional view is 0.2 mm to 0.3 mm. <6> The method for manufacturing a semiconductor device according to any one of <1> to <4>, wherein the area of ​​the semiconductor package in a plan view is 2500 mm ２The method for manufacturing a semiconductor device according to any one of <1> to <5>, wherein the package substrate is rectangular in plan view, and the lengths of each of the four sides of the package substrate in plan view are independently 50 mm or more. <8> The method for manufacturing a semiconductor device according to any one of <1> to <7>, wherein the mass of the semiconductor package is 100 g or more. <9> The method for manufacturing a semiconductor device according to any one of <1> to <8>, wherein the package substrate includes a core layer including a copper-clad laminate. <10> The method for manufacturing a semiconductor device according to any one of <1> to <9>, wherein the semiconductor package includes a silicon interposer mounted on the package substrate in electrical connection with a plurality of semiconductor chips, or includes a plurality of semiconductor chips. <11> A semiconductor device in which a semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate, and a motherboard having a plurality of metal pads are electrically connected via the plurality of solder balls and the plurality of metal pads, and at a plurality of connection portions where the plurality of solder balls and the plurality of metal pads are electrically connected, a ratio of a minimum solder volume per connection portion to a maximum solder volume per connection portion is 0.6 to 0.95. <12> The semiconductor device according to <11>, in which a ratio of a solder volume per connection portion in at least one connection portion located on a peripheral edge of the semiconductor package to a solder volume per connection portion in at least one connection portion located in a central portion of the semiconductor package is 0.6 to 0.95. <13> The semiconductor device according to <11>, in which the package substrate is rectangular in plan view, and the solder volume per connection portion located at a corner of the rectangle is smaller than the solder volume per connection portion located at a non-corner portion. <14> The semiconductor device according to any one of <11> to <13>, wherein the package substrate includes a core layer including a copper-clad laminate. <15> The semiconductor device according to any one of <11> to <14>, wherein the semiconductor package includes a silicon interposer mounted on the package substrate and electrically connected to a plurality of semiconductor chips, or includes a plurality of semiconductor chips.

[0015] According to the present disclosure, it is possible to provide a method for manufacturing a semiconductor device that can reduce connection defects at the edges and center of a semiconductor package and a motherboard and that is excellent in manufacturing efficiency of semiconductor devices.The present disclosure can provide a semiconductor device in which connection defects at the edges and center of a semiconductor package and a motherboard are reduced.

[0016] While the present disclosure has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments and is not to be limited to the disclosed exemplary embodiments.

[0017] Hereinafter, embodiments of the present disclosure will be described in detail. However, the present disclosure is not limited to the following embodiments. In the following embodiments, components (including element steps, etc.) are not essential unless otherwise specified. The same applies to numerical values ​​and their ranges, and do not limit the present disclosure.

[0018] In the present disclosure, the term "step" includes not only a step that is independent of other steps, but also a step that cannot be clearly distinguished from other steps as long as the purpose of that step is achieved. In the present disclosure, numerical ranges indicated using "to" include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described in stages in the present disclosure, the upper or lower limit value described in one numerical range may be replaced with the upper or lower limit value of another numerical range described in stages. Furthermore, in the numerical ranges described in the present disclosure, the upper or lower limit value of that numerical range may be replaced with the value shown in the examples.

[0019] <Method for manufacturing a semiconductor device> The method for manufacturing a semiconductor device disclosed herein includes the steps of preparing a package substrate, a semiconductor package having a plurality of solder balls on one side of the package substrate, and a motherboard having a plurality of metal pads and a plurality of solder pastes arranged on some of the metal pads, and arranging the semiconductor package and the motherboard so that the plurality of solder balls face the plurality of metal pads (hereinafter also referred to as the "arranging step"); and heating the semiconductor package and the motherboard and electrically joining the plurality of solder balls and the plurality of metal pads (hereinafter also referred to as the "joining step"). In the arranging step, the motherboard is prepared in which the solder paste is not arranged on at least some of the metal pads arranged on the peripheral edge side, and the semiconductor package and the motherboard are arranged via spacers.

[0020] In the manufacturing method of the present disclosure, a semiconductor package and a motherboard are arranged via a spacer, with solder paste not being applied to metal pads arranged on at least a portion of the peripheral edge of the motherboard. The semiconductor package and the motherboard are then heated to electrically bond the multiple solder balls to the multiple metal pads, thereby manufacturing a semiconductor device. This reduces connection defects at the edges and center of the semiconductor package and the motherboard, and improves the manufacturing efficiency of the semiconductor device. The reason for this is believed to be as follows. The present disclosure is not limited to the following assumption.

[0021] By placing the semiconductor package and the motherboard via a spacer, the occurrence of bridging, where solder pieces adjacent to the edges of the semiconductor package and the motherboard come into contact with each other during the bonding process, tends to be reduced. However, even when a spacer is used, the gap between the semiconductor package and the motherboard widens at the center of the semiconductor package at the melting temperature of the solder balls, making connection failures between the two more likely to occur. Increasing the amount of solder paste applied to the metal pads can reduce connection failures in the center, but there is a problem of bridging becoming more likely at the edges.

[0022] In the present disclosure, multiple solder balls and multiple metal pads are electrically connected to each other while leaving solder paste undisposed on at least some of the metal pads located on the peripheral edge of the motherboard. This increases the amount of solder paste on the metal pads located in the center, etc., thereby reducing connection failures in the center. Furthermore, because some of the metal pads on the peripheral edge are free of solder paste, the occurrence of bridges where adjacent solder balls come into contact can be reduced.

[0023] Furthermore, by using a printing technique such as screen printing, solder paste can be selectively placed on multiple metal pads. Therefore, a motherboard can be obtained by a simple process in which some metal pads have no solder paste placed on them and the remaining metal pads have solder paste placed on them. Therefore, compared to placing solder paste on multiple metal pads so that the amount of solder paste decreases from the center to the periphery of the motherboard, the process of placing solder paste is simpler and the manufacturing efficiency of the semiconductor device is superior.

[0024] [Placement Process] The manufacturing method of the present disclosure includes a process (placement process) of preparing the semiconductor package and the motherboard, and arranging the semiconductor package and the motherboard so that the multiple solder balls and the multiple metal pads face each other.

[0025] (Semiconductor Package) A semiconductor package used in manufacturing a semiconductor device has a package substrate and a plurality of solder balls on one surface of the package substrate.

[0026] The package substrate has a plurality of solder balls, which are electrically connected to metal pads on the motherboard, and the plurality of solder balls are located at positions corresponding to the connection points with the metal pads on the motherboard.

[0027] The package substrate may include, for example, a buildup layer, a core layer, a solder resist layer, etc., or these layers may be stacked together. For example, when viewed from the side on which the multiple solder balls are provided, the package substrate may include a buildup layer, a core layer, and a buildup layer stacked together in this order, or a solder resist layer, a buildup layer, a core layer, a buildup layer, and a solder resist layer stacked together in this order. The package substrate may include through holes, vias, etc.

[0028] The package substrate may have a core layer including a copper-clad laminate, which is a member in which copper foil is laminated on both sides of an insulating layer including, for example, resin-impregnated glass cloth.

[0029] The glass transition temperature Tg of the insulating layer measured by the tensile method of dynamic mechanical analysis (DMA) may be 200°C or higher, 250°C to 400°C, 280°C to 350°C, or 300°C to 350°C, from the viewpoint of heat resistance.

[0030] The linear expansion coefficient α1 of the insulating layer, measured by the compression method of thermomechanical analysis (TMA), may be 3.0 ppm / °C to 15.0 ppm / °C, 4.0 ppm / °C to 11.0 ppm / °C, 5.0 ppm / °C to 8.0 ppm / °C, or 5.5 ppm / °C to 8.0 ppm / °C. By setting the linear expansion coefficient α1 of the insulating layer to 5.0 ppm / °C or more, semiconductor devices that can simultaneously reduce solder bridges and connection defects tend to be produced with a high yield. The linear expansion coefficient α1 of the insulating layer refers to the linear expansion coefficient below the glass transition temperature of the insulating layer.

[0031] The linear expansion coefficient α2 of the insulating layer, measured by a compression method of thermomechanical analysis (TMA), may be 0.1 ppm / °C to 3.0 ppm / °C, 0.3 ppm / °C to 2.0 ppm / °C, or 0.5 ppm / °C to 1.5 ppm / °C. The linear expansion coefficient α2 of the insulating layer means the linear expansion coefficient at or above the glass transition temperature of the insulating layer.

[0032] The storage modulus of the insulating layer at 30° C. measured by the tensile method of dynamic mechanical analysis (DMA) may be 15 GPa to 40 GPa, 20 GPa to 35 GPa, or 20 GPa to 30 GPa.

[0033] The storage modulus of the insulating layer at 260° C. measured by the tensile method of dynamic mechanical analysis (DMA) may be 10 GPa to 30 GPa, 12 GPa to 25 GPa, or 15 GPa to 25 GPa.

[0034] The semiconductor package may include components other than the package substrate and the plurality of solder balls, such as an interposer, a semiconductor chip, a stiffener, and a lid.

[0035] An interposer is a component that electrically connects multiple semiconductor chips to a package substrate and is disposed on the package substrate. Examples of interposers include silicon interposers and organic interposers.

[0036] When a semiconductor package includes an interposer, it is preferable that the semiconductor package include a silicon interposer on a package substrate from the viewpoint of fine connection between semiconductor chips. Silicon allows for electrical connection using fine wiring compared to organic materials, and the use of a silicon interposer with a linear expansion coefficient similar to that of semiconductor chips improves the reliability between electrically connected semiconductor chips. Furthermore, when a silicon interposer is used, multiple semiconductor chips are mounted on the silicon interposer, and after processing such as sealing, the silicon interposer is mounted on a package substrate. Therefore, compared to mounting an organic interposer on the package substrate and then mounting semiconductor chips individually on the organic interposer, this method tends to improve yield and is more efficient in manufacturing good products.

[0037] The semiconductor chip includes a processor such as a central processing unit (CPU) or a graphics processing unit (GPU), a memory such as a dynamic random access memory (DRAM) or a NAND, a power supply circuit, a sensor, etc. The semiconductor chip may be a semiconductor chip that is three-dimensionally mounted (3D mounted) by vertically stacking a processor or a system on chip (SoC) that includes a processor, or a memory such as a high bandwidth memory (HBM) that has multiple stacked dynamic random access memories (DRAMs), etc. Alternatively, the semiconductor chip may be a semiconductor chip (e.g., a 2.5D mounted semiconductor chip) in which a processor or a memory such as an SoC or an HBM is mounted in a planar direction on an interposer such as a silicon interposer.

[0038] The semiconductor chip is mounted on a package substrate, an interposer, etc., and is connected by solder bumps or wire bonding to wiring formed on the package substrate, interposer, etc. Furthermore, the space between the semiconductor chip and the package substrate, interposer, etc. may be sealed with a sealing material such as an underfill material.

[0039] A single semiconductor chip or multiple semiconductor chips may be arranged on the package substrate. The semiconductor chip arranged on the package substrate may be sealed with a sealing material such as LMC (Liquid Molding Compound). Furthermore, when multiple semiconductor chips are arranged, the multiple semiconductor chips may all be sealed with a sealing material.

[0040] The stiffener is a component for reducing warpage of a semiconductor package. For example, the stiffener may be disposed on the outer periphery of the package substrate in a plan view, or on a portion of the outer periphery or the entire outer periphery. The shape of the stiffener is not particularly limited, and may be frame-shaped, rod-shaped, or the like. The material, width, and the like of the stiffener may be adjusted depending on the linear expansion coefficient of the material constituting the package substrate, the area ratio of the semiconductor chip in the semiconductor package in a plan view, and the like. The width of the stiffener may be, for example, 10 mm to 30 mm, or 15 mm to 25 mm.

[0041] The material of the stiffener is not particularly limited, and examples thereof include copper, copper alloys such as Cu-Mo alloy and Cu-W alloy, and SUS such as SUS304 and SUS430. The stiffener may be adhered to the package substrate using an adhesive or the like. The surface of the stiffener may be plated to improve adhesive strength.

[0042] The lid is a member that covers the semiconductor chip and can function as a member that dissipates heat generated in the semiconductor chip. The material of the lid is not particularly limited, but from the viewpoint of heat dissipation, a metal with low thermal resistance such as copper is preferable.

[0043] The area of ​​the semiconductor package in plan view is 2500 mm ２ It may be 4000 mm or more, ２ It may be 5000 mm or more. ２ It may be 5625 mm or more. ２ or more (for example, 75 mm x 75 mm or more), ２ ~22,500 mm ２Generally, when a large semiconductor package is mounted on a motherboard, connection failures are likely to occur. In the manufacturing method of the present disclosure, ２ Even when a relatively large semiconductor package such as that described above is used, poor connections at the edges and center can be suitably reduced.

[0044] When the package substrate is rectangular in plan view, the lengths of the four sides of the package substrate in plan view may each independently be 50 mm or more, 60 mm or more, 75 mm or more, 80 mm or more, or 80 mm to 150 mm. The manufacturing method disclosed herein can suitably reduce connection defects at the edges and center, even when using a relatively large semiconductor package having the aforementioned length of 50 mm or more.

[0045] The mass of the semiconductor package may be 100 g or more, 100 g to 300 g, or 120 g to 200 g. Generally, when a high-mass semiconductor package is mounted on a motherboard, bridging is likely to occur due to the weight of the semiconductor package. The manufacturing method disclosed herein can effectively reduce the occurrence of bridging even when a relatively heavy semiconductor package having a mass of 100 g or more is used.

[0046] (Motherboard) A motherboard used in manufacturing a semiconductor device is a component electrically connected to a semiconductor package, and includes a plurality of metal pads electrically connected to a plurality of solder balls provided on the semiconductor package. Solder paste is disposed on some of the metal pads (two or more metal pads). The motherboard may be a conventionally known electronic circuit board used in semiconductor packaging.

[0047] In a motherboard used in manufacturing a semiconductor device, among a plurality of metal pads, at least a portion of the metal pads arranged on the peripheral edge side do not have solder paste applied thereto. Methods for selectively applying solder paste to the plurality of metal pads are not particularly limited, and include screen printing, inkjet printing, spray printing, etc. Among these, screen printing and inkjet printing are preferred from the viewpoint of productivity.

[0048] A solder paste may be formed on some of the metal pads (two or more metal pads) by screen printing. For example, an aperture member (e.g., a stencil) having a plurality of openings may be placed facing the metal pads, solder paste may be applied to the aperture member, and the solder paste may be printed on the metal pads facing the openings using a squeegee. By performing screen printing while masking the metal pads on which solder paste is not to be applied (e.g., metal pads located at least partially on the peripheral edge), a motherboard can be easily obtained in which solder paste is not applied to the metal pads located at least partially on the peripheral edge. Alternatively, from the perspective of improving productivity and reducing foreign matter contamination, screen printing may be performed using an aperture member that does not have openings at positions facing the metal pads on which solder paste is not to be applied (e.g., an aperture member that does not have openings at positions facing the metal pads located at least partially on the peripheral edge).

[0049] Solder paste may be formed on some of the metal pads (two or more metal pads) by inkjet printing. The locations where solder paste is formed and the amount of solder paste can be easily adjusted by setting the inkjet printing program, etc.

[0050] The metal pads on which solder paste is not applied may be metal pads arranged on at least a portion of the peripheral edge side. For example, solder paste does not have to be applied to all of the metal pads arranged on the peripheral edge side.

[0051] For example, when the package substrate is rectangular in plan view, it is preferable that the plurality of solder balls are arranged along the periphery of the rectangle, and a configuration (Configuration 1) in which the plurality of metal pads are also arranged so as to face the plurality of solder balls is more preferable. In this case, in the rectangular region in which the plurality of metal pads of the motherboard are arranged, it is preferable that the metal pads located at the corners do not have solder paste arranged thereon. In this region, the metal pads located on the peripheral edge side other than the corners may or may not have solder paste arranged thereon.

[0052] In the rectangular region in which a plurality of metal pads are arranged in the above-described configuration 1, the ratio (Y / X) of the length Y (Y in FIG. 3) of the portion of the metal pad where solder paste is not arranged in the direction from the corner to the length X (X in FIG. 3, the dots in FIG. 3 indicate the arrangement of the metal pads) may be 0.05 to 0.6, 0.1 to 0.4, 0.15 to 0.3, or 0.2 to 0.25. The ratio (Z / X) of the length Z (Z in FIG. 3) of the portion of the metal pad where solder paste is not arranged in the direction perpendicular to the length X (approximately the length of one side of the package substrate in a plan view) and inside the rectangular region may be 0.01 to 0.2, 0.02 to 0.15, or 0.04 to 0.1. The arrangement, size, distance between metal pads, density, etc. of the metal pads are not limited to the configuration of FIG. 3.

[0053] The numerical range of the length X is the same as the numerical range of the lengths of the four sides of the package substrate in a plan view, and may be 50 mm or more, 60 mm or more, 75 mm or more, 80 mm or more, or 80 mm to 150 mm. The length Y may be 5 mm to 50 mm, 10 mm to 40 mm, 15 mm to 25 mm, or 20 mm to 25 mm. The length Z may be 0.5 mm to 25 mm, 1 mm to 20 mm, 2 mm to 15 mm, or 4 mm to 10 mm.

[0054] Of the multiple metal pads arranged on the motherboard, the percentage of metal pads on which no solder paste is arranged may be 35% by number or less, or may be 9% to 25% by number.

[0055] For solder pastes disposed on two or more metal pads, the volume of solder paste per metal pad is independently 0.01 mm ３ ~0.03mm ３ 0.015 mm ３ ~0.03mm ３ 0.02 mm ３ ~0.028mm ３ may be.

[0056] It is preferable that the volume of the solder paste placed on each of two or more metal pads hardly changes. For example, for multiple solder pastes, the volume of the solder paste per metal pad relative to the maximum volume of the solder paste per metal pad is preferably independently 80% or more, and more preferably 90% to 100%. The maximum volume of the solder paste per metal pad means the volume of the solder paste with the largest volume among the multiple solder pastes. For example, when the maximum volume is 0.03 mm ３ , the volume of solder paste per metal pad is 0.024 mm ３ (0.03 mm ３ ×0.8) or more is preferable.

[0057] For the solder paste disposed on each of two or more metal pads, the height of the solder paste may be 0.05 mm to 0.25 mm, or 0.1 mm to 0.2 mm. The area of ​​the solder paste in a plan view may be the same as the area of ​​the metal pad on which the solder paste is disposed in a plan view, or may be larger or smaller than the area of ​​the metal pad in a plan view.

[0058] In the above-mentioned placement step, the semiconductor package and the motherboard are placed via a spacer. The spacer is preferably placed between the semiconductor package and the motherboard while being located at an edge of the package substrate in a plan view. When the package substrate is rectangular in plan view, the spacer is preferably placed between the semiconductor package and the motherboard while being located at a corner of the semiconductor package.

[0059] The height of the spacer in cross section may be 0.1 mm to 0.5 mm, and from the viewpoint of suitably reducing poor connection between the semiconductor package and the motherboard at the bridge where adjacent solder joints come into contact and at the center, it is preferably 0.2 mm to 0.35 mm, and more preferably 0.2 mm to 0.3 mm.

[0060] [Bonding Step] The manufacturing method of the present disclosure includes, after the placement step, a step of heating the semiconductor package and the motherboard to electrically bond the plurality of solder balls and the plurality of metal pads (bonding step).

[0061] In the bonding process, the semiconductor package and the motherboard are heated, and the solder balls and solder paste are reflowed to electrically bond the solder balls to the metal pads. The reflow bonds the solder balls to the solder paste on the metal pads where the solder paste is applied. On the other hand, the reflow bonds the solder balls to the metal pads where the solder paste is not applied. After bonding, the spacer is removed to obtain the semiconductor device.

[0062] During reflow, in a plan view, the peripheral edges of the semiconductor package are lowered in the vertical direction, while the central portion of the semiconductor package is raised in the vertical direction. In other words, reflow causes warping of the semiconductor package. As a result, bridging is more likely to occur near the peripheral edges, and connection failures are more likely to occur near the central portion.

[0063] On the other hand, in the manufacturing method of the present disclosure, by using spacers as described above and providing metal pads on the peripheral edge side of the motherboard without solder paste, it is possible to reduce connection failures at the edges and center of the semiconductor package and motherboard.

[0064] A cross-sectional view showing the configuration of a semiconductor device manufactured by the manufacturing method of the present disclosure is shown in Fig. 1. The semiconductor device 100 shown in Fig. 1 includes a motherboard 1 and a semiconductor package 10, and a connection portion 15 is formed by connecting a plurality of metal pads 14 provided on the motherboard 1 to a plurality of solder balls provided on the semiconductor package 10 by reflow soldering, either directly or via solder paste.

[0065] The semiconductor package 10 includes a package substrate 2 having a plurality of solder balls provided on one surface thereof, a semiconductor chip 3, a stiffener 4, a silicon interposer 8, and the like.

[0066] When viewed from the side where the solder balls are provided, the package substrate 2 is laminated in the following order: solder resist layer 13, buildup layer 12, core layer 11, buildup layer 12, and solder resist layer 13. On the side opposite to the side where the solder balls are provided of the package substrate 2, a frame-shaped stiffener 4 is adhered via an adhesive to the peripheral edge in plan view, and is electrically connected to the silicon interposer 8 via solder bumps. Furthermore, the space between the silicon interposer 8 and the solder resist layer 13 is sealed with an underfill material 9.

[0067] The semiconductor chip 3 includes a processor 5 such as a CPU or a GPU and a memory 6 such as an HBM, and is sealed with a sealing material 7 such as LMC. Furthermore, the semiconductor chip 3 is electrically connected to a silicon interposer 8 via solder bumps, and the space between the semiconductor chip 3 and the silicon interposer 8 is sealed with an underfill material.

[0068] <Semiconductor Device> The semiconductor device disclosed herein comprises a semiconductor package having a package substrate and a plurality of solder balls on one surface of the package substrate, and a motherboard having a plurality of metal pads, which are electrically connected via the plurality of solder balls and the plurality of metal pads, and at a plurality of connection portions where the plurality of solder balls and the plurality of metal pads are electrically connected, the ratio of the minimum solder volume per connection portion to the maximum solder volume per connection portion satisfies 0.6 to 0.95.

[0069] The semiconductor device of the present disclosure includes a plurality of connection portions where a plurality of solder balls and a plurality of metal pads are electrically joined, and the ratio of the minimum solder volume per connection portion to the maximum solder volume per connection portion (minimum solder volume / maximum solder volume) satisfies 0.6 to 0.95. In other words, the semiconductor device includes both connection portions with larger solder volumes and connection portions with smaller solder volumes, which makes it possible to reduce connection defects at the edges and center of the semiconductor package and motherboard.

[0070] Possible aspects of each configuration in the semiconductor device of the present disclosure are the same as those of each configuration in the above-described method for manufacturing a semiconductor device of the present disclosure.

[0071] The semiconductor device of the present disclosure can be manufactured by applying the semiconductor device manufacturing method of the present disclosure described above. For example, a connection portion with a larger solder volume can be achieved by electrically connecting a solder ball and a metal pad with solder paste disposed on the metal pad. Also, a connection portion with a smaller solder volume can be achieved by electrically connecting a solder ball and a metal pad with no solder paste disposed on the metal pad. By adjusting the amount of solder paste disposed on the metal pad, it is possible to adjust the minimum solder volume / maximum solder volume.

[0072] In order to effectively reduce connection defects at the edges and center of the semiconductor package and motherboard, it is preferable that the solder volume per connection at the center is larger than the solder volume per connection at the peripheral edges.

[0073] The solder volume per connection portion in at least one connection portion located in the central portion of the semiconductor package (hereinafter also referred to as solder volume A) may be larger than the solder volume per connection portion in at least one connection portion located on the peripheral edge of the semiconductor package (hereinafter also referred to as solder volume B). For example, the ratio of solder volume B to solder volume A (solder volume B / solder volume A) may satisfy 0.6 to 0.95, 0.7 to 0.95, or 0.7 to 0.9.

[0074] The package substrate may be rectangular in plan view, and in this case, it is preferable that a plurality of connection portions, in which solder balls and metal pads are electrically joined, are arranged along the periphery of the rectangle. Furthermore, it is preferable that the solder volume per connection portion located at the corners of the rectangle (hereinafter also referred to as solder volume C) is smaller than the solder volume per connection portion located at a location other than the corners (hereinafter also referred to as solder volume D). The ratio of solder volume C to solder volume D (solder volume C / solder volume D) may satisfy 0.6 to 0.95, 0.7 to 0.95, or 0.7 to 0.9.

[0075] In the present disclosure, the solder volume per connection can be determined by the following method. If the connection is severable, the pad area on the package substrate side, the pad area on the motherboard side, the projected area of ​​the solder (because it is not a perfect sphere but is flattened in the plane direction), etc. can be measured using X-rays, and the solder volume can be determined from these measurement results and the height of the connection determined from the cut surface. If the connection is not severable, three-dimensional image data of the connection can be obtained non-destructively by X-ray CT (e.g., high-resolution X-ray CT), and the solder volume can be determined from the three-dimensional image data.

[0076] The present disclosure will be specifically described below using examples, but the scope of the present disclosure is not limited to these examples.

[0077] In the following experimental example, a sample 100A simulating a semiconductor device as shown in FIG. 2 was fabricated. Sample 100A was fabricated using a motherboard 1A having multiple metal pads 14, a laminated substrate 2A having a core layer 11, a build-up layer 12, and a solder resist layer 13, and further having multiple solder balls (approximately spherical with a radius of 300 μm), a stiffener 4, an adhesive, and a member 3A simulating a semiconductor chip. The member 3A and the laminated substrate 2A were connected with solder bumps, and the space between them was sealed with an underfill material 9. A connection 15 was formed by connecting the metal pads 14 and the solder balls directly or via solder paste (not shown) by reflow soldering. Details of each member are as follows.

[0078] Motherboard: A rectangular motherboard with each side measuring 160 mm and having multiple metal pads in a rectangular area. Build-up layer: A laminated structure of Ajinomoto Build-up Film (ABF) GX-92 (thickness 30 μm) manufactured by Ajinomoto Fine-Techno Co., Ltd. and a copper layer (thickness 18 μm). Core layer: A copper-clad laminate in which copper foil (thickness 12 μm) is laminated on both sides of an insulating layer. Solder resist layer: Photosensitive solder resist (SR) manufactured by Showa Denko Materials Inc. The arrangement of the solder resist layer, build-up layer, and core layer is as follows: SR (15μm) / Copper foil (18μm) / ABF (30μm) / ABF (30μm) / Copper foil (18μm) / ABF (30μm) / ABF (30μm) / Copper foil (1 8μm) / ABF (30μm) / ABF (30μm) / Copper foil (18μm) / ABF (30μm) / ABF (30μm) / Copper foil (12μm) / Core layer (1400 ~1500μm) / Copper foil (12μm) / ABF (30μm) / ABF (30μm) / Copper foil (18μm) / ABF (30μm) / ABF (30μm) / Copper foil (1 8μm) / ABF (30μm) / ABF (30μm) / Copper foil (18μm) / ABF (30μm) / ABF (30μm) / Copper foil (18μm) / SR (15μm) Stiffener: Copper stiffener, width 16 mm, thickness 2.5 mm Adhesive: Silicone adhesive KE-1867 manufactured by Shin-Etsu Chemical Co., Ltd. Semiconductor chip imitation component: WALTS-TEG FBW200A-0000JY manufactured by Waltz Corporation (50 mm per side, solder bump Cu 30 μm + SnAg 30 μm)

[0079] As the insulating layers contained in the copper clad laminate, insulating layers 1 to 5 having the physical properties shown in Table 1 below were used.

[0080]

[0081] <Sample Preparation> Solder paste was placed on multiple metal pads on a motherboard. Specifically, a stencil with multiple openings was placed on the motherboard so that the openings faced the metal pads of the motherboard, and the solder paste was printed on the metal pads by screen printing. The stencil opening height was 130 μm, and the stencil opening diameter was 350 μm or 450 μm. The height of the formed solder paste was 130 μm (0.13 mm). For solder paste printing, motherboards were prepared with metal pads in which the four corners of the peripheral edge of the rectangular area where the metal pads were provided were masked to leave no solder paste printed on them, and motherboards with metal pads printed without the masking were prepared. A package member was prepared in which a stiffener was attached using an adhesive to a laminated substrate (a rectangular substrate with a side length of 100 mm) with multiple solder balls, and WALTS-TEG was connected via solder bumps. In the package member, the gap between the WALTS-TEG and the laminated substrate is sealed with an underfill material. The package member and motherboard are arranged via spacers. Two spacers are arranged per corner of the package member, for a total of eight spacers. The heights of the spacers are 200 μm, 250 μm, 300 μm, and 350 μm. The package member and motherboard on which the spacers are arranged are then heated, and the solder balls and metal pads are electrically connected by reflow. In this way, a sample simulating the semiconductor device shown in FIG. 2 was produced. The volume of solder paste per metal pad was 450 × 450 × 130 (μm ３ ) or 350 x 350 x 130 (μm ３ ) and the volume of the solder ball is 4 / 3×π×(300) ３ (μm ３ From these volume values, the volume ratio of the connection part with a small solder volume (solder balls only) to the connection part with a large solder volume (solder balls + solder paste) was calculated to be 0.81 or 0.88.

[0082] <Evaluation of Solder Bridges> The prepared samples were observed with X-rays to check for the presence or absence of solder bridges where adjacent solder joints come into contact with each other. In particular, the presence or absence of solder bridges near the corners and center of the package members was checked in a plan view.

[0083] <Connection Evaluation> The resistance of the connection parts of the prepared samples was measured using a tester. Specifically, in a plan view, the resistance of the connection parts in three rows vertically and horizontally along the four sides of the package member, and the resistance of the connection parts in three rows vertically and horizontally on the inside along the four sides of the WALTS-TEG were measured. Connection parts where the resistance value significantly increased were evaluated as having poor connection.

[0084] [Experimental Example 1] A copper-clad laminate was used as the core layer, in which copper foil was laminated on both sides of insulating layer 1 in Table 1. Furthermore, a motherboard was prepared with metal pads on which solder paste was printed without masking, using a stencil with a stencil opening diameter of 350 μm and a spacer with a spacer height of 300 μm in the above-mentioned <Sample Preparation>, to prepare a sample.

[0085] [Experimental Examples 2 to 5] Samples were prepared in the same manner as in Experimental Example 1, except that the stencil opening diameter and spacer height were changed to the values ​​shown in Table 2. In Experimental Example 5, insulating layer 2 was used instead of insulating layer 1 in Table 1.

[0086] The samples prepared in Experimental Examples 1 to 5 were used to evaluate solder bridges and connections. The results are shown in Table 2.

[0087]

[0088] The results of Experimental Examples 1 to 5 revealed that it is difficult to simultaneously reduce solder bridges and poor connections.

[0089] [Experimental Example 6] A copper-clad laminate in which copper foil was laminated on both sides of insulating layer 2 in Table 1 was used as the core layer. Furthermore, a motherboard with metal pads on which no solder paste was printed was prepared by masking the four corners of the peripheral edge using a stencil with a stencil opening diameter of 450 μm and a spacer with a spacer height of 250 μm as described above in the "Sample Preparation" section. In Experimental Example 6, 15 rows (Y in FIG. 3, ratio to the length of one side: 0.15) x 4 rows (Z in FIG. 3, ratio to the length of one side: 0.04) of masking were performed on the four corners of the peripheral edge.

[0090] In Experimental Example 7, a copper-clad laminate was used as the core layer, in which copper foil was laminated on both sides of insulating layer 4 in Table 1. Furthermore, a sample was produced in the same manner as in Experimental Example 6, except that 20 rows (Y in FIG. 3 , ratio to the length of one side: 0.2) x 4 rows (Z in FIG. 3 , ratio to the length of one side: 0.04) were masked at the four corners of the peripheral edge.

[0091] The samples prepared in Experimental Examples 6 and 7 were used to evaluate solder bridges and connections. The results are shown in Table 3.

[0092]

[0093] In Experimental Example 6, no solder bridges were found near the center of the package member, and some solder bridges were found near the corners, but the number of solder bridges was significantly reduced compared to Experimental Examples 2 to 5. In Experimental Example 7, no solder bridges were found near the corners or center of the package member. Furthermore, in Experimental Examples 6 and 7, no unconnected portions were found with the tester. In Experimental Examples 6 and 7 (especially Experimental Example 7), it was possible to reduce both solder bridges and poor connections.

[0094] [Experimental Examples 8 to 12] Furthermore, in Experimental Examples 8 to 12, multiple samples were produced using copper-clad laminates in which copper foil was laminated on both sides of insulating layers 1 to 5 in Table 1, and the yield rate of non-defective products capable of simultaneously reducing solder bridges and connection defects was evaluated. The results are shown in Table 4. In Table 4, "Outer side, first to third round from the outside" refers to the percentage of samples in which no connection defects occurred at the connection points corresponding to the metal pads arranged in a frame shape from the first to third round from the outside (A in Figure 3) in the rectangular area in which the metal pads are arranged in the plan view of the motherboard in Figure 3 (number of samples without connection defects / total number of samples). In Table 4, "Inside, 1st to 3rd laps from the outside" refers to the percentage of samples (number of samples without connection defects / total number of samples) that did not have connection defects at the connection points corresponding to the metal pads arranged in a frame shape from the first to third pads (B in Figure 3) inside the rectangular area where the metal pads are arranged in the plan view of the motherboard in Figure 3.

[0095]

[0096] In Experimental Examples 8 to 12, samples that were able to reduce both solder bridges and connection defects were obtained at a high yield rate (for example, 75% or more).

[0097] All publications, patent applications, and technical standards mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.

Claims

1. Prepare a package substrate, a semiconductor package having a plurality of solder balls on one surface of the package substrate, a mother board including a plurality of metal pads and a plurality of solder pastes disposed on some of the plurality of metal pads, and arrange the semiconductor package and the mother board such that the plurality of solder balls and the plurality of metal pads face each other, heat the semiconductor package and the mother board to electrically join the plurality of solder balls and the plurality of metal pads, including, in the arranging step, prepare the mother board in which the solder paste is not disposed on at least a part of the metal pads disposed on the peripheral edge side, and arrange the semiconductor package and the mother board via a spacer. A method for manufacturing a semiconductor device.

2. Regarding the plurality of solder pastes, the volume of the solder paste per metal pad is, independently of each other, 0.01 mm ３ to 0.03 mm ３ The method for manufacturing a semiconductor device according to claim 1, wherein the thickness is as described above.

3. For the plurality of solder pastes, the volume of the solder paste per metal pad with respect to the maximum volume of the solder paste per metal pad is 80% or more independently. The method for manufacturing a semiconductor device according to claim 1 or claim 2.

4. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the plurality of solder pastes are formed on some of the plurality of metal pads by screen printing.

5. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the height of the spacer in a cross-sectional view is 0.2 mm to 0.3 mm.

6. The area in the plan view of the semiconductor package is 2500 mm ２ or more, the method of manufacturing a semiconductor device according to claim 1 or claim 2.

7. The package substrate is rectangular in a plan view, and the lengths of the four sides of the package substrate in the plan view are each independently 50 mm or more. The method for manufacturing a semiconductor device according to claim 1 or claim 2.

8. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the mass of the semiconductor package is 100 g or more.

9. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the package substrate includes a core layer including a copper-clad laminate.

10. The method for manufacturing a semiconductor device according to claim 1 or claim 2, wherein the semiconductor package includes a silicon interposer electrically connected and mounted on a plurality of semiconductor chips on the package substrate, or includes a plurality of semiconductor chips.

11. A package substrate, a semiconductor package having a plurality of solder balls on one surface of the package substrate, and a mother board including a plurality of metal pads are electrically joined via the plurality of solder balls and the plurality of metal pads. A semiconductor device in which, in a plurality of connection portions where the plurality of solder balls and the plurality of metal pads are electrically joined, the ratio of the minimum value of the solder volume per connection portion to the maximum value of the solder volume per connection portion is 0.6 to 0.

95.

12. The semiconductor device according to claim 11, wherein the ratio of the solder volume per connection portion in at least one connection portion located at the central portion of the semiconductor package to the solder volume per connection portion in at least one connection portion located at the peripheral edge portion of the semiconductor package is 0.6 to 0.

95.

13. The semiconductor device according to claim 11, wherein the package substrate is rectangular in plan view, and the solder volume per connection portion in a connection portion located at a corner of the rectangle is smaller than the solder volume per connection portion in a connection portion located other than the corner.

14. The semiconductor device according to any one of claims 11 to 13, wherein the package substrate includes a core layer including a copper-clad laminate.

15. The semiconductor device according to any one of claims 11 to 13, wherein the semiconductor package includes a silicon interposer electrically connected and mounted on a plurality of semiconductor chips on the package substrate, or includes a plurality of semiconductor chips.