Semiconductor substrate, apparatus and method for producing semiconductor substrate, and method for producing semiconductor device

Abstract

The present invention comprises: a template substrate that includes a growth suppression region and a first seed region aligned in a first direction; and a first semiconductor part that is positioned above the template substrate and that includes a nitride semiconductor. The first semiconductor part has: a first protruding portion that extends from the first seed region to a position nearer the upper side than the growth suppression region; a growth suppression film in contact with the first protruding portion; a first base section positioned above the first protruding portion; and a first wing section that is connected to the first base section, and is positioned over a gap, apart from the growth suppression region.

Description

Semiconductor substrate, semiconductor substrate manufacturing method and manufacturing apparatus, and semiconductor device manufacturing method

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] For example, when a GaN layer is formed on a heterogeneous substrate, the GaN layer is 10 ８ cm －２ On the silicon substrate, ９ cm －２ At a defect density of about 1000 nm, threading dislocations occur at the interface between dissimilar materials, degrading the performance of semiconductor devices formed on GaN layers. Therefore, the epitaxial lateral overgrowth (ELO) method has been investigated as a technique for forming a nitride semiconductor layer (e.g., a GaN layer) with a low defect density on a heterogeneous substrate. For example, a mask pattern that prevents the growth of a nitride semiconductor layer is formed on a base substrate including a heterogeneous substrate and a seed layer. The seed layer exposed in the opening where the mask portion is not present is used as a growth starting point for laterally growing the nitride semiconductor layer on the mask portion, thereby reducing the defect density of the nitride semiconductor layer on the mask portion (see Patent Document 1).

[0003] JP 2013-251304 A

[0004] The technique of Patent Document 1 has a problem in that the laterally growing nitride semiconductor layer comes into contact with the mask portion, thereby reducing the flatness of the nitride semiconductor layer.

[0005] The semiconductor substrate according to the present disclosure comprises a template substrate including a growth inhibition region and a first seed region aligned in a first direction, and a first semiconductor portion located above the template substrate and including a nitride semiconductor, the first semiconductor portion having a first raised portion extending from the first seed region to a position above the growth inhibition region, a growth inhibition film in contact with the first raised portion, a first base portion located above the first raised portion, and a first wing portion connected to the first base, separated from the growth inhibition region, and located above a gap.

[0006] The first semiconductor portion including the nitride semiconductor can have a low defect density and high flatness.

[0007] FIG. 1 is a plan view showing a configuration of a semiconductor substrate according to the present embodiment. FIG. 2 is a cross-sectional view showing a configuration of a semiconductor substrate according to the present embodiment. FIG. 3 is a cross-sectional view showing another configuration of a semiconductor substrate according to the present embodiment. FIG. 4 is a cross-sectional view showing another configuration of a semiconductor substrate according to the present embodiment. FIG. 5 is a cross-sectional view showing another configuration of a semiconductor substrate according to the present embodiment. FIG. 6 is a cross-sectional view showing another configuration of a semiconductor substrate according to the present embodiment. FIG. 7 is a cross-sectional view showing another configuration of a semiconductor substrate according to the present embodiment. FIG. 8 is a flow chart showing a manufacturing method of a semiconductor substrate according to the present embodiment. FIG. 9 is a block diagram showing a manufacturing apparatus for a semiconductor substrate according to the present embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor substrate according to Example 1. FIG. 11 is a cross-sectional view showing another configuration of a semiconductor substrate according to Example 1. FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. FIG. 13 is a cross-sectional view showing another configuration of a semiconductor substrate according to Example 1. FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1. FIG. 15 is a graph showing XRD scan measurement results in a comparative example. FIG. 16 is a graph showing XRD scan measurement results in Example 1. FIG. 17 is a plan view of a semiconductor substrate including an upper layer portion. FIG. 18 is a cross-sectional view of a semiconductor substrate including an upper layer portion. FIG. 19 is a plan view showing a method for element isolation in Example 1. FIG. 19 is a cross-sectional view showing the method for element isolation in Example 1. FIG. 19 is a schematic diagram showing a configuration of an electronic device according to Example 1. FIG. 19 is a cross-sectional view showing a configuration of a semiconductor substrate according to Example 2. FIG. 10 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 4. FIG. 11 is a plan view showing the configuration of a semiconductor substrate of Example 5. FIG. 12 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 5. FIG. 13 is a cross-sectional view showing a method for manufacturing a semiconductor substrate. FIG. 14 is a cross-sectional view showing a method for manufacturing a template substrate. FIG. 15 is a cross-sectional view showing a method for manufacturing a template substrate. FIG. 16 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 6. FIG. 17 is a flow chart showing a method for manufacturing a semiconductor device of Example 7. FIG. 18 is a cross-sectional view showing a method for manufacturing a semiconductor device of Example 7.

[0008] FIG. 1 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. FIG. 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 1 and 2 , the semiconductor substrate 10 includes a template substrate TS having a mask pattern 6 including a mask portion 5 and a first opening K1 aligned in a first direction X1, and a first semiconductor portion 8A located above the template substrate TS and including a nitride semiconductor. The first semiconductor portion 8A includes a first protrusion R1 extending from a first seed region S1 located below the first opening K1 to a position above the upper surface of the mask portion 5, a first base B1 located above the first protrusion R1, and a first wing portion F1 connected to the first base B1, separated from the mask portion 5, and located above the gap JD. The semiconductor substrate 10 may include a growth suppression film 7 in contact with the first protrusion R1. The direction from the main substrate 1 toward the first semiconductor portion 8A is defined as "upward." Viewing an object with a line of sight parallel to the normal direction of the semiconductor substrate 10 (including perspective) is sometimes called a “planar view.” The mask portion 5 and the first opening K1 may be aligned in the first direction X1 in the planar view.

[0009] The template substrate TS may have a main substrate 1 having a lattice constant different from that of the first semiconductor portion 8A, and a seed portion 3 including a first seed region S1. The first opening K1, the first raised portion R1, and the first base portion B1 may overlap in a planar view, and the mask portion 5 and the first wing portion F1 may overlap in a planar view. The first wing portion F1 does not need to be in contact with the side surface of the first raised portion R1.

[0010] As shown in FIGS. 1 and 2 , the semiconductor substrate 10 includes a template substrate TS including a first seed region S1 (the exposed surface of the seed portion 3) and a growth inhibition region DA (the mask portion 5) aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS and including a nitride semiconductor. The first semiconductor portion 8A includes a first raised portion R1 extending from the first seed region S1 to a position above the growth inhibition region DA, a first base portion B1 positioned above the first raised portion R1, and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and positioned above the gap JD. The semiconductor substrate 10 may include a growth inhibition film 7 in contact with the first raised portion R1 at a position above the growth inhibition region DA. The first wing portion F1 does not need to be in contact with the side surface of the first raised portion R1. The first seed region S1 and the growth inhibition region DA only need to be aligned in the first direction X1 in a plan view.

[0011] The first semiconductor portion 8A contains a nitride semiconductor as a main component. The nitride semiconductor can be expressed, for example, as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). A GaN-based semiconductor is a semiconductor containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0012] The first semiconductor portion 8A may be doped (e.g., n-type including donors) or non-doped. A semiconductor substrate means a substrate including a semiconductor, and the main substrate 1 of the template substrate TS may or may not include a semiconductor (e.g., silicon, silicon carbide). An example of a main substrate 1 that does not include a semiconductor is a sapphire substrate. The main substrate 1 may be a free-standing substrate (wafer). The main substrate 1 and the seed portion 3 may be collectively referred to as a base substrate. The template substrate TS including the base substrate and the mask pattern 6 may be referred to as a growth substrate.

[0013] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor portion 8A. The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor portion 8A (nitride semiconductor such as GaN). The thickness direction Z of the first semiconductor portion 8A may be the c-axis direction (<0001> direction) of the first semiconductor portion 8A.

[0014] The first semiconductor portion 8A can be formed by an epitaxial lateral overgrowth (ELO) method, starting from a first protrusion R1 grown from the seed portion 3 exposed below the first opening K1. Of the first semiconductor portion 8A, a base B1 located above the first opening K1 becomes a dislocation inherited portion with many threading dislocations, and a first wing portion F1 located above the mask portion 5 becomes a low-defect portion with a lower threading dislocation density than the dislocation inherited portion.

[0015] In this way, by forming the first raised portion R1 and forming the first wing portion F1 that extends laterally (in a direction parallel to the first direction X1) from the first base portion B1 on the first raised portion R1 and is separated from the mask portion 5 and positioned above the void JD, it is possible to form a wide first wing portion F1 that has a low defect density and high flatness. The entire first wing portion F1 may be separated from the mask portion 5. In other words, the entire first wing portion F1 does not need to be in contact with the mask portion 5. This makes it possible to form a wide first wing portion F1 that has a low defect density and high flatness.

[0016] The semiconductor substrate 10 may include a second semiconductor portion 8C located above the template substrate TS. The template substrate TS may have a second seed region S2 adjacent to the first seed region S1 with the mask portion 5 interposed therebetween, and the second semiconductor portion 8C may have a second raised portion R2 extending from the second seed region S2 to a position above the mask portion 5, a second base portion B2 located above the second raised portion R2, and a second wing portion F2 connected to the second base portion B2, separated from the mask portion 5, and located above the gap JD. The first wing portion F1 and the second wing portion F2 may be aligned in the first direction X1 with a gap GP interposed therebetween.

[0017] In the following, the first raised portion R1 and the second raised portion R2 may be collectively referred to as raised portion R, the first semiconductor portion 8A and the second semiconductor portion 8C may be collectively referred to as semiconductor portion 8, the first wing portion F1 and the second wing portion F2 may be collectively referred to as wing portion F, the first base portion B1 and the second base portion B2 may be collectively referred to as base portion B, the first opening K1 and the second opening K2 of the mask pattern 6 may be collectively referred to as opening K, and the first seed region S1 and the second seed region S2 may be collectively referred to as seed region S.

[0018] The growth inhibiting film 7 may be in contact with the upper surface 5T (growth inhibiting area DA) of the mask portion 5. The first raised portion R1 may be in contact with the upper surface 5T (growth inhibiting area DA) of the mask portion 5. The first raised portion R1 may extend over the end portion 5E of the mask portion 5. The mask portion 5 and the growth inhibiting film 7 may be formed of, for example, the same silicon nitride. In such a case, it is difficult to observe the growth inhibiting film 7 on the mask portion 5 separately from the mask portion 5. The first wing portion F1 may have an edge E1 located above the mask portion 5.

[0019] The growth suppression film 7 may be in contact with the side surface RS of the first protrusion R1. This suppresses the growth of the semiconductor portion 8 from the side surface RS, making it easier to form a void JD. To achieve the effects of this embodiment, the growth suppression film 7 only needs to be formed on at least a portion of the side surface RS of the first protrusion R1, and may include a first film portion 7j in contact with the side surface RS of the first protrusion R1 and a second film portion 7i in contact with the top surface RT of the first protrusion R1. The growth suppression film 7 does not need to be a complete film; it may be a film including one or more minute openings (a film with an imperfect shape). Forming the second film portion 7i suppresses threading dislocations and the like propagated from the seed portion 3 to the first protrusion R1, thereby achieving a new effect of improving the surface flatness and crystallinity of the top surface RT of the first protrusion R1.

[0020] The side surface RS of the first protrusion R1 may be a tapered surface that narrows upward. This allows the width of the gap JD facing the back surface of the first wing portion F1 to be wider than the width facing the upper surface 5T of the mask portion 5, thereby forming a wide first wing portion F1 with low defects. The tapered side surface RS may intersect with the upper surface 5T (growth inhibition area DA) of the mask portion 5. The growth inhibition film 7 may be in contact with the upper surface RT of the first protrusion R1. Of the growth inhibition film 7 in contact with the first protrusion R1, a second film portion 7i (a portion in contact with the upper surface RT of the first protrusion R1) located on the upper surface RT of the first protrusion R1 may be included in the first semiconductor portion 8A. This reduces stress from the template substrate TS.

[0021] The first protrusion R1 may have a growth starting point PG of the nitride semiconductor at a position above the mask portion 5. The growth starting point PG may not be in contact with the growth suppression film 7, or may be in contact with a portion where the growth suppression film 7 is locally thin. A corner RC where the top surface RT and side surface RS of the first protrusion R1 intersect may be included in the growth starting point PG. The corner RC may be located above the mask portion 5. In other words, the corner RC and the mask portion 5 may overlap in a planar view.

[0022] In this way, by forming a mask pattern 6 having an opening K and then forming the first raised portion R1, corners RC are formed in the first raised portion R1. Then, by forming a growth inhibiting film 7 in contact with the first raised portion R1, the corners RC of the first raised portion R1 can be utilized as growth starting points PG. It has been found that by forming the first raised portion R1 of the nitride semiconductor by crystal growth from the seed portion 3 (seed region) exposed in the opening K or by patterning using dry etching or the like, and by forming growth starting points PG at the upper ends (e.g., both corners) of the first raised portion R1, a good nitride semiconductor layer (first base portion B1 and first wing portion F1) grows even after the growth inhibiting film 7 is formed on the first raised portion R1, and threading dislocations on the first raised portion R1 can be reduced.

[0023] By using both corners of the first protrusion R1 (two corners RC aligned in the first direction X1) as growth starting points PG, lateral film growth occurs from both sides, forming voids in the first base portion B1 (particularly the central portion). In this manner, the first base portion B1 may include voids, which relieves stress from the template substrate TS. The voids may be located above the second film portion 7i of the growth inhibiting film 7. The growth inhibiting film 7 may be a silicon nitride film. The first direction X1 is the <11-20> direction, the top surface of the first protrusion R1 may be a polar plane, and the side surface of the first protrusion R1 may be a semipolar or nonpolar plane. In this manner, by using the protrusion R to form the growth inhibiting film 7 on the top of the protrusion R, lateral film growth (growth) of the nitride semiconductor is possible even above the opening K, and defects can be effectively suppressed in the portion of the semiconductor portion 8 located above the growth inhibiting film 7 above the opening K (e.g., base portion B).

[0024] The mask portion 5 and the first opening K1 may each have a shape whose longitudinal direction is a second direction X2 that is perpendicular to the first direction X1. The main substrate 1 may be a silicon substrate, a sapphire substrate, or a silicon carbide substrate, and the nitride semiconductor included in the first semiconductor portion 8A may be a GaN-based semiconductor.

[0025] The seed portion 3 is doped with argon or oxygen as an impurity at a concentration of 2×10 １８ / cm ３ The mask portion 5 may be made of a nitride semiconductor containing at least one of the above. The thickness of the mask portion 5 may be 50 nm or less. The thickness of the growth inhibiting film 7 may be thinner than the thickness of the mask portion 5. This makes it easier for the wing portion F to grow from the protrusion R while inhibiting growth on the mask portion. The thickness of the growth inhibiting film 7 may be ⅓ or less of the thickness of the mask portion 5.

[0026] When the ELO layer contacts the mask portion, the thickness of the mask portion needs to be at least 100 nm, and interference between the mask portion and the ELO layer can impair the surface flatness of the ELO layer. However, in Example 1, the wing portion F is floating in the air and does not contact the mask portion 5, so even if the mask portion 5 is made very thin, the growth of the wing portion F is not inhibited. By making the mask portion 5 thin, the flatness of the back surface of the wing portion F is improved. If the thickness of the mask portion 5 is made 50 nm or less, flatness is improved, and it can also be set to 30 nm or less.

[0027] The deviation between the c-axis direction of the first base portion B1 and the c-axis direction of the edge of the first wing portion F1 may be 0.2 degrees or less. The threading dislocation density in the first base portion B1 and the threading dislocation density in the first wing portion F1 may each be 5×10 ６ [pcs / cm ２ The first semiconductor portion 8A may have two paired first wing portions F1 extending from the first base portion B1 in the first direction X1 and in the opposite direction.

[0028] The ratio of the width in the first direction X1 to the thickness of the gap JD (aspect ratio of the gap) may be 5.0 or more. The gap JD is a space sandwiched between the mask portion 5 (growth suppression area DA) and the first wing portion F1. The ratio of the width in the first direction X1 to the thickness of the first wing portion F1 may be 2.0 or more, 5.0 or more, 10 or more, 20 or more, or 50 or more. The width of the first wing portion F1 (width in the first direction X1) may be 7.0 μm or more, 10.0 μm or more, 20.0 μm or more, or 40.0 μm or more. The width of the first wing portion F1 is preferably 80.0 μm or less. This reduces the risk of the semiconductor portion 8 warping upward due to gravity. The thickness of the first wing portion F1 may be 10.0 μm or less, 5.0 μm or less, or 2.0 μm or less. As shown in FIG. 2 , the width of the gap GP may be greater than the thickness of the void JD. The ratio of the width of the first wing portion F1 to the width of the first base portion B1 may be 3.0 or more. The thickness of the void JD may be 3.0 μm or less. The thickness (height) of the void JD is the distance from the upper surface (growth inhibition area DA) of the mask portion 5 to the lower surface (rear surface) of the semiconductor portion 8. The width of the void JD is the distance in the first direction X1 from the side surface of the first protrusion R1 to the edge E1 of the semiconductor portion 8.

[0029] 3 and 4 are cross-sectional views showing another configuration of the semiconductor substrate according to this embodiment. As shown in FIG. 3, the seed portions 3 may be formed in a pattern (e.g., stripes aligned in the first direction X1), and the seed portions 3 may not be disposed under the mask portions 5. As shown in FIG. 4, a buffer portion 2 may be formed between the seed portions 3 and the main substrate 1. The buffer portion 2 may be planar as shown in FIG. 4, or may be patterned. As shown in FIG. 4, the buffer portion 2 and the seed portion 3 may be planar, or the buffer portion 2 and the seed portion 3 may be patterned. In FIGS. 3 and 4, a silicon substrate may be used for the main substrate 1, AlN may be used for the buffer portion 2, and a GaN-based semiconductor may be used for the seed portion 3.

[0030] 5 is a cross-sectional view showing another configuration of the semiconductor substrate according to the present embodiment, in which the first wing portion F1 may be divided into a plurality of parts PA arranged in a second direction X2 perpendicular to the first direction X1.

[0031] Fig. 6 is a cross-sectional view showing another configuration of the semiconductor substrate according to this embodiment. Fig. 7 is a plan view showing another configuration of the semiconductor substrate according to this embodiment. As shown in Figs. 6 and 7, the semiconductor substrate 10 may include an upper layer portion 9 located above the first semiconductor portion 8A and including an active layer and a p-type layer. An anode EA and a cathode EC may be provided on the upper layer portion 9.

[0032] 8 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to this embodiment. FIG. 9 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. As shown in FIGS. 8 and 9 , the method for manufacturing a semiconductor substrate according to this embodiment includes the steps of: preparing a template substrate TS including a growth-inhibited region DA (mask portion 5) and a first seed portion S1 (a first opening K1 exposing the seed portion 3) aligned in a first direction X1; forming a first protrusion R1 extending from the first seed region S1 to a position above the growth-inhibited region DA (the upper surface 5T of the mask portion 5) and including a nitride semiconductor; forming a growth-inhibiting film 7 in contact with the first protrusion R1; and forming a first base B1 located above the first protrusion R1 and a first wing F1 connected to the first base B1, separated from the growth-inhibited region DA (mask portion 5), and positioned above the gap JD, each of which includes a nitride semiconductor.

[0033] The first base portion B1 and the first wing portion F1 may be formed using a corner RC where the top surface RT and side surface RS of the first protrusion R1 intersect as a growth starting point PG. As described above, the first base portion B1 and the first wing portion F1 may be formed using the corner RC as the growth starting point PG, but this is not limitative. There is no problem in forming a defect portion (e.g., a minute opening) in the growth inhibiting film 7 and using the defect portion of the growth inhibiting film 7 as the growth starting point for the first base portion B1 and the first wing portion F1.

[0034] The first protrusion R1, the growth suppression film 7, the first base B1, and the first wing F1 may be successively formed using an MOCVD apparatus. The first protrusion R1 may include a GaN-based semiconductor, the growth suppression film 7 may be silicon nitride, and the first protrusion R1 may be formed by supplying a gallium source material and a nitrogen source material. The growth suppression film 7 may be formed by supplying a silicon-based material while stopping the supply of the gallium source material and continuing the supply of the nitrogen source material. The first base B1 and the first wing F1 may include a GaN-based semiconductor, and the first base B1 and the first wing F1 may be formed by supplying a gallium source material while stopping the supply of the silicon-based material and continuing the supply of the nitrogen source material. Alternatively, the supply of a small amount of silicon-based material may be continued at a doping level.

[0035] The growth of the first wing portion F1 and the second wing portion F2 may be stopped before the first wing portion F1 and the second wing portion F2 growing in a direction toward the first wing portion F1 meet. The template substrate TS has a seed portion 3 including a first seed region S1, and the seed portion 3 may be formed by a sputtering method.

[0036] Fig. 10 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 in Fig. 9, an apparatus M45 that performs steps S20, S30, and S40 in Fig. 9, and a control device MC that controls the apparatus M10 and the apparatus M45. The apparatus M45 may be an MOCVD apparatus.

[0037] Example 1 As the main substrate 1, a silicon substrate, a silicon carbide substrate (4H-SiC, 6H-SiC substrate), a sapphire substrate, a nitride substrate (GaN, AlN substrate, etc.), a ScMgAlO substrate, etc. can be used.

[0038] The seed portion 3 is formed above the main substrate 1 and serves as a starting point for growing the semiconductor portion 8. The seed portion 3 only needs to be formed in at least a part of the opening K (of the mask pattern 6), and may be planar or patterned (for example, striped). The seed portion 3 may be formed from a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). The thickness of the seed portion 3 is approximately 10 nm to 500 nm.

[0039] A buffer section 2 may be formed between the main substrate 1 and the seed section 3 (e.g., a GaN layer), and the buffer section 2 improves the crystallinity and flatness of the seed section 3. The buffer section 2 may be planar or may have a pattern (e.g., stripe shape) that matches the seed section 3. The buffer section 2 may be made of a GaN layer, an AlN layer, an AlGaN layer, an AlInN layer, AlGaInN, Al, or the like formed at a low temperature (500°C or less). The thickness of the buffer section 2 is approximately 10 nm to 500 nm. When a silicon substrate is used for the main substrate 1, it is desirable that the buffer section 2 in contact with the silicon substrate does not contain gallium in order to suppress meltback.

[0040] The layer between the main substrate 1 and the semiconductor portion 8 may be referred to as an underlayer (including at least one of the buffer portion 2 and the seed portion 3). A GaN layer may be formed as the underlayer (e.g., the seed portion 3) by sputtering. In this case, for example, a sputtering target containing gallium nitride as the main component (containing 25 atm% or more of gallium) and having an oxygen content of 5 atm% or less may be used, and the sputtering gas pressure may be set to less than 0.3 Pa. The sputtering method may be selected appropriately from DC sputtering, RF sputtering, AC sputtering, DC magnetron sputtering, ECR (Electron Cyclotron Resonance) sputtering, RF magnetron sputtering, PSD (Pulse Sputter Deposition), Laser Ablation, and the like.

[0041] The sputtering target used may have an oxygen content of 5 atm% or less, 3 atm% or less, or 1 atm% or less in order to improve the crystallinity of the entire film. The purity is also preferably as high as possible, and the metal impurity content may be less than 0.1% or less than 0.01%. When forming a GaN layer by sputtering, using a gallium nitride target with a low oxygen content can provide effects such as improved surface flatness, improved crystallinity, and suppression of surface hillocks (protrusions).

[0042] When a nitride semiconductor (AlN, GaN, etc.) is formed by sputtering as the underlayer, the degree of vacuum in the apparatus before film formation is set to 3×10 －５ Pa or less or 1 x 10 －５ The pressure may be set to Pa or less. Prior to film formation, a base substrate (such as a main substrate or a main substrate with a buffer) may be pretreated to remove organic layers or irregularities on the surface of the base substrate, thereby enabling epitaxial growth. Specific examples of pretreatment include reverse sputtering, acid treatment, and UV treatment, but reverse sputtering is preferable from the viewpoint of preventing re-adhesion of impurities after treatment. Reverse sputtering is a method of cleaning the surface of the base substrate by bombarding plasmatized atoms with the base substrate. The substrate temperature during film formation may be room temperature, but film quality can be further improved by heating the substrate (for example, at 400° to 1000°).

[0043] The power density during discharge is 5 W / cm ２ or less than 1.5 W / cm ２ The lower limit of the power density is 0.1 W / cm ２ or 0.3 W / cm ２ The power density is the power applied during discharge divided by the area of ​​the sputtering target. If the power density is too high, the raw material may be sputtered from the target in a clustered state.

[0044] In Example 1, a GaN underlayer (e.g., a seed portion) was formed by RF sputtering. A gallium nitride target (oxygen content: 0.4 atom%) was used, the film formation pressure was set to 0.1 Pa, and 20 to 40 sccm of nitrogen gas was introduced. Although argon gas was not used in Example 1, argon gas may of course be introduced. The discharge density was 125 W / cm. ２ The film formation temperature was room temperature.

[0045] When the underlayer (including at least one of the buffer portion 2 and the seed portion 3) is formed using a sputtering method, a laser ablation method, or the like, the internal stress can be controlled from compressive stress to tensile stress depending on the film formation conditions, and therefore the stress on the semiconductor portion 8 can be controlled. The internal stress can also be controlled by the amount of argon taken into the underlayer. The stress on the semiconductor portion 8 may be controlled by locally (pattern-wise) forming the underlayer on the undersubstrate.

[0046] The mask pattern 6 is formed on the base substrate using a material that suppresses vertical growth (growth in the c-axis direction) of the nitride semiconductor and enables lateral growth (e.g., growth in the a-axis direction). The openings K (exposed portions of the seed portions 3) in the mask pattern 6 serve as the starting points for growth of the semiconductor portions 8. Examples of materials for the mask portions 5 of the mask pattern 6 include silicon nitride, silicon carbide, silicon carbonitride, diamond-like carbon, silicon oxide, silicon oxynitride, etc., as well as silicon-free materials such as titanium nitride, molybdenum nitride, tungsten nitride, and tantalum carbide, as well as high-melting-point metals (molybdenum, tungsten, platinum, etc.). The mask portions 5 may be a single-layer film made of one of these materials or a multilayer film made up of a combination of multiple materials. The thickness of the mask portions 5 may be approximately 5 nm to 2 μm.

[0047] 11 is a cross-sectional view showing the configuration of a semiconductor substrate according to Example 1. In Example 1, a silicon substrate is used as the main substrate 1, and an AlN layer serving as a seed portion 3 is formed on a portion of the main substrate. By forming an Al layer of about 1 to 5 nm as a buffer portion 2 between the seed portion 3 (AlN layer) and the main substrate 1 (silicon substrate), the crystallinity of the seed portion 3 (AlN layer) can be improved.

[0048] A mask pattern 6 having a first opening K1 is formed on the seed portion 3. A raised portion R is formed from the opening K. The surface of the raised portion R is elevated by H1 from the upper surface 5T of the mask portion 5. From the viewpoint of ensuring the crystallinity and surface flatness of the semiconductor portion 8, the height H1 may be 0 < H1 < 8 μm or 0.2 μm < H1 < 4 μm. The raised portion R is formed into a convex shape having a top surface RT and a side surface RS. The top surface RT may be a c-plane, and the side surface RS may be a (11-22) plane or a (11-20) plane, or a plane angled between the (11-22) plane and the (11-20) plane. The raised portion R may have a corner RC formed by the top surface RT and the side surface RS. A growth suppression film 7 having a thickness of approximately 0.1 nm to 10 nm is formed on the semiconductor substrate 10 so as to contact the raised portion R. In Example 1, SiN is used for the growth suppression film 7. Depending on the film formation conditions, SiON, SiGaO, or SiGaON may be used as the growth inhibiting film 7. The growth inhibiting film 7 may have a uniform shape within the surface, or may have a shape with partial defects (holes or being significantly thinner than the surrounding area). It is sufficient for the growth inhibiting film 7 to suppress the formation of the semiconductor portion 8 even if only slightly.

[0049] The base B and wing portions F are formed above the growth suppression film 7 on the protrusion R and are completely separated from the mask portion 5. The wing portions F of the semiconductor portion 8 have a defect density two orders of magnitude lower than the base portion B on the opening K and good crystallinity, making them suitable for forming the active region of the upper layer (device layer). The wing portions F are regions from the upper surface edge of the protrusion R to the edge of the semiconductor portion 8, and this region may be used as the device region. Because the back surface of the wing portions F is separated from the mask portion 5, the formation of the wing portions F can be performed without being affected by the mask portion 5. In Example 1, adjacent semiconductor portions 8 are separated and do not meet, which effectively relieves stress from the main substrate 1 and seed portion 3, which are made of materials different from the semiconductor portions 8. This makes it possible to suppress cracking and ensure the surface flatness of the semiconductor portions 8. Adjacent semiconductor portions 8 can also be made to meet each other.

[0050] In Example 1, the width of the opening K was 5 μm, the width of the mask portion 5 was 50 μm, the pitch width RP of the raised portions R was 55 μm, and the height H1 of the raised portions R was 1.5 μm. The back surface of the semiconductor portion 8 was the same height as the top surface RT of the raised portions R, and the thickness (height) of the gap JD was 1.5 μm. Furthermore, the growth of the semiconductor portion 8 was stopped so that the width of the gap GP between adjacent semiconductor portions 8 was 10 μm.

[0051] 12 is a cross-sectional view showing another configuration of the semiconductor substrate of Example 1. After the semiconductor portion 8 is formed, an upper layer portion 9 (device layer) is formed on the semiconductor portion 8. Specifically, a stacked structure of an LED, laser, PD, power device, etc. can be formed using MOCVD, MBE, sputtering, etc. At least a portion of the active region of the upper layer portion 9 may be formed on the wing portion F (device region), and in Example 1, the entire active region is formed on the wing portion F. An electrode ET (anode, cathode, gate, etc.) may be provided on the upper layer portion 9.

[0052] 13 and 14 are cross-sectional views showing a method for manufacturing a semiconductor substrate according to Example 1. As shown in FIG. 13 , an AlN layer serving as a seed portion 3 is formed on a main substrate 1 (silicon substrate) by sputtering to a thickness of 100 nm. Next, a mask layer MF (e.g., SiN) having a thickness of 10 nm is formed on the seed portion 3 (AlN layer) by sputtering. Next, a resist Z applied to the mask layer MF is patterned into stripes using a typical photolithography method. After that, openings K and mask portions 5 are formed in the mask layer MF by dry etching (e.g., ICP (Ion Coupled Plasma), etc.), exposing the seed portion 3 (AlN layer). The resist Z is then removed to create a template substrate TS.

[0053] After the template substrate TS is transferred to the MOCVD apparatus, the first step of film formation for ELO is performed, as shown in Fig. 14. This forms raised portions R (first raised portion R1 and second raised portion R2). The film formation conditions were a film formation temperature of 1100°C, an ammonia flow rate of 7.5 slm, and a TMG (trimethylgallium) flow rate of 5 sccm.

[0054] The protrusion R needs only to exceed the upper surface of the mask portion 5, and may protrude slightly laterally from the opening K or may be contained within the opening K. In Fig. 14, the growth of the protrusion R was stopped when the film thickness reached 1.5 µm and the protrusion protruded slightly laterally from the edge of the opening.

[0055] Next, the film formation temperature was lowered by about 150° C. from the initial growth temperature, the supply of TMG was stopped, and SiH ４ (Silane): Flow rate 400 sccm, and ammonia (NH ３ ): A flow rate of 7.5 slm is supplied to deposit a thin SiN layer (about 1 nm thick). As a result, a growth suppression film 7 is formed on the side surface RS and the top surface RT of the protrusion R.

[0056] Next, the film formation temperature is raised to 250° C., and TMG and ammonia are supplied again to form the semiconductor portion 8. At this time, it was found that the growth suppression film 7 significantly affects the film formation of the semiconductor portion 8, and wing portions F are formed on the protrusions R in a state where they are floating above the mask portion 5. In other words, the back surface of the wing portions F of the semiconductor portion 8 is completely separated from the mask portion 5.

[0057] It was found that the protrusion R has a convex shape and has a top surface RT and side surfaces RS, as well as a corner RC, which are planes with different crystal orientations, so that growth on the side surfaces RS of the protrusion R is more effectively suppressed than on the top surface RT. This unique crystal growth is a new discovery by the inventors. The fact that the top surface RT of the protrusion R is a c-plane (polar plane) and the side surfaces RS are semi-polar planes "(11-22) plane, etc." or non-polar planes "(11-20) plane, etc." affects the formation state of the growth suppression film 7 and the crystal growth state of the semiconductor portion 8, and as a result, it is thought that the semiconductor portion 8 is formed preferentially on the top surface RT.

[0058] FIG. 15 is a cross-sectional view showing another configuration of the semiconductor substrate of Example 1. In FIG. 11 , the height of the back surface of the semiconductor portion 8 is formed at approximately the same height as the upper surface RT of the protrusion R. However, in FIG. 15 , the height of the semiconductor portion 8 is lowered to a position below the upper surface of the protrusion R, and the semiconductor portion 8 is formed. This can be selected by controlling the film formation conditions of the semiconductor portion 8 and the growth suppression film 7 (film formation temperature, film formation time, gas flow rate, etc.). In either case, the effects of Example 1 can be obtained. In FIG. 15 , the height H1 of the protrusion R is 1.5 μm, but the back surface of the semiconductor portion 8 is formed at a position 100 nm lower than the height of the upper surface RT of the protrusion R, resulting in a thickness (height) of the gap JD of 1.4 μm.

[0059] From Example 1, it was found that forming the wing portion F without interference from the main substrate 1, the seed portion 3, and the mask portion 5 is very effective in suppressing misalignment of the crystal axis of the wing portion F. In other words, in order to suppress misalignment of the crystal axis, the wing portion F may be completely separated from the mask portion 5. In this case, it is preferable that the wing portion F be in contact only with the raised portion R, the growth suppression film 7, and the base portion B.

[0060] Fig. 16 is a graph showing the results of XRD scan measurement in the comparative example. Fig. 17 is a graph showing the results of XRD scan measurement in Example 1. Figs. 16 and 17 show the results of measurement of the (002) plane, with the X-ray incident direction being <11-20>. In Example 1, a 1.5 μm GaN layer was used for the seed portion 3, and a 200 nm AlN layer was used for the buffer portion 2. In the comparative example, the same buffer portion and seed portion as in Example 1 were used, and the ELO layer was formed so as to contact the mask portion.

[0061] In Figure 16, three peaks are observed. The central peak is the peak of the GaN layer (base) on the seed portion, and the crystal axis of the c-plane is nearly perpendicular to the surface of the mask portion. The remaining two peaks are peaks of the GaN layer in the wing portion, and a Δ (peak angle difference) of 0.8 degrees was observed. This means that the c-axes of the two wing portions on both sides of the base portion are grown with a deviation of approximately 0.4° from the center to opposite sides, indicating poor flatness of the semiconductor portion 8. In contrast, in Figure 17 of Example 1, the peaks are not separated, and there is essentially one peak. This indicates that the crystal axes of the two wing portions F on both sides of the base portion B are aligned, and the deviation is very small.

[0062] 17 is a very good result for a semiconductor portion 8 having wide wing portions F. It is believed that at least one of the fact that the back surface of the wing portions F of the semiconductor portion 8 is separated from the mask portion 5 and the fact that the semiconductor portion 8 is in contact only with the raised portion R contributes to suppressing misalignment of the crystal axes of the two wing portions F on both sides of the base portion B. In Example 1, it was also found that indium (In) was incorporated uniformly on the surface of the semiconductor portion 8 during the formation of the upper layer portion 9, which improved, for example, the yield and luminous efficiency of the light-emitting element.

[0063] The growth suppression film 7 in contact with the raised portion R has an effect other than floating the semiconductor portion 8 above the mask portion 5. When a material different from that of the semiconductor portion 8 is used for at least one of the main substrate 1, seed portion 3, and buffer portion 2, stress may occur in the semiconductor portion 8 due to differences in thermal expansion coefficient and lattice constant. However, it has been found that by positioning the growth suppression film 7 between the raised portion R and the semiconductor portion 8, such stress is alleviated, significantly suppressing defects, cracks, etc. in the semiconductor portion 8. This effect is extremely important in terms of improving the quality and yield of the upper layer portion 9.

[0064] In Example 1, it was also found that the defect density in the base portion B and the wing portion F was significantly reduced. Depending on the formation state of the growth suppression film 7, as shown in FIG. 14 , the growth of the base portion B and the wing portion F can be initiated from the edges (corners RC) on both sides of the protrusion R, and the crystals growing from these edges (corners RC) toward the center can undergo a growth process in which they meet near the center of the upper surface of the protrusion R. This reduces the defect density in the base portion B (crystals on the protrusion R). By significantly reducing the defect density in the entire region of the semiconductor portion 8 (the entire width spanning the base portion B and the wing portions F), it becomes possible to form the active region of the upper layer portion 9 also in the base above the opening. This technique has not been known until now and is considered to be an extremely useful technology in industry.

[0065] In Example 1, the growth inhibiting film 7 was formed by supplying silane gas and ammonia gas, but other methods can also be used. For example, after the protrusion R has been formed, a silicon-containing coating (growth inhibiting film 7) can be formed in contact with the protrusion R by flowing only ammonia gas without flowing silane gas for several minutes, using residual silicon in the apparatus. Furthermore, after the protrusion R has been formed, the substrate can be temporarily removed from the MOCVD apparatus and the surface of the protrusion can be slightly oxidized to form the growth inhibiting film 7 containing silicon and oxygen. In Example 1, a silicon substrate was used as the main substrate 1, but a SiC substrate or a sapphire substrate can also be suitably used.

[0066] FIG. 18 is a plan view of a semiconductor substrate including an upper layer portion. FIG. 19 is a cross-sectional view of a semiconductor substrate including an upper layer portion. The upper layer portion 9 may be formed on the semiconductor portion 8 by changing the film formation conditions (e.g., by lowering the film formation temperature by about 100° C.) after stopping the growth of the semiconductor portion 8. The upper layer portion 9 may include at least one of a p-type layer, an n-type layer, and an electron blocking layer in addition to the active layer. Even when the upper layer portion 9 is formed on the semiconductor substrate 10, the backside transfer phenomenon, in which the upper layer material is supplied to the back side of the semiconductor portion 8, is significantly suppressed, and problems such as light absorption caused by the backside transfer phenomenon are also eliminated.

[0067] In the semiconductor substrate 10 shown in FIGS. 18 and 19 , the anode EA and cathode EC are formed above the wing portion F of the semiconductor portion 8. In a typical LED, the active region (light-emitting region) is directly below the anode EA, which is made of a transparent electrode such as ITO (indium tin oxide). In Example 1, the backlighting phenomenon is suppressed, eliminating the problem of light emitted from the active region being absorbed by the back surface of the wing portion F. At least a portion of the anode EA may be located above the wing portion F, or the entire anode EA may be located above the wing portion F. Because the area directly below the cathode EC is not generally an active region, the cathode EC may be formed above the base portion B. In FIGS. 18 and 19 , the anode EA and cathode EC are formed above the same wing portion F, but this is not limiting. As shown in FIGS. 6 and 7 , the anode EA may be formed above one of two wing portions F facing each other across the base portion B, and the cathode EC may be formed above the other.

[0068] In conventional ELO methods, cracks can occur in the semiconductor layer due to differences in the thermal expansion coefficients of the heterogeneous substrate and the semiconductor layer. In contrast, in Example 1, the semiconductor portion 8 is located above the gap and physically separated from the mask portion 5. The bond between the protrusion R and the semiconductor portion 8 is weak due to the growth suppression film 7. Adjacent semiconductor portions 8 do not meet (there is a gap GP). These three features effectively alleviate internal stress and suppress the occurrence of cracks, even when using a heterogeneous substrate (e.g., a Si substrate or a SiC substrate). Furthermore, by widening the width of the wing portion F (e.g., to 7 μm or more), stress can be alleviated by the wing portion F.

[0069] FIG. 20 is a plan view showing the element isolation method in Example 1. FIG. 21 is a cross-sectional view showing the element isolation method in Example 1. As shown in FIGS. 20 and 21 , the element body 20 (including the wing portion F, the upper layer portion 9, the anode EA, and the cathode EC) is separated from the template substrate. Because there is a gap JD below the wing portion F, by applying downward pressure to the element body 20 with an adhesive pressing body YS (adhesive plate, adhesive sheet, etc.), the base portion of the element body 20 (the connection portion with the template substrate TS) easily cracks, and the element body 20 is separated from the template substrate TS. Specifically, the element body 20 is peeled off from the template substrate TS while being held by the pressing body YS. In this way, the gap JD functions effectively in element isolation, allowing the element body 20 to be peeled off without damaging the element body 20.

[0070] Specific examples of the element 20 include a light emitting diode (LED), a semiconductor laser, a Schottky diode, a photodiode, and a transistor (including a power transistor and a high electron mobility transistor).

[0071] 22 is a schematic diagram showing the configuration of an electronic device according to Example 1. The electronic device 30 includes an element assembly 20, a drive substrate 23 on which the element assembly 20 is mounted, and a control circuit 25 that controls the drive substrate 23. The control circuit 25 may include a processor. Examples of the electronic device 30 include a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a lighting device, a communication device, an information processing device, a sensing device, and a power control device.

[0072] In Figure 22, the element body 20 is bonded and electrically connected to the drive substrate 23 in a state where it has been peeled off from the template substrate TS, but it may also be bonded and electrically connected to the drive substrate 23 in an unpeeled state (the template substrate TS and the element body 20 thereon).

[0073] 23 is a cross-sectional view showing the configuration of a semiconductor substrate of Example 2. In Example 2, the seed layer 3 does not cover the entire surface of the main substrate 1, but is striped. An opening K of the mask pattern 6 exists on the seed portion 3 (AlN layer). In Example 2, the width of the opening K is slightly narrower than that of the seed portion 3, and the AlN layer (seed portion 3) is located below the opening K across the entire width of the opening K. Therefore, the raised portion R, which is a GaN layer, and the silicon substrate, which is the main substrate 1, are spatially separated by the AlN layer, and meltback of Ga and silicon is suppressed.

[0074] By using a buffer layer locally, stress from the buffer layer can be alleviated. By forming the semiconductor portion 8 and the growth suppression film 7 by the method shown in Example 1, the wing portion F is completely separated from the mask portion 5, and the wing portion F is in contact only with the raised portion R, and the deviation of the crystal axis of the wing portion F can be suppressed to the same level as in Example 1. In Example 2, a silicon substrate was used for the main substrate 1, but a SiC substrate or a sapphire substrate can also be said to be suitable for the main substrate 1.

[0075] Example 3 In Example 3, the semiconductor substrate shown in Figure 4 was fabricated. In Example 3, a GaN layer was formed as the seed portion 3 on the AlN layer that constituted the buffer portion 2. The GaN layer that constituted the seed portion 3 was deposited, for example, by sputtering. By depositing the semiconductor portion 8 and the growth suppression film 7 using the method shown in Example 1, the wing portion F was completely separated from the mask portion 5, and the wing portion F was in contact only with the raised portion R, allowing the misalignment of the crystal axis of the wing portion F to be suppressed to the same level as in Example 1. While a silicon substrate was used for the main substrate 1 in Example 2, a SiC substrate or a sapphire substrate may also be suitable for the main substrate 1.

[0076] 24 is a cross-sectional image showing the configuration of a semiconductor substrate of Example 4. In the semiconductor substrate 10 shown in FIG. 24, the width Ws (length in the first direction) of the first semiconductor portion 8A is 50.9 [μm], the thickness of the gap JD is 347 [nm], the thickness of the first wing portion F1 is 3.52 [μm], and the opening width (seed region width) is 3.13 [μm]. The threading dislocation density of each of the first base portion B1 and the first wing portion F1 is 5×10 ６[pcs / cm ２ The overall width Ws (length in the first direction) of the first semiconductor portion 8A may be 5 times or more, 10 times or more, 20 times or more, or 50 times or more the thickness of the first wing portion F1.

[0077] Fifth Embodiment FIG. 25 is a plan view illustrating the configuration of a semiconductor substrate according to a fifth embodiment. FIG. 26 is a cross-sectional view illustrating the configuration of a semiconductor substrate according to a fifth embodiment. As shown in FIGS. 25 and 26 , a semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth-inhibiting region (non-seed portion) DA aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS. The first semiconductor portion 8A includes a first protrusion R1 extending from the first seed region S1 to a position above the growth-inhibiting region DA, a growth-inhibiting film 7 in contact with the first protrusion R1, a first base B1 positioned above the first protrusion R1, and a first wing portion F1 connected to the first base B1, separated from the growth-inhibiting region DA, and positioned above the gap JD. The first wing portion F1 may include a wing end (edge) E1 positioned above the growth-inhibiting region DA. This configuration can improve the flatness of the first wing portion F1.

[0078] The first semiconductor portion 8A may have a protrusion R1 formed in a mesa shape on the first seed region S1 and connected to the first base portion B1. The growth inhibiting film 7 may be in contact with the side and top surfaces of the protrusion R1 and may be located on the growth inhibiting region DA.

[0079] In the semiconductor substrate 10, the template substrate TS includes a main substrate 1 and an underlayer 4, and the underlayer 4 may be unmodified in the first seed region S1 and modified in the growth inhibition region DA. The gap JD may have a ratio of its width in the first direction X1 to its thickness TJ (e.g., the thickness below the wing end E1) of 5.0 or more.

[0080] 27 is a cross-sectional view showing a method for manufacturing a semiconductor substrate, which includes the steps of preparing a template substrate TS including a first seed region S1 and a growth inhibition region DA, forming a raised portion R1 from the first region S1 above the template substrate TS, forming a growth inhibition film 7 in contact with the raised portion R1, and forming a first base portion B1 located above the raised portion R1 and a first wing portion F1 connected to the first base portion B1, separated from the growth inhibition region DA, and located above the gap JD.

[0081] 27 , the first base portion B1 and the first wing portion F1 may be formed using the corner portion RC of the protrusion R1 as the growth starting point. While the corner portion RC may be used as the growth starting point in this manner, this is not limitative. Alternatively, a defect (e.g., a minute opening) may be formed in the growth inhibiting film 7 on the first protrusion R1, and the defect in the growth inhibiting film 7 may be used as the growth starting point for the first base portion B1 and the first wing portion F1.

[0082] The protrusion R1, the growth suppression film 7, the first base B1, and the first wing F1 may be successively formed using an MOCVD apparatus. The first protrusion R1 includes a GaN-based semiconductor, the growth suppression film 7 is silicon nitride, and a gallium source material (organic material such as trimethylgallium (TMG) or triethylgallium (TEG)) and a nitrogen source material (ammonia gas (NH ３ )) to form the first protrusion R1, and while maintaining the supply of the raw material that serves as the nitrogen source, the supply of the raw material that serves as the gallium source is stopped to supply a silicon-based material (e.g., SiH ４ The growth suppression film 7 may be formed by supplying a silicon-based material to the first base portion B1 and the first wing portion F1. The first base portion B1 and the first wing portion F1 may contain a GaN-based semiconductor, and the supply of the silicon-based material may be stopped and a gallium-based material may be supplied while maintaining the supply of the nitrogen-based material. Alternatively, the supply of a small amount of silicon-based material may be continued at a doping level.

[0083] By forming the growth suppression film 7 in this manner, continuous film formation can be performed without removing the substrate from the MOCVD apparatus while forming the void DJ below the wing portion F, thereby reducing the manufacturing time and manufacturing costs. By forming the void DJ and forming the wing portion F so that it does not come into contact with the underlayer 4 (growth suppression region DA), stresses and the like applied to the semiconductor portion 8 from the main substrate 1 and the underlayer 4 can be effectively alleviated.

[0084] 28 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in Fig. 28, the template substrate TS of Fig. 26 may be obtained by performing the steps of forming an underlayer 4 containing an underlayer material, depositing a resist RZ on the underlayer 4, patterning the resist RZ, subjecting the exposed underlayer material to plasma processing, and removing the resist RZ. The underlayer 4 may be formed by sputtering.

[0085] In the plasma treatment, for example, argon plasma is irradiated onto the exposed surface 4D of the underlayer 4 to modify the surface of the irradiated region, thereby forming a growth-inhibited region DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, or the like into the chamber, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture of these plasmas in addition to argon plasma. As a result, the growth-inhibited region DA may contain argon, oxygen, nitrogen, or the like as impurities. In such a case, the underlayer material may be aluminum nitride, and the growth-inhibited region DA may be aluminum oxynitride. Alternatively, the underlayer material may be AlScN (aluminum scandium nitride), and the growth-inhibited region DA may be AlScON (aluminum scandium oxynitride).

[0086] 29 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in FIG. 29 , the following steps may be performed: patterning a resist RZ on an underlayer 4 (e.g., an AlN layer); forming a coating CM (e.g., a silicon nitride film of approximately 10 nm) covering the underlayer 4 and the resist RZ; removing the resist RZ (lift-off patterning the coating CM); annealing the coating CM and the underlayer 4 (e.g., heat treatment at 1000°C); and removing the coating CM (e.g., removing the silicon nitride film using BHF). In this way, interdiffusion between the coating CM and the underlayer 4 during annealing can form a growth suppression region DA located below the coating CM on the surface of the underlayer 4. Note that by forming the coating CM by sputtering, surface modification below the coating CM can be performed without annealing. The underlayer material may be AlScN, ScN, ZnO, CrN, or the like, containing a different material (e.g., a metal element other than Group III elements) such as Sc (scandium), Zn, or Cr. The underlayer 4 may have a single-layer structure or a multilayer structure, or may have a multilayer structure including a periodic structure.

[0087] FIG. 30 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in FIG. 30 , the process may include patterning a resist RZ on an underlayer 4 (e.g., an AlN layer), implanting impurity ions into the exposed underlayer material, and removing the resist RZ. Examples of impurities include silicon (Si), iron (Fe), and magnesium (Mg). The implantation process involves implanting impurity ions into the exposed surface 4D of the underlayer 4 to modify the surface and form a growth suppression region DA. The underlayer material may be AlScN, ScN, ZnO, CrN, or the like, containing a heterogeneous material (e.g., a metal element other than Group III) such as Sc (scandium), Zn, or Cr. The underlayer 4 may have a single-layer structure or a multilayer structure. It may also have a multilayer structure including a periodic structure.

[0088] Sixth Embodiment FIGS. 31 and 32 are cross-sectional views illustrating the configuration of a semiconductor substrate according to a sixth embodiment. As shown in FIGS. 31 and 32 , a semiconductor substrate 10 includes a template substrate TS including a first seed region S1 and a growth-inhibiting region (non-seed portion) DA aligned in a first direction X1, and a first semiconductor portion 8A positioned above the template substrate TS. The first semiconductor portion 8A includes a first protrusion R1 extending from the first seed region S1 to a position above the growth-inhibiting region DA, a growth-inhibiting film 7 in contact with the first protrusion R1, a first base B1 positioned above the first protrusion R1, and a first wing portion F1 connected to the first base B1, separated from the growth-inhibiting region DA, and positioned above a gap JD. The first wing portion F1 may include a wing end E1 positioned above the growth-inhibiting region DA. This configuration enhances the flatness of the first wing portion F1.

[0089] 31 includes a main substrate 1, a buffer layer 2, and a seed portion 3, and the buffer layer 2 may be a growth suppression layer (a layer that suppresses the growth of nitride semiconductor crystals). The buffer layer 2 may include at least one of a 4H—SiC layer, a 6H—SiC layer, a 3C—SiC layer, a sapphire layer, a diamond layer, and a ScAlMgO layer. A seed portion 3 (e.g., AlN) including a first seed region S1 is locally formed on the buffer layer 2, and the region of the buffer layer 2 that does not overlap with the seed portion 3 functions as a growth suppression region DA. A Si substrate, a SiC substrate, a sapphire substrate, or the like can be used for the main substrate 1.

[0090] 32 includes a main substrate 1 and a seed portion 3. The main substrate 1 may be a growth-inhibiting substrate (a substrate that inhibits the growth of nitride semiconductor crystals) such as a 3C-SiC substrate, and may be, for example, a 4H-SiC substrate, a 6H-SiC substrate, a 3C-SiC substrate, a sapphire substrate, a diamond substrate, or a ScAlMgO substrate. A seed portion 3 (e.g., AlN) including a first seed region S1 is locally formed on the main substrate 1, and a region of the upper surface of the main substrate 1 that does not overlap with the seed portion 3 functions as a growth-inhibiting region DA.

[0091] Seventh Embodiment FIG. 33 is a flowchart illustrating a method for manufacturing a semiconductor device according to a seventh embodiment. FIG. 34 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a seventh embodiment. As illustrated in FIGS. 33 and 34 , a semiconductor body 20 (semiconductor device) or a semiconductor device 21 including the semiconductor body 20 and the transfer substrate PS can be obtained by performing steps S60 of preparing a semiconductor substrate 10, S70 of forming an upper layer portion 9 above a first wing portion F1, and S80 of peeling the first wing F1 from the template substrate TS while the first wing portion F1 and the upper layer portion 9 are held on the transfer substrate PS. The upper layer portion 9 (functional layer) may be, for example, a nitride semiconductor layer (e.g., a GaN-based semiconductor layer) including an active layer, and the semiconductor devices (20 and 21) may include electrodes, insulating films, and the like located on the upper layer portion 9.

[0092] 34 , since the growth suppression film 7 is located on the raised portion R1, the bond between the raised portion R1 and the first wing portion F1 is weak, and the first wing portion F1 can be easily peeled off. The first wing F1 and the first base portion B1 may be peeled off from the template substrate TS by cleaving at the boundary between the first base portion B1 and the first raised portion R1.

[0093] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0094] REFERENCE SIGNS LIST 1 Main substrate 2 Buffer portion (buffer layer) 3 Seed portion 5 Mask portion 6 Mask pattern 7 Growth inhibition film 8A First semiconductor portion 8C Second semiconductor portion 10 Semiconductor substrate 20 Semiconductor device (element body) 25 Semiconductor device 50 Semiconductor substrate manufacturing apparatus DA Growth inhibition region R1 First raised portion R2 Second raised portion E1 Edge of first semiconductor portion B1 First base portion B2 Second base portion F1 First wing portion F2 Second wing portion JD Void S1 First seed region S2 Second seed region DA Growth inhibition region TS Template substrate

Claims

1. a template substrate including a first seed region and a non-seed region aligned in a first direction; and a first semiconductor portion located above the template substrate and including a nitride semiconductor; A semiconductor substrate, wherein the first semiconductor portion has a first raised portion extending upward from the first seed region, a growth inhibition film in contact with the first raised portion, a first base portion located above the first raised portion, and a first wing portion extending from the first base portion in the first direction and separated from the non-seed region.

2. The semiconductor substrate of claim 1 , wherein the first wing portion has a wing end located above the non-seed region.

3. The semiconductor substrate according to claim 2 , wherein the growth suppression film is a film having one or more openings.

4. The semiconductor substrate of claim 1 , wherein the first wing portion does not contact a side surface of the first raised portion.

5. The semiconductor substrate of claim 4 , wherein the first raised portion rises up to an edge of the non-seed region.

6. the template substrate has a mask portion that functions as the non-seed region and a first opening that does not have the mask portion; The semiconductor substrate of claim 1 , wherein the first opening overlaps the first seed region.

7. a second semiconductor portion located above the template substrate; the template substrate has a second seed region adjacent to the first seed region via the non-seed region; the second semiconductor portion has a second raised portion extending upward from the second seed region, a second base portion located above the second raised portion, and a second wing portion extending from the second base portion in the first direction and separated from the non-seed region; The semiconductor substrate according to claim 1 , wherein the first wing portion and the second wing portion are aligned in the first direction with a gap therebetween.

8. The semiconductor substrate according to claim 1 , wherein the growth inhibiting film is in contact with a side surface of the first protrusion.

9. The semiconductor substrate according to claim 8 , wherein the side surface is a tapered surface having an upward narrowing shape.

10. The semiconductor substrate of claim 9 , wherein the tapered surface meets a top surface of the non-seed region.

11. The semiconductor substrate according to claim 8 , wherein the growth inhibiting film is in contact with an upper surface of the first protrusion.

12. The semiconductor substrate according to claim 11 , wherein a portion of the growth inhibiting film that contacts an upper surface of the first protrusion is included within the first semiconductor portion.

13. The semiconductor wafer according to claim 8 , wherein the first raised portion has a growth starting point of a nitride semiconductor at a position above the non-seed region.

14. 14. The semiconductor substrate according to claim 13, wherein the growth starting point is not in contact with the growth inhibiting film or is in contact with a portion where the growth inhibiting film is locally thin.

15. The semiconductor substrate according to claim 13 , wherein a corner where an upper surface and a side surface of the first protrusion intersect is included in the growth origin.

16. The semiconductor substrate of claim 15 , wherein the corner is located above the non-seed region.

17. The semiconductor substrate of claim 2 , wherein the first base portion includes a void.

18. The semiconductor substrate according to claim 2 , wherein the growth suppression film is a silicon nitride film.

19. the first direction is a <11-20> direction, the top surface of the first protuberance is a polar surface; The semiconductor substrate according to claim 1 , wherein a side surface of the first protrusion is a semi-polar or non-polar surface.

20. The semiconductor substrate according to claim 1 , wherein the non-seed region and the first seed region each have a shape whose longitudinal direction is a second direction perpendicular to the first direction.

21. The semiconductor substrate according to claim 20 , wherein the first wing portion is separated into a plurality of parts aligned in the second direction.

22. The semiconductor substrate according to claim 1 , wherein the template substrate has a main substrate having a lattice constant different from that of the first semiconductor portion, and a seed portion including the first seed region.

23. 23. The semiconductor substrate according to claim 22, wherein the main substrate is a silicon substrate, a sapphire substrate or a silicon carbide substrate, and the nitride semiconductor is a GaN-based semiconductor.

24. The semiconductor substrate of claim 22 , wherein the seed portion is not disposed under the non-seed region.

25. The seed portion is doped with argon or oxygen as an impurity at 2×10 １８ / cm ３ The semiconductor substrate according to claim 22 , which is made of a nitride semiconductor containing the above.

26. 7. The semiconductor substrate according to claim 6, wherein the mask portion has a thickness of 50 nm or less.

27. The semiconductor substrate according to claim 6 , wherein the growth inhibiting film is thinner than the mask portion.

28. The semiconductor substrate according to claim 2 , wherein a deviation between the c-axis direction of the first base portion and the c-axis direction of the wing end is 0.2 degrees or less.

29. The semiconductor substrate according to claim 1 , further comprising an upper layer portion located above the first semiconductor portion and including an active layer and a p-type layer.

30. The threading dislocation density in the first base portion and the threading dislocation density in the first wing portion are each 5×10 ６ [pcs / cm ２ 2. The semiconductor substrate according to claim 1, wherein the surface area of ​​the semiconductor substrate is less than or equal to 100 nm.

31. The semiconductor substrate according to claim 1 , wherein the first semiconductor portion has two paired first wing portions extending from the first base portion in the first direction and in the opposite direction.

32. The template substrate includes a main substrate and an underlayer; In the first seed region, the underlayer is not modified; The semiconductor substrate of claim 1 , wherein the underlayer is modified in the non-seed region.

33. the template substrate has a buffer layer and a seed portion located locally on the buffer layer and including the first seed region; The semiconductor substrate according to claim 1 , wherein a region of the buffer layer that does not overlap with the seed portion functions as the non-seed region.

34. providing a template substrate including a non-seed region and a first seed region aligned in a first direction; forming a first raised portion extending upward from the first seed region and including a nitride semiconductor; forming a growth inhibiting film in contact with the first protrusion; forming a first base portion located above the first raised portion and a first wing portion extending from the first base portion in the first direction and separated from the non-seed region, each of the first wing portion including a nitride semiconductor.

35. The method for manufacturing a semiconductor substrate according to claim 34 , wherein the first base portion and the first wing portion are formed from a corner where an upper surface and a side surface of the first protrusion portion intersect as a growth starting point.

36. 35. The method for manufacturing a semiconductor substrate according to claim 34, wherein the first protrusion, the growth suppression film, the first base and the first wing are successively formed using an MOCVD apparatus.

37. the first protruding portion includes a GaN-based semiconductor; the growth suppression film is silicon nitride, forming the first protrusion by supplying a raw material serving as a gallium source and a raw material serving as a nitrogen source; 37. The method for manufacturing a semiconductor substrate according to claim 36, wherein the growth inhibiting film is formed by stopping the supply of the raw material to be the gallium source and supplying a silicon-based material while maintaining the supply of the raw material to be the nitrogen source.

38. the first base portion and the first wing portion include a GaN-based semiconductor; 38. The method for manufacturing a semiconductor substrate according to claim 37, wherein the first base and the first wing are formed by stopping the supply of the silicon-based material and supplying the raw material to be the gallium source while maintaining the supply of the raw material to be the nitrogen source.

39. the template substrate has a second seed region adjacent to the first seed region via the non-seed region; forming a second protuberance extending upward from the second seed region, a second base located above the second protuberance, and a second wing extending from the second base in the first direction and separated from the non-seed region, each of the second protuberance including a nitride semiconductor; 35. The method of claim 34, wherein growth of the first wing portion and the second wing portion is stopped before the first wing portion and the second wing portion growing in a direction toward the first wing portion meet.

40. the template substrate has a seed portion including the first seed region; The method for manufacturing a semiconductor substrate according to claim 34, wherein the seed portion is formed by a sputtering method.

41. A step of preparing a semiconductor substrate according to any one of claims 1 to 33; forming an upper layer portion above the first wing portion; and peeling the first wing portion from the template substrate while the first wing portion and the upper layer portion are held on a transfer substrate.

42. 42. The method of claim 41, further comprising: peeling the first wing portion from the template substrate by cleaving at a boundary between the first base portion and the first protrusion portion.