GaN substrate, nitride semiconductor device and method for manufacturing the same

Abstract

The present invention relates to a GaN substrate which has a main surface 1 having an inclination angle of 0 to 10° relative to (0001) crystal plane that is a Ga polar plane, and also has an Si-doped GaN layer on at least the surface of the main surface 1, in which the Si concentration in the Si-doped GaN layer is 1×1018 atoms / cm3 or more, and the total of bottom surface areas of concave defects on the surface of the Si-doped GaN layer is 15% or less relative to the total surface area of the surface of the Si-doped GaN layer.

Description

GaN substrate

[0001] The present invention relates to a gallium nitride (GaN) substrate.

[0002] The substrates used in currently commercially produced InGaN laser diodes (LDs) are conductive GaN substrates with a relatively high carrier concentration, and research and development of vertical GaN power devices using such conductive GaN substrates has been actively conducted in recent years.

[0003] Among GaN substrates used in laser diodes and vertical GaN power devices, n-type GaN substrates are conductive by doping the entire substrate with an n-type donor or by providing a doped layer in part of the substrate's layer structure. There is a demand for lower resistance in n-type GaN substrates, and many attempts have been made to increase the donor doping concentration in the doped layer. When fabricating devices, metal for the negative electrode is placed on the n-type GaN substrate. Because the higher the donor concentration, the better the ohmic contact between the metal and the semiconductor. Therefore, n-type GaN substrates with high carrier concentrations have long been desired. However, when attempting to obtain a high carrier concentration n-type GaN substrate by using, for example, a Ge-doped layer using Ge as the donor, pits are generated.

[0004] Therefore, Non-Patent Document 1 discloses a GaN substrate having a Si-doped GaN layer that employs Si as a donor and is doped with Si at a high concentration.

[0005] M. Iwinska et al., "Homoepitaxial growth of HVPE-GaN doped with Si", Journal of Crystal Growth, Vol. 456, pp. 91-96, 2016

[0006] However, Si is 10 １８ atoms / cm ３When doping is performed at a high concentration on the order of 10 ...

[0007] Furthermore, since the ionization energy of Si is small enough to ionize it sufficiently at room temperature, the activation rate should, in principle, be approximately 100%. However, it has been found that when Si is doped at a high concentration, as in Non-Patent Document 1, the doped carrier impurity Si does not function as an original carrier, and the activation rate tends to decrease. This is thought to be due to the fact that Si atoms do not enter their original Ga site positions, but instead enter, for example, interstitial sites or antisites (N sites).

[0008] Thus, there is a trade-off between increasing the Si concentration and the yield of device manufacturing. Furthermore, even if Si is doped at a high concentration, it is difficult to achieve a correspondingly low resistance, and further improvement is desired.

[0009] Therefore, an object of the present invention is to provide a GaN substrate that can achieve both low resistance and improvement of device yield degradation, as an aspect A. Another object of the present invention is to provide a GaN substrate that achieves low resistance commensurate with the doped Si concentration.

[0010] In addition, Si is 10 １８ atoms / cm ３ It was found that when doping is performed at a high concentration on the order of 1000 or more, the conductivity at the edge of the GaN substrate decreases, and semiconductor devices manufactured using this GaN substrate have high resistance on the negative electrode side.

[0011] Therefore, an object of the present invention, as aspect B, is to provide a GaN substrate in which low resistance corresponding to the doped Si concentration is realized uniformly over the entire substrate.

[0012] As a result of extensive research, the present inventors have found that narrowing the terrace width during epitaxial growth of Si-doped GaN crystals can suppress the occurrence of cissing and furthermore facilitate the appropriate incorporation of Si atoms into kink sites. This has led to the discovery that a GaN substrate that solves the above-mentioned problems can be obtained, and has led to the completion of Aspect A of the present invention.

[0013] Furthermore, the present inventors have conducted extensive research and found that the non-uniformity in resistance is due to the fact that Si doping is not uniform, and that Si cannot be effectively incorporated, particularly at the edge of the GaN substrate. Further research by the present inventors has revealed that a GaN substrate that solves the above-mentioned problems can be obtained by using vapor phase epitaxy to form the Si-doped GaN layer, narrowing the terrace width during this process, and setting the distance between the nozzle for ejecting the GaCl gas, which is the raw material, and the substrate surface in the reactor within a specific range, thereby completing Aspect B of the present invention.

[0014] That is, the gist of the present invention including the above-mentioned Aspect A and Aspect B is as follows: [1] A GaN substrate having a primary surface 1 tilted at an angle of 0 to 10 degrees from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the primary surface 1, wherein the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ a GaN substrate, wherein the total bottom area of ​​the concave defects on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer.

[0015] [2] A GaN substrate having a primary surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the primary surface 1, wherein the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ In the Si-doped GaN layer, the Si concentration is set to a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３) the value expressed by {(b / a)×100}(%) is 90% or more.

[0016] [3] A GaN substrate having a primary surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the primary surface 1, wherein the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ The maximum Si concentration at the surface of the Si-doped GaN layer is α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ ), the value expressed by [{(α-β) / α}×100] (%) is 10% or less.

[0017] [4] The GaN substrate according to any one of [1] to [3], wherein the thickness of the Si-doped GaN layer is 50 μm or more. [5] The GaN substrate according to any one of [1] to [4], wherein the total bottom area of ​​recesses having a depth of 5 μm or more on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer. [6] The GaN substrate according to any one of [1] to [5], wherein the surface of the Si-doped GaN layer has one or more 5 mm x 5 mm square lattices that are free of concave defects. [7] The GaN substrate according to any one of [1] to [6], wherein the surface of the Si-doped GaN layer has one or more 5 mm x 5 mm square lattices that are free of concave defects. [8] The GaN substrate according to any one of [1] to [6], wherein the surface of the Si-doped GaN layer has one or more 5 mm x 5 mm square lattices that are free of concave defects. [9] The GaN substrate according to any one of [1] to [6], wherein the resistivity of the Si-doped GaN layer at 300 K is 1×10 －２ [9] The GaN substrate according to any one of [1] to [7], wherein the resistivity of the Si-doped GaN layer at 300 K is 8×10 Ωcm or less. －３

[10] The GaN substrate according to any one of [1] to [8], wherein the resistivity of the Si-doped GaN layer at 300 K is 4×10 －３

[11] The GaN substrate according to any one of [1] to [9], wherein the Si concentration of the Si-doped GaN layer is 5×10 １８ atoms / cm ３

[12] The GaN substrate according to any one of [1] to

[10] , wherein the Si concentration of the Si-doped GaN layer is 9×10 or more. １８ atoms / cm ３

[13] The GaN substrate according to any one of [1] to

[12] , wherein the GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more.

[0018]

[14] A GaN substrate having a main surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the main surface 1, wherein the Si-doped GaN layer has a thickness of 50 μm or more, and the total bottom area of ​​recesses having a depth of 5 μm or more on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer.

[0019]

[15] A GaN substrate having a main surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the main surface 1, wherein the thickness of the Si-doped GaN layer is 50 μm or more, and the Si concentration in the Si-doped GaN layer is a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ) the value expressed by {(b / a)×100}(%) is 90% or more.

[0020]

[16] A GaN substrate having a primary surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the primary surface 1, wherein the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ the thickness of the Si-doped GaN layer is 50 μm or more, and the maximum Si concentration at the surface of the Si-doped GaN layer is α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ ), the value expressed by [{(α-β) / α}×100] (%) is 10% or less.

[0021] One embodiment of the above-mentioned Aspect A of the present invention is as follows: [1] A GaN substrate having a main surface 1 inclined at an angle of 0 to 10 degrees from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the main surface 1, wherein the thickness of the Si-doped GaN layer is 50 μm or more, and the total bottom area of ​​recesses having a depth of 5 μm or more on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer.

[0022] [2] A GaN substrate having a main surface 1 tilted at an angle of 0 to 10° from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer at least on the surface of the main surface 1, wherein the thickness of the Si-doped GaN layer is 50 μm or more, and the Si concentration in the Si-doped GaN layer is a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ) the value expressed by {(b / a)×100}(%) is 90% or more.

[0023] [3] The Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ [4] The GaN substrate according to any one of [1] to [3], wherein the surface of the Si-doped GaN layer has one or more 5 mm x 5 mm square lattices with no recesses of 5 μm or more in depth. [5] The resistivity of the Si-doped GaN layer at 300 K is 1×10 －２ [6] The GaN substrate according to any one of [1] to [4], wherein the resistivity of the Si-doped GaN layer at 300 K is 8×10 －３ [7] The GaN substrate according to any one of [1] to [5], wherein the resistivity of the Si-doped GaN layer at 300 K is 4×10 －３ [8] The GaN substrate according to any one of [1] to [6], wherein the Si concentration of the Si-doped GaN layer is 5×10 １８ atoms / cm ３[9] The GaN substrate according to any one of [1] to [7], wherein the Si concentration of the Si-doped GaN layer is 9×10 １８ atoms / cm ３

[10] The GaN substrate according to any one of [1] to [9], wherein the GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more.

[0024] One embodiment of the above-mentioned aspect B of the present invention is as follows: [1] A GaN substrate having a primary surface 1 tilted at an angle of 0 to 10 degrees from a (0001) crystal plane, which is a Ga polar plane, and having a Si-doped GaN layer on at least the surface of the primary surface 1, wherein the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ the thickness of the Si-doped GaN layer is 50 μm or more, and the maximum Si concentration at the surface of the Si-doped GaN layer is α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ [2] The GaN substrate according to [1], wherein the GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more. [3] The resistivity of the Si-doped GaN layer at 300 K is 1×10 －２ [4] The GaN substrate according to [1] or [2], wherein the resistivity of the Si-doped GaN layer at 300 K is 8×10 －３ [5] The GaN substrate according to any one of [1] to [3], wherein the resistivity of the Si-doped GaN layer at 300 K is 4×10 －３ [6] The GaN substrate according to any one of [1] to [4], wherein the Si concentration of the Si-doped GaN layer is 9×10 １８ atoms / cm ３ The GaN substrate according to any one of [1] to [5] above.

[0025] According to Aspect A of the present invention, it is possible to provide a GaN substrate that achieves low resistance while improving the deterioration of device yield. It is also possible to provide a GaN substrate that achieves low resistance commensurate with the doped Si concentration. Therefore, it is highly suitable as an n-type conductive GaN substrate for use in laser diodes and vertical GaN power devices.

[0026] Furthermore, according to Aspect B of the present invention, it is possible to provide a GaN substrate in which low resistance corresponding to the doped Si concentration is realized uniformly across the entire substrate, making it highly suitable as an n-type conductive GaN substrate for use in laser diodes and vertical GaN power devices.

[0027] Fig. 1 is a schematic cross-sectional view showing one embodiment of a GaN substrate according to the first to fourth embodiments. Fig. 2 is an explanatory diagram of the off-angle provided in the underlayer crystal used in the method for forming a Si-doped GaN layer, where Fig. 2(a) shows the underlayer crystal being cut obliquely with respect to the (0001) surface, Fig. 2(b) shows the underlayer crystal after cutting, and Fig. 2(c) is an enlarged view of the circled portion in Fig. 2(b). Fig. 3 shows a case where the off-angle of the (0001) surface of the underlayer crystal is larger than that in Fig. 2(c). Fig. 4 is a process cross-sectional view illustrating a method for manufacturing a first c-plane GaN wafer used in manufacturing a GaN substrate according to the first to fourth embodiments, in which Fig. 4(a) shows a seed wafer, Fig. 4(b) shows a state in which a first GaN thick film has been grown on the seed wafer, and Fig. 4(c) shows a state in which the obtained first GaN thick film has been thinned to obtain a plurality of first c-plane GaN wafers. Fig. 5 is a process cross-sectional view illustrating a method for manufacturing a second c-plane GaN wafer used in manufacturing a GaN substrate according to the first to fourth embodiments, in which Fig. 5(a) shows a state in which a first c-plane GaN wafer has been grown on the first c-plane GaN wafer, and Fig. 5(c) shows a state in which the obtained second GaN thick film has been thinned to obtain a second c-plane GaN wafer. 6A and 6B are cross-sectional views illustrating the steps of the GaN substrate manufacturing method according to the first to fourth embodiments, in which FIG. 6A shows the state of the second c-plane GaN wafer, and FIG. 6B shows the state of the Si-doped GaN layer grown on the second c-plane GaN wafer. FIG. 7 is a schematic diagram showing the basic configuration of an HVPE apparatus. FIG. 8 is a fluorescent image of the GaN substrate surface obtained in Example 1-1. FIG. 9 is a fluorescent image of the GaN substrate surface obtained in Comparative Example 1-1.

[0028] The present invention will be described in detail below, but the present invention is not limited to the following embodiments and can be practiced with various modifications within the scope of the gist. Furthermore, the use of "to" to indicate a range of numerical values ​​means that the numerical values ​​before and after it are included as the lower limit and upper limit.

[0029] [GaN Substrate (1)] One aspect of the GaN substrate according to the first embodiment has a primary surface 1 that is inclined at an angle of 0 to 10° from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer on at least the surface of the primary surface 1, and the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ The total bottom area of ​​the recesses on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer.

[0030] Another aspect of the GaN substrate according to the first embodiment has a primary surface 1 that is inclined at an angle of 0 to 10 degrees from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer at least on the surface of primary surface 1, the Si-doped GaN layer having a thickness of 50 μm or more. The total bottom area of ​​recesses having a depth of 5 μm or more on the surface of the Si-doped GaN layer is 15% or less of the total area of ​​the surface of the Si-doped GaN layer.

[0031] One aspect of the GaN substrate according to the second embodiment has a primary surface 1 that is inclined at an angle of 0 to 10° from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer on at least the surface of the primary surface 1, and the Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ In the Si-doped GaN layer, the Si concentration is set to a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100}(%) is 90% or more.

[0032] Another aspect of the GaN substrate according to the second embodiment has a primary surface 1 that is inclined at an angle of 0 to 10° from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer on at least the surface of the primary surface 1, the Si-doped GaN layer having a thickness of 50 μm or more. In the Si-doped GaN layer, the Si concentration is a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100}(%) is 90% or more.

[0033] In both the first and second embodiments, the inclination of the main surface 1 from the (0001) crystal plane may be 0 to 10°, preferably 0 to 5°, and more preferably 0 to 2.5°. The lower limit of the inclination is 0°, but it may be 0.2° or more. The upper limit of the inclination is 10°, but it is preferably 5° or less, more preferably 2.5° or less, and may be 1.5° or less, or may be 1° or less.

[0034] In both the first and second embodiments, the GaN substrate has a Si-doped GaN layer on the surface of the principal surface 1. In this specification, "having a Si-doped GaN layer on the surface of the principal surface 1" means that the outermost surface of the principal surface 1 of the GaN substrate coincides with the outermost surface of the Si-doped GaN layer.

[0035] In both the first and second embodiments, as shown in FIG. 1 , the GaN substrate 100 may be (0001) oriented and may have a GaN crystal layer 120 and a Si-doped GaN layer 110 on the (0001) surface 101, which is the Ga-polar surface side. Alternatively, after forming the Si-doped GaN layer 110, the GaN crystal layer 120 used as the base crystal may be removed to obtain a GaN substrate 110 consisting solely of the Si-doped GaN layer 110. A (0001) oriented GaN substrate is a substrate having a major surface, i.e., a large-area surface, that is parallel or approximately parallel to the (0001) crystal plane, i.e., the c-plane, and is also referred to as a c-plane GaN substrate. Here, "parallel" or "approximately parallel" means that the inclination from the (0001) crystal plane, which is the Ga-polar plane, is 0 to 10 degrees.

[0036] The Si-doped GaN layer 110 in both embodiments refers to a layer in which some of the Ga in the GaN crystal is substituted with Si. By having a Si-doped GaN layer in the GaN substrate, the resistance of the substrate can be reduced, making it useful as a conductive substrate. The Si concentration in the Si-doped GaN layer 110 is 1×10 １８ atoms / cm ３ In this case, the resistance of the substrate can be further reduced, and the usefulness as a conductive substrate can be enhanced. From the viewpoint of reducing the resistance, the Si concentration in the Si-doped GaN layer 110 is preferably 2×10 １８ atoms / cm ３More preferably, 5 × 10 １８ atoms / cm ３ More preferably, 7 × 10 １８ atoms / cm ３ More preferably, 9×10 １８ atoms / cm ３ The upper limit of the Si concentration is not particularly limited, but for example, 1×10 ２１ atoms / cm ３ Herein, the concentration of donor impurities such as Si (silicon) in the Si-doped GaN layer can be determined by secondary ion mass spectrometry (SIMS). Although the concentration of donor impurities such as Si may vary along the c-axis direction, the average donor impurity concentration from a depth of 3 μm to a depth of 50 μm from the surface of the Si-doped GaN layer can be defined as the concentration of the donor impurity.

[0037] The higher the Si concentration in the Si-doped GaN layer 110, the more likely it is that repelling will occur. As mentioned above, repelling is a SiNx film that forms on the surface of a GaN crystal, where N atoms that would normally bond with Ga atoms instead bond with Si atoms, forming a silicon nitride film. Where repelling occurs, epitaxial growth of GaN is inhibited, and if epitaxial growth continues without repelling, it will result in a depression on the surface of the resulting GaN substrate. These surface depressions are sometimes referred to as "depression defects" in this specification. The presence of depressions on the surface of a GaN substrate reduces the yield of device manufacturing using that GaN substrate.

[0038] In contrast, the Si-doped GaN layer 110 in the first embodiment suppresses the occurrence of repelling, thereby reducing recesses on the surface of the GaN substrate and achieving low substrate resistance without deteriorating the yield of device manufacturing.

[0039] Although the details of the mechanism by which such a GaN substrate is obtained are not clear, it is believed that the mechanism is as follows: ３ When molecules such as silicon dioxide react with silicon dioxide to form silicon nitride, they rarely react with silicon dioxide to form silicon nitride.３ It is believed that when molecules such as NH4 and NH5 exist in an adsorbed state on the same terrace of the GaN crystal surface, they meet and react due to thermal motion, etc., to form cissing. In contrast, in the present invention, it has been discovered that the occurrence of cissing can be suppressed by narrowing the terrace. This is because the time it takes for Si atoms adsorbed on the terrace, i.e., Si adatoms, to reach the kink sites located at the step edges can be shortened, thereby preventing cissing by the NH4 adsorbed on the terrace. ３ As a result, even if the Si concentration is increased and the density of Si adatoms on the terrace is increased, the probability of encountering adsorbed N atoms is reduced, and depressions on the surface of the Si-doped GaN layer due to the occurrence of cissing are reduced, resulting in a smooth surface.

[0040] As described above, the recesses on the surface of the Si-doped GaN layer in this specification are synonymous with recessed defects and refer to defects on the surface where no crystals are present. However, recesses may particularly refer to those with a depth of 5 μm or more. In the first embodiment, the total bottom area of ​​the recessed defects relative to the total surface area of ​​the Si-doped GaN layer is 15% or less, preferably 10% or less, more preferably 5% or less, even more preferably 1% or less, and particularly preferably 0.1% or less, although a lower value is preferable and even 0% is acceptable. The smaller the total bottom area of ​​the recesses, the less likely cissing occurs, and the more likely it is that a decrease in yield in device manufacturing can be suppressed. In the first embodiment, the total bottom area of ​​recesses with a depth of 5 μm or more relative to the total surface area of ​​the Si-doped GaN layer is also preferably 15% or less, more preferably 10% or less, even more preferably 5% or less, even more preferably 1% or less, and particularly preferably 0.1% or less, although a lower value is preferable and even 0% is acceptable.

[0041] The presence of concave defects can be identified by observation using a microscope or the like, and the total bottom area thereof can also be calculated. In particular, for concaves with a depth of 5 μm or more, the total bottom area of ​​the concaves can be distinguished by differences in color when the surface of the Si-doped GaN layer is observed under ultraviolet irradiation and a fluorescent image is obtained. Using this color difference, the total bottom area of ​​all concaves with a depth of 5 μm or more can be calculated from the fluorescent image, allowing for a more precise calculation of the total bottom area of ​​concaves with a depth of 5 μm or more relative to the area of ​​the entire surface of the Si-doped GaN layer.

[0042] It was also found that the activation rate decreases as the Si concentration in the Si-doped GaN layer 110 increases. The activation rate refers to the proportion of impurities that function as carriers among the doped carrier impurities present in the crystal. In this specification, the Si concentration in the Si-doped GaN layer is expressed in terms of a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100} (%) can be taken as the activation rate.

[0043] As mentioned above, the ionization energy of Si is small enough to ionize it at room temperature, so in principle the activation rate should be about 100%. However, a possible reason for the low activation rate is that Si atoms do not occupy the Ga site, which is their natural position, but instead occupy, for example, interstitial sites or antisites (N sites).

[0044] In contrast to this, the Si-doped GaN layer 110 in the second embodiment can maintain a high activation rate even when the Si concentration is increased, and can achieve a low resistance due to the high Si concentration.

[0045] Although the details are unclear, we believe the following: One reason why Si atoms do not enter Ga sites (their natural positions) but instead enter interstitial sites or antisites (N sites) is thought to be that the terraces are wide and the Si atoms have a long travel distance before being incorporated into the kink sites. In contrast, in the present invention, the activation rate was improved by narrowing the terraces. We believe this is because the narrow terraces shorten the distance the Si atoms have to travel to reach the kink sites, thereby increasing the probability that the Si atoms will be incorporated into the appropriate kink sites and function as dopants. As a result, even if the Si concentration is increased and the density of Si adatoms on the terraces is increased, the Si atoms are incorporated into the appropriate kink sites, thereby achieving a high activation rate and a low resistivity commensurate with the Si concentration.

[0046] In the second embodiment, the Si concentration in the Si-doped GaN layer is set to a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100}(%) is 90% or more, preferably 95% or more, more preferably 98% or more, the higher the better, and 100% is the most preferable. It can be said that the higher the value expressed above, i.e., the activation rate, the more likely it is that a lower resistance corresponding to the doped Si concentration can be achieved.

[0047] The above describes the recesses on the surface of the Si-doped GaN layer in the first embodiment and the activation rate in the second embodiment. However, this does not exclude the possibility that the GaN substrate according to the first embodiment has a high activation rate in addition to low resistance and suppression of deterioration in yield in device manufacturing, and that the GaN substrate according to the second embodiment has a low resistivity corresponding to the Si concentration due to a high activation rate and can suppress deterioration in yield in device manufacturing.

[0048] That is, in the first embodiment, the Si concentration of the Si-doped GaN layer is set to a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３), the value represented by {(b / a)×100}(%) is preferably 90% or more, more preferably 95% or more, even more preferably 98% or more, the higher the better, and 100% is the most preferable.

[0049] In the second embodiment, the total bottom area of ​​the concave defects on the surface of the Si-doped GaN layer is preferably 15% or less of the area of ​​the entire surface of the Si-doped GaN layer, preferably 10% or less, more preferably 5% or less, even more preferably 1% or less, and particularly preferably 0.1% or less, although a lower value is preferable and it may even be 0%. In the second embodiment, the total bottom area of ​​the concaves on the surface of the Si-doped GaN layer that are 5 μm or more deep is preferably 15% or less of the area of ​​the entire surface of the Si-doped GaN layer, preferably 10% or less, more preferably 5% or less, even more preferably 1% or less, and particularly preferably 0.1% or less, although a lower value is preferable and it may even be 0%.

[0050] In both embodiments, it is preferable that one or more 5 mm x 5 mm square lattices free of concave defects exist on the surface of the Si-doped GaN layer. The presence of one or more such square lattices reduces the occurrence of cissing in the GaN substrate and can suppress a decrease in yield in device manufacturing, making the GaN substrate highly useful for device manufacturing. From the same perspective, it is more preferable that one or more 10 mm x 10 mm square lattices free of concave defects exist on the surface of the Si-doped GaN layer, particularly preferably one or more 15 mm x 15 mm square lattices free of concave defects exist, and particularly preferably one or more 25 mm x 25 mm square lattices free of concave defects exist. The presence of the above-mentioned square lattices can be confirmed by observing the surface of the GaN substrate with a microscope or the like.

[0051] In both embodiments, it is preferable that the surface of the Si-doped GaN layer has one or more 5 mm x 5 mm square lattices that are free of recesses with a depth of 5 μm or greater. The presence of one or more such square lattices reduces the occurrence of cissing on the GaN substrate and can suppress a decrease in yield in device manufacturing, thereby making the GaN substrate highly useful for device manufacturing. From the same perspective, it is more preferable that the surface of the Si-doped GaN layer has one or more 10 mm x 10 mm square lattices that are free of recesses with a depth of 5 μm or greater, particularly preferably one 15 mm x 15 mm square lattices that are free of recesses with a depth of 5 μm or greater, and particularly preferably one 25 mm x 25 mm square lattices that are free of recesses with a depth of 5 μm or greater. The presence of the above-mentioned square lattices can be confirmed by observing a fluorescent image of the GaN substrate.

[0052] It should be noted that the concave defects and recesses with a depth of 5 μm or more do not limit the size of the GaN substrate. For example, the above description can be applied as is when the GaN substrate is a wafer with a diameter of 45 mm or more. However, when the GaN substrate is a square substrate with a minor axis of less than 5 mm or a wafer with a diameter of 7 mm or less, it is not possible to obtain a 5 mm × 5 mm square lattice on the surface of the Si-doped GaN layer. Even in such cases, if the requirements of the first and second embodiments are met, the GaN substrate is included in the GaN substrate according to the present invention.

[0053] In both embodiments, the thickness of the Si-doped GaN layer is preferably 50 μm or more, and more preferably 50 to 300 μm. This allows the Si-doped GaN layer alone to have self-supporting properties, and even when a GaN substrate consisting of only the Si-doped GaN layer is formed, it can function as a substrate. The thickness of the Si-doped GaN layer is preferably 50 μm or more, more preferably 80 μm or more, and even more preferably 100 μm or more. There is no particular upper limit to the thickness, but it may be, for example, 300 μm or less, or may be 200 μm or less, or 150 μm or less. Note that the thickness of the Si-doped GaN layer in this specification refers to a thickness of the Si-doped GaN layer having a Si concentration of 1×10 １８ atoms / cm ３The thickness of the Si-doped GaN layer is equal to or greater than 100 nm, and can be measured by the SIMS method described above. If the thickness of the Si-doped GaN layer is not uniform, the thinnest minimum thickness should be within the above range.

[0054] In both embodiments, the Si-doped GaN layer may contain, in addition to Si (silicon), a Group 14 element such as Ge (germanium) or a Group 16 element such as O (oxygen) or S (sulfur) as donor impurities. The total concentration of donor impurities other than Si is, for example, 10% or less of the Si concentration, and may be 5% or less, 1% or less, or 0%, i.e., no donor impurities are contained.

[0055] As will be described later, the GaN substrate according to both embodiments is preferably grown by, for example, vapor phase epitaxy, and more preferably by hydride vapor phase epitaxy (HVPE). The Si-doped GaN layer obtained by the above method contains 100% O (oxygen) even if not intentionally added. １５ atoms / cm ３ In other words, the Si-doped GaN layer can have an O (oxygen) concentration of 1×10 １５ atoms / cm ３ It may be more than that.

[0056] On the other hand, the Si-doped GaN layer contains non-negligible concentrations of donor impurities other than Si and O when intentionally doped with such donor impurities. Note that "intentional doping" refers to the case where a target element is added as a single element or a compound as a raw material in order to dope the Si-doped GaN layer with the target element.

[0057] Therefore, unless the Si-doped GaN layer is intentionally doped with a donor impurity other than Si and O, the total donor impurity concentration of the Si-doped GaN layer may be considered to be equal to the sum of the Si concentration and the O concentration. Whether or not the Si-doped GaN layer is doped with a donor impurity other than Si and O can be confirmed by elemental analysis or the like.

[0058] The concentration of donor impurities other than Si is set to 1×10 １７ atoms / cm ３Preferably less than 8 x 10 １６ atoms / cm ３ Less than 5 x 10 is more preferable. １６ atoms / cm ３ For the same reason, the total concentration of donor impurities other than Si is more preferably 2×10 １７ atoms / cm ３ Preferably less than 8 x 10 １６ atoms / cm ３ Less than 5 x 10 is more preferable. １６ atoms / cm ３ The following is even more preferred:

[0059] The Si-doped GaN layer may contain elements other than the Ga, N, and Si that constitute the GaN crystal, as well as the Group 14 and Group 16 element atoms that act as other donor impurities. The other elements may be intentionally or unintentionally contained, and examples thereof include H (hydrogen), C (carbon), and Cl (chlorine). The total concentration of these other elements is 10 １６ ~10 １７ atoms / cm ３ Orders are also accepted.

[0060] The full width at half maximum of the rocking curve obtained by (004) X-ray diffraction of the Si-doped GaN layer is preferably 50 arcsec or less. The rocking curve is a diffraction intensity distribution obtained when the direction of the incident X-rays and the position of the detector are fixed and only the crystal sample is rotated in X-ray diffraction measurement, and is an index of crystal quality.

[0061] The smaller the full width at half maximum of the rocking curve, the fewer the crystal defects and the better the crystal quality. The full width at half maximum is preferably 40 arcsec or less, more preferably 30 arcsec or less, and even more preferably 20 arcsec or less. The lower limit of the full width at half maximum is not particularly limited, but is usually 5 arcsec or more. In this specification, the full width at half maximum is synonymous with what is generally referred to as the half width. That is, the maximum intensity f of the peak ｍａｘ For half the strength, 1 / 2f ｍａｘ This means the distance between the positions indicated.

[0062] The full width at half maximum can be adjusted by the growth method (vapor phase method, liquid phase method, or the like) of the GaN crystal layer in the Si-doped GaN layer, the crystal characteristics of the seed substrate used when growing the GaN crystal layer, the crystal growth conditions, the selection of the growth surface, the impurity content, etc.

[0063] In both embodiments, the dislocation density at the surface of the Si-doped GaN layer is 5×10 ６ cm －２ In this case, it is possible to suppress the degradation of device performance due to dislocations. From the same viewpoint, the dislocation density on the surface of the Si-doped GaN layer is preferably 2×10 or less. ６ cm －２ More preferably, 1×10 ６ cm －２ The following is even more preferable: The dislocation density of the Si-doped GaN layer is preferably equal to or greater than the dislocation density of the GaN crystal layer serving as the underlying crystal layer, and more specifically, is preferably 0.5 to less than 2 times the dislocation density of the GaN crystal layer serving as the underlying crystal layer. Furthermore, the fact that both dislocation densities are the same or nearly the same means that no new dislocations are generated at the GaN crystal layer / Si-doped GaN layer interface.

[0064] In both embodiments, the GaN crystal layer on which the Si-doped GaN layer is formed serves as an underlayer crystal, and is a layer on which GaN is epitaxially grown. The GaN crystal layer has a resistivity of 1×10 at room temperature. ５ The layer may be less than Ωcm, i.e. not semi-insulating.

[0065] In both embodiments, the GaN crystal layer may unintentionally and unavoidably contain elements other than Ga and N, such as Si, O, and H. For example, the Si concentration is 5×10 １７ atoms / cm ３ The O concentration may be 2×10 １７ atoms / cm ３ The H concentration may be 5×10 １６ atoms / cm ３ The concentration of each of the other elements may be 5×10 or less. １５ atoms / cm ３ It may be the following:

[0066] In both embodiments, when the GaN substrate is used to manufacture a nitride semiconductor device, the GaN crystal layer may be removed and the Si-doped GaN layer may be used for the nitride semiconductor device chip. In such a use, there are no particular requirements for the electrical properties of the GaN crystal layer.

[0067] The Si-doped GaN layer in the GaN substrate may be formed directly on the c-plane of the GaN crystal layer, or may be formed via a regrowth interface. The regrowth interface refers to the boundary surface that occurs when crystals that will become the Si-doped GaN layer grow on the GaN crystal layer, and its existence can be confirmed, for example, by observing the cross section of the GaN substrate wafer using a scanning electron microscope, cathodoluminescence observation, or fluorescence microscope. The regrowth interface can exist when the steps of growing the GaN crystal layer and the Si-doped GaN layer are not continuous.

[0068] The conductivity type, i.e., carrier type, of the Si-doped GaN layer in the GaN substrate according to both embodiments is typically n-type. The resistivity of the Si-doped GaN layer at 300 K in both embodiments is 1×10 －２ Ωcm or less is preferable, and 8×10 －３ Ωcm or less is more preferable, and 4×10 －３ The lower the resistivity, the better. －５ The resistivity is Ωcm or more. The lower the resistivity, the higher the electron mobility, enabling high-temperature and high-speed operation and a high-output nitride semiconductor device. The resistivity of the Si-doped GaN layer can be measured using the four-terminal Van der Pauw method, with terminals connected to the Si-doped GaN layer.

[0069] The GaN substrate according to both embodiments is preferably used as a wafer, but the shape of the main surface may be square, rectangular, hexagonal, octagonal, elliptical, or the like, and is not particularly limited. It may also be an irregular shape.

[0070] In contrast to the GaN substrate according to the first embodiment, conventional GaN substrates have been unable to produce a continuous surface free of concave defects or recesses with a depth of 5 μm or more on the surface of the Si-doped GaN layer, and even when a surface free of such concave defects or recesses is cut out, only small pieces are obtained. In contrast, with the Si-doped GaN layer according to the first embodiment, a surface free of such concave defects or recesses can be produced without cutting, resulting in a large-area GaN substrate in which the total bottom area of ​​the concave defects or the total bottom area of ​​the recesses with a depth of 5 μm or more is 15% or less of the total surface area of ​​the Si-doped layer. That is, when the GaN substrate according to the first embodiment is a wafer, its diameter is preferably 25 mm or more. Furthermore, in consideration of nitride semiconductor applications, the diameter of the GaN substrate according to both embodiments, when it is a wafer, is typically 45 mm or more, but may be 50 mm or more, 95 mm or more, or 145 mm or more. Typically, it is 50 to 55 mm (about 2 inches), 100 to 105 mm (about 4 inches), 150 to 155 mm (about 6 inches), etc. Furthermore, when the GaN crystal has a shape other than a disk, a size can be adopted such that the diameter of the disk having the same area as the main surface is the above size.

[0071] The preferred thickness of the GaN substrate varies depending on the diameter of the primary surface. When the diameter is approximately 2 inches, the thickness of the GaN substrate is preferably 250 to 450 μm. Here, the thickness is preferably 250 μm or more, more preferably 300 μm or more, even more preferably 350 μm or more, and preferably 450 μm or less, and more preferably 400 μm or less. When the diameter is approximately 4 inches, the thickness of the GaN substrate is preferably 350 to 750 μm. Here, the thickness is preferably 350 μm or more, more preferably 400 μm or more, and preferably 750 μm or less, more preferably 650 μm or less, and even more preferably 600 μm or less. When the diameter is approximately 6 inches, the thickness of the GaN substrate is preferably 450 to 800 μm. Here, the thickness is preferably 450 μm or more, more preferably 550 μm or more, and preferably 800 μm or less, and more preferably 700 μm or less. When the GaN substrate is made of only a Si-doped GaN layer, the thickness of the Si-doped GaN layer is preferably within the above range.

[0072] The (000-1) surface 102, which is the N-polar surface of the GaN substrate according to both embodiments, serves as the backside and may be mirror-finished, roughened, or matte-finished. The (0001) surface 101, which is the Ga-polar surface of the GaN substrate, serves as the front surface and is used in a nitride semiconductor device by further epitaxially growing a nitride semiconductor layer on this surface.

[0073] The (0001) surface 101, which is a Ga polar surface, may be an as-grown surface as it is after crystal growth, but is preferably a surface that has been planarized by processing such as polishing, CMP (Chemical Mechanical Polishing), etching, etc. The (0001) surface 101 may also be a surface formed by cutting, or may be a surface that has been subjected to the above-mentioned planarization without cutting.

[0074] The root mean square roughness (RMS) of the (0001) surface 101 of the GaN substrate according to both embodiments, measured by atomic force microscope (AFM), is preferably less than 5 nm, more preferably less than 2 nm, even more preferably less than 1 nm, and may be less than 0.5 nm, within a measurement range of 2 μm × 2 μm.

[0075] The edges of the GaN substrate according to both embodiments may be chamfered. In addition, various markings may be applied to the GaN substrate as needed, such as an orientation flat or notch that indicates the crystal orientation, and an index flat that makes it easy to distinguish between the front and back surfaces.

[0076] Semiconductor devices using GaN substrates according to both embodiments are basically nitride semiconductor devices, which are semiconductor devices in which the main part of the device structure is formed from nitride semiconductors.

[0077] The nitride semiconductor is also called a nitride-based Group III-V compound semiconductor, a Group III nitride-based compound semiconductor, a GaN-based semiconductor, or the like, and includes GaN as well as compounds in which part or all of the gallium in GaN is substituted with another Group 13 element of the periodic table (B, Al, In, etc.).

[0078] There is no limitation on the type of nitride semiconductor device in which the GaN substrate according to both embodiments can be used, and examples include light-emitting devices such as laser diodes (LDs) and light-emitting diodes (LEDs), and electronic devices such as rectifiers, bipolar transistors, and field-effect transistors.

[0079] [Method for Manufacturing GaN Substrate (1)] The method for manufacturing the GaN substrate according to the first embodiment and the GaN substrate according to the second embodiment is not particularly limited as long as the desired characteristics are obtained. As a result of intensive research, the present inventors have found that, as one aspect of the manufacturing method, the GaN substrate according to the first embodiment and the GaN substrate according to the second embodiment can be manufactured by using a vapor phase epitaxy method to form a Si-doped GaN layer and setting the off-angle of the base crystal within a specific range during the formation.

[0080] Therefore, the third embodiment of the present invention provides a Si-doped GaN layer in which the total bottom area of ​​concave defects on the surface of the Si-doped GaN layer is 15% or less of the total surface area, a Si-doped GaN layer in which the total bottom area of ​​concaves with a depth of 5 μm or more is 15% or less of the total surface area, or a Si-doped GaN layer in which the Si concentration is α (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a) × 100} (%) is 90% or more. One aspect of the method for producing a Si-doped GaN layer according to the third embodiment is a method for producing a Si-doped GaN layer having a thickness of 50 μm or more on a base crystal by vapor phase epitaxy, characterized in that the off-angle of the base crystal is 0.5° or more. Another aspect of the method for producing a Si-doped GaN layer according to the third embodiment is a method for producing a Si-doped GaN layer having a Si concentration of 1×10 １８ atoms / cm ３ The method for producing the above-described Si-doped GaN layer on a base crystal by vapor phase epitaxy is characterized in that the off-angle of the base crystal is set to 0.5° or more.

[0081] That is, one aspect of the method for manufacturing the GaN substrate according to the first embodiment and the GaN substrate according to the second embodiment includes, as one step, the method for manufacturing the Si-doped GaN layer according to the third embodiment.

[0082] The Si concentration of the Si-doped GaN layer manufactured by the method for manufacturing a Si-doped GaN layer according to the third embodiment is 1×10 １８ atoms / cm ３ It is preferable that this is equal to or greater than this.

[0083] The base crystal for forming the Si-doped GaN layer is preferably a c-plane GaN substrate seed, and the Si-doped GaN layer, i.e., a (0001)-oriented GaN layer doped with Si, is grown on its surface by vapor phase epitaxy.

[0084] Fig. 2 is an explanatory diagram of the off-angle provided to the underlayer crystal used in the method for forming the Si-doped GaN layer. In Fig. 2(a), the underlayer crystal is cut at an angle indicated by the dashed line with respect to the (0001) surface. Fig. 2(b) shows the underlayer crystal after cutting, and Fig. 2(c) is an enlarged view of the circled area.

[0085] As shown in Figure 2(c), the angle at which the (0001) surface of the base crystal is cut is called the off-angle θ, and the cut surface becomes stepped with a step the thickness of one atom when cut. The terrace width W, which represents the width of the terrace T, varies depending on the off-angle θ when cutting. That is, the smaller the off-angle θ, the wider the terrace width W. As shown in Figure 3, when the off-angle θ is increased compared to Figure 2(c), the terrace width W becomes narrower.

[0086] Here, by setting the off-angle θ to 0.5° or more, the terrace width W is narrowed, and the total bottom area of ​​concave defects or the total bottom area of ​​recesses with a depth of 5 μm or more on the surface of the resulting Si-doped GaN layer can be set to 15% or less of the total surface area of ​​the Si-doped GaN layer, thereby obtaining a GaN crystal according to the first embodiment.

[0087] The reason for this is unclear, but is thought to be as follows: When forming a Si-doped GaN layer by vapor phase growth, a gas containing Si atoms and a gas containing N atoms are used as raw materials. As mentioned above, Si atoms and N atoms, when in the gas phase, rarely react to form silicon nitride, which becomes cissing. However, when Si adsorbed on the terrace T, i.e., Si adatoms, and molecules containing N atoms adsorbed on the terrace T meet due to thermal motion or the like, they react to form cissing.

[0088] As shown in Figure 2(c), the wider the terrace width W, the longer it takes for Si adatoms adsorbed on the surface of the terrace T to migrate and reach the step edge E where the kink site S is located, which is a growth site necessary for incorporation into the GaN crystal. As a result, the probability that the Si adatoms will encounter N atoms adsorbed on the surface of the terrace T while migrating to the step edge E and react with each other, resulting in cissing, increases. In contrast, as shown in Figure 3, by increasing the off-angle θ of the base crystal compared to conventional methods, the terrace width W becomes narrower, and as a result, the probability of encounters between Si adatoms and adsorbed N atoms on the terrace T can be reduced, which is thought to suppress the occurrence of cissing.

[0089] The Si concentration in the Si-doped GaN layer is, for example, 1×10 １８ atoms / cm ３ When highly doped with Si to a concentration as high as or greater than 0.5°, conventionally, the density of Si adatoms on the terrace T increases, and the Si adatoms encounter and react with adsorbed N atoms, forming many cissors. However, by setting the off angle θ to 0.5° or greater, the Si adatoms arrive at the step edges E where the kink sites S are located without forming cissors, and Si is incorporated into the kink sites S. As a result, even when epitaxially grown, the resulting Si-doped GaN layer has a smooth surface with few recesses.

[0090] In order to shorten the migration time of the Si adatoms on the terrace T until they reach the step edge E, it is possible to change the growth conditions for crystal growth. However, it has been found that shortening the migration time by changing the growth temperature, for example, requires increasing the growth temperature by 100°C. Such a high temperature increase is not realistic. For example, if GaN crystal growth at 1000°C is attempted at 1100°C, the GaN will decompose and will not grow.

[0091] Similarly, for the GaN substrate according to the second embodiment, by setting the off angle θ of the base crystal to 0.5° or more, the terrace width W becomes narrow, and in the obtained Si-doped GaN layer, the Si concentration becomes a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100} (%) can be made 90% or more.

[0092] The reason for this is unclear, but is believed to be as follows. The relationship between the off-angle θ and the terrace width W is as described above. Conventionally, the off-angle θ is, for example, about 0.3°. When the base crystal is cut at this angle, the terrace T becomes wide, increasing the probability that Si atoms will not enter their original Ga site but will instead enter interstitials or antisites (N sites). The terrace width W when the off-angle θ is 0.3° is approximately 1.5 times that when the off-angle θ is 0.5°. In contrast, by setting the off-angle to 0.5° or more, the terrace width W becomes smaller, shortening the travel distance of Si adatoms to reach the kink sites S. This allows Si atoms to be incorporated into appropriate kink sites and function as dopants. As a result, the Si concentration is increased from the viewpoint of reducing resistivity. Consequently, even if the density of Si adatoms on the terrace T increases, Si atoms are incorporated into appropriate kink sites, thereby achieving a high activation rate.

[0093] Therefore, in order to obtain the Si-doped GaN layer in both embodiments, the off-angle of the base crystal in the third embodiment is preferably 0.5 to 1°. Here, the off-angle is preferably 0.5° or more, more preferably 0.55° or more, and even more preferably 0.6° or more. On the other hand, from the viewpoint of suppressing bunching and maintaining the plane orientation characteristics of the C-plane, the off-angle is preferably 1° or less, more preferably 0.9° or less, and even more preferably 0.8° or less.

[0094] With respect to the off-angle of the base crystal, the GaN substrates according to the first and second embodiments can be obtained by employing conventionally known manufacturing methods.

[0095] For example, as shown in Fig. 4(a), a seed wafer 1 is prepared, and a first GaN thick film 2 made of intentionally undoped GaN and oriented in the (0001) direction is grown thereon by HVPE or the like, as shown in Fig. 4(b). Furthermore, as shown in Fig. 4(c), the first GaN thick film 2 may be processed as necessary to obtain a plurality of first c-plane GaN wafers 3.

[0096] An example of the seed wafer 1 is a c-plane sapphire wafer, preferably provided with a release layer on its main surface. When providing a release layer, a GaN layer several hundred nanometers thick is grown on the c-plane sapphire wafer via a low-temperature buffer layer by metalorganic vapor phase epitaxy (MOVPE), and then a Ti (titanium) layer several tens of nanometers thick is formed on the GaN layer by vacuum deposition. Then, for example, a 80% H ２ (hydrogen) and 20% NH ３ The peeling layer can be formed by annealing the film at 1060° C. for 30 minutes in a mixed gas atmosphere of (ammonia).

[0097] The first GaN thick film 2 is preferably thick enough to form a free-standing first c-plane GaN wafer 3, and is preferably grown to a thickness of, for example, several mm or more, from which two or more first c-plane GaN wafers 3 can be obtained.

[0098] As shown in Fig. 5(b), a second GaN thick film 4 made of intentionally undoped GaN and oriented in the (0001) direction is grown by HVPE on the (0001) crystal plane of the Ga polarity plane of the first c-plane GaN wafer 3 obtained as described above and shown in Fig. 5(a). Then, as shown in Fig. 5(c), the second GaN thick film 4 may be processed as necessary to obtain a plurality of second c-plane GaN wafers 5.

[0099] The second c-plane GaN wafer 5 obtained as described above will serve as the base crystal for forming the Si-doped GaN layer. Before cutting the wafer obliquely to the (0001) crystal plane of the Ga polarity plane, it may be subjected to appropriate planarization processing using grinding, polishing, CMP, or other techniques, as desired. Furthermore, after planarization, it may be subjected to surface roughening processing by etching. Conventional methods can be used for planarization and surface roughening.

[0100] The off-angle, which is the inclination angle when cutting obliquely with respect to the (0001) crystal plane of the Ga polar plane, is preferably 0.5° or more as described above, and the off-cut direction, which is the inclination direction, is preferably the m-axis direction or the a-axis direction.

[0101] The (0001) crystal plane of the GaN crystal layer can be cut out using a wire slicer or a laser slicer.

[0102] A Si-doped GaN layer 6a is formed on the (0001) crystal plane of the second c-plane GaN wafer 5, the surface of which is cut out as shown in Fig. 6(a). Between the second c-plane GaN wafer 5 and the Si-doped GaN layer 6a, a Si-doped GaN layer having a Si concentration of 1 × 10 is formed as shown in Fig. 6(b). １８ atoms / cm ３ There may be an intervening region 6b having a thickness of less than 1 / 2 mm.

[0103] When growing the above-mentioned GaN crystal or Si-doped GaN crystal by the HVPE method, for example, an HVPE apparatus 20 shown in FIG. 7 can be used.

[0104] 7 includes a hot-wall reactor 21, a gallium reservoir 22 and a susceptor 23 disposed within the reactor 21, and a first heater 24 and a second heater 25 disposed outside the reactor 21. The first heater 24 and the second heater 25 each surround the reactor 21 in an annular shape.

[0105] The reactor 21 is a quartz tube chamber. Inside the reactor 21, there are a first zone Z1 that is mainly heated by a first heater 24 and a second zone Z2 that is mainly heated by a second heater 25. An exhaust pipe P Ｅ is connected to the end of the reactor 21 on the second zone Z2 side. The gallium reservoir 22 disposed in the first zone Z1 is a quartz container having a gas inlet and a gas outlet. The susceptor 23 disposed in the second zone Z2 is made of, for example, graphite. A mechanism for rotating the susceptor 23 can be provided as desired.

[0106] To grow GaN in the HVPE apparatus 20, a seed is placed on the susceptor 23, and the inside of the reactor 21 is heated by the first heater 24 and the second heater 25. At the same time, NH 3 diluted with a carrier gas is heated. ３ (ammonia) through the ammonia inlet pipe P １ into the second zone Z2 through a hydrogen chloride inlet pipe P ２ This HCl reacts with metallic gallium in the gallium reservoir 22, and the resulting GaCl (gallium chloride) is introduced through the gallium chloride introduction pipe P ３ The mixture is transported to the second zone Z2 through the

[0107] NH in the second zone Z2 ３ and GaCl react with each other, and the resulting GaN crystallizes on the seed placed on the susceptor 23. When intentionally doping the growing GaN, a doping gas diluted with a carrier gas is introduced through a dopant introduction pipe P ４ The ammonia is introduced into the second zone Z2 in the reactor 21 through the ammonia introduction pipe P １ , hydrogen chloride introduction pipe P ２ , gallium chloride introduction tube P３ and dopant introduction tube P ４ The part of the NH 3 that is placed inside the reactor 21 is made of quartz. ３ The carrier gas for diluting each of the HCl and doping gas is H ２ (hydrogen gas), N ２ (nitrogen gas) or H ２ and N ２ A mixed gas of the above is preferably used.

[0108] The preferred conditions for growing GaN using the HVPE apparatus 20 are as follows: The temperature of the gallium reservoir 22 is, for example, 500 to 1000°C, preferably 700°C or higher, and preferably 900°C or lower. The temperature of the susceptor 23 is, for example, 900 to 1100°C, preferably 930°C or higher, more preferably 950°C or higher, and preferably 1050°C or lower, more preferably 1020°C or lower.

[0109] NH in reactor 21 ３ The V / III ratio, which is the ratio of the GaCl partial pressure (V) to the GaCl partial pressure (III), is, for example, 1 to 20, preferably 2 or more, more preferably 3 or more, and preferably 10 or less. If the V / III ratio is too large or too small, it will cause deterioration in the morphology of the GaN growth surface. Deterioration in the morphology of the growth surface can cause a decrease in crystal quality.

[0110] The growth rate of GaN was determined by the NH ３ The growth rate can be controlled by using the product of the partial pressure and the GaCl partial pressure as a parameter. The growth rate is, for example, 20 to 200 μm / h, and when growing a Si-doped GaN layer, it is preferably 120 μm / h or less, more preferably 100 μm / h or less, and even more preferably 80 μm / h or less. An excessively high growth rate deteriorates the surface morphology of the grown GaN.

[0111] When doping with Si, it is preferable to gradually increase the supply rate of the doping gas to a predetermined value over a period of several minutes to several tens of minutes from the start of supply in order to prevent deterioration of the morphology of the growth surface. For the same reason, it is preferable to start supplying the doping gas when the GaN layer has grown to at least several μm.

[0112] The doping gas for Si doping is SiH ４ (silane), SiH ３ Cl (monochlorosilane), SiH ２ Cls (dichlorosilane), SiHCl ３ (trichlorosilane) or SiCl ４ (tetrachlorosilane) is preferred. The partial pressure of the doping gas for Si doping is 1×10 －６ ~2 x 10 －４ kPa is preferred, and 2×10 －６ kPa or more is more preferable, and 1 × 10 －４ kPa or less is more preferable.

[0113] H in the carrier gas ２ The molar ratio of H in the carrier gas can affect the impurity concentration of the grown GaN. ２ The molar ratio of is calculated based on the flow rate of each gas species supplied as a carrier gas from outside the reactor into the reactor. The O concentration of GaN grown by the HVPE method when doped with Si is calculated based on the H ２ When the molar ratio of １６ atoms / cm ３ Below, further 1 x 10 １６ atoms / cm ３ This is due to the improved surface morphology during growth.

[0114] GaN grown using the HVPE apparatus 10 may contain O at concentrations detectable by SIMS, even when not intentionally doped. The O source is the quartz (SiO ２) and / or moisture remaining or penetrating into the reactor. In addition to the Si from the doping gas, the Si is also present in the reactor and quartz (SiO ２ ) as a Si source.

[0115] 7, the components arranged in the reactor 11 can be made of quartz and carbon, as well as silicon carbide (SiC), silicon nitride (SiNx), boron nitride (BN), alumina, tungsten (W), molybdenum (Mo), etc. As a result, the concentration of each impurity except for Si, O, and H in GaN grown using the HVPE apparatus 10 is 5×10 or less unless intentional doping is performed. １５ atoms / cm ３ It can be as follows:

[0116] The method for producing a Si-doped GaN layer according to the third embodiment may include a step of planarizing the Ga-polar surface of the produced Si-doped GaN layer, which may be an as-grown surface as crystals are grown. The planarization step may be performed by known processing methods such as polishing, CMP (Chemical Mechanical Polishing), and etching.

[0117] The method for manufacturing a Si-doped GaN layer according to the third embodiment may include slicing a Si-doped GaN layer having a thickness of 50 μm or more formed on a base crystal to obtain one or more freestanding GaN substrates. In this case, a thick Si-doped GaN layer is grown to a thickness sufficient to obtain a freestanding GaN substrate. When slicing a Si-doped GaN substrate to obtain a freestanding GaN substrate, the plane orientation of the primary surface cut out during slicing can be adjusted as desired. For example, by slicing the freestanding GaN substrate so that the off-angle is smaller from the as-grown Ga-polar surface of the Si-doped GaN layer, a GaN substrate having a Si-doped GaN layer with a primary surface having a reduced off-angle can be obtained. This method can also be used to obtain the GaN substrates according to the first and second embodiments. In this case, the off-angle of the primary surface of the obtained GaN substrate does not necessarily have to match the off-angle of the primary surface of the base crystal used in the manufacturing process.

[0118] [GaN Substrate (2)] One aspect of the GaN substrate according to the fourth embodiment has a primary surface 1 that is inclined at an angle of 0 to 10° from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer on at least the surface of the primary surface 1. The Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ The maximum Si concentration on the surface of the Si-doped GaN layer is defined as α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ ), the value expressed by [{(α-β) / α}×100] (%) is 10% or less. Another aspect of the GaN substrate according to the fourth embodiment has a primary surface 1 that is inclined at an angle of 0 to 10° from the (0001) crystal plane, which is a Ga polar plane, and has a Si-doped GaN layer on at least the surface of the primary surface 1. The Si concentration of the Si-doped GaN layer is 1×10 １８ atoms / cm ３ The thickness of the Si-doped GaN layer is 50 μm or more. The maximum Si concentration at the surface of the Si-doped GaN layer is α (atoms / cm ３ ), the minimum value is β (atoms / cm ３), the value expressed by [{(α-β) / α}×100] (%) is 10% or less.

[0119] In the fourth embodiment, the inclination of the main surface 1 from the (0001) crystal plane may be 0 to 10°, preferably 0 to 5°, and more preferably 0 to 2.5°. The lower limit of the inclination is 0°, but it may be 0.2° or more. The upper limit of the inclination is 10°, but it is preferably 5° or less, more preferably 2.5° or less, and may be 1.5° or less, or may be 1° or less.

[0120] In the fourth embodiment, the GaN substrate has a Si-doped GaN layer on the surface of the principal surface 1. In this specification, "having a Si-doped GaN layer on the surface of the principal surface 1" means that the outermost surface of the principal surface 1 of the GaN substrate coincides with the outermost surface of the Si-doped GaN layer.

[0121] In the fourth embodiment, as shown in FIG. 1 , the GaN substrate 100 may be (0001) oriented and may have a GaN crystal layer 120 and a Si-doped GaN layer 110 on the (0001) surface 101, which is the Ga-polar surface side. Alternatively, the GaN crystal layer 120 used as the base crystal may be removed after the Si-doped GaN layer 110 is formed, resulting in a GaN substrate 110 consisting solely of the Si-doped GaN layer 110. A (0001) oriented GaN substrate is a substrate having a major surface, i.e., a large-area surface, that is parallel or approximately parallel to the (0001) crystal plane, i.e., the c-plane, and is also referred to as a c-plane GaN substrate. Here, "parallel" or "approximately parallel" means that the inclination from the (0001) crystal plane, which is the Ga-polar plane, is 0 to 10 degrees.

[0122] The Si-doped GaN layer 110 in the fourth embodiment refers to a layer in which part of Ga in a GaN crystal is substituted with Si. The Si concentration in the Si-doped GaN layer 110 is 1×10 １８ atoms / cm ３ As a result, low resistance can be achieved, making the substrate useful as a conductive substrate. From the viewpoint of low resistance, the Si concentration in the Si-doped GaN layer 110 is set to 2×10 １８ atoms / cm ３ More than 5 × 10 is preferable. １８ atoms / cm ３More preferably, 7 × 10 １８ atoms / cm ３ More preferably, 9×10 １８ atoms / cm ３ The upper limit of the Si concentration is not particularly limited, but for example, 1×10 ２１ atoms / cm ３ Herein, the concentration of donor impurities such as Si (silicon) in the Si-doped GaN layer can be determined by secondary ion mass spectrometry (SIMS). Although the concentration of donor impurities such as Si may vary along the c-axis direction, the average donor impurity concentration from a depth of 3 μm to a depth of 50 μm from the surface of the Si-doped GaN layer can be defined as the concentration of the donor impurity.

[0123] The higher the Si concentration in the Si-doped GaN layer 110, the more difficult it is to make the Si concentration uniform in the direction parallel to the primary surface 1. This is because the reaction precursor such as chlorosilane used in doping Si is NH ３ It is thought that the cause is deactivation due to reaction with, etc. When the Si concentration is 1×10 １８ atoms / cm ３ When attempting to form the above-mentioned Si-doped GaN layer, the deactivation of the reaction precursor is particularly pronounced at the edge of the substrate, resulting in a decrease in the Si incorporation concentration, which inhibits the reduction of resistance. Therefore, it is believed that the resistance of the negative electrode side of semiconductor devices fabricated at the edge of the substrate is high.

[0124] In contrast, even if the Si concentration is high, the Si-doped GaN layer 110 of the fourth embodiment can achieve a low resistance corresponding to the Si concentration uniformly over the entire substrate.

[0125] Although the details of the mechanism by which such a substrate is obtained are unclear, we believe the following: One possible reason why Si atoms do not enter Ga sites (their natural positions) but instead enter interstitials or antisites (N sites) is that the terraces are wide, requiring the Si atoms to travel a long distance before being incorporated into kink sites. In contrast, in the present invention, narrowing the terraces shortens the distance the Si atoms must travel to reach the kink sites, making it easier for the Si atoms to be incorporated into appropriate kink sites. Furthermore, by increasing the distance L between the nozzle outlet of the GaCl gas ejection nozzle and the substrate surface compared to conventional methods, gas diffusivity is enhanced, resulting in favorable incorporation of Si atoms not only in regions of the substrate close to the nozzle, but also at the edge of the substrate. As a result, we believe it is possible to obtain a GaN substrate with improved uniformity of the Si concentration and uniformly reduced resistance corresponding to the Si concentration throughout the substrate.

[0126] In the fourth embodiment, the maximum Si concentration at the surface of the Si-doped GaN layer is set to α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ ), the value represented by [{(α-β) / α}×100] (%) is 10% or less, preferably 8% or less, more preferably 5% or less, even more preferably 3% or less, particularly preferably 2% or less, and the lower the better, but is usually 0.01% or more.

[0127] The maximum value of the Si concentration α (atoms / cm) at the surface of the Si-doped GaN layer ３ ) and minimum value β (atoms / cm ３ Specifically, the Si concentration is measured by the following method. First, the Si concentration is measured by SIMS at three locations on the surface of the Si-doped GaN layer: the center, a position 12.5 mm from the center, and a position 25 mm from the center. The maximum value α of the Si concentration is usually present in a region close to the center of the Si-doped GaN layer. On the other hand, the minimum value β (atoms / cm ３) is usually present in a region near the edge of the Si-doped GaN layer. Of the Si concentrations measured at the three points mentioned above, the maximum value is taken as α, and the minimum value is taken as β. Note that the above does not limit the size of the GaN substrate. For example, the above can be applied as is when the GaN substrate is a wafer or the like with a diameter of 50 mm or more. However, when the GaN substrate is a square substrate with a minor axis of less than 50 mm or a wafer with a diameter of less than 50 mm, there may be no position 12.5 mm or 25 mm from the center. In such cases, the Si concentration is measured by SIMS at three locations on the surface of the Si-doped GaN layer: the center, the edge, and the midpoint between the center and the edge, and the maximum value is taken as α and the minimum value is taken as β.

[0128] It can be said that the smaller the value expressed by the above [{(α-β) / α}×100] (%), that is, the smaller the difference between the maximum value α and the minimum value β of the Si concentration, the more uniformly the low resistance corresponding to the doped Si concentration can be achieved across the entire substrate.

[0129] In the fourth embodiment, the thickness of the Si-doped GaN layer is preferably 50 μm or more. This allows the Si-doped GaN layer alone to have self-supporting properties, and even when a GaN substrate consisting of only the Si-doped GaN layer is formed, it can function as a substrate. The thickness of the Si-doped GaN layer is preferably 50 to 300 μm. Here, the thickness is preferably 50 μm or more, more preferably 80 μm or more, and even more preferably 100 μm or more. There is no particular limit to the upper limit of the thickness, but it may be, for example, 300 μm or less, or may be 200 μm or less, or 150 μm or less. Note that the thickness of the Si-doped GaN layer in this specification refers to a thickness of the Si-doped GaN layer when the Si concentration is 1×10 １８ atoms / cm ３ The thickness of the Si-doped GaN layer is equal to or greater than 100 nm, and can be measured by the SIMS method described above. If the thickness of the Si-doped GaN layer is not uniform, the thinnest minimum thickness should be within the above range.

[0130] In the fourth embodiment, the Si-doped GaN layer may contain, in addition to Si (silicon), a Group 14 element such as Ge (germanium) or a Group 16 element such as O (oxygen) or S (sulfur) as donor impurities. The total concentration of donor impurities other than Si is, for example, 10% or less of the Si concentration, and may be 5% or less, 1% or less, or 0%, i.e., may not be contained.

[0131] As will be described later, the GaN substrate according to the fourth embodiment is preferably grown by, for example, vapor phase epitaxy, and more preferably by hydride vapor phase epitaxy (HVPE). The Si-doped GaN layer obtained by the above method contains 100% O (oxygen) even if not intentionally added. １５ atoms / cm ３ In other words, the Si-doped GaN layer can have an O (oxygen) concentration of 1×10 １５ atoms / cm ３ It may be more than that.

[0132] On the other hand, the Si-doped GaN layer contains non-negligible concentrations of donor impurities other than Si and O when intentionally doped with such donor impurities. Note that "intentional doping" refers to the case where a target element is added as a single element or a compound as a raw material in order to dope the Si-doped GaN layer with the target element.

[0133] Therefore, unless the Si-doped GaN layer is intentionally doped with a donor impurity other than Si and O, the total donor impurity concentration of the Si-doped GaN layer may be considered to be equal to the sum of the Si concentration and the O concentration. Whether or not the Si-doped GaN layer is doped with a donor impurity other than Si and O can be confirmed by elemental analysis or the like.

[0134] The concentration of donor impurities other than Si is set to 1×10 １７ atoms / cm ３ Preferably less than 8 x 10 １６ atoms / cm ３ Less than 5 x 10 is more preferable. １６ atoms / cm ３For the same reason, the total concentration of donor impurities other than Si is more preferably 2×10 １７ atoms / cm ３ Preferably less than 8 x 10 １６ atoms / cm ３ Less than 5 x 10 is more preferable. １６ atoms / cm ３ The following is even more preferred:

[0135] The Si-doped GaN layer may contain elements other than the Ga, N, and Si that constitute the GaN crystal, as well as the Group 14 and Group 16 element atoms that act as other donor impurities. The other elements may be intentionally or unintentionally contained, and examples thereof include H (hydrogen), C (carbon), and Cl (chlorine). The total concentration of these other elements is 10 １６ ~10 １７ atoms / cm ３ Orders are also accepted.

[0136] The full width at half maximum of the rocking curve obtained by (004) X-ray diffraction of the Si-doped GaN layer is preferably 50 arcsec or less. The rocking curve is a diffraction intensity distribution obtained when the direction of the incident X-rays and the position of the detector are fixed and only the crystal sample is rotated in X-ray diffraction measurement, and is an index of crystal quality.

[0137] The smaller the full width at half maximum of the rocking curve, the fewer the crystal defects and the better the crystal quality. The full width at half maximum is preferably 40 arcsec or less, more preferably 30 arcsec or less, and even more preferably 20 arcsec or less. The lower limit of the full width at half maximum is not particularly limited, but is usually 5 arcsec or more. In this specification, the full width at half maximum is synonymous with what is generally referred to as the half width. That is, the maximum intensity f of the peak ｍａｘ For half the strength, 1 / 2f ｍａｘ This means the distance between the positions indicated.

[0138] The full width at half maximum can be adjusted by the growth method (vapor phase method, liquid phase method, or the like) of the GaN crystal layer in the Si-doped GaN layer, the crystal characteristics of the seed substrate used when growing the GaN crystal layer, the crystal growth conditions, the selection of the growth surface, the impurity content, etc.

[0139] In the fourth embodiment, the dislocation density at the surface of the Si-doped GaN layer is 5×10 ６ cm －２ In this case, it is possible to suppress the degradation of device performance due to dislocations. From the same viewpoint, the dislocation density on the surface of the Si-doped GaN layer is preferably 2×10 or less. ６ cm －２ More preferably, 1×10 ６ cm －２ The following is even more preferable: The dislocation density of the Si-doped GaN layer is preferably equal to or greater than the dislocation density of the GaN crystal layer serving as the underlying crystal layer, and more specifically, is preferably 0.5 to less than 2 times the dislocation density of the GaN crystal layer serving as the underlying crystal layer. Furthermore, the fact that both dislocation densities are the same or nearly the same means that no new dislocations are generated at the GaN crystal layer / Si-doped GaN layer interface.

[0140] In the fourth embodiment, the GaN crystal layer on which the Si-doped GaN layer is formed serves as an underlayer crystal, and is a layer on which GaN is epitaxially grown. The GaN crystal layer has a resistivity of 1×10 at room temperature. ５ The layer may be less than Ωcm, i.e. not semi-insulating.

[0141] In the fourth embodiment, the GaN crystal layer may unintentionally and unavoidably contain elements other than Ga and N, such as Si, O, and H. For example, the Si concentration is 5×10 １７ atoms / cm ３ The O concentration may be 2×10 １７ atoms / cm ３ The H concentration may be 5×10 １６ atoms / cm ３ The concentration of each of the other elements may be 5×10 or less. １５ atoms / cm ３ It may be the following:

[0142] In the fourth embodiment, when the GaN substrate is used to manufacture a nitride semiconductor device, the GaN crystal layer may be removed and the Si-doped GaN layer may be used for the nitride semiconductor device chip. In such a use, there are no particular requirements for the electrical properties of the GaN crystal layer.

[0143] The Si-doped GaN layer in the GaN substrate may be formed directly on the c-plane of the GaN crystal layer, or may be formed via a regrowth interface. The regrowth interface refers to the boundary surface that occurs when crystals that will become the Si-doped GaN layer grow on the GaN crystal layer, and its existence can be confirmed, for example, by observing the cross section of the GaN substrate wafer using a scanning electron microscope, cathodoluminescence observation, or fluorescence microscope. The regrowth interface can exist when the steps of growing the GaN crystal layer and the Si-doped GaN layer are not continuous.

[0144] The conductivity type, i.e., carrier type, of the Si-doped GaN layer in the GaN substrate according to the fourth embodiment is typically n-type. The resistivity of the Si-doped GaN layer in the fourth embodiment at 300 K is 1×10 －２ Ωcm or less is preferable, and 8×10 －３ Ωcm or less is more preferable, and 4×10 －３ The lower the resistivity, the better. －５ The resistivity is Ωcm or more. The lower the resistivity, the higher the electron mobility, enabling high-temperature and high-speed operation and a high-output nitride semiconductor device. The resistivity of the Si-doped GaN layer can be measured using the four-terminal Van der Pauw method, with terminals connected to the Si-doped GaN layer.

[0145] The GaN substrate according to the fourth embodiment is preferably used as a wafer, but the shape of the main surface may be square, rectangular, hexagonal, octagonal, elliptical, or the like, and is not particularly limited. It may also be an irregular shape.

[0146] When the GaN substrate according to the fourth embodiment is a wafer, in consideration of nitride semiconductor applications, its diameter is usually 45 mm or more, but may be 50 mm or more, 95 mm or more, or 145 mm or more. It is typically 50 to 55 mm (about 2 inches), 100 to 105 mm (about 4 inches), 150 to 155 mm (about 6 inches), etc. Furthermore, when the GaN crystal has a shape other than a disk, a size can be adopted such that the diameter of the disk having the same area as the main surface is the above-mentioned size.

[0147] The preferred thickness of the GaN substrate varies depending on the diameter of the primary surface. When the diameter is approximately 2 inches, the thickness of the GaN substrate is preferably 250 to 450 μm. Here, the thickness is preferably 250 μm or more, more preferably 300 μm or more, even more preferably 350 μm or more, and preferably 450 μm or less, and more preferably 400 μm or less. When the diameter is approximately 4 inches, the thickness of the GaN substrate is preferably 350 to 750 μm. Here, the thickness is preferably 350 μm or more, more preferably 400 μm or more, and preferably 750 μm or less, more preferably 650 μm or less, and even more preferably 600 μm or less. When the diameter is approximately 6 inches, the thickness of the GaN substrate is preferably 450 to 800 μm. Here, the thickness is preferably 450 μm or more, more preferably 550 μm or more, and preferably 800 μm or less, and more preferably 700 μm or less. When the GaN substrate is made of only a Si-doped GaN layer, the thickness of the Si-doped GaN layer is preferably within the above range.

[0148] The (000-1) surface 102, which is the N-polar surface of the GaN substrate according to the fourth embodiment, serves as the back surface and may be mirror-finished, roughened, or matte-finished. The (0001) surface 101, which is the Ga-polar surface of the GaN substrate, serves as the front surface and is used in a nitride semiconductor device by further epitaxially growing a nitride semiconductor layer on this surface.

[0149] The (0001) surface 101, which is a Ga polar surface, may be an as-grown surface as it is after crystal growth, but is preferably a surface that has been planarized by processing such as polishing, CMP (Chemical Mechanical Polishing), etching, etc. The (0001) surface 101 may also be a surface formed by cutting, or may be a surface that has been subjected to the above-mentioned planarization without cutting.

[0150] The root mean square roughness (RMS) of the (0001) surface 101 of the GaN substrate according to the fourth embodiment, measured with an atomic force microscope (AFM), is preferably less than 5 nm, more preferably less than 2 nm, even more preferably less than 1 nm, and may be less than 0.5 nm, within a measurement range of 2 μm×2 μm.

[0151] The edges of the GaN substrate according to the fourth embodiment may be chamfered. Even in this case, the value of the Si concentration expressed as [{(α-β) / α}×100] (%) is 10% or less. Furthermore, various markings may be applied to the GaN substrate as needed, such as an orientation flat or notch to indicate the crystal orientation, or an index flat to easily distinguish between the front and back surfaces.

[0152] The semiconductor device using the GaN substrate according to the fourth embodiment is basically a nitride semiconductor device, which is a semiconductor device in which the main part of the device structure is formed from a nitride semiconductor.

[0153] The nitride semiconductor is also called a nitride-based Group III-V compound semiconductor, a Group III nitride-based compound semiconductor, a GaN-based semiconductor, or the like, and includes GaN as well as compounds in which part or all of the gallium in GaN is substituted with another Group 13 element of the periodic table (B, Al, In, etc.).

[0154] There is no limitation on the type of nitride semiconductor device in which the GaN substrate according to the fourth embodiment is used, and examples include light-emitting devices such as laser diodes (LDs) and light-emitting diodes (LEDs), and electronic devices such as rectifiers, bipolar transistors, and field-effect transistors.

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[0156] Therefore, in the present invention, the maximum Si concentration at the surface of the Si-doped GaN layer is set to α (atoms / cm ３ ), the minimum value is β (atoms / cm ３ The present invention also relates to a method for producing a Si-doped GaN layer in which the value expressed by [{(α-β) / α}×100] (%) is 10% or less when the Si concentration is 1×10 １８ atoms / cm ３ The present invention relates to a method for producing the above-described Si-doped GaN layer on a base crystal by vapor phase epitaxy, characterized in that the off-angle of the base crystal is 0.5° or more, and the distance between the nozzle opening for spraying a gas containing Ga atoms onto the base crystal and the surface of the base crystal is preferably 100 mm or more. Here, the thickness of the Si-doped GaN layer is preferably 50 μm or more.

[0157] That is, one aspect of the method for producing a GaN substrate described above in [GaN substrate (2)] includes the method for producing the Si-doped GaN layer as one step.

[0158] The base crystal for forming the Si-doped GaN layer is preferably a c-plane GaN substrate seed, and the Si-doped GaN layer, i.e., a (0001)-oriented GaN layer doped with Si, is grown on its surface by vapor phase epitaxy.

[0159] Fig. 2 is an explanatory diagram of the off-angle provided to the underlayer crystal used in the method for forming the Si-doped GaN layer. In Fig. 2(a), the underlayer crystal is cut at an angle indicated by the dashed line with respect to the (0001) surface. Fig. 2(b) shows the underlayer crystal after cutting, and Fig. 2(c) is an enlarged view of the circled area.

[0160] As shown in Figure 2(c), the angle at which the (0001) surface of the base crystal is cut is called the off-angle θ, and the cut surface becomes stepped with a step the thickness of one atom when cut. The terrace width W, which represents the width of the terrace T, varies depending on the off-angle θ when cutting. That is, the smaller the off-angle θ, the wider the terrace width W. As shown in Figure 3, when the off-angle θ is increased compared to Figure 2(c), the terrace width W becomes narrower.

[0161] Here, the reason why the terrace width W is narrowed by setting the off-angle θ to 0.5° or more is that, specifically, as shown in FIG. 2C, the wider the terrace width W, the longer it takes for Si adatoms adsorbed on the surface of the terrace T to migrate to and reach the step edge E where the kink site S is located, which is a growth site necessary for incorporation into the GaN crystal. In contrast, as shown in FIG. 3, by making the off-angle θ of the base crystal larger than conventionally, the terrace width W is narrowed, and the time it takes for the adatoms to migrate to and reach the step edge E where the kink site S is located is shortened. As a result, Si atoms are more likely to enter appropriate sites.

[0162] In the reactor 21 shown in FIG. 7, a gas containing Ga atoms is injected onto the base crystal through an introduction pipe P ３ By setting the distance L between the nozzle opening and the surface of the underlying crystal to preferably 100 mm or more, the gas is diffused more effectively, and as a result, Si atoms are more likely to be incorporated into appropriate sites.

[0163] The Si concentration in the Si-doped GaN layer is 1×10 １８ atoms / cm ３When Si is highly doped to a high concentration of 0.5° or more, the uniformity of the Si concentration on the surface of the Si-doped GaN layer is reduced in the conventional method. However, when the off-angle θ is set to 0.5° or more and a gas containing Ga atoms is injected into the base crystal through an introduction pipe P ３ By making the distance L between the nozzle opening and the surface of the underlying crystal preferably 100 mm or more, the Si concentration at the edge of the substrate can be made as high as that near the center of the substrate, and low resistance corresponding to the doped Si concentration can be achieved uniformly across the entire substrate.

[0164] Therefore, to obtain the Si-doped GaN layer in the fourth embodiment, the off-angle of the base crystal is preferably 0.5 to 1°. Here, the off-angle is preferably 0.5° or more, more preferably 0.55° or more, and even more preferably 0.6° or more. On the other hand, from the viewpoints of suppressing bunching and maintaining the plane orientation characteristics of the C-plane, the off-angle is preferably 1° or less, more preferably 0.9° or less, and even more preferably 0.8° or less.

[0165] In addition, a gas containing Ga atoms is injected onto the substrate crystal through an introduction pipe P ３ The distance L between the nozzle opening and the surface of the base crystal is preferably 100 to 300 mm. Here, the distance L is preferably 100 mm or more, more preferably 110 mm or more, and even more preferably 120 mm or more. On the other hand, from the viewpoint of maintaining the growth rate, the distance L is preferably 300 mm or less, more preferably 250 mm or less, and even more preferably 200 mm or less. From the viewpoint of further improving the uniformity of the Si concentration, the introduction pipe P, which ejects a gas containing N atoms onto the base crystal, １ and dopant introduction tube P ４ The nozzle opening of the introduction pipe P ３ It is preferable to install the nozzle on the same horizontal line as the nozzle opening of the introduction pipe P. １ and introduction pipe P ４ The distance L between the nozzle opening and the surface of the substrate crystal is ３ It is preferable that the distance L between the nozzle opening and the surface of the underlying crystal is equal to the distance L between the nozzle opening and the surface of the underlying crystal. In this case, the uniformity of the Si concentration can be further improved.

[0166] With respect to the other factors than the off-angle of the underlying crystal and the distance L, a conventionally known manufacturing method can be employed to obtain the GaN substrate having the Si-doped GaN layer according to the fourth embodiment.

[0167] For example, as shown in Fig. 4(a), a seed wafer 1 is prepared, and a first GaN thick film 2 made of intentionally undoped GaN and oriented in the (0001) direction is grown thereon by HVPE or the like, as shown in Fig. 4(b). Furthermore, as shown in Fig. 4(c), the first GaN thick film 2 may be processed as necessary to obtain a plurality of first c-plane GaN wafers 3.

[0168] An example of the seed wafer 1 is a c-plane sapphire wafer, preferably provided with a release layer on its main surface. When providing a release layer, a GaN layer several hundred nanometers thick is grown on the c-plane sapphire wafer via a low-temperature buffer layer by metalorganic vapor phase epitaxy (MOVPE), and then a Ti (titanium) layer several tens of nanometers thick is formed on the GaN layer by vacuum deposition. Then, for example, a 80% H ２ (hydrogen) and 20% NH ３ The peeling layer can be formed by annealing the film at 1060° C. for 30 minutes in a mixed gas atmosphere of (ammonia).

[0169] The first GaN thick film 2 is preferably thick enough to form a free-standing first c-plane GaN wafer 3, and is preferably grown to a thickness of, for example, several mm or more, from which two or more first c-plane GaN wafers 3 can be obtained.

[0170] As shown in Fig. 5(b), a second GaN thick film 4 made of intentionally undoped GaN and oriented in the (0001) direction is grown by HVPE on the (0001) crystal plane of the Ga polarity plane of the first c-plane GaN wafer 3 obtained as described above and shown in Fig. 5(a). Then, as shown in Fig. 5(c), the second GaN thick film 4 may be processed as necessary to obtain a plurality of second c-plane GaN wafers 5.

[0171] The second c-plane GaN wafer 5 obtained as described above will serve as the base crystal for forming the Si-doped GaN layer. Before cutting the wafer obliquely to the (0001) crystal plane of the Ga polarity plane, it may be subjected to appropriate planarization processing using grinding, polishing, CMP, or other techniques, as desired. Furthermore, after planarization, it may be subjected to surface roughening processing by etching. Conventional methods can be used for planarization and surface roughening.

[0172] The off-angle, which is the inclination angle when cutting obliquely with respect to the (0001) crystal plane of the Ga polar plane, is preferably 0.5° or more as described above, and the off-cut direction, which is the inclination direction, is preferably the m-axis direction or the a-axis direction.

[0173] The (0001) crystal plane of the GaN crystal layer can be cut out using a wire slicer or a laser slicer.

[0174] A Si-doped GaN layer 6a is formed on the (0001) crystal plane of the second c-plane GaN wafer 5, the surface of which is cut out as shown in Fig. 6(a). Between the second c-plane GaN wafer 5 and the Si-doped GaN layer 6a, a Si-doped GaN layer having a Si concentration of 1 × 10 is formed as shown in Fig. 6(b). １８ atoms / cm ３ There may be an intervening region 6b having a thickness of less than 1 / 2 mm.

[0175] When growing the above-mentioned GaN crystal or Si-doped GaN crystal by the HVPE method, for example, an HVPE apparatus 20 shown in FIG. 7 can be used.

[0176] 7 includes a hot-wall reactor 21, a gallium reservoir 22 and a susceptor 23 disposed within the reactor 21, and a first heater 24 and a second heater 25 disposed outside the reactor 21. The first heater 24 and the second heater 25 each surround the reactor 21 in an annular shape.

[0177] The reactor 21 is a quartz tube chamber. Inside the reactor 21, there are a first zone Z1 that is mainly heated by a first heater 24 and a second zone Z2 that is mainly heated by a second heater 25. An exhaust pipe P Ｅis connected to the end of the reactor 21 on the second zone Z2 side. The gallium reservoir 22 disposed in the first zone Z1 is a quartz container having a gas inlet and a gas outlet. The susceptor 23 disposed in the second zone Z2 is made of, for example, graphite. A mechanism for rotating the susceptor 23 can be provided as desired.

[0178] To grow GaN in the HVPE apparatus 20, a seed is placed on the susceptor 23, and the inside of the reactor 21 is heated by the first heater 24 and the second heater 25. At the same time, NH 3 diluted with a carrier gas is heated. ３ (ammonia) through the ammonia inlet pipe P １ into the second zone Z2 through a hydrogen chloride inlet pipe P ２ This HCl reacts with metallic gallium in the gallium reservoir 22, and the resulting GaCl (gallium chloride) is introduced through the gallium chloride introduction pipe P ３ The substrate surface in the second zone Z2 and the gallium chloride introduction pipe P ３ As mentioned above, the distance L between the nozzle opening of the ammonia introduction pipe P and the nozzle opening of the ammonia introduction pipe P is preferably 100 mm or more. １ and dopant introduction tube P ４ The nozzle opening is connected to the gallium chloride introduction tube P ３ It is preferable to install the nozzle on the same horizontal plane as the nozzle opening.

[0179] NH in the second zone Z2 ３ and GaCl react with each other, and the resulting GaN crystallizes on the seed placed on the susceptor 23. When intentionally doping the growing GaN, a doping gas diluted with a carrier gas is introduced through a dopant introduction pipe P ４ The ammonia is introduced into the second zone Z2 in the reactor 21 through the ammonia introduction pipe P １ , hydrogen chloride introduction pipe P ２ , gallium chloride introduction tube P ３ and dopant introduction tube P ４ The part of the NH 3 that is placed inside the reactor 21 is made of quartz. ３The carrier gas for diluting each of the HCl and doping gas is H ２ (hydrogen gas), N ２ (nitrogen gas) or H ２ and N ２ A mixed gas of the above is preferably used.

[0180] The preferred conditions for growing GaN using the HVPE apparatus 20 are as follows: The temperature of the gallium reservoir 22 is, for example, 500 to 1000°C, preferably 700°C or higher, and preferably 900°C or lower. The temperature of the susceptor 23 is, for example, 900 to 1100°C, preferably 930°C or higher, more preferably 950°C or higher, and preferably 1050°C or lower, more preferably 1020°C or lower.

[0181] NH in reactor 21 ３ The V / III ratio, which is the ratio of the GaCl partial pressure (V) to the GaCl partial pressure (III), is, for example, 1 to 20, preferably 2 or more, more preferably 3 or more, and preferably 10 or less. If the V / III ratio is too large or too small, it will cause deterioration in the morphology of the GaN growth surface. Deterioration in the morphology of the growth surface can cause a decrease in crystal quality.

[0182] The growth rate of GaN was determined by the NH ３ The growth rate can be controlled by using the product of the partial pressure and the GaCl partial pressure as a parameter. The growth rate is, for example, 20 to 200 μm / h, and when growing a Si-doped GaN layer, it is preferably 120 μm / h or less, more preferably 100 μm / h or less, and even more preferably 80 μm / h or less. An excessively high growth rate deteriorates the surface morphology of the grown GaN.

[0183] When doping with Si, it is preferable to gradually increase the supply rate of the doping gas to a predetermined value over a period of several minutes to several tens of minutes from the start of supply in order to prevent deterioration of the morphology of the growth surface. For the same reason, it is preferable to start supplying the doping gas when the GaN layer has grown to at least several μm.

[0184] The doping gas for Si doping is SiH ４(silane), SiH ３ Cl (monochlorosilane), SiH ２ Cls (dichlorosilane), SiHCl ３ (trichlorosilane) or SiCl ４ (tetrachlorosilane) is preferred. The partial pressure of the doping gas for Si doping is 1×10 －６ ~2 x 10 －４ kPa is preferred, and 2×10 －６ kPa or more is more preferable, and 1 × 10 －４ kPa or less is more preferable.

[0185] H in the carrier gas ２ The molar ratio of H in the carrier gas can affect the impurity concentration of the grown GaN. ２ The molar ratio of is calculated based on the flow rate of each gas species supplied as a carrier gas from outside the reactor into the reactor. The O concentration of GaN grown by the HVPE method when doped with Si is calculated based on the H ２ When the molar ratio of １６ atoms / cm ３ Below, further 1 x 10 １６ atoms / cm ３ This is due to the improved surface morphology during growth.

[0186] GaN grown using the HVPE apparatus 10 may contain O at concentrations detectable by SIMS, even when not intentionally doped. The O source is the quartz (SiO ２ ) and / or moisture remaining or penetrating into the reactor. In addition to the Si from the doping gas, the Si is also present in the reactor and quartz (SiO ２ ) as a Si source.

[0187] 7, the components arranged in the reactor 11 can be made of quartz and carbon, as well as silicon carbide (SiC), silicon nitride (SiNx), boron nitride (BN), alumina, tungsten (W), molybdenum (Mo), etc. As a result, the concentration of each impurity except for Si, O, and H in GaN grown using the HVPE apparatus 10 is 5×10 or less unless intentional doping is performed. １５ atoms / cm ３ It can be as follows:

[0188] The method for manufacturing a Si-doped GaN layer according to the fourth embodiment may include a step of planarizing the Ga-polar surface of the manufactured Si-doped GaN layer, which may be an as-grown surface as crystals are grown. The planarization step may be performed by known processing methods such as polishing, CMP (Chemical Mechanical Polishing), and etching.

[0189] The method for manufacturing a Si-doped GaN layer according to the fourth embodiment may include slicing the Si-doped GaN layer grown on the base crystal to obtain one or more freestanding GaN substrates. In this case, a thick Si-doped GaN layer is grown to a thickness sufficient to obtain a freestanding GaN substrate. When slicing a Si-doped GaN substrate to obtain a freestanding GaN substrate, the plane orientation of the primary surface cut out during slicing can be adjusted as desired. For example, by slicing the freestanding GaN substrate so as to have a lower off-angle from the as-grown Ga-polar surface of the Si-doped GaN layer, a GaN substrate having a Si-doped GaN layer with a primary surface having a lower off-angle can be obtained. This method can also be used to obtain the GaN substrates according to the first and second embodiments. In this case, the off-angle of the primary surface of the obtained GaN substrate does not necessarily have to match the off-angle of the primary surface of the base crystal used in the manufacturing process.

[0190] The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.

[0191] [Example 1-1] 1. Epitaxial Growth of GaN Crystal Using a vapor phase growth apparatus equipped with a quartz hot-wall reactor, a Si-doped GaN layer was epitaxially grown by HVPE on a freestanding GaN seed with a diameter of 62 mm and a thickness of 400 μm. The offcut direction and off-angle of the freestanding GaN seed were the m-axis direction and 0.55°. In this process, the following steps were sequentially performed: (1) a temperature increase step, (2) a Si-doped GaN layer growth step, and (3) a cooling step.

[0192] (1) Temperature-raising step First, a free-standing GaN seed was placed in a reactor. Next, the reactor temperature was raised from room temperature to 1000°C while supplying ammonia and a carrier gas to the free-standing GaN seed. A mixed gas of hydrogen gas and nitrogen gas was used as the carrier gas.

[0193] (2) Si-doped GaN layer growth step: While maintaining the reactor temperature at 1000° C., a mixed gas containing ammonia and gallium chloride was supplied as a source gas under the following growth conditions to epitaxially grow a Si-doped GaN layer to a thickness of 200 μm on the freestanding GaN seed. The growth rate was 50 μm / hr, and the growth conditions were: reactor pressure 101 kPa, ammonia partial pressure 2.57 kPa, GaCl partial pressure 1.23 kPa, hydrogen gas partial pressure 51.67 kPa, nitrogen gas partial pressure 45.40 kPa, HCl gas partial pressure 0.13 kPa, and dichlorosilane partial pressure 4.36×10 －５ The gas partial pressure (P Ｇ ) is the ratio (r) of the volumetric flow rate of the gas in question to the total volumetric flow rate of all gases supplied into the reactor, expressed as a function of the reactor pressure (P Ｒ ), that is, P Ｇ = r × P Ｒ The value is expressed as:

[0194] (3) Cooling Step After completing the Si-doped GaN layer growth step (2) above, the supply of gallium chloride to the freestanding GaN seeds was stopped, and the reactor heating was stopped to allow the reactor temperature to drop to room temperature. The gases flowing into the reactor were ammonia and nitrogen gas until the temperature dropped to 600°C, and then only nitrogen gas. The surface of the as-grown GaN crystal removed from the reactor was mirror-finished and flat across the entire surface.

[0195] 2. Fabrication of GaN Substrates Laser coring was performed on the as-grown GaN crystal obtained in 1 above to obtain a GaN substrate that would serve as a circular epitaxial substrate with a diameter of 50.8 mm. Next, lapping and polishing of the +C and -C faces were performed sequentially to complete a 2-inch c-plane GaN substrate with a Si-doped GaN layer thickness of 100 μm and a GaN crystal layer thickness of 300 μm. The offcut direction and off angle of the c-plane GaN substrate were in the m-axis direction and 0.55°.

[0196] 3. Evaluation of GaN Substrates <Observation of Recesses on the Surface of the Si-Doped GaN Layer> The GaN substrates used to form the circular epitaxial substrates obtained in 2. above were irradiated with ultraviolet light and observed to obtain fluorescent images. The results are shown in FIG. 8 , and no recesses accompanied by repelling were observed on the surface of the Si-doped GaN layer. That is, on the surface of the Si-doped GaN layer of the GaN substrate, the total bottom area of ​​the recesses with a depth of 5 μm or more was 0% of the total surface area of ​​the Si-doped GaN layer. Furthermore, on the surface of the Si-doped GaN layer of the GaN substrate, one or more 25 mm × 25 mm square lattices without recesses with a depth of 5 μm or more were found.

[0197] <Measurement of Si concentration> The Si concentration of the Si-doped GaN layer in the c-plane GaN substrate obtained above was measured by SIMS. As a result, the Si concentration was 7×10 １８ atoms / cm ３ It was.

[0198] [Example 1-2] The GaN substrate obtained in Example 1-1 is a substrate in which the GaN crystal layer used is a free-standing GaN seed, i.e., an undoped GaN seed, and a Si-doped GaN layer is formed on top of it. Therefore, it is difficult to measure the carrier concentration accurately by Hall measurement. Therefore, instead of the free-standing GaN seed in Example 1-1, a Si-doped GaN layer was formed on top of the free-standing GaN seed. １８ atoms / cm ３ A Si-doped GaN layer was grown on a semi-insulating GaN seed, which was a Mn-doped GaN substrate having a resistivity of 1×10. The Si-doped GaN layer was grown under the same growth conditions as in Example 1-1, except that the growth time was changed so that the thickness of the Si-doped GaN layer was 50 μm. Here, the resistivity of the Mn-doped GaN substrate was 1×10. ２０ Since the resistivity is Ωcm or more, no current flows through the semi-insulating GaN seed during Hall measurements, making it possible to perform accurate Hall measurements. The surface of the as-grown GaN crystal removed from the reactor after the cooling step was mirror-finished and flat all over.

[0199] <Observation of Recesses on the Surface of the Si-Doped GaN Layer> Fluorescent images of the surface of the asgrown GaN crystal were obtained in the same manner as in Example 1-1, and no recesses accompanied by cissing were observed on the surface of the Si-doped GaN layer. That is, on the surface of the Si-doped GaN layer of the GaN substrate, the total bottom area of ​​the recesses with a depth of 5 μm or more was 0% of the total surface area of ​​the Si-doped GaN layer. Furthermore, on the surface of the Si-doped GaN layer of the GaN substrate, one or more 25 mm × 25 mm square lattices without recesses with a depth of 5 μm or more were found.

[0200] <Measurement of Si concentration> The Si concentration of the Si-doped GaN layer in the c-plane GaN substrate obtained above was measured by SIMS. As a result, the Si concentration was 7×10 １８ atoms / cm ３ It was.

[0201] <Measurement of Carrier Concentration, Resistivity, and Carrier Type> For Hall measurements, 30 nm of Ti and 100 nm of Au were successively vacuum-deposited on the surface of the c-plane GaN substrate obtained above. Hall measurements were performed at 300 K using the four-terminal Van der Pauw method, with terminals connected to the Si-doped GaN layer of the substrate. As a result, the carrier concentration of the Si-doped GaN layer was 7×10 １８ atoms / cm ３ , resistivity is 5 x 10 －３ From this result, the Si concentration of the Si-doped GaN layer was determined to be a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100} (%), i.e., the activation rate, was 100%.

[0202] [Example 1-3] In the growth conditions for the Si-doped GaN layer growth step, the dichlorosilane partial pressure was set to 6.16 × 10 －５ Asgrown GaN crystals were obtained in the same manner as in Example 1-2, except that the pressure was changed to 100 kPa. The asgrown GaN crystals taken out of the reactor after the cooling step had a flat, mirror-like surface over the entire surface.

[0203] <Observation of Recesses on the Surface of the Si-Doped GaN Layer> Fluorescent images of the surface of the asgrown GaN crystal were obtained in the same manner as in Example 1-1, and as a result, no recesses accompanied by repelling were observed on the surface of the Si-doped GaN layer. That is, on the surface of the Si-doped GaN layer of the GaN substrate, the total bottom area of ​​the recesses with a depth of 5 μm or more was 0% of the total surface area of ​​the Si-doped GaN layer. Furthermore, on the surface of the Si-doped GaN layer of the GaN substrate, one or more 25 mm × 25 mm square lattices without recesses with a depth of 5 μm or more were found.

[0204] <Measurement of Si concentration> The Si concentration of the Si-doped GaN layer in the c-plane GaN substrate obtained above was measured by SIMS. As a result, the Si concentration was 9×10 １８ atoms / cm３ It was.

[0205] <Measurement of Carrier Concentration, Resistivity, and Carrier Type> Hall measurements were carried out at 300 K in the same manner as in Example 1-2. As a result, the carrier concentration of the Si-doped GaN layer was 9×10 １８ atoms / cm ３ , resistivity is 3.5 × 10 －３ The carrier type was n-type, and the activation rate was 100%.

[0206] Comparative Example 1-1 A Si-doped GaN layer was grown in the same manner as in Example 1-1, except that the offcut direction and off angle of the free-standing GaN seed were set to the m-axis direction and 0.35°, and an as-grown GaN crystal was obtained.

[0207] A fluorescent image of the surface of the asgrown GaN crystal was obtained in the same manner as in Example 1-1. The fluorescent image is shown in Figure 9, and depressions due to repelling were observed on the surface of the Si-doped GaN layer. The depth of the depressions that became depression defects was approximately 200 μm, which was almost equal to the growth thickness of the Si-doped GaN layer. Furthermore, the total bottom area of ​​depressions with a depth of 5 μm or more was 16% of the total surface area of ​​the Si-doped GaN layer, and the total bottom area of ​​depression defects was 16% or more.

[0208] Comparative Example 1-2 An as-grown GaN crystal was obtained by growing a Si-doped GaN layer in the same manner as in Example 1-1, except that the offcut direction and off angle of the free-standing GaN seed were set to the a-axis direction and 0.40°.

[0209] A fluorescent image of the surface of the asgrown GaN crystal was obtained in the same manner as in Example 1-1. As a result, depressions due to repelling were observed on the surface of the Si-doped GaN layer. The depth of the depressions that became depression defects was approximately 200 μm, which was almost equal to the growth thickness of the Si-doped GaN layer. Furthermore, the total bottom area of ​​depressions with a depth of 5 μm or more was more than 16% of the total surface area of ​​the Si-doped GaN layer, and the total bottom area of ​​depression defects was also more than 16%.

[0210] [Reference Example 1-1] A c-plane GaN substrate with a diameter of 50.8 mm was obtained in the same manner as in Example 1-1, except that a Si-doped GaN layer on a free-standing GaN seed was epitaxially grown to a thickness of 5 mm to obtain an as-grown GaN crystal, and the obtained as-grown GaN crystal was sliced ​​with a wire saw, followed by laser coring and surface polishing. The offcut direction and off angle of the c-plane GaN substrate were the m-axis direction and 0.35°.

[0211] <Measurement of Carrier Concentration, Resistivity, and Carrier Type> Hall measurements were carried out at 300 K in the same manner as in Example 1-2. As a result, the carrier concentration of the Si-doped GaN layer was 5×10 １８ atoms / cm ３ , resistivity is 4.9 × 10 －３ The carrier type was n-type.

[0212] As this reference example suggests, by modifying the crystal growth conditions and processing conditions of Example 1-1, it is possible to obtain a c-plane GaN substrate having an off-angle different from the off-angle of the free-standing GaN seed.

[0213] Example 2-1 1. Epitaxial Growth of GaN Crystal Using a vapor phase growth apparatus equipped with a quartz hot-wall reactor, a Si-doped GaN layer was epitaxially grown by HVPE on a freestanding GaN seed with a diameter of 62 mm and a thickness of 400 μm. The offcut direction and off-angle of the freestanding GaN seed were the m-axis direction and 0.55°. The distance L between the GaCl gas nozzle outlet and the freestanding GaN seed surface was 150 mm. The ammonia gas nozzle outlet and the dopant gas nozzle outlet were installed on the same horizontal plane. That is, the distance L between the ammonia gas nozzle outlet and the dopant gas nozzle outlet and the freestanding GaN seed surface was also 150 mm. In this process, the following steps were sequentially performed: (1) a temperature increase step, (2) a Si-doped GaN layer growth step, and (3) a cooling step.

[0214] (1) Temperature-raising step First, a free-standing GaN seed was placed in a reactor. Next, the reactor temperature was raised from room temperature to 1000°C while supplying ammonia and a carrier gas to the free-standing GaN seed. A mixed gas of hydrogen gas and nitrogen gas was used as the carrier gas.

[0215] (2) Si-doped GaN layer growth step: While maintaining the reactor temperature at 1000° C., a mixed gas containing ammonia and gallium chloride was supplied as a source gas under the following growth conditions to epitaxially grow a Si-doped GaN layer to a thickness of 200 μm on the freestanding GaN seed. The growth rate was 50 μm / hr, and the growth conditions were: reactor pressure 101 kPa, ammonia partial pressure 2.57 kPa, GaCl partial pressure 1.23 kPa, hydrogen gas partial pressure 51.67 kPa, nitrogen gas partial pressure 45.40 kPa, HCl gas partial pressure 0.13 kPa, and dichlorosilane partial pressure 4.36×10 －５ The gas partial pressure (P Ｇ ) is the ratio (r) of the volumetric flow rate of the gas in question to the total volumetric flow rate of all gases supplied into the reactor, expressed as a function of the reactor pressure (P Ｒ ), that is, P Ｇ = r × P Ｒ The value is expressed as:

[0216] (3) Cooling Step After completing the Si-doped GaN layer growth step (2) above, the supply of gallium chloride to the freestanding GaN seeds was stopped, and the reactor heating was stopped to allow the reactor temperature to drop to room temperature. The gases flowing into the reactor were ammonia and nitrogen gas until the temperature dropped to 600°C, and then only nitrogen gas. The surface of the as-grown GaN crystal removed from the reactor was mirror-finished and flat across the entire surface.

[0217] 2. Fabrication of GaN Substrates The as-grown GaN crystals obtained in step 1 above were subjected to laser coring to obtain circular epitaxial GaN substrates with a diameter of 50.8 mm. Next, the +C and −C faces were sequentially lapped and polished to complete 2-inch c-plane GaN substrates with a Si-doped GaN layer thickness of 100 μm and a GaN crystal layer thickness of 300 μm.

[0218] 3. Evaluation of GaN Substrate <Measurement of Si Concentration> The Si concentration of the Si-doped GaN layer in the c-plane GaN substrate obtained above was measured by SIMS. As a result, the Si concentration at the center of the surface of the Si-doped GaN layer was 7.5 × 10 １８ atoms / cm ３ Furthermore, the in-plane distribution of Si concentration on the surface of the Si-doped GaN layer of the c-plane GaN substrate was measured. Specifically, the Si concentration was measured at three locations on the surface of the Si-doped GaN layer: the center, a position 12.5 mm from the center, and a position 25 mm from the center, i.e., the edge. The maximum value α of the Si concentration was observed at the center, and its value was 7.5 × 10 １８ atoms / cm ３ The minimum value β of the Si concentration was observed at the edge, and its value was 7.4 × 10 １８ atoms / cm ３ As a result, the value expressed as [{(α-β) / α}×100] (%) was 1.3%, which indicated that the Si concentration was uniform over the entire surface of the Si-doped GaN layer, suggesting that a low resistance corresponding to the Si concentration could be achieved uniformly over the entire surface of the GaN substrate.

[0219] [Reference Example 2-1] The GaN substrate obtained in Example 2-1 is a substrate in which the GaN crystal layer used is a free-standing GaN seed, i.e., an undoped GaN seed, and a Si-doped GaN layer is formed thereon. Therefore, it is difficult to measure the carrier concentration accurately by Hall measurement. Therefore, instead of the free-standing GaN seed in Example 2-1, a Si-doped GaN layer was formed thereon. １８ atoms / cm ３A Si-doped GaN layer was grown on a semi-insulating GaN seed, which was a Mn-doped GaN substrate having a resistivity of 1×10. The Si-doped GaN layer was grown under the same growth conditions as in Example 2-1, except that the growth time was changed so that the thickness of the Si-doped GaN layer was 50 μm. Here, the resistivity of the Mn-doped GaN substrate was 1×10. ２０ Since the resistivity is Ωcm or more, no current flows through the semi-insulating GaN seed during Hall measurements, making it possible to perform accurate Hall measurements. The surface of the as-grown GaN crystal removed from the reactor after the cooling step was mirror-finished and flat all over.

[0220] <Measurement of Si concentration> The Si concentration of the Si-doped GaN layer on the c-plane GaN substrate obtained above was measured by SIMS. As a result, the Si concentration at the center of the surface of the Si-doped GaN layer was 7×10 １８ atoms / cm ３ It was.

[0221] <Measurement of Carrier Concentration, Resistivity, and Carrier Type> For Hall measurements, 30 nm of Ti and 100 nm of Au were successively vacuum-deposited on the surface of the c-plane GaN substrate obtained above. Hall measurements were performed at 300 K using the four-terminal Van der Pauw method, with terminals connected to the Si-doped GaN layer of the substrate. As a result, the carrier concentration of the Si-doped GaN layer was 7×10 １８ atoms / cm ３ , resistivity is 5 x 10 －３ From this result, the Si concentration of the Si-doped GaN layer was determined to be a (atoms / cm ３ ), and the carrier concentration is b (atoms / cm ３ ), the value expressed by {(b / a)×100} (%), i.e., the activation rate, was 100%.

[0222] Comparative Example 2-1 In Example 2-1, the offcut direction and off angle of the free-standing GaN seed were set to the m-axis direction and 0.35°, and the distances between the GaCl gas ejection nozzle outlet, the ammonia gas ejection nozzle outlet, and the dopant gas ejection nozzle outlet and the free-standing GaN seed surface were set to 100 mm. In the same manner, a Si-doped GaN layer was grown, and an as-grown GaN crystal was obtained.

[0223] In the same manner as in Example 2-1, a GaN substrate was obtained as a circular epitaxial substrate with a diameter of 50.8 mm. The in-plane distribution of the Si concentration on the surface of the Si-doped GaN layer of the c-plane GaN substrate was then measured. Specifically, the Si concentration was measured at three locations on the surface of the Si-doped GaN layer: the center, a position 12.5 mm from the center, and a position 25 mm from the center, i.e., the edge. The maximum value α of the Si concentration was observed in the center, and its value was 3.9 × 10 １８ atoms / cm ３ The minimum value β of the Si concentration was observed at the edge, and its value was 1.6 × 10 １８ atoms / cm ３ As a result, the value expressed by [{(α-β) / α}×100] (%) was 58%, which indicated that the Si concentration was very non-uniform over the entire surface of the Si-doped GaN layer compared to Example 2-1, suggesting that a reduction in resistance commensurate with the Si concentration could not be achieved uniformly over the entire surface of the GaN substrate.

[0224] Although the present invention has been described in detail and with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention. This application is based on Japanese patent applications filed on December 21, 2022 (Patent Application No. 2022-204832) and Japanese patent applications filed on December 21, 2022 (Patent Application No. 2022-204833), the contents of which are incorporated herein by reference.

[0225] REFERENCE SIGNS LIST 1 seed wafer 2 first GaN thick film 3 first c-plane GaN wafer 4 second GaN thick film 5 second c-plane GaN wafer 6a Si-doped GaN layer 6b intermediate region 20 HVPE apparatus 21 reactor 22 gallium reservoir 23 susceptor 24 first heater 25 second heater 100 GaN substrate 101 (0001) surface 102 (000-1) surface 110 Si-doped GaN layer 120 GaN crystal layer

Claims

1. It has a main surface 1 whose inclination from the (0001) crystal plane, which is a Ga polar plane, is 0 to 10°. A GaN substrate having at least a Si-doped GaN layer on the surface of the main surface 1, The Si concentration in the Si-doped GaN layer is 1 × 10⁻¹⁰ １８ atoms / cm ３ That's all. A GaN substrate in which the total bottom area of ​​concave defects on the surface of the Si-doped GaN layer is 15% or less of the total surface area of ​​the Si-doped GaN layer.

2. It has a main surface 1 whose inclination from the (0001) crystal plane, which is a Ga polar plane, is 0 to 10°. A GaN substrate having at least a Si-doped GaN layer on the surface of the main surface 1, The Si concentration in the Si-doped GaN layer is 1 × 10⁻¹⁰ １８ atoms / cm ３ That's all. In the Si-doped GaN layer, the Si concentration is set to a (atoms / cm³). ３ ), carrier concentration b (atoms / cm³) ３ If, then, the value expressed as {(b / a) × 100} (%) is 90% or more, A GaN substrate having a resistivity of 1 × 10⁻² Ωcm or less at 300K in the Si-doped GaN layer.

3. It has a main surface 1 whose inclination from the (0001) crystal plane, which is a Ga polar plane, is 0 to 10°. A GaN substrate having at least a Si-doped GaN layer on the surface of the main surface 1, The Si concentration in the Si-doped GaN layer is 1 × 10⁻¹⁰ １８ atoms / cm ３ That's all. Regarding the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is α (atoms / cm ３ ), and the minimum value is β (atoms / cm ３ ), a GaN substrate in which the value represented by [{(α - β) / α}× 100] (%) is 10% or less.

4. The GaN substrate according to any one of claims 1 to 3, wherein the thickness of the Si-doped GaN layer is 50 μm or more.

5. The GaN substrate according to any one of claims 1 to 3, wherein the total bottom area of ​​recesses with a depth of 5 μm or more on the surface of the Si-doped GaN layer is 15% or less of the total surface area of ​​the Si-doped GaN layer.

6. The GaN substrate according to any one of claims 1 to 3, wherein one or more 5 mm × 5 mm square grids without concave defects are present on the surface of the Si-doped GaN layer.

7. The GaN substrate according to any one of claims 1 to 3, wherein one or more 5 mm × 5 mm square grids without recesses of 5 μm or more in depth are present on the surface of the Si-doped GaN layer.

8. The resistivity of the Si-doped GaN layer at 300K is 1 × 10⁻¹⁰ －２ A GaN substrate according to claim 1 or 3, wherein the density is Ωcm or less.

9. The resistivity of the Si-doped GaN layer at 300K is 8 × 10 －３ A GaN substrate according to any one of claims 1 to 3, wherein the density is Ωcm or less.

10. The resistivity of the Si-doped GaN layer at 300K is 4 × 10 －３ A GaN substrate according to any one of claims 1 to 3, wherein the density is Ωcm or less.

11. The Si concentration in the Si-doped GaN layer is 5 × 10 １８ atoms / cm ３ The above is the GaN substrate according to any one of claims 1 to 3.

12. The Si concentration in the Si-doped GaN layer is 9 × 10 １８ atoms / cm ３ The above is the GaN substrate according to any one of claims 1 to 3.

13. The GaN substrate is a wafer, The GaN substrate according to any one of claims 1 to 3, wherein the diameter of the wafer is 50 mm or more.

14. It has a main surface 1 whose inclination from the (0001) crystal plane, which is a Ga polar plane, is 0 to 10°. A GaN substrate having at least a Si-doped GaN layer on the surface of the main surface 1, The thickness of the Si-doped GaN layer is 50 μm or more. A GaN substrate in which, on the surface of the Si-doped GaN layer, the total bottom area of ​​recesses with a depth of 5 μm or more is 15% or less of the total surface area of ​​the Si-doped GaN layer.

15. It has a main surface 1 whose inclination from the (0001) crystal plane, which is a Ga polar plane, is 0 to 10°. A GaN substrate having at least a Si-doped GaN layer on the surface of the main surface 1, The Si concentration in the Si-doped GaN layer is 1 × 10⁻¹⁰ １８ atoms / cm ３ That's all. The thickness of the Si-doped GaN layer is 50 μm or more. The maximum value of the Si concentration on the surface of the Si-doped GaN layer is α (atoms / cm²). ３ ), the minimum value is β (atoms / cm ３ A GaN substrate in which the value expressed as [{(α-β) / α}×100](%) is 10% or less when ) is taken as follows.

16. A nitride semiconductor device comprising a GaN substrate according to any one of claims 1 to 3, 14, or 15, and a nitride semiconductor layer epitaxially grown on the main surface 1 of the GaN substrate.

17. A method for manufacturing a nitride semiconductor device, comprising the step of epitaxially growing a nitride semiconductor layer on the main surface 1 of a GaN substrate according to any one of claims 1 to 3, 14, or 15.