Semiconductor device, semiconductor module, and manufacturing method

Abstract

Provided are: a semiconductor device comprising a switching element in which a first main electrode plate, a second main electrode plate, and a control electrode plate are provided on one surface, a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate; and a semiconductor module comprising the semiconductor device.

Description

Semiconductor device, semiconductor module, and manufacturing method

[0001] The present invention relates to a semiconductor device, a semiconductor module, and a manufacturing method.

[0002] Patent Document 1 states that "a semiconductor module 100 including a semiconductor assembly 110 including a plurality of semiconductor chips 30 can constitute a power device such as an inverter or an IPM (Intelligent Power Module) including a control circuit" (paragraph 0031), "as an example, the PCB 40 is electrically connected to the semiconductor chip 30 by a bonding wire 55" (paragraph 0032), "the external connection portion 50 may be nickel-plated. By connecting a copper bus bar to the external connection portion 50, a large current can be applied to each main terminal 52 of the semiconductor assembly 110" (paragraph 0033), and "the semiconductor assembly 110 may have a metal wiring plate 70 that electrically connects the semiconductor chip 30 and the main terminal 52. Instead of the metal wiring plate 70, the semiconductor chip 30 and the main terminal 52 may be electrically connected by a conductive member such as a wire or a ribbon" (paragraph 0035).

[0003] Patent Document 2 states, "Two semiconductor elements 3 are electrically connected by a wiring member W1. One semiconductor element 3 is electrically connected to a second circuit layer 24 via a wiring member W2. The second circuit layer 24 is electrically connected to an external terminal 27 (described later) via a wiring member W3. The other semiconductor element 3 is electrically connected to a third circuit layer 25 via a wiring member W4. The third circuit layer 25 is electrically connected to another external terminal 27 via a wiring member W5." (paragraph 0023), and further states, "In addition, conductor wires are used for each of the above-mentioned wiring members. The material of the conductive wires may be gold, copper, aluminum, One or a combination of gold alloy, copper alloy, and aluminum alloy can be used. Furthermore, it is also possible to use a material other than conductive wire as the wiring member. For example, a ribbon can be used as the wiring member." (Paragraph 0024), and it is also stated that "The insulating circuit board 2 and the semiconductor element 3 are covered by a case 11 that serves as a housing that surrounds the periphery. The case 11 is composed of an annular wall portion 12 that surrounds the outer periphery of the insulating circuit board 2, and a lid portion 13 that covers the insulating circuit board 2 and the semiconductor element 3 from above, and is formed of, for example, a synthetic resin." (Paragraph 0025). [Prior art documents] [Patent documents] [Patent document 1] JP 2021-2610 A [Patent document 2] WO 2020 / 121680 Problem to be solved

[0004] The semiconductor module is made smaller, and the physical distance between the control circuit and the semiconductor device is reduced. General disclosure

[0005] In a first aspect of the present invention, a semiconductor device is provided, comprising: a switching element having a first main electrode and a control electrode on one surface and a second main electrode on the opposite surface; and a mounting substrate having, on a mounting surface of the switching element, a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode, and having, in an area of ​​the mounting surface of the switching element where the switching element is not arranged, a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode.

[0006] The semiconductor device may include a sealing portion that covers the mounting surface of the switching element on the mounting substrate and the surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

[0007] In any of the semiconductor devices described above, the switching element may be disposed between the first main electrode plate and the control electrode plate on the mounting surface of the mounting substrate where the switching element is mounted.

[0008] In any of the above semiconductor devices, the first main electrode wiring may have a plurality of bumps in contact with the first main electrode, and the control wiring may have a plurality of bumps in contact with the control electrode.

[0009] In any of the above semiconductor devices, the mounting substrate may have an insulating substrate, and first main electrode wiring, a first main electrode plate, control wiring, and a control electrode plate formed on the insulating substrate.

[0010] In any of the above semiconductor devices, the mounting substrate may have a heat conductive plate formed on the surface of the insulating substrate opposite to the mounting surface.

[0011] In any of the above semiconductor devices, the mounting substrate may further have a sub-wiring connected to the first main electrode on the mounting surface of the switching element, and may have a sub-electrode plate connected to the sub-wiring in an area of ​​the mounting surface of the switching element where the switching element is not arranged.

[0012] In any of the above semiconductor devices, the switching element may be a power MOSFET or an IGBT.

[0013] In any of the above semiconductor devices, the switching element may be a SiC semiconductor element.

[0014] In a second aspect of the present invention, there is provided a semiconductor module comprising at least one semiconductor device, a main substrate to which is connected on the back surface thereof a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate of the at least one semiconductor device, and a heat sink in contact with the surface of the at least one semiconductor device opposite the main substrate.

[0015] In the above-mentioned semiconductor module, the main substrate may have, on its front surface, a terminal connected to a first main electrode plate of at least one semiconductor device via wiring within the main substrate, and a terminal connected to a second main electrode or a second main electrode plate via wiring within the main substrate.

[0016] Any of the above semiconductor modules may further include at least one control device mounted on the front surface of the main board for controlling the at least one semiconductor device.

[0017] Any of the above semiconductor modules may be an inverter device, and the at least one semiconductor device may include a plurality of semiconductor devices respectively assigned to an upper arm and a lower arm of each of the one or more phases.

[0018] In any of the above semiconductor modules, the semiconductor devices of the plurality of semiconductor devices assigned to the upper arm of each phase may be arranged in a row on the back surface of the main substrate, and the semiconductor devices of the plurality of semiconductor devices assigned to the lower arm of each phase may be arranged in a row on the back surface of the main substrate alongside the row of semiconductor devices assigned to the upper arm of each phase.

[0019] In any of the above semiconductor modules, on the back surface of the main board, each semiconductor device assigned to the upper arm of each phase may be arranged in an orientation such that the first main electrode plate is located on the side of the semiconductor device assigned to the opposing lower arm among the multiple semiconductor devices, and on the back surface of the main board, each semiconductor device assigned to the lower arm of each phase may be arranged in an orientation such that the first main electrode plate is located on the side of the semiconductor device assigned to the opposing upper arm among the multiple semiconductor devices.

[0020] In a third aspect of the present invention, there is provided a manufacturing method comprising: preparing a switching element having a first main electrode and a control electrode on one side and a second main electrode on the opposite side; fabricating a mounting substrate having first main electrode wiring and control wiring on a mounting surface on which the switching element is to be mounted; bonding the first main electrode to the first main electrode wiring and bonding the control electrode to the control wiring, thereby mounting the switching element on the mounting surface of the mounting substrate on which the switching element is to be mounted; and bonding a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode to an area on the mounting surface of the mounting substrate on which the switching element is to be mounted, where the switching element is not arranged.

[0021] The above manufacturing method may further comprise sealing with a sealing material so as to cover the mounting surface of the switching element on the mounting substrate and the surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

[0022] Any of the above manufacturing methods may include preparing a main substrate having a back surface connected to a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate of at least one semiconductor device; connecting at least one semiconductor device to the back surface of the main substrate; and attaching a heat sink to a surface of the at least one semiconductor device opposite to the main substrate.

[0023] Any of the above manufacturing methods may include mounting at least one control device that controls at least one semiconductor device on the front surface of the main substrate.

[0024] In a fourth aspect of the present invention, there is provided a semiconductor module comprising: at least one semiconductor device having a first main electrode plate, a second main electrode plate, and a control electrode plate on one side, the first main electrode connected to the first main electrode plate, the second main electrode connected to the second main electrode plate, and a switching element having a control electrode connected to the control electrode plate; a main substrate having a back side to which the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected; and a heat sink provided on the back side of the main substrate to which the at least one semiconductor device is connected.

[0025] In the above-mentioned semiconductor module, the main substrate may have at least one main substrate recess on its back surface in which at least a portion of the at least one semiconductor device is embedded, and the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device may be connected to the main substrate at the bottom surface of the at least one main substrate recess.

[0026] Any of the above semiconductor modules may include a thermally conductive material in at least a part of the gap between the main board and the heat sink.

[0027] In any of the above semiconductor modules, the heat sink may have at least one heat sink protrusion on the surface facing the at least one semiconductor device at a position corresponding to the at least one semiconductor device.

[0028] In any of the semiconductor modules described above, the heat sink may have, on a surface facing the at least one semiconductor device, at least one heat sink recess in which at least a portion of the at least one semiconductor device is embedded.

[0029] In any of the above semiconductor modules, the heat sink may have a plate-like member having a surface facing the main board and the at least one semiconductor device, and at least one protrusion member provided on the surface of the plate-like member opposite the main board and the at least one semiconductor device, and the main board may be fixed to the heat sink by at least one thermally conductive fixing member that passes from the front surface of the main board through the plate-like member of the heat sink to the at least one protrusion member.

[0030] In any of the above semiconductor modules, each of the at least one fixing member may be a screw, and each of the at least one protruding member may have a screw hole into which the screw is fitted.

[0031] In any of the above semiconductor modules, the at least one semiconductor device may include at least one first semiconductor device and at least one second semiconductor device, and the negative side main electrode plate of the first main electrode plate and the second main electrode plate of each of the at least one first semiconductor device may be electrically connected to the positive side main terminal plate of the first main electrode plate and the second main electrode plate of a corresponding second semiconductor device among the at least one second semiconductor device.

[0032] In any of the above semiconductor modules, the at least one semiconductor device may have a structure in which the second main electrode plate is disposed between a first main electrode plate and the control electrode plate on one surface.

[0033] In any of the above semiconductor modules, on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device may be arranged with the first main electrode plates facing each other.

[0034] In any of the above semiconductor modules, on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device may be arranged with the first main electrode plate and the control electrode plate facing each other.

[0035] In any of the semiconductor modules described above, the main substrate may include a positive terminal connected to a positive main electrode plate of the first and second main electrode plates of the at least one first semiconductor device via positive wiring within the main substrate, a negative terminal connected to a negative main electrode plate of the first and second main electrode plates of the at least one second semiconductor device via negative wiring within the main substrate, and an output terminal connected to the negative main electrode plate of the first and second main electrode plates of the at least one first semiconductor device and the positive main electrode plate of the first and second main electrode plates of the at least one second semiconductor device via output wiring within the main substrate, and the positive wiring, negative wiring, and output wiring may be provided in a main wiring region of the main substrate corresponding to the area from the at least one first semiconductor device to the at least one second semiconductor device in a top view.

[0036] Any of the above semiconductor modules includes first and second at least one first semiconductor devices arranged in a line on the rear surface of the main substrate, first and second at least one second semiconductor devices arranged in a line on the rear surface of the main substrate alongside the first and second at least one first semiconductor device, and first output terminals connected to a negative main electrode plate of the first and second main electrode plates of the at least first semiconductor device and a positive main electrode plate of the first and second main electrode plates of the at least second semiconductor device via first output wiring within the main substrate. and a second output terminal connected to a negative main electrode plate of the first and second main electrode plates of the second at least first semiconductor device and a positive main electrode plate of the first and second main electrode plates of the second at least second semiconductor device via a second output wiring in the main substrate, and the positive wiring, the negative wiring, the first output wiring, and the second output wiring may be provided in a main wiring region of the main substrate corresponding to the area between a row of the first and second at least one first semiconductor device and a row of the first and second at least one second semiconductor device in a top view.

[0037] Any of the above semiconductor modules may include at least one first control device mounted on the front surface of the main substrate and electrically connected to the control electrode plate of at least one of the at least one first semiconductor devices, and at least one second control device mounted on the front surface of the main substrate and electrically connected to the control electrode plate of at least one of the at least one second semiconductor devices, wherein the at least one first control device may be arranged in a first control wiring region on the side of the at least one first semiconductor device relative to the main wiring region in a top view, and the at least one second control device may be arranged in a second control wiring region on the side of the at least one second semiconductor device relative to the main wiring region in a top view.

[0038] Any of the above semiconductor modules may include a first control connector arranged in the first control wiring area on the front surface of the main board and electrically connected to the at least one first control device, and a second control connector arranged in the second control wiring area on the front surface of the main board and electrically connected to the at least one second control device.

[0039] Any of the above semiconductor modules may include at least one snubber capacitor disposed in the main wiring region on the front surface of the main board.

[0040] In any of the above semiconductor modules, on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device may be arranged side by side in a direction perpendicular to the arrangement of the first main electrode plate, the second main electrode plate, and the control electrode plate.

[0041] In any of the semiconductor modules described above, the main substrate may include a positive terminal connected to a positive main electrode plate of the first and second main electrode plates of the at least one first semiconductor device via positive wiring within the main substrate, a negative terminal connected to a negative main electrode plate of the first and second main electrode plates of the at least one second semiconductor device via negative wiring within the main substrate, and an output terminal connected to the negative main electrode plate of the first and second main electrode plates of the at least first semiconductor device and the positive main electrode plate of the first and second main electrode plates of the at least second semiconductor device via output wiring within the main substrate, and the positive wiring, negative wiring, and output wiring may extend in a direction in which each of the at least one first semiconductor device and a corresponding second semiconductor device of the at least one second semiconductor device are aligned.

[0042] In a fifth aspect of the present invention, there is provided a manufacturing method including: preparing at least one semiconductor device having a first main electrode plate, a second main electrode plate, and a control electrode plate on one side, the first main electrode being connected to the first main electrode plate, the second main electrode being connected to the second main electrode plate, and the control electrode being connected to the control electrode plate; preparing a main substrate having a back side to which the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected; connecting the at least one semiconductor device to the back side of the main substrate; and attaching a heat sink to the back side of the main substrate to which the at least one semiconductor device is connected.

[0043] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0044] 13A and 13B are perspective views of a switching element 10 according to the present embodiment; a perspective view of a semiconductor device 200 according to the present embodiment; a manufacturing method for a semiconductor device 200 according to the present embodiment; a perspective view of a configuration in which a second main electrode plate 230 is bonded to a switching element 10 according to the present embodiment; a perspective view of a mounting substrate 210 according to the present embodiment; a perspective view of a configuration in which a switching element 10 to which a second main electrode plate 230 is bonded is bonded to a mounting substrate 210 according to the present embodiment; a perspective view of a configuration in which a first main electrode plate 220, a control electrode plate 240, and a sub-electrode plate 250 are bonded to a mounting substrate 210 according to the present embodiment; a perspective view of a semiconductor module 800 according to the present embodiment; a schematic view showing the internal structure of a semiconductor module 800 according to the present embodiment; a diagram showing the connections of each wiring within a semiconductor module 800 according to the present embodiment; a manufacturing method for a semiconductor module 800 according to the present embodiment; a schematic view of a method for manufacturing a semiconductor module 800 according to the present embodiment; a schematic view of a cross section of a semiconductor module 800 according to the present embodiment; a schematic view of an enlarged region S of FIG. 13A; a perspective view of a semiconductor device 1500 according to a first modified example of the present embodiment; 16 is a perspective view of a semiconductor module 1600 according to a second modified example of the present embodiment. FIG. 17 is a view of a semiconductor device 1500 according to a second modified example of the present embodiment, as seen from the heat sink 1630 side. FIG. 18 shows connections of each wiring in a semiconductor module 1800 according to a third modified example of the present embodiment. FIG. 19 shows connections of each wiring in a semiconductor module 1900 according to a fourth modified example of the present embodiment. FIG. 20 shows a semiconductor module 2000 according to a fifth modified example of the present embodiment. FIG. 21 shows a semiconductor module 2100 according to a sixth modified example of the present embodiment. FIG. 22 shows a semiconductor module 2200 according to a seventh modified example of the present embodiment. FIG. 23 is a schematic cross-sectional view of a semiconductor module 2300 according to an eighth modified example of the present embodiment. FIG. 24 is a schematic cross-sectional view of a semiconductor module 2400 according to a ninth modified example of the present embodiment. FIG. 25 is a schematic cross-sectional view of a semiconductor module 2500 according to a tenth modified example of the present embodiment. FIG. 26 is a schematic cross-sectional view of a semiconductor module 2600 according to an eleventh modified example of the present embodiment. FIG. 27 is a schematic cross-sectional view of a semiconductor module 2500 according to a twelfth modified example of the present embodiment.

[0045] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0046] FIG. 1 is a perspective view of a switching element 10 according to this embodiment. The switching element 10 is a semiconductor switching element such as a metal-oxide semiconductor field-effect transistor (MOSFET). The switching element 10 may be a vertical-structure power MOSFET. The switching element 10 may be a Si semiconductor element such as a Si-MOSFET, or a SiC semiconductor element such as a SiC-MOSFET capable of faster switching, or may be one using a wide-gap semiconductor such as GaN, diamond, a gallium nitride-based material, a gallium oxide-based material, AlN, AlGaN, or ZnO. Alternatively, the switching element 10 may be a semiconductor switching element such as an insulated gate bipolar transistor (IGBT), or may be a SiC-IGBT. The switching element 10 may also be a high-electron mobility transistor (HEMT).

[0047] The switching element 10 may be a semiconductor chip, having a first main electrode 100 and a control electrode 110 on one surface (the upper surface in the figure) and a second main electrode 120 on the opposite surface. In the example shown in the figure, the switching element 10 further has a sense electrode 130 on the upper surface in the figure. If the switching element 10 is a MOSFET, the switching element 10 has a source and a drain as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sense source as the sense electrode 130. If the switching element 10 is an IGBT, the switching element 10 has an emitter and a collector as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sense emitter as the sense electrode 130. For convenience of explanation, this embodiment will be described assuming that the switching element 10 is a MOSFET.

[0048] 2 is a perspective view of a semiconductor device 200 according to this embodiment. A semiconductor module using a switching element such as the switching element 10 shown in FIG. 1 typically has a structure in which one surface of the switching element (e.g., the surface on the side of the second main electrode 120) is bonded to a wiring pattern on a substrate, and the electrodes on the other surface (e.g., the first main electrode 100, the control electrode 110, and the sense electrode 130) are electrically connected to other wiring patterns by wire bonding. Such a semiconductor module is realized as an integrated module by resin-sealing the substrate on which the switching element is mounted, the bonding wires, and the metal plates connected to the positive terminal, negative terminal, and output terminal.

[0049] In contrast, the semiconductor device 200 has a structure in which each electrode plate electrically connected to each electrode of the switching element 10 is exposed on one surface of the plate-shaped semiconductor device 200. In this embodiment, the semiconductor device 200 includes a mounting substrate 210, a first main electrode plate 220, a second main electrode plate 230, a control electrode plate 240, a sub-electrode plate 250, and a sealing portion 260.

[0050] The mounting substrate 210 mounts the switching element 10 on its mounting surface (the upper surface in the figure). The first main electrode plate 220 is electrically connected to the first main electrode 100 of the switching element 10. The second main electrode plate 230 is electrically connected to the second main electrode 120 of the switching element 10. The control electrode plate 240 is electrically connected to the control electrode 110 of the switching element 10. The sub-electrode plate 250 is electrically connected to the first main electrode 100 of the switching element 10. Here, the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 are exposed on the surface of the semiconductor device 200 opposite the mounting substrate 210 side (the side of the mounting substrate 210 on which the switching element 10 is mounted). The sealing portion 260 covers the mounting surface of the mounting substrate 210 on which the switching element 10 is mounted, while leaving the first main electrode plate 220 , the second main electrode plate 230 , the control electrode plate 240 , and the sub-electrode plate 250 exposed.

[0051] Instead of modularizing a switching element such as the switching element 10 as described above, the semiconductor device 200 of this embodiment is used, and each electrode plate on one side of the semiconductor device 200 is bonded to a wiring pattern on a substrate, so that all the necessary electrodes in the switching element 10 can be electrically connected to the wiring on the substrate without wire bonding.

[0052] The semiconductor device 200 may further have an electrode plate electrically connected to the sense electrode 130 on the same surface as the first main electrode plate 220, etc. The first main electrode plate 220 and the sub-electrode plate 250 are both electrically connected to the first main electrode 100 of the switching element 10, but the first main electrode plate 220 has a large area and is used to pass a large current, while the sub-electrode plate 250 is used to control the switching element 10 in a pair with the control electrode plate 240. In another embodiment, the semiconductor device 200 may not include the sub-electrode plate 250, in which case the first main electrode plate 220 is also used to control the switching element 10.

[0053] 3 shows a method for manufacturing the semiconductor device 200 according to this embodiment. The method for manufacturing the semiconductor device 200 will be described below with reference to FIGS. 4 to 7, which show the configuration of the semiconductor device 200 during manufacturing. In S300 (step 300), a switching element 10 is prepared, which has a first main electrode 100 and a control electrode 110 on one side and a second main electrode 120 on the opposite side.

[0054] In S310, a second main electrode plate 230 is bonded to the surface of the switching element 10 facing the second main electrode 120. FIG. 4 is a perspective view of a configuration in which the second main electrode plate 230 is bonded to the switching element 10 according to this embodiment. The second main electrode plate 230 is a conductive plate such as a copper plate. The second main electrode plate 230 may be bonded to the second main electrode 120 using a nanosilver sintering agent, or may be bonded by direct gold-to-gold bonding. This electrically connects the second main electrode plate 230 to the second main electrode 120 of the switching element 10. In addition to the above, the second main electrode plate 230 may be bonded by solder or direct copper-to-copper bonding. Furthermore, a plurality of regularly or irregularly arranged bumps on the second main electrode plate 230 may be bonded to the second type electrode of the switching element 10.

[0055] In S320, the mounting substrate 210 is fabricated. Fig. 5 is a perspective view of the mounting substrate 210 according to this embodiment. In this step, the mounting substrate 210 is fabricated, having wiring patterns of first main electrode wiring 510, control wiring 520, and sub-wiring 530 on the mounting surface of an insulating substrate 500 made of Si, silicon nitride, aluminum nitride, or the like, on which the switching elements 10 are to be mounted. The insulating substrate 500 may be fabricated using ceramic materials, including those mentioned above.

[0056] The first main electrode wiring 510 is formed of a conductive metal film or metal plate such as copper. The first main electrode wiring 510 includes a first main electrode contact 513, wiring 515, and a first main electrode plate contact 517. The first main electrode contact 513 is an area connected to the first main electrode 100 of the switching element 10. The wiring 515 electrically connects the first main electrode contact 513 and the first main electrode plate contact 517. The first main electrode plate contact 517 is an area connected to the first main electrode plate 220.

[0057] Like the first main electrode wiring 510, the control wiring 520 is formed of a conductive metal film or metal plate such as copper. The control wiring 520 includes a control electrode contact 523, wiring 525, and a control electrode plate contact 527. The control electrode contact 523 is an area connected to the control electrode 110 of the switching element 10. The wiring 525 electrically connects the control electrode contact 523 and the control electrode plate contact 527. The control electrode plate contact 527 is an area connected to the control electrode plate 240.

[0058] Like the first main electrode wiring 510, the sub wiring 530 is formed of a conductive metal film or metal plate such as copper. The sub wiring 530 includes a first main electrode contact 513, wiring 535, and a sub-electrode plate contact 537. The first main electrode contact 513 is shared with the first main electrode wiring 510. The sub wiring 530 may utilize a portion of the first main electrode contact 513 used by the first main electrode wiring 510. The wiring 535 electrically connects the first main electrode contact 513 and the sub-electrode plate contact 537. The wiring 535 may have a smaller wiring width than the wiring 515. The sub-electrode plate contact 537 is an area connected to the sub-electrode plate 250.

[0059] Here, each electrode of the switching element 10, such as the first main electrode contact 513 and the first main electrode plate contact 517 of the first main electrode wiring 510, the control electrode contact 523 and the control electrode plate contact 527 of the control wiring 520, and the sub-electrode plate contact 537 of the sub-wiring 530, or each region bonded to each electrode plate, such as the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250, may have a plurality of bumps arranged regularly or irregularly. These bumps may be made of a conductive metal such as gold. These bumps may be formed, for example, by arranging a conductive metal bump precursor in each region by transfer or the like and then baking and hardening the bump precursor.

[0060] In S330, the switching element 10 is mounted on the mounting surface of the mounting substrate 210 on which the wiring patterns are formed. FIG. 6 is a perspective view of a configuration in which the switching element 10, to which the second main electrode plate 230 is bonded, is bonded to the mounting substrate 210 according to this embodiment. As shown in FIG. 4 , the switching element 10, to which the second main electrode plate 230 is bonded, is bonded to the mounting surface of the mounting substrate 210 with the upper surface of the switching element 10 in FIG. 4 facing downward. As a result, the first main electrode 100 of the switching element 10 is bonded to the first main electrode contact 513 of the first main electrode wiring 510 and the sub-wiring 530, and the control electrode 110 of the switching element 10 is bonded to the control electrode contact 523 of the control wiring 520. This bonding method may be the same as the method for bonding the second main electrode plate 230 to the second main electrode 120.

[0061] In S340, each electrode plate is bonded to each wiring of the mounting substrate 210. FIG. 7 is a perspective view of a configuration in which the first main electrode plate 220, the control electrode plate 240, and the sub-electrode plate 250 are bonded to the mounting substrate 210 according to this embodiment. As shown in FIG. 6 , the first main electrode plate contact 517 of the first main electrode wiring 510, the control electrode plate contact 527 of the control wiring 520, and the sub-electrode plate contact 537 of the sub-wiring 530 are located in areas of the mounting surface of the mounting substrate 210 where the switching elements 10 are to be mounted, where the switching elements 10 are not to be disposed. In this step, the first main electrode plate 220, the control electrode plate 240, and the sub-electrode plate 250 are bonded to the first main electrode plate contact 517, the control electrode plate contact 527, and the sub-electrode plate contact 537, respectively. This bonding method may be similar to the method for bonding the second main electrode plate 230 to the second main electrode 120.

[0062] As a result, first main electrode plate 220, control electrode plate 240, and sub-electrode plate 250 are located in areas of the mounting surface for switching element 10 where switching element 10 is not arranged, and are electrically connected to first main electrode wiring 510, control wiring 520, and sub-wiring 530, respectively. In this manner, mounting substrate 210 is fabricated, which has insulating substrate 500 and first main electrode wiring 510, first main electrode plate 220, control wiring 520, control electrode plate 240, sub-wiring 530, and sub-electrode plate 250 formed on insulating substrate 500.

[0063] Here, in the semiconductor device 200 according to this embodiment, on the mounting surface of the mounting substrate 210 on which the switching element 10 is mounted, the switching element 10 is disposed between the first main electrode plate 220 and the control electrode plate 240. The sub-electrode plate 250 may be disposed on the same side as the control electrode plate 240 with respect to the switching element 10. This allows the semiconductor device 200 to be configured such that control wiring can be connected to the control electrode plate 240 and the sub-electrode plate 250 located at one end of the semiconductor device 200.

[0064] In S350, the mounting surface of the mounting substrate 210 is sealed with a sealing material so that each electrode plate is exposed, thereby forming a sealing portion 260, thereby obtaining the semiconductor device 200 shown in Fig. 2. Here, the sealing portion 260 covers the mounting surface of the mounting substrate 210 for the switching element 10 and the surface of the switching element 10 facing the mounting substrate 210, while exposing the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 on the terminal surface (the upper surface in Fig. 2) of the semiconductor device 200. This sealing may be resin sealing using a molding material.

[0065] In this step, after sealing is performed to cover the mounting surface of the mounting substrate 210 on which the switching element 10 is mounted and the surface of the switching element 10 facing the mounting substrate 210, the terminal surface of the semiconductor device 200 may be polished to remove excess sealing material and expose each electrode plate. In other embodiments, the sealing step may be omitted, and the semiconductor device 200 may not include the sealing portion 260. After this step, an anti-oxidation film may be formed by plating the exposed surface of each electrode plate with Sn, for example.

[0066] According to the manufacturing method described above, it is possible to manufacture a semiconductor device 200 in which each terminal electrically connected to each electrode of the switching element 10 is exposed on one surface. Note that in the manufacturing method described above, the second main electrode plate 230 is bonded to the surface of the switching element 10 on the side of the second main electrode 120 in S310, but this step may be omitted. In this case, the second main electrode 120 may be directly exposed on the terminal surface of the semiconductor device 200.

[0067] In the manufacturing method described above, the order of the steps may be changed as far as possible. For example, S340 may be performed before S330, and the electrode plates may be bonded to the wiring of the mounting substrate 210 before the switching element 10 is mounted on the mounting substrate 210. Alternatively, S310 may be performed after S330, and the mounting substrate 210 may be mounted on the switching element 10 before the second main electrode plate 230 is bonded to the surface of the switching element 10 facing the second main electrode 120. Furthermore, S300, S310, and S320 may be performed in any order, or may be performed in parallel.

[0068] The semiconductor device 200 may include a temperature sensing diode or other temperature sensor for measuring the temperature of the semiconductor device 200 or the switching element 10. In this case, the semiconductor device 200 may further include an electrode plate connected to electrodes of the temperature sensor, such as the anode and cathode electrodes of the temperature sensing diode, on the same surface as the first main electrode plate 220, etc.

[0069] Furthermore, the number of electrode plates arranged on the same surface as the first main electrode plate 220 and the like in the semiconductor device 200, as well as the size, shape, and type of each electrode plate, may be appropriately selected depending on the usage of the semiconductor device 200, a temperature sensor or other additional circuits added to the semiconductor device 200, and the like. For example, the area of ​​the control electrode plate 240 in the semiconductor device 200 may be further reduced, and a new electrode plate may be provided in the area freed up as a result. The newly provided electrode plate may be, for example, at least one of a sense electrode plate electrically connected to the sense electrode 130, one or more temperature sense electrode plates connected to the electrodes of the temperature sensor of the switching element 10 or the like as described above, or an electrode plate (e.g., a sub-electrode plate) having the same potential as the second main electrode plate 230. Furthermore, for example, another electrode plate, such as the second main electrode plate 230, may be extended into the area freed up by reducing the area of ​​the control electrode plate 240.

[0070] Such additional electrodes may be used for measuring electrical quantities to monitor the state of semiconductor device 200 or switching element 10. Such additional electrodes may be arranged at positions away from large current paths such as first main electrode plate 220 and second main electrode plate 230 and the main wiring connected to these main electrode plates, such as near the side of semiconductor device 200 on which control electrode plate 240 and sub-electrode plate 250 are provided. This allows semiconductor device 200 to reduce the influence of at least one of noise and heat generated by the flow of large current on the additional electrodes.

[0071] Furthermore, for example, a second sub-electrode plate separate from the sub-electrode plate 250 may be provided in an area freed up by reducing the area of ​​the control electrode plate 240. The sub-electrode plate 250 (also referred to as the "first sub-electrode plate") and the second sub-electrode plate may be arranged on either side of the control electrode plate 240 so that the control electrode plate 240 is sandwiched between the two sub-electrodes. This arrangement in which the control electrode plate is sandwiched between two sub-electrodes is similar to the control electrode plate 1540 and two sub-electrodes 1550 in FIG. 15 . To achieve this arrangement, the mounting substrate 210 may have, in addition to the sub-wiring 530, a second sub-wiring on the mounting surface of the switching element 10 that electrically connects the first main electrode 100 of the switching element 10 to the second sub-electrode plate. The sub-wiring 530 (also referred to as the "first sub-wiring") and the second sub-wiring may be arranged on either side of the control wiring 520 so that the control wiring 520 is sandwiched between the sub-wirings. In this way, by sandwiching the control electrode plate 240 between two sub-electrode plates, the semiconductor device 200 can reduce the wiring inductance in the path through which the current that drives the semiconductor device 200 (i.e., the current of the control signal that flows through the control electrode 110 of the switching element 10) flows.

[0072] Fig. 8 is a perspective view of a semiconductor module 800 according to this embodiment. Fig. 9 is a schematic diagram showing the internal structure of the semiconductor module 800 according to this embodiment. The semiconductor module 800 includes one or more semiconductor devices 200, a main substrate 810, one or more control devices 820, and a heat sink 830.

[0073] The semiconductor module 800 according to this embodiment is an inverter device and includes a plurality of semiconductor devices 200. The plurality of semiconductor devices 200 are respectively assigned to an upper arm and a lower arm of each of one or more phases. In the example of FIGS. 8 and 9 , the semiconductor module 800 is a three-phase inverter, and two semiconductor devices 200 are assigned to the upper arm and two semiconductor devices 200 are assigned to the lower arm of each phase. Therefore, the semiconductor module 800 includes 12 semiconductor devices 200 (= 3 phases × (2 upper arms + 2 lower arms)). Note that the semiconductor module 800 may include any number of semiconductor devices 200 depending on the application.

[0074] The main substrate 810 may be a printed wiring board, and the electrodes on the back surface are connected to the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 of each of the multiple semiconductor devices 200. The main substrate 810 has P wiring 812, N wiring 813, U wiring 814, V wiring 815, and W wiring 816 in its inner layers. In FIG. 9 , the P wiring 812, N wiring 813, U wiring 814, V wiring 815, and W wiring 816 are separately and schematically illustrated on the underside of the main substrate 810 to make the structure of the wiring layers easier to see.

[0075] The P wiring 812, the N wiring 813, the U wiring 814, the V wiring 815, and the W wiring 816 may be conductive patterns formed on different inner layers of the main substrate 810. In this embodiment, the N wiring 813 is formed on two or more layers connected by a conductive through via or the like, and at least a portion of each of the P wiring 812, the U wiring 814, the V wiring 815, and the W wiring 816 is sandwiched between the two layers of the N wiring 813.

[0076] The main substrate 810 has, on its front surface, terminals that are connected to the first main electrode plates 220 of the multiple semiconductor devices 200 via wiring within the main substrate 810, and terminals that are connected to the second main electrode plate 230 via wiring within the main substrate 810. In the example of this embodiment, the main substrate 810 has, on its front surface, a P terminal (positive terminal), an N terminal (negative terminal), a U terminal (U-phase output terminal), a V terminal (V-phase output terminal), and a W terminal (W-phase output terminal). Connection between each terminal provided on the front surface of the main substrate 810 and one or more semiconductor devices 200 via each wiring such as the P wiring 812 will be described later with reference to FIG. 10 .

[0077] The multiple control devices 820 are mounted on the front surface of the main board 810. Each of the one or more control devices 820 is electrically connected to the control electrode plate 240 and the sub-electrode plate 250 of one or more semiconductor devices 200 via wiring within the main board 810. Each control device 820 controls the semiconductor device 200 by controlling the voltage of the control electrode plate 240 relative to the sub-electrode plate 250 of the semiconductor device 200. Each control device 820 may be connected to one semiconductor device 200 and control that one semiconductor device 200, or may be connected to two or more semiconductor devices 200 and control that two or more semiconductor devices 200. Note that the one or more control devices 820 may control one or more semiconductor devices 200 in response to a control signal from an external control device.

[0078] The heat sink 830 is in contact with the surface of one or more semiconductor devices 200 opposite to the main substrate 810. The heat sink 830 may be, for example, a heat spreader, a heat sink, or a heat exchanger for liquid cooling.

[0079] FIG. 10 shows the connections of the wiring within the semiconductor module 800 according to this embodiment. In this diagram, semiconductor devices 200 (UU1) and 200 (UU2) are assigned to the U-phase upper arm, and semiconductor devices 200 (UD1) and 200 (UD2) are assigned to the U-phase lower arm. The second main electrode 230 of each semiconductor device 200 in the U-phase upper arm is connected to the P terminal via a P wiring 812. The first main electrode 220 of each semiconductor device 200 in the U-phase upper arm is connected to the U terminal via a U wiring 814. The second main electrode 230 of each semiconductor device 200 in the U-phase lower arm is connected to the U terminal and the first main electrode 220 of each semiconductor device 200 in the U-phase upper arm via a U wiring 814. The first main electrode 220 of each semiconductor device 200 in the U-phase lower arm is connected to the N terminal via an N wiring 813. With this connection, each semiconductor device 200 in the U-phase upper arm and each semiconductor device 200 in the U-phase lower arm are connected in series in this order between the P terminal and the N terminal, and the node between the first main electrode plate 220 (e.g., source) of each semiconductor device 200 in the U-phase upper arm and the second main electrode plate 230 (e.g., drain) of each semiconductor device 200 in the U-phase lower arm is connected to the U terminal.

[0080] Semiconductor devices 200 (VU1) and 200 (VU2) are assigned to the V-phase upper arm, and semiconductor devices 200 (VD1) and 200 (VD2) are assigned to the V-phase lower arm. Each semiconductor device 200 in the V-phase upper arm and V-phase lower arm is connected in the same manner as each semiconductor device 200 in the U-phase upper arm and U-phase lower arm, except that it is connected to the V-terminal instead of the U-terminal.

[0081] Semiconductor devices 200 (WU1) and 200 (WU2) are assigned to the W-phase upper arm, and semiconductor devices 200 (WD1) and 200 (WD2) are assigned to the W-phase lower arm. Each semiconductor device 200 in the W-phase upper arm and W-phase lower arm is connected in the same manner as each semiconductor device 200 in the U-phase upper arm and U-phase lower arm, except that it is connected to the W-terminal instead of the U-terminal.

[0082] As shown in the figure, the semiconductor devices 200 assigned to the upper arms of each phase out of the plurality of semiconductor devices 200 may be arranged in a row (the upper row in the figure) on the back surface of the main substrate 810. The semiconductor devices 200 assigned to the lower arms of each phase out of the plurality of semiconductor devices 200 may be arranged in a row (the lower row in the figure) on the back surface of the main substrate 810 alongside the row of the semiconductor devices 200 assigned to the upper arms of each phase. With this arrangement, the second main electrode plates 230 of the semiconductor devices 200 in the upper arms and the first main electrode plates 220 of the semiconductor devices 200 in the lower arms are aligned in a row, so that the P wiring 812 and the N wiring 813 can be extended in the arrangement direction of the semiconductor devices 200 in the upper arms and the arrangement direction of the semiconductor devices 200 in the lower arms, respectively, and connected to each semiconductor device 200. Accordingly, the U wiring 814, V wiring 815, and W wiring 816 can also extend in the arrangement direction of each semiconductor device 200 and be connected to the first main electrode plate 220 of each semiconductor device 200 in the corresponding upper arm and the second main electrode plate 230 of each semiconductor device 200 in the corresponding lower arm.

[0083] As shown in the figure, on the back surface of the main substrate 810, each semiconductor device 200 assigned to the upper arm of each phase may be arranged in an orientation such that the first main electrode plate 220 is located on the side of the semiconductor device 200 assigned to the opposing lower arm among the plurality of semiconductor devices 200 (the first main electrode plate 220 is oriented toward the bottom in the figure). On the back surface of the main substrate 810, each semiconductor device 200 assigned to the lower arm of each phase may be arranged in an orientation such that the first main electrode plate 220 is located on the side of the semiconductor device 200 assigned to the opposing upper arm among the plurality of semiconductor devices 200 (the first main electrode plate 220 is oriented toward the top in the figure). In such an arrangement, the control electrode plate 240 and the sub-electrode plate 250 of each semiconductor device 200 are located at the end of the semiconductor device 200 opposite the semiconductor device 200 of the opposing arm. This allows the semiconductor devices 200 of the upper and lower arms to face each other, and makes it possible to arrange control wiring outside the area where P wiring 812, N wiring 813, U wiring 814, V wiring 815, and W wiring 816, through which large currents flow, are arranged.

[0084] 11 shows a method for manufacturing a semiconductor module 800 according to this embodiment. In S1100, at least one semiconductor device 200 is prepared. In S1110, a main substrate 810 is prepared, the back surface of which is to be connected the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 of the at least one semiconductor device 200.

[0085] In S1120, at least one control device 820 is mounted on the front surface of the main board 810 by soldering or the like to the front surface of the main board 810. In S1130, at least one semiconductor device 200 is sandwiched between the back surface of the main board 810 and the heat sink 830, each electrode plate of the semiconductor device 200 is connected to the back surface of the main board 810, and the heat sink 830 is attached to the surface of each semiconductor device 200 opposite to the main board 810.

[0086] FIG. 12 is a schematic diagram of a manufacturing method for a semiconductor module 800 according to this embodiment. In particular, this diagram illustrates step S1130 in FIG. 11 using a schematic cross-sectional structure of a main substrate 810, a semiconductor device 200, and a heat sink 830. The main substrate 810 has at least one control device 820 mounted on its front surface and has terminals such as a P terminal and a U terminal. Each terminal, such as the P terminal and the U terminal, may have a structure in which a conductive metal layer is formed by plating or the like on the inner surface of a non-through hole or a through hole that is deep enough to reach a wiring layer having a wiring pattern to which the terminal is electrically connected. Alternatively, each terminal may be formed by embedding a conductive terminal member (e.g., a columnar copper part with a screw hole inside) in the main substrate 810 that is deep enough to reach a wiring layer having a wiring pattern to which the terminal is electrically connected.

[0087] The main substrate 810 has, on its back surface, a first main electrode plate contact 1280 to be bonded to the first main electrode plate 220 of the semiconductor device 200, a second main electrode plate contact 1285 to be bonded to the second main electrode plate 230, and a control electrode plate contact 1290 to be bonded to the control electrode plate 240. The main substrate 810 may further have an electrode plate contact to be bonded to the sub-electrode plate 250. The U terminal and the first main electrode plate contact 1280 may be electrically connected by a conductive through via and a U wiring 814, and the P terminal and the second main electrode plate contact 1285 may be electrically connected by a P wiring 812.

[0088] 11 , at least one semiconductor device 200 may first be connected to the back surface of the main substrate 810. That is, the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 of each semiconductor device 200 are connected to corresponding electrodes on the back surface of the main substrate 810 (first main electrode plate contact 1280 for the first main electrode plate 220 in this figure, second main electrode plate contact 1285 for the second main electrode plate 230, and control electrode plate contact 1290 for the control electrode plate 240) by nanosilver paste, direct gold-to-gold bonding, or the like.

[0089] Next, a heat sink 830 may be attached to the surface of at least one semiconductor device 200 opposite the main substrate 810. The semiconductor device 200 and the heat sink 830 may be directly pressure-bonded to each other, or may be in contact with each other via a thermally conductive material. The thermally conductive material may be a paste-like thermally conductive grease or filler, a thermally conductive or heat-dissipating sheet, or any other thermal interface material (TIM). Alternatively, the semiconductor device 200 and the heat sink 830 may be pressure-bonded to each other with a thermally conductive material provided on one or both of the semiconductor device 200 and the heat sink 830. As shown in this figure, the mounting substrate 210 of the semiconductor device 200 may have a thermally conductive plate 1270 formed on the surface of the insulating substrate 500 opposite the mounting surface of the switching element 10. The thermally conductive plate 1270 may be a thermally conductive component having a higher thermal conductivity than the insulating substrate 500, such as a copper plate.

[0090] 13 is a schematic cross-sectional view of the semiconductor module 800 according to this embodiment. In the step S1130 of FIG. 11 , the main substrate 810 may be fixed to the heat sink 830 by threading screws, which penetrate the main substrate 810 and reach an area on the surface of the heat sink 830 where the semiconductor device 200 is not located, into screw holes provided on the surface of the heat sink 830, as in the example of this figure. The semiconductor module 800 may be sold and used in the configuration shown in this figure, or may be sold and used in a configuration in which the space between the main substrate 810 and the heat sink 830 is sealed with a resin seal or the like.

[0091] FIG. 14 is a schematic diagram enlarging region S shown in FIG. 13 . Electrode plates such as the second main electrode plate 230 and the control electrode plate 240 in the semiconductor device 200 are electrically connected to terminals on the front surface of the main substrate 810 or the control device 820 via electrode contacts and wiring on the main substrate 810. The semiconductor module 800 can be made smaller or thinner by connecting the switching elements 10 to terminals such as the P terminal with relatively short wiring distances using inner-layer wiring on the main substrate 810. The semiconductor module 800 can also reduce the inductance between the first main electrode plate 220 and the second main electrode plate 230 of the switching elements 10 and each terminal (also referred to as “main circuit inductance”), as well as the inductance between the control electrode plate 240 and the sub-electrode plate 250 of the switching elements 10 and the control device 820 (also referred to as “gate control circuit inductance”).

[0092] Furthermore, in the semiconductor module 800, a second main electrode plate 230 is joined to the surface of the switching element 10 on the second main electrode 120 side (the upper surface in the figure), and the second main electrode plate 230 is electrically connected to a P terminal and the like on the front surface of the main substrate 810 via wiring and the like within the main substrate 810. Here, such electrical connection paths are formed from a metal material with high thermal conductivity, such as copper, so that the semiconductor module 800 can transfer heat from the surface of the switching element 10 on the second main electrode 120 side to each terminal and the like through the wiring pattern within the main substrate 810, and dissipate the heat to bus bars and the like connected to each terminal.

[0093] Furthermore, the surface of the switching element 10 on the side of the first main electrode 100, the control electrode 110, etc. (the lower surface in the figure) is electrically connected to the first main electrode contact 513 of the first main electrode wiring 510 and the control electrode contact 523 of the control wiring 520, etc., which are formed on the mounting surface of the switching element 10 on the insulating substrate 500. The semiconductor module 800 can transfer heat from the surface on the side of the control electrode 110, etc. of the switching element 10 to the heat sink 830 via the first main electrode wiring 510, the control wiring 520, the insulating substrate 500, and the thermal conduction plate 1270, and can dissipate the heat from the heat sink 830.

[0094] As a modification of this embodiment, a 2-in-1 module may be configured in which the upper and lower arms for one phase are mounted by assembling the semiconductor device 200 (UU1) and the semiconductor device 200 (UD1) of the semiconductor devices 200 shown in FIG. 10 with a main board 810 that wires the two semiconductor devices 200. Also, a 6-in-1 module may be configured with the upper and lower arms for three phases. In this case, the number of semiconductor devices 200 that constitute the upper and lower arms is not limited to one. Furthermore, in this case, the semiconductor devices 200 are formed into individual semiconductor devices 200 by dicing or the like after step S350 shown in FIG. 3 , but the semiconductor devices 200 that constitute the 2-in-1 module or the 6-in-1 module may be formed as an integrated unit without dicing.

[0095] In an inverter device according to another modification of this embodiment, a smoothing capacitor (not shown) may be connected to the P terminal and the N terminal of the semiconductor module of FIG. 8 , and current sensors (not shown) may be provided at least at two of the U terminal, the V terminal, and the W terminal. The current sensors may be mounted on the main board 810, on a separate board (not shown), or on an inner layer of the main board 810. In addition, when the current sensors are mounted on the main board 810, a magnetic shield plate may be appropriately provided around at least a portion of the current sensor. The magnetic shield plate may be mounted so as to be inserted into a slit provided in the main board 810, or may be mounted as a pattern on an inner layer of the main board 810.

[0096] The connection between the smoothing capacitor and the main board 810 may be realized by connecting a terminal of the smoothing capacitor to a connection terminal provided on the main board 810. An example of such a connection of the smoothing capacitor is shown in Fig. 21 . Also, the heat sink 830 in Fig. 8 may be provided separately for at least one semiconductor device 200, or may be provided separately for all semiconductor devices 200.

[0097] 8 may also include a temperature sensor (not shown). The temperature sensor may be mounted on the main board 810 or may be provided on an inner layer of the main board 810. By providing the temperature sensor on an inner layer of the main board 810, the temperature of the semiconductor device 200 can be measured more accurately.

[0098] 8 may also include a gate resistor (not shown). The gate resistor is connected in series to the control wiring between the control electrode plate 240 of the semiconductor device 200 and the control device 820. The gate resistor may be mounted on the main substrate 810 or may be provided on an inner layer of the main substrate 810. By providing the gate resistor on an inner layer of the main substrate 810, the gate resistor can be placed in close proximity to the semiconductor device 200, thereby reducing voltage oscillations generated at the control electrode 110 of the semiconductor device 200.

[0099] 8 may also include a snubber capacitor (not shown). The snubber capacitor may be mounted on the main board 810 or provided on an inner layer of the main board 810. By providing the snubber capacitor on an inner layer of the main board 810, the snubber capacitor can be placed in close proximity to the semiconductor device 200, thereby further suppressing high voltages that transiently occur when the semiconductor device 200 is switched.

[0100] 8, an external control device (not shown) that generates signals for controlling at least the control device may be installed so as to cover at least a portion of the front surface of the main board 810. The control signals generated in this manner are input to the control device via a control connector (described later in FIG. 16).

[0101] 8 may be mounted on the main substrate 810 in accordance with the heat distribution of the semiconductor device 200. For example, the surface of the main substrate 810 directly above the semiconductor device 200 may be avoided. In addition, slits may be provided in the main substrate 810 around the control device 820 to mitigate the influence of temperature during mounting.

[0102] 8 may be mounted in a position determined according to the wiring path of the main wiring. As an example, each control device 820 may be disposed on the front surface of the main board 810, avoiding a position directly above each main wiring (P wiring 812, N wiring 813, U wiring 814, V wiring 815, and W wiring 816). This prevents the control device 820 from malfunctioning due to the influence of noise generated by a large current flowing through the main wiring.

[0103] 8, another heat sink may be provided on the surface of the main substrate 810 opposite to the side on which the heat sink 830 is disposed. In this case, the heat sink may be a heat capacity body separate from the heat sink 830.

[0104] FIG. 15 is a perspective view of a semiconductor device 1500 according to a first modification of this embodiment. The semiconductor device 1500 is a modification of the semiconductor device 200 shown in FIGS. 1 to 7 , and therefore will not be described further below except for the differences. The semiconductor device 1500 may be the same size as the semiconductor device 200 or may have a size similar to that of the semiconductor device 200. The semiconductor device 1500 has a structure in which each electrode plate electrically connected to each electrode of a switching element, such as the switching element 10 shown in FIG. 1 , is exposed on one side of the plate-shaped semiconductor device 1500. While this modification will be described with reference to a case in which the switching element 10 is used as the switching element, the semiconductor device 1500 may also be equipped with a switching element other than the switching element 10.

[0105] In this modification, the semiconductor device 1500 includes a mounting substrate 1510, a first main electrode plate 1520, a second main electrode plate 1530, a sub-electrode plate 1550, a control electrode plate 1540, and a sealing portion 1560. The first main electrode plate 1520, the second main electrode plate 1530, the sub-electrode plate 1550, and the control electrode plate 1540 are provided on one surface (the upper surface in the figure) of the semiconductor device 1500. The semiconductor device 1500 may have a structure in which the second main electrode plate 1530 is disposed between the first main electrode plate 1520 and the control electrode plate 1540 on one surface.

[0106] The mounting substrate 1510 mounts a switching element such as the switching element 10 on its mounting surface (the upper surface in the figure). The mounting substrate 1510 corresponds to the mounting substrate 210 in the semiconductor device 200. The mounting substrate 1510 may mount the switching element 10 by bonding the surface of the switching element 10 on the side of the second main electrode 120 to the mounting surface of the mounting substrate 1510. The mounting substrate 1510 may have a different wiring and electrode contact pattern than the mounting substrate 210 depending on the orientation in which the switching element 10 is mounted.

[0107] The first main electrode plate 1520 is electrically connected to the second main electrode 120 of the switching element 10. The first main electrode plate 1520 corresponds to the first main electrode plate 220 of the semiconductor device 200. The second main electrode plate 1530 is electrically connected to the first main electrode 100 of the switching element 10. The second main electrode plate 1530 corresponds to the second main electrode plate 230 of the semiconductor device 200. In this modification, the second main electrode plate 1530 is joined to the first main electrode 100 in a region on the surface of the switching element 10 facing the first main electrode 100, where the first main electrode 100 is formed. The second main electrode plate 1530 may have a notch so as not to be positioned above a region on the surface of the switching element 10 facing the first main electrode 100, where the control electrode 110 is formed. The second main electrode plate 1530 may be drawn out to the side of the semiconductor device 1500 opposite to the first main electrode plate 1520 (toward the back of the drawing), except for a central portion at the back of the drawing adjacent to the control electrode plate 1540, and this drawn-out portion may be used as a sub-electrode plate 1550. The sub-electrode plate 1550 corresponds to the sub-electrode plate 250 of the semiconductor device 200.

[0108] The control electrode plate 1540 is electrically connected to the control electrode 110 of the switching element 10. The control electrode plate 1540 corresponds to the control electrode plate 240 of the semiconductor device 200. The control electrode plate 1540 is joined to the control electrode 110 in a region where the control electrode 110 is formed on the surface of the switching element 10 on the first main electrode 100 side. The control electrode plate 1540 may be extended to the side of the semiconductor device 1500 opposite the first main electrode plate 1520 side (toward the back of the drawing). The sealing portion 1560 covers the mounting surface of the mounting substrate 1510 for the switching element 10 while exposing the first main electrode plate 1520, the second main electrode plate 1530, and the control electrode plate 1540.

[0109] Here, semiconductor device 200 has a structure in which second main electrode plate 230, to which second main electrode 120 of switching element 10 is connected, is disposed between first main electrode plate 220 connected to first main electrode 100 of switching element 10 and control electrode plate 240 connected to control electrode 110 of switching element 10, while semiconductor device 1500 may have a structure in which second main electrode plate 1530 connected to first main electrode 100 of switching element 10 is disposed between first main electrode plate 1520 connected to second main electrode 120 of switching element 10 and control electrode plate 1540 connected to control electrode 110 of switching element 10. In this case, the first main electrode plate 220 and second main electrode plate 230 of semiconductor device 200 and the first main electrode plate 1520 and second main electrode plate 1530 of semiconductor device 1500 have the polarity of the main electrodes of switching element 10 reversed. For example, if the first main electrode plate 220 of the semiconductor device 200 is the source and the second main electrode plate 230 is the drain, the first main electrode plate 1520 of the semiconductor device 1500 is the drain and the second main electrode plate 1530 is the source. By using the semiconductor device 200 and the semiconductor device 1500 with different electrode arrangements, a semiconductor device with a more appropriate electrode arrangement can be selected and used depending on the mounting position of each semiconductor device in the semiconductor module 800 or other semiconductor module.

[0110] For convenience of explanation, when focusing on the arrangement of the semiconductor device, among the main electrodes of the switching elements such as the switching element 10 mounted on the semiconductor device 1500, the main electrode connected to the first main electrode plate 1520 may be referred to as the first main electrode, and the main electrode connected to the second main electrode plate 1530 may be referred to as the second main electrode. For example, when the first main electrode 100 of the switching element 10 is connected to the second main electrode plate 1530 and the second main electrode 120 of the switching element 10 is connected to the first main electrode plate 1520, for convenience of explanation, the first main electrode 100 of the switching element 10 will also be referred to as the second main electrode, and the second main electrode 120 of the switching element 10 will also be referred to as the first main electrode.

[0111] Fig. 16 is a perspective view of a semiconductor module 1600 according to a second modified example of this embodiment. Fig. 17 is a view of a semiconductor device 1500 according to the second modified example of this embodiment, viewed from the heat sink 1630 side. The semiconductor module 1600 is a modified example of the semiconductor module 800 shown in Figs. 8 to 14, and therefore a description thereof will be omitted hereinafter except for the differences. The semiconductor module 1600 includes one or more semiconductor devices 200, a main board 1610, one or more control devices 1620, one or more snubber capacitors 1640, one or more control connectors 1650, a heat sink 1630, and a fixing member 1660.

[0112] The semiconductor module 1600 according to this modification is an inverter device, similar to the semiconductor module 800. In the example of FIGS. 16 and 17 , the semiconductor module 1600 is a three-phase inverter, in which one semiconductor device 200 is assigned to the upper arm and one semiconductor device 200 is assigned to the lower arm for each phase. Therefore, the semiconductor module 1600 includes six semiconductor devices 200 (= three phases × (one upper arm + one lower arm)). Similar to the semiconductor module 800 shown in FIGS. 8 and 9 , the semiconductor module 1600 has a structure in which a plurality of semiconductor devices 200 are sandwiched between a main substrate 1610 and a heat sink 1630. For this reason, the plurality of semiconductor devices 200 are not shown in FIGS. 16 and 17 .

[0113] The semiconductor module 1600 may include semiconductor devices 200 for one phase, semiconductor devices 200 for two phases, or any number of phases, and may include one or more semiconductor devices 200 for each arm of each phase. The semiconductor module 1600 may have any circuit configuration using semiconductor devices 200, such as a three-level inverter or multilevel inverter having one or more phases, or a diode bridge, and may include any number of semiconductor devices 200 depending on the application. The semiconductor module 1600 may also include semiconductor devices 1500 instead of the semiconductor devices 200 as at least some of the semiconductor devices.

[0114] The main substrate 1610 corresponds to the main substrate 810 in the semiconductor module 800. The back surface of the main substrate 1610 is connected to the first main electrode plate 220, the second main electrode plate 230, and the control electrode plate 240 of at least one semiconductor device 200. When the semiconductor module 1600 mounts at least one semiconductor device 1500, the back surface of the main substrate 1610 is connected to the first main electrode plate 1520, the second main electrode plate 1530, and the control electrode plate 1540 of at least one semiconductor device 1500.

[0115] Of the semiconductor devices such as semiconductor device 200 and semiconductor device 1500, the three semiconductor devices (also referred to as "first semiconductor devices") of the upper arm are arranged at positions corresponding to the positions between the three control devices 1620a and the three snubber capacitors 1640a (the three snubber capacitors 1640 on the left side of the six snubber capacitors 1640 in the figure) on the back surface of main board 1610. Therefore, the three semiconductor devices of the upper arm are arranged in a row in the Y direction in the figure on the back surface of main board 1610.

[0116] The three semiconductor devices of the lower arm (also referred to as "second semiconductor devices") are arranged at positions corresponding to between the three control devices 1620b and the three snubber capacitors 1640b (the three snubber capacitors 1640 on the right side of the six snubber capacitors 1640 in the figure) on the back surface of the main board 1610. Therefore, the three semiconductor devices of the lower arm are arranged in a row in the Y direction in the figure alongside the three semiconductor devices of the upper arm on the back surface of the main board 1610.

[0117] Main board 1610 has a P terminal and an N terminal near the edge on its front surface that is farthest in the Y direction in the drawing. Main board 1610 also has a U terminal, a V terminal, and a W terminal near the edge on its front surface opposite the edge on which the P terminal and N terminal are provided. The P terminal, N terminal, U terminal, V terminal, and W terminal may have through holes into which bolts or the like can be inserted to secure high-current distribution cables, bus bars, or the like to each terminal.

[0118] The P wiring between the P terminal and each semiconductor device 200, the N wiring between the N terminal and each semiconductor device 200, the U wiring between the U terminal and the U-phase semiconductor device 200, the V wiring between the V terminal and the V-phase semiconductor device 200, and the W wiring between the W terminal and the W-phase semiconductor device 200 are provided in a range or region in the X direction within main substrate 1610 corresponding to the gap between three control devices 1620a and three control devices 1620b, and extend in the Y direction. The region in main substrate 1610 corresponding to the gap between the row of three semiconductor devices 200 on the upper arm and the row of semiconductor devices 200 on the lower arm is referred to as the "main wiring region." The main wiring region may be a region in rectangular main substrate 1610 extending from the side of the U-terminal, V-terminal, and W-terminal to the side of the P-terminal and N-terminal within the range between the row of three first semiconductor devices 200 on the upper arm and the row of three second semiconductor devices 200 on the lower arm. The main wiring region will be further described below using examples in FIGS.

[0119] One or more control devices 1620 are mounted on the front surface of the main board 1610. The control devices 1620 correspond to the control devices 820 in the semiconductor module 800. Each of the one or more control devices 1620 is electrically connected to the control electrode plate 240 and the sub-electrode plate 250 of one or more semiconductor devices 200 via wiring within the main board 1610. The control devices 1620 control the semiconductor devices 200 by controlling the voltage of the control electrode plate 240 relative to the sub-electrode plate 250 of the semiconductor device 200. Each control device 1620 may be connected to one semiconductor device 200 to control that single semiconductor device 200, or may be connected to two or more semiconductor devices 200 to control those two or more semiconductor devices 200. The control devices 1620 that control one or more semiconductor devices 1500 may be electrically connected to the control electrode plate 1540 and the sub-electrode plate 1550 of each semiconductor device 1500 via wiring within the main board 1610.

[0120] In this modification, each of the three control devices 1620a (also referred to as the "first control device 1620a") controls each of the three first semiconductor devices 200 in the upper arm. The three first control devices 1620a are arranged side by side in the Y direction on the front surface of the semiconductor module 1600, farther away from the three second semiconductor devices 200 in the lower arm than the three first semiconductor devices 200 in the upper arm (i.e., to the left in the X direction in the figure). The region of the main substrate 1610 where each first control device 1620a for controlling the upper arm is arranged, which is adjacent to the first semiconductor devices 200 in the upper arm with respect to the main wiring region in a top view, is referred to as the "first control wiring region." The first control wiring region may be a region of the rectangular main substrate 1610 located to the left of the main wiring region in the X direction and extending in the Y direction (the left side in the X direction). The first control wiring region will be described further below using the examples of FIGS. 18 and 19 .

[0121] Each of the three control devices 1620b (also referred to as "second control device 1620b") controls the three second semiconductor devices 200 of the lower arm. The three second control devices 1620b are arranged side by side in the Y direction on the front surface of the semiconductor module 1600, farther away from the three first semiconductor devices 200 of the upper arm than the three second semiconductor devices 200 of the lower arm (i.e., to the right in the X direction in the figure). The area of ​​the main substrate 1610 where the second control devices 1620b for controlling the lower arm are arranged, which is adjacent to the second semiconductor devices 200 of the lower arm with respect to the main wiring area in a top view, is referred to as the "second control wiring area." The second control wiring area may be an area of ​​the rectangular main substrate 1610 located to the right of the main wiring area in the X direction and extending in the Y direction (the right side in the X direction). The second control wiring area will be described further below using the examples of FIGS. 18 and 19 .

[0122] The plurality of snubber capacitors 1640 are arranged in the main wiring region on the front surface of the main board 1610. At least one snubber capacitor 1640a (also referred to as a "first snubber capacitor 1640a") may be provided corresponding to each phase of the upper arm. In this modification, three snubber capacitors 1640a are provided corresponding to the three phases of the upper arm. The three snubber capacitors 1640a may be provided above the P wiring within the main board 1610. Each snubber capacitor 1640a is connected in parallel with the corresponding semiconductor device 200 between the P wiring and the output wiring of the corresponding phase, which is the U wiring, V wiring, or W wiring, to suppress the generation of a transient high voltage when the corresponding semiconductor device 200 is switched.

[0123] At least one snubber capacitor 1640b (also referred to as a "second snubber capacitor 1640b") may be provided corresponding to each phase of the lower arm. In this modification, three snubber capacitors 1640b are provided corresponding to the three phases of the lower arm. The three snubber capacitors 1640b may be provided above the N wiring in the main board 1610. Each snubber capacitor 1640b is connected in parallel with the corresponding semiconductor device 200 between the N wiring and the output wiring of the corresponding phase, which is the U wiring, V wiring, or W wiring, to suppress the generation of a transient high voltage when the corresponding semiconductor device 200 is switched.

[0124] Each snubber capacitor may be connected between the P wiring and the N wiring of the corresponding arm. This connection method also allows the snubber capacitor to suppress the generation of a transient high voltage when the corresponding semiconductor device 200 is switched.

[0125] At least one control connector 1650 is mounted on the front surface of the main board 1610 and is electrically connected to at least one control device 1620. The semiconductor module 1600 is electrically connected to an external control device via a cable that is detachably connected to the at least one control connector 1650. The at least one control device 1620 may receive control signals from the external control device via the cable and the at least one control connector 1650 to control one or more semiconductor devices 200.

[0126] In this variation, at least one control connector 1650a (also referred to as "first control connector 1650a") is disposed in a first control wiring region on the front surface of the main board 1610 and is electrically connected to at least one first control device 1620a. At least one control connector 1650b (also referred to as "second control connector 1650b") is disposed in a second control wiring region on the front surface of the main board 1610 and is electrically connected to at least one second control device 1620b.

[0127] The heat sink 1630 is provided on the rear surface of the main board 1610 to which at least one semiconductor device 1500 is connected. The heat sink 1630 contacts the surface of one or more semiconductor devices 200 opposite to the main board 810. The heat sink 1630 corresponds to the heat sink 830 in the semiconductor module 800. The heat sink 1630 may be, for example, a heat spreader, a heat sink, or a heat exchanger for liquid cooling.

[0128] In this modification, the heat sink 1630 has a structure in which one or more protruding members 1670 and one or more protruding members 1710 are provided on a surface of a plate-like member (main body of the heat sink 1630) that faces the main substrate 1610 and at least one semiconductor device 1500, on the surface of the plate-like member opposite the main substrate 1610 and at least one semiconductor device 1500. The plate-like member of the heat sink 1630 may have a size that does not cover the P terminal, N terminal, U terminal, V terminal, and W terminal on the back surface of the main substrate 1610.

[0129] Each of the one or more protruding members 1670 is a cylindrical or other arbitrary shaped protrusion that protrudes from the surface of the plate-like member of the heat sink 1630 opposite the main substrate 1610. The protruding member 1670 is fixed to the main substrate 1610 by a fixing member 1660 that extends from the front surface of the main substrate 1610, penetrates the plate-like member of the heat sink 1630, and reaches the protruding member 1670. In this way, the heat sink 1630 is fixed to the back surface of the main substrate 1610. This will be described later using the example of FIG. 23 .

[0130] At least some of the multiple protrusion members 1670 (six protrusion members 1670 in the example shown in this figure) are arranged along the Y-direction sides located on the left and right sides of the X-direction of the heat sink 1630. In addition, other parts of the multiple protrusion members 1670 (two protrusion members 1670 in the example shown in this figure) are arranged along the Y-direction sides in the central part of the heat sink 1630 in the X-direction of the figure.

[0131] Each of the one or more protruding members 1710 is a cylindrical or other arbitrary shaped protrusion that protrudes from the surface of the plate-like member of the heat sink 1630 opposite the main board 1610. The protruding member 1670 does not need to have the function of being fixed to the main board 1610 by the fixing member 1660 or the like. The multiple protruding members 1710 may be arranged in a range corresponding to the main wiring region of the main board 1610.

[0132] The protruding members 1670 and 1710 increase the surface area of ​​the heat sink 1630 to improve heat dissipation efficiency. The surfaces of the heat sink 1630 on which the protruding members 1670 and 1710 are provided may be in contact with the gaseous or liquid refrigerant or may be exposed to the refrigerant flow path.

[0133] FIG. 18 shows the connections of the wiring within a semiconductor module 1800 according to a third modified example of this embodiment. This modified example is a modification of the connection structure of the wiring within the semiconductor module 800 shown in FIG. 10 , and therefore, description thereof will be omitted hereinafter except for the differences. In the semiconductor module 800 shown in FIG. 10 , the six sets of semiconductor devices 200 on the upper and lower arms are arranged in the order of U-phase, V-phase, W-phase, U-phase, V-phase, and W-phase from the left side of FIG. 10 . In contrast, in the semiconductor module 1800 shown in FIG. 18 , the six sets of semiconductor devices 200 on the upper and lower arms are arranged in the order of W-phase, W-phase, V-phase, V-phase, U-phase, and U-phase from the left side of FIG. 18 , with two semiconductor devices 200 adjacent to each other on the upper and lower sides corresponding to each phase.

[0134] For the U-phase, the at least one semiconductor device 200 includes at least one first semiconductor device 200 (UU1, UU2) and at least one second semiconductor device 200 (UD1, UD2). The at least one first semiconductor device 200 (UU1, UU2) is an upper arm semiconductor device 200 (the upper semiconductor device 200 in the figure), and the at least one second semiconductor device 200 (UD1, UD2) is a lower arm semiconductor device 200 (the lower semiconductor device 200 in the figure). The at least one first semiconductor device 200 for the U-phase is also referred to as the first at least one first semiconductor device 200. Furthermore, the at least one second semiconductor device 200 for the U-phase is also referred to as the first at least one second semiconductor device 200.

[0135] Similarly, for the V-phase, the at least one semiconductor device 200 includes at least one first semiconductor device 200 (VU1, VU2) and at least one second semiconductor device 200 (VD1, VD2). The at least one first semiconductor device 200 of the V-phase is also referred to as the second at least one first semiconductor device 200. Also, the at least one second semiconductor device 200 of the V-phase is also referred to as the second at least one second semiconductor device 200.

[0136] Similarly, for the W-phase, the at least one semiconductor device 200 includes at least one first semiconductor device 200 (WU1, WU2) and at least one second semiconductor device 200 (WD1, WD2). The at least one first semiconductor device 200 of the W-phase is also referred to as the third at least one first semiconductor device 200. The at least one second semiconductor device 200 of the W-phase is also referred to as the third at least one second semiconductor device 200.

[0137] The first semiconductor devices 200 of the U-phase, V-phase, and W-phase are arranged in a row on the rear surface of the main substrate 1610. The second semiconductor devices 200 of the U-phase, V-phase, and W-phase are arranged in a row on the rear surface of the main substrate 1610, alongside the row of the first semiconductor devices 200.

[0138] In this modification, on the back surface of the main substrate 1610, each of the at least one first semiconductor device 200 and a corresponding second semiconductor device 200 among the at least one second semiconductor device 200 are arranged with their first main electrode plates 220 facing each other. This allows the semiconductor module 1800 to arrange the control electrode plate 240 and sub-electrode plate 250, to which control wiring is connected, on the opposite side of the opposing semiconductor device 200, making it easier to arrange the control wiring away from the main wiring, such as the P wiring 1812, N wiring 1813, U wiring 1814, V wiring 1815, and W wiring 1816, which carry the main current. Depending on the convenience of implementation, etc., each of the at least one first semiconductor device 200 and a corresponding second semiconductor device 200 among the at least one second semiconductor device 200 may be arranged on the back surface of the main substrate 1610 with their first main electrode plates 220 and control electrode plates 240 facing each other.

[0139] The positive-side main electrode plate (the second main electrode plate 230 serving as a drain in the example shown in the figure) of each of the first main electrode plates 220 and second main electrode plates 230 of at least one first semiconductor device 200 (UU1, UU2, VU1, VU2, WU1, WU2) of each phase is connected to the P-terminal via a P-wiring 1812 in the main substrate 1610. The negative-side main electrode plate (the first main electrode plate 220 serving as a source) of each of the first main electrode plates 220 and second main electrode plates 230 of at least one second semiconductor device 200 (UD1, UD2, VD1, VD2, WD1, WD2) of each phase is connected to the N-terminal via an N-wiring 1813 in the main substrate 1610. The negative-side main electrode plate (first main electrode plate 220 as source) of each of the first main electrode plates 220 and second main electrode plates 230 of at least one first semiconductor device 200 in each phase is electrically connected to the positive-side main terminal plate (second main electrode plate 230 as drain) of the first main electrode plate 220 and second main electrode plate 230 of the corresponding second semiconductor device 200 of at least one second semiconductor device 200.

[0140] For the U phase, the negative side main electrode plate (first main electrode plate 220 as source) of the first main electrode plate 220 and the second main electrode plate 230 of at least the first semiconductor device 200 (UU1, UU2) and the positive side main electrode plate (second main electrode plate 230 as drain) of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (UD1, UD2) are connected to the U terminal, which is the first output terminal, via U wiring 1814, which is the first output wiring in the main substrate 1610. For the V phase, the negative side main electrode plate (first main electrode plate 220 as source) of the first main electrode plate 220 and the second main electrode plate 230 of at least the first semiconductor device 200 (VU1, VU2) and the positive side main electrode plate (second main electrode plate 230 as drain) of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (VD1, VD2) are connected to the V terminal, which is the second output terminal, via V wiring 1815, which is the second output wiring in the main substrate 1610. For the W phase, the negative side main electrode plate (first main electrode plate 220 as source) of the first main electrode plate 220 and the second main electrode plate 230 of at least the first semiconductor device 200 (WU1, WU2) and the positive side main electrode plate (second main electrode plate 230 as drain) of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (WD1, WD2) are connected to the U terminal, which is the first output terminal, via W wiring 1816, which is the third output wiring in the main substrate 1610.

[0141] P wiring 1812, N wiring 1813, U wiring 1814, V wiring 1815, and W wiring 1816 are provided in a main wiring region of main substrate 1610 corresponding to the area from the row of first semiconductor devices 200 of the U-phase, V-phase, and W-phase to the row of second semiconductor devices 200 of the U-phase, V-phase, and W-phase in top view. Here, when control electrode plate 240 of each semiconductor device 200 is disposed on the opposite side of the opposing semiconductor device 200, the main wiring region may be an area including first main electrode plate 220 and second main electrode plate 230 of semiconductor device 200. In contrast, control devices such as control device 1620 and most of the control wiring from the control device to control electrode plate 240 and sub-electrode plate 250 of each semiconductor device 200 are provided in a control wiring region distinct from the main wiring region. This allows the semiconductor module 1800 to prevent noise from being applied to the control devices and control wiring within the control wiring area due to a large current flowing through the main wiring arranged in the main wiring area.

[0142] The semiconductor module 800 may have the wiring connection structure according to this modification, instead of the wiring connection structure shown in Fig. 10. The semiconductor module 1600 shown in Figs. 16 and 17 may have a wiring connection structure in which the number of semiconductor devices 200 for each phase arm in the figures is one (i.e., a structure in which the semiconductor devices 200 UU2, UD2, VU2, VD2, WU2, and WD2 are removed from the semiconductor module 1800).

[0143] 19 shows the connections of the wiring within a semiconductor module 1900 according to a fourth modification of the present embodiment. The semiconductor module 1900 according to this modification is a modification of the semiconductor module 1800 shown in FIG. 18 , and therefore, a description thereof will be omitted hereinafter except for the differences.

[0144] The semiconductor module 1900 includes semiconductor devices 1500 instead of the semiconductor devices 200 as the semiconductor devices of the lower arm. The positive-side second main electrode plate 230 of each first semiconductor device 200 is connected to the P-terminal via P wiring 1912 in the main substrate 1610, as in the semiconductor module 1800. The negative-side main electrode plate of each second semiconductor device 1500 is the second main electrode plate 1530, and therefore the second main electrode plate 1530 of each second semiconductor device 1500 is connected to the N-terminal via N wiring 1913. The positive-side main electrode plate of each second semiconductor device 1500 is the first main electrode plate 1520, and therefore the first main electrode plate 1520 of each second semiconductor device 1500 is connected to the first main electrode plate 220 of the corresponding first semiconductor device 200 and to the U-terminal, V-terminal, or W-terminal via U wiring 1914, V wiring 1915, or W wiring 1916.

[0145] According to this modification, by configuring the upper and lower arms using semiconductor device 1500 and semiconductor device 200 whose main electrode plates have polarities different from those of semiconductor device 200, it is sufficient for output wiring such as U wiring 1914, V wiring 1915, and W wiring 1916 to connect between the opposing first main electrode plates 220 and 1520. Therefore, according to this modification, the wiring length from the P wiring to the N wiring via the semiconductor devices of the upper and lower arms can be further shortened.

[0146] FIG. 20 shows a semiconductor module 2000 according to a fifth modification of this embodiment. This modification is a modification of the semiconductor module 1600 shown in FIGS. 16 and 17, and therefore, a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be applied to the semiconductor module 800 shown in FIGS. 8 and 9, the semiconductor module 1800 shown in FIG. 18, and the semiconductor module 1900 shown in FIG. 19. The semiconductor module 2000 includes one or more semiconductor devices 200, a main board 2010, one or more control devices 2020, and one or more control connectors 2050.

[0147] The semiconductor module 2000 according to this modification has a configuration equivalent to the upper and lower arms of one phase of an inverter device. In the semiconductor module 2000, four semiconductor devices 200 are assigned to the upper arm and four semiconductor devices 200 are assigned to the lower arm. Alternatively, the semiconductor module 2000 may have a number of semiconductor devices 200 other than four (1, 2, 3, or any number greater than or equal to 5) in each of the upper and lower arms. Similar to the semiconductor module 1600 shown in FIGS. 16 and 17 , the semiconductor module 2000 has a structure in which multiple semiconductor devices 200 are sandwiched between a main board 2010 and a heat sink (not shown) on the back side of the drawing. For this reason, the multiple semiconductor devices 200 are not shown in FIG. 20 . Note that the semiconductor module 2000 may have a configuration in which some of the semiconductor devices 200 are replaced with semiconductor devices 1500, as in the semiconductor module 1900, for example.

[0148] The main board 2010 corresponds to the main board 1610 in the semiconductor module 1600. On the back surface of the main board 2010, the four semiconductor devices 200 (first semiconductor devices 200) of the upper arm are arranged in a row to the right of the four first control devices 2020a in the figure when viewed from above, and the four semiconductor devices 200 (second semiconductor devices 200) of the lower arm are arranged in a row to the left of the four second control devices 2020b in the figure when viewed from above.

[0149] The main substrate 2010 has a P terminal and an N terminal near the upper edge of the front surface in the figure. The main substrate 2010 also has an output terminal near the edge of the front surface opposite the edge on which the P terminal and N terminal are provided. The output terminal may be used as a U terminal, a V terminal, a W terminal, or other terminal. The P wiring between the P terminal and each semiconductor device 200 in the upper arm, the N wiring between the N terminal and each semiconductor device 200 in the lower arm, and the output wiring between the output terminal and each semiconductor device 200 are provided in a main wiring region of the main substrate 2010 corresponding to the area between the four semiconductor devices 200 in the upper arm (corresponding to the right side of the four control devices 2020a in the figure) and the four semiconductor devices 200 in the lower arm (corresponding to the left side of the four control devices 2020b in the figure) in a top view, and extend in the vertical direction in the figure.

[0150] The multiple control devices 2020 are mounted on the front surface of the main substrate 2010. The control devices 2020 correspond to the control devices 1620 in the semiconductor module 1600. In this modification, each of the four control devices 2020a (first control devices 2020a) controls each of the four first semiconductor devices 200 in the upper arm. The four first control devices 2020a are arranged side by side in the vertical direction in the figure in a first control wiring region on the front surface of the main substrate 2010, which is adjacent to the four first semiconductor devices 200 in the upper arm with respect to the main wiring region in a top view. Each of the four control devices 2020b (second control devices 2020b) controls each of the four second semiconductor devices 200 in the lower arm. The four second control devices 2020b are arranged in a line in the vertical direction in the figure in a second control wiring area on the front surface of the main board 2010, which is adjacent to the four second semiconductor devices 200 of the lower arm relative to the main wiring area when viewed from above.

[0151] The plurality of control connectors 2050 are mounted on the front surface of the main board 2010 and are electrically connected to the plurality of control devices 2020. The control connectors 2050 correspond to the control connectors 1650 in the semiconductor module 1600. In this modification, the first control connector 2050a is arranged in a first control wiring region on the front surface of the main board 2010 and is electrically connected to each of the first control devices 2020a. The second control connector 2050b is arranged in a second control wiring region on the front surface of the main board 2010 and is electrically connected to each of the second control devices 2020b.

[0152] An inverter device having multiple phases may be realized by mounting the same number of semiconductor modules 2000 as the number of phases. For example, a three-phase inverter device is realized by arranging a semiconductor module 2000 for a U phase, a semiconductor module 2000 for a V phase, and a semiconductor module 2000 for a W phase in parallel. These multiple semiconductor modules 2000 may be arranged side by side in the horizontal direction in the figure. Alternatively, an inverter device having multiple phases may be realized by using the semiconductor module 2000 shown in this figure as a basic block and mounting basic blocks for multiple phases using a single main board.

[0153] FIG. 21 shows a semiconductor module 2100 according to a sixth modified example of this embodiment, together with a film capacitor 2180. This modified example is a modification of the semiconductor module 1600 shown in FIGS. 16 and 17, and therefore a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modified example may be applied to the semiconductor module 800 shown in FIGS. 8 and 9, the semiconductor module 1800 shown in FIG. 18, the semiconductor module 1900 shown in FIG. 19, and the semiconductor module 2000 shown in FIG. 20. The semiconductor module 2100 includes one or more semiconductor devices 200, a main board 2110, one or more control devices 2120, and one or more control connectors 2150.

[0154] The semiconductor module 2100 according to this modification is an inverter device, similar to the semiconductor module 1600. In the example shown in the figure, the semiconductor module 2100 is a three-phase inverter, with four semiconductor devices 200 assigned to the upper arm and four semiconductor devices 200 assigned to the lower arm for each phase. Therefore, the semiconductor module 2100 includes 24 semiconductor devices 200 (= 3 phases × (4 upper arms + 4 lower arms)). Similar to the semiconductor module 1600 shown in Figures 16 and 17, the semiconductor module 2100 has a structure in which multiple semiconductor devices 200 are sandwiched between a main board 2110 and a heat sink (not shown) on the back side of the drawing. For this reason, the multiple semiconductor devices 200 are not shown in Figure 21. Note that the semiconductor module 2100 may have a configuration in which some of the semiconductor devices 200 are replaced with semiconductor devices 1500, as in the semiconductor module 1900, for example.

[0155] The main board 2110 corresponds to the main board 1610 in the semiconductor module 1600. On the back surface of the main board 2110, the 12 semiconductor devices 200 (first semiconductor devices 200) of the upper arm are arranged in a row to the right of the 12 first control devices 2120a in the figure, and the 12 semiconductor devices 200 (second semiconductor devices 200) of the lower arm are arranged in a row to the left of the 12 second control devices 2120b in the figure.

[0156] The main board 2110 has a P terminal and an N terminal near the upper edge of the front surface. The main board 2110 also has output terminals, a U terminal, a V terminal, and a W terminal, near the edge opposite the edge on the front surface where the P terminal and N terminal are provided. The P wiring between the P terminal and each semiconductor device 200 in the upper arm, the N wiring between the N terminal and each semiconductor device 200 in the lower arm, and the output wiring between each output terminal and each corresponding semiconductor device 200 are provided in a main wiring region on the main board 2110 corresponding to the area between the right side of the 12 control devices 2120a and the left side of the 12 control devices 2120b, and extend in the vertical direction of the figure. The semiconductor module 2100 may have a configuration similar to that of the semiconductor module 1800 of FIG. 18 or the semiconductor module 1900 of FIG. 19, with the number of semiconductor devices per arm per phase increased from two to four.

[0157] The multiple control devices 2120 are mounted on the front surface of the main substrate 2110. The control devices 2120 correspond to the control devices 1620 in the semiconductor module 1600. In this modification, each of the 12 control devices 2120a (first control devices 2120a) controls each of the 12 first semiconductor devices 200 in the upper arm. The 12 first control devices 2120a are arranged side by side in the vertical direction in the figure in a first control wiring region on the front surface of the main substrate 2110, which is adjacent to the 12 first semiconductor devices 200 in the upper arm with respect to the main wiring region in a top view. Each of the 12 control devices 2120b (second control devices 2120b) controls each of the 12 second semiconductor devices 200 in the lower arm. The twelve second control devices 2120b are arranged in a row in the vertical direction in the figure in a second control wiring area on the front surface of the main board 2010, which is adjacent to the twelve second semiconductor devices 200 of the lower arm relative to the main wiring area when viewed from above.

[0158] The plurality of control connectors 2150 are mounted on the front surface of the main board 2110 and are electrically connected to the plurality of control devices 2120. The control connectors 2150 correspond to the control connectors 1650 in the semiconductor module 1600. In this modification, one first control connector 2150a is provided for each upper arm of each phase. Each first control connector 2150a is arranged in a first control wiring region on the front surface of the main board 2110 and is electrically connected to the four first control devices 2120a corresponding to each phase. One second control connector 2150b is provided for each lower arm of each phase. Each second control connector 2150b is arranged in a second control wiring region on the front surface of the main board 2110 and is electrically connected to the four first control devices 2120b corresponding to each phase.

[0159] The film capacitor 2180 can be connected to the semiconductor module 2100 on the side where the P terminal and N terminal are provided. The film capacitor 2180 may have substantially the same width (horizontal length in the figure) as the semiconductor module 2100, or may have a width larger or smaller than that of the semiconductor module 2100. The film capacitor 2180 is electrically connected between the P terminal and the N terminal. The film capacitor 2180 has a larger capacitance than a snubber capacitor such as the snubber capacitor 1640. The film capacitor 2180 stabilizes the potentials of the P terminal and the N terminal of the semiconductor module 2100 and suppresses fluctuations in the potentials of the P terminal and the N terminal even when the magnitude of the current output from each output terminal changes significantly. The semiconductor module 2100 may be connected to a capacitor other than a film capacitor instead of the film capacitor 2180. In the semiconductor module 800 shown in Figures 8 and 9, the semiconductor module 1600 shown in Figures 16 and 17, the semiconductor module 1800 shown in Figure 18, the semiconductor module 1900 shown in Figure 19, and the semiconductor module 2000 shown in Figure 20, a capacitor such as film capacitor 2180 may be connected between the P terminal and the N terminal.

[0160] FIG. 22 shows a semiconductor module 2200 according to a seventh modification of this embodiment. This modification is a modification of the semiconductor module 800 shown in FIG. 10, the semiconductor module 1800 shown in FIG. 18, and the semiconductor module 1900 shown in FIG. 19, and therefore a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may also be applied to the semiconductor module 2000 shown in FIG. 20 and the semiconductor module 2100 shown in FIG. 21. The semiconductor module 2200 includes a plurality of semiconductor devices 200.

[0161] In this modification, on the back surface of a main substrate such as main substrate 810, main substrate 1610, main substrate 2010, or main substrate 2110, at least one first semiconductor device 200 and a corresponding second semiconductor device 200 among at least one second semiconductor device 200 are arranged side by side in a direction perpendicular to the arrangement of the first main electrode plate 220, the second main electrode plate 230, and the control electrode plate 240 (the arrangement direction of the electrode plates in the semiconductor device 200). In the example of this figure, the first semiconductor device 200 on the upper side in the figure and the second semiconductor device 200 on the lower side in the figure are arranged side by side in a direction perpendicular to the arrangement direction of the electrode plates.

[0162] The positive terminal of the semiconductor module 2200 is connected via a positive wiring to the positive main electrode plate of the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (in the example of this figure, the second main electrode plate 230 of the upper semiconductor device 200). The negative terminal of the semiconductor module 2200 is connected via a negative wiring to the negative main electrode plate of the first main electrode plate 220 and the second main electrode plate 230 of the second semiconductor device 200 (in the example of this figure, the first main electrode plate 220 of the lower semiconductor device 200). The output terminal of the semiconductor module 2200 is connected via output wiring to the negative main electrode plate of the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (in the example of this figure, the first main electrode plate 220 of the upper semiconductor device 200) and to the positive main electrode plate of the first main electrode plate 220 and the second main electrode plate 230 of the second semiconductor device 200 (in the example of this figure, the second main electrode plate 230 of the lower semiconductor device 200).

[0163] In the semiconductor module 2200, the positive wiring, negative wiring, and output wiring extend in a direction in which each of the at least one first semiconductor device 200 and a corresponding one of the at least one second semiconductor device 200 are aligned. In the example shown in the figure, the positive wiring, negative wiring, and output wiring extend in the vertical direction in the figure.

[0164] In the example shown in the figure, the semiconductor module 2200 includes one semiconductor device 200 for each arm. Alternatively, the semiconductor module 2200 may include two or more semiconductor devices 200 for each arm, and two or more first semiconductor devices 200 and two or more second semiconductor devices 200 may be arranged in a line in a direction perpendicular to the arrangement direction of the electrode plates. Furthermore, the semiconductor module 2200 may include one or more first semiconductor devices 200 and one or more second semiconductor devices 200 for each of the multiple phases, and these semiconductor devices 200 may be arranged in a line in a direction perpendicular to the arrangement direction of the electrode plates.

[0165] Figure 23 is a schematic cross-sectional view of a semiconductor module 2300 according to an eighth modification of this embodiment. This modification is a modification of the semiconductor module 1600 shown in Figure 16 in terms of overall structure, and a modification of the semiconductor module 800 shown in Figures 8 to 14 in terms of cross-sectional structure, so a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be made to the semiconductor module 1800 shown in Figure 18, the semiconductor module 1900 shown in Figure 19, the semiconductor module 2000 shown in Figure 20, the semiconductor module 2100 shown in Figure 21, and the semiconductor module 2200 shown in Figure 22.

[0166] 11 . In S1100, one or more semiconductor devices 200 are prepared, each having a first main electrode plate 220, a second main electrode plate 230, and a control electrode plate 240 on one side, a first main electrode connected to the first main electrode plate 220, a second main electrode connected to the second main electrode plate 230, and a control electrode connected to the control electrode plate 240. Some of the semiconductor devices may be semiconductor devices 1500 instead of semiconductor devices 200.

[0167] In S1110, a main substrate 1610 is prepared, the back surface of which is connected the first main electrode plate 220, the second main electrode plate 230, the sub-electrode plate 250, and the control electrode plate 240 of at least one semiconductor device 200. In this modification, the main substrate 1610 has at least one main substrate recess 2315 on its back surface, into which at least a portion of at least one semiconductor device 200 is embedded. The main substrate 1610 may have separate main substrate recesses 2315 for each of all semiconductor devices 200 mounted on the back surface of the main substrate 1610. Alternatively, the main substrate 1610 may have a common main substrate recess 2315 for two or more semiconductor devices 200.

[0168] The main substrate recess 2315 may have a depth equal to or greater than the thickness of the semiconductor device 200, such that the entire semiconductor device 200 is accommodated therein. Alternatively, the main substrate recess 2315 may have a depth less than the thickness of the semiconductor device 200, such that only a portion of the semiconductor device 200 is accommodated therein, with the remaining portion protruding from the back surface of the main substrate 1610.

[0169] In S1120, at least one control device 1620 is mounted on the front surface of the main board 1610 by soldering or the like to the front surface of the main board 1610. In this modification, the control device 1620 is arranged in a control wiring area that is located on the side of the semiconductor device 200 to which it is connected, relative to a main wiring area in which main wiring connected to the first main electrode plate 220 and the second main electrode plate 230 of the semiconductor device 200 is arranged.

[0170] In S1130, at least one semiconductor device 200 is sandwiched between the back surface of the main substrate 1610 and the heat sink 1630, and each electrode plate of the semiconductor device 200 is connected to the back surface of the main substrate 1610. The first main electrode plate 220, the second main electrode plate 230, and the control electrode plate 240 of the at least one semiconductor device 200 are connected to the main substrate 1610 at the bottom surface of at least one main substrate recess 2315. Note that in S1120 and S1130, at least one control device 1620 may be mounted on the front surface of the main substrate 1610 after the at least one semiconductor device 200 is connected to the back surface of the main substrate 1610.

[0171] Then, the heat sink 1630 is attached to the rear surface of the main board 1610 to which at least one semiconductor device 200 is connected. In this way, the heat sink 1630 is attached to the surface of each semiconductor device 200 opposite to the main board 1610.

[0172] A thermally conductive material 2390 may be embedded, painted, injected, or attached to part or all of the gap between the main substrate 1610 and the heat sink 1630. The thermally conductive material 2390 may be a paste-like thermally conductive grease or filler, a thermally conductive sheet or a heat dissipation sheet, or any other TIM (Thermal Interface Material). The thermally conductive material 2390 can increase the thermal conductivity between the insulating substrate 500 side of the semiconductor device 200 (or the thermally conductive plate 1270) and the back surface of the main substrate 1610 and the heat sink 1630, thereby enabling more efficient cooling of the semiconductor device 200 and the main substrate 1610.

[0173] Furthermore, the main board 1610 is fixed to the heat sink 1630 by at least one thermally conductive fixing member 1660 that penetrates from the front surface of the main board 1610 through the plate-like member of the heat sink 1630 and reaches at least one protruding member 1670. As an example, each fixing member 1660 may be a screw, and each protruding member 1670 may have a screw hole into which the screw fits. The fixing member 1660 and the protruding member 1670 may be made of metal, such as copper, aluminum, iron, or stainless steel. As a result, the fixing member 1660 for fixing the heat sink 1630 to the main board 1610 transfers heat from the main board 1610 to the protruding member 1670, and the protruding member 1670 can release heat from the fixing member 1660 to the refrigerant. Therefore, the fixing member 1660 and the protruding member 1670 can improve the cooling performance of the main board 1610.

[0174] Figure 24 is a schematic cross-sectional view of a semiconductor module 2400 according to a ninth modification of this embodiment. This modification is a modification of the semiconductor module 2300 shown in Figure 23, and therefore, a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be applied to the semiconductor module 800 shown in Figures 8 to 14, the semiconductor module 1600 shown in Figure 16, the semiconductor module 1800 shown in Figure 18, the semiconductor module 1900 shown in Figure 19, the semiconductor module 2000 shown in Figure 20, the semiconductor module 2100 shown in Figure 21, and the semiconductor module 2200 shown in Figure 22.

[0175] In this modification, the main substrate 1610 does not have a main substrate recess 2315, and the heat sink 1630 has at least one heat sink recess 2410 on the surface facing at least one semiconductor device 200, in which at least a portion of at least one semiconductor device 200 is embedded. The heat sink 1630 may have a separate heat sink recess 2410 for each of all semiconductor devices 200 mounted on the back surface of the main substrate 1610. Alternatively, the heat sink 1630 may have a common heat sink recess 2410 for two or more semiconductor devices 200. The heat sink recess 2410 may have a depth less than the thickness of the semiconductor device 200, so that only a portion of the semiconductor device 200 is accommodated within the recess, and the remaining portion may protrude from the top surface of the heat sink 1630 in the figure. Alternatively, the heat sink recess 2410 may have a depth approximately equal to the thickness of the semiconductor device 200, so that the entire semiconductor device 200 is accommodated within the recess.

[0176] The thermally conductive material 2390 may be in a paste or liquid form and may also be filled into the heat sink recess 2410. One or more grooves may be formed in the bottom surface of the heat sink recess 2410, extending from below the semiconductor device 200 to the periphery. The one or more grooves may also be formed along the side surface of the heat sink recess 2410. In this way, when the heat sink 1630 is pressed against the main substrate 1610 to secure the heat sink 1630 to the main substrate 1610, excess thermally conductive material 2390 flows out from below the semiconductor device 200 to the periphery through the multiple grooves. This allows the semiconductor module 2400 to more closely attach the heat sink 1630 to the semiconductor device 200.

[0177] By having the heat sink recess 2410 on the heat sink 1630 side of the semiconductor module 2400, it is possible to reduce the gap between the main board 1610 and the heat sink 1630 and improve the cooling efficiency of the main board 1610. The main board 1610 of the semiconductor module 2400 may further have a main board recess 2315, and the semiconductor device 200 may be housed between the main board recess 2315 and the heat sink recess 2410.

[0178] Figure 25 is a schematic cross-sectional view of a semiconductor module 2500 according to a tenth modification of this embodiment. This modification is a modification of the semiconductor module 2400 shown in Figure 24, and therefore, a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be applied to the semiconductor module 800 shown in Figures 8 to 14, the semiconductor module 1600 shown in Figure 16, the semiconductor module 1800 shown in Figure 18, the semiconductor module 1900 shown in Figure 19, the semiconductor module 2000 shown in Figure 20, the semiconductor module 2100 shown in Figure 21, and the semiconductor module 2200 shown in Figure 22.

[0179] In this modification, the thermally conductive material 2390 is provided only near or around each semiconductor device 200 in the gap between the main substrate 1610 and the heat sink 1630. In the example shown in the figure, the thermally conductive material 2390 is filled in the heat sink recess 2410 and covers the surface and side surfaces of the semiconductor device 200 facing the heat sink 1630. This allows the semiconductor module 2500 to improve the cooling efficiency of the semiconductor device 200.

[0180] Fig. 26 is a schematic cross-sectional view of a semiconductor module 2600 according to an eleventh modification of this embodiment. This modification is a modification of the semiconductor module 2300 shown in Fig. 23, and therefore, a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be applied to the semiconductor module 800 shown in Figs. 8 to 14, the semiconductor module 1600 shown in Fig. 16, the semiconductor module 1800 shown in Fig. 18, the semiconductor module 1900 shown in Fig. 19, the semiconductor module 2000 shown in Fig. 20, the semiconductor module 2100 shown in Fig. 21, and the semiconductor module 2200 shown in Fig. 22.

[0181] In this modification, the main substrate 1610 does not have a main substrate recess 2315, and the heat sink 1630 has at least one heat sink protrusion 2620 on the surface facing at least one semiconductor device 200, at a position corresponding to at least one semiconductor device 200. The heat sink 1630 may have a heat sink protrusion 2620 for each of all semiconductor devices 200 mounted on the back surface of the main substrate 1610. Alternatively, the heat sink 1630 may have a heat sink protrusion 2620 common to two or more semiconductor devices 200.

[0182] The upper surface of the heat sink protrusion 2620 may have one or more grooves formed thereon, extending from below the semiconductor device 200 to the periphery thereof. This allows excess thermally conductive material 2390 to flow through the grooves from below the semiconductor device 200 to the periphery thereof when the heat sink 1630 is pressed against the main substrate 1610 to secure the heat sink 1630 to the main substrate 1610. This allows the semiconductor module 2600 to more closely attach the heat sink 1630 to the semiconductor device 200.

[0183] By having the heat sink protrusion 2620 on the heat sink 1630 side, the semiconductor module 2600 can reduce the gap between the semiconductor device 200 and the heat sink 1630, thereby improving the cooling efficiency of the semiconductor device 200. The main substrate 1610 of the semiconductor module 2600 may further have a main substrate recess 2315 to accommodate at least a portion of the semiconductor device 200. The main substrate 1610 may also have a main substrate protrusion at a position where each semiconductor device 200 is connected.

[0184] Figure 27 is a schematic cross-sectional view of a semiconductor module 2700 according to a twelfth modification of this embodiment. This modification is a modification of the semiconductor module 2600 shown in Figure 26, and therefore, a description thereof will be omitted hereinafter except for the differences. Note that the same modifications as those of this modification may be applied to the semiconductor module 800 shown in Figures 8 to 14, the semiconductor module 1600 shown in Figure 16, the semiconductor module 1800 shown in Figure 18, the semiconductor module 1900 shown in Figure 19, the semiconductor module 2000 shown in Figure 20, the semiconductor module 2100 shown in Figure 21, and the semiconductor module 2200 shown in Figure 22.

[0185] In this modification, the thermally conductive material 2390 is provided only near or around each semiconductor device 200 in the gap between the main substrate 1610 and the heat sink 1630. In the example shown in the figure, the thermally conductive material 2390 is disposed on the heat sink protrusion 2620 by coating or the like, and covers the surface and side surfaces of the semiconductor device 200 facing the heat sink 1630. This allows the semiconductor module 2700 to improve the cooling efficiency of the semiconductor device 200.

[0186] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0187] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0188] According to the present specification, the following aspects are also disclosed.

[0189] In a first aspect, a semiconductor device is provided, comprising: a switching element having a first main electrode and a control electrode on one surface and a second main electrode on the opposite surface; and a mounting substrate having, on a mounting surface of the switching element, a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode, and having, in an area of ​​the mounting surface of the switching element where the switching element is not arranged, a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode.

[0190] The semiconductor device may include a sealing portion that covers the mounting surface of the switching element on the mounting substrate and the surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

[0191] In any of the semiconductor devices described above, the switching element may be disposed between the first main electrode plate and the control electrode plate on the mounting surface of the mounting substrate where the switching element is mounted.

[0192] In any of the above semiconductor devices, the first main electrode wiring may have a plurality of bumps in contact with the first main electrode, and the control wiring may have a plurality of bumps in contact with the control electrode.

[0193] In any of the above semiconductor devices, the mounting substrate may have an insulating substrate, and first main electrode wiring, a first main electrode plate, control wiring, and a control electrode plate formed on the insulating substrate.

[0194] In any of the above semiconductor devices, the mounting substrate may have a heat conductive plate formed on the surface of the insulating substrate opposite to the mounting surface.

[0195] In any of the above semiconductor devices, the mounting substrate may further have a sub-wiring connected to the first main electrode on the mounting surface of the switching element, and may have a sub-electrode plate connected to the sub-wiring in an area of ​​the mounting surface of the switching element where the switching element is not arranged.

[0196] In any of the above semiconductor devices, the switching element may be a power MOSFET, an IGBT, or a HEMT.

[0197] In any of the above semiconductor devices, the switching element may be a Si semiconductor, a SiC semiconductor element, or a GaN semiconductor element.

[0198] In a second aspect, a semiconductor module is provided that includes at least one semiconductor device, a main substrate to which a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate of the at least one semiconductor device are connected on its back surface, and a heat sink that contacts the surface of the at least one semiconductor device opposite the main substrate.

[0199] In the above-mentioned semiconductor module, the main substrate may have, on its front surface, a terminal connected to a first main electrode plate of at least one semiconductor device via wiring within the main substrate, and a terminal connected to a second main electrode or a second main electrode plate via wiring within the main substrate.

[0200] Any of the above semiconductor modules may further include at least one control device mounted on the front surface of the main board for controlling the at least one semiconductor device.

[0201] Any of the above semiconductor modules may be an inverter device, and the at least one semiconductor device may include a plurality of semiconductor devices respectively assigned to an upper arm and a lower arm of each of the one or more phases.

[0202] In any of the above semiconductor modules, the semiconductor devices of the plurality of semiconductor devices assigned to the upper arm of each phase may be arranged in a row on the back surface of the main substrate, and the semiconductor devices of the plurality of semiconductor devices assigned to the lower arm of each phase may be arranged in a row on the back surface of the main substrate alongside the row of semiconductor devices assigned to the upper arm of each phase.

[0203] In any of the above semiconductor modules, on the back surface of the main board, each semiconductor device assigned to the upper arm of each phase may be arranged in an orientation such that the first main electrode plate is located on the side of the semiconductor device assigned to the opposing lower arm among the multiple semiconductor devices, and on the back surface of the main board, each semiconductor device assigned to the lower arm of each phase may be arranged in an orientation such that the first main electrode plate is located on the side of the semiconductor device assigned to the opposing upper arm among the multiple semiconductor devices.

[0204] In a third aspect, there is provided a manufacturing method comprising: preparing a switching element having a first main electrode and a control electrode on one side and a second main electrode on the opposite side; fabricating a mounting substrate having first main electrode wiring and control wiring on a mounting surface on which the switching element is to be mounted; bonding the first main electrode to the first main electrode wiring and bonding the control electrode to the control wiring, thereby mounting the switching element on the mounting surface of the mounting substrate on which the switching element is to be mounted; and bonding a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode to an area on the mounting surface of the mounting substrate on which the switching element is to be mounted, where the switching element is not arranged.

[0205] The above manufacturing method may further comprise sealing with a sealing material so as to cover the mounting surface of the switching element on the mounting substrate and the surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

[0206] Any of the above manufacturing methods may include preparing a main substrate having a back surface connected to a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate of at least one semiconductor device; connecting at least one semiconductor device to the back surface of the main substrate; and attaching a heat sink to a surface of the at least one semiconductor device opposite to the main substrate.

[0207] Any of the above manufacturing methods may include mounting at least one control device that controls at least one semiconductor device on the front surface of the main substrate.

[0208] 10 Switching element, 100 First main electrode, 110 Control electrode, 120 Second main electrode, 130 Sense electrode, 200 Semiconductor device, 210 Mounting substrate, 220 First main electrode plate, 230 Second main electrode plate, 240 Control electrode plate, 250 Sub-electrode plate, 260 Sealing portion, 500 Insulating substrate, 510 First main electrode wiring, 513 First main electrode contact, 515 Wiring, 517 First main electrode plate contact, 520 Control wiring, 523 Control electrode contact, 525 Wiring, 527 Control electrode plate contact, 530 Sub-wiring, 535 Wiring, 537 Sub-electrode plate contact, 800 Semiconductor module, 810 Main substrate, 812 P wiring, 813 N wiring, 814 U wiring, 815 V wiring, 816 W wiring, 820 Control device, 830 Heat sink, 1270 heat conduction plate, 1280 first main electrode plate contact, 1285 second main electrode plate contact, 1290 control electrode plate contact, 1500 semiconductor device, 1510 mounting substrate, 1520 first main electrode plate, 1530 second main electrode plate, 1540 control electrode plate, 1550 sub-electrode plate, 1560 sealing portion, 1600 semiconductor module, 1610 main substrate, 1620 control device, 1630 heat sink, 1640 snubber capacitor, 1650 control connector, 1660 fixing member, 1670 protruding member, 1710 protruding member, 1800 semiconductor module, 1812 P wiring, 1813 N wiring, 1814 U wiring, 1815 V wiring, 1816 W wiring, 1900 semiconductor module, 1912 P wiring, 1913 N wiring, 1914 U wiring, 1915 V wiring, 1916 W wiring, 2000 semiconductor module, 2010 main board, 2020 control device, 2050 control connector, 2100 semiconductor module, 2110 main board, 2120 control device, 2150 control connector, 2180 film capacitor, 2200 semiconductor module, 2300 semiconductor module, 2315 main board recess, 2390 thermally conductive material, 2400 semiconductor module, 2410 heat sink recess, 2500 semiconductor module, 2600 semiconductor module, 2620 heat sink protrusion, 2700 semiconductor module.

Claims

1. a switching element having a first main electrode and a control electrode on one surface and a second main electrode on an opposite surface; a mounting substrate having a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode on a mounting surface of the switching element, and having a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode in an area on the mounting surface of the switching element where the switching element is not arranged; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising a sealing portion that covers a mounting surface of the switching element on the mounting substrate and a surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

3. The semiconductor device according to claim 1 , wherein the switching element is disposed between the first main electrode plate and the control electrode plate on a mounting surface of the mounting substrate where the switching element is mounted.

4. the first main electrode wiring has a plurality of bumps in contact with the first main electrode, The control wiring has a plurality of bumps that contact the control electrode. The semiconductor device of claim 1 .

5. The mounting substrate is An insulating substrate; The first main electrode wiring, the first main electrode plate, the control wiring, and the control electrode plate formed on an insulating substrate; 10. The semiconductor device of claim 1 ,

6. The semiconductor device according to claim 5 , wherein the mounting substrate has a heat conductive plate formed on a surface of the insulating substrate opposite to the mounting surface.

7. The mounting substrate further includes a sub-wiring connected to the first main electrode on a mounting surface of the switching element, and includes a sub-electrode plate connected to the sub-wiring in an area of ​​the mounting surface of the switching element where the switching element is not disposed. The semiconductor device of claim 1 .

8. The semiconductor device according to claim 1 , wherein the switching element is a power MOSFET or an IGBT.

9. The semiconductor device according to claim 1 , wherein the switching element is a SiC semiconductor element.

10. At least one semiconductor device according to any one of claims 1 to 9; a main substrate to which the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate of the at least one semiconductor device are connected on a rear surface thereof; a heat sink in contact with a surface of the at least one semiconductor device opposite to the main substrate; A semiconductor module comprising:

11. 11. The semiconductor module according to claim 10, wherein the main substrate has, on its front surface, a terminal connected to the first main electrode plate of the at least one semiconductor device via wiring within the main substrate, and a terminal connected to the second main electrode or the second main electrode plate via wiring within the main substrate.

12. The semiconductor module according to claim 10 , further comprising at least one control device mounted on the front surface of the main board for controlling the at least one semiconductor device.

13. The semiconductor module is an inverter device, The at least one semiconductor device includes a plurality of semiconductor devices respectively assigned to an upper arm and a lower arm of each phase of one or more phases. The semiconductor module according to claim 10.

14. Among the plurality of semiconductor devices, the semiconductor devices assigned to the upper arms of each phase are arranged in a row on the rear surface of the main substrate, Among the plurality of semiconductor devices, the semiconductor devices assigned to the lower arm of each phase are arranged in a row on the rear surface of the main substrate, aligned with the row of the semiconductor devices assigned to the upper arm of each phase. The semiconductor module according to claim 13.

15. On the rear surface of the main substrate, each semiconductor device assigned to an upper arm of each phase is arranged in an orientation such that the first main electrode plate is located on a side of a semiconductor device assigned to an opposing lower arm among the plurality of semiconductor devices, On the rear surface of the main substrate, each semiconductor device assigned to a lower arm of each phase is arranged in such a manner that the first main electrode plate is located on the side of the semiconductor device assigned to the opposing upper arm among the plurality of semiconductor devices. The semiconductor module according to claim 14.

16. providing a switching element having a first main electrode and a control electrode on one side and a second main electrode on an opposite side; preparing a mounting substrate having a first main electrode wiring and a control wiring on a mounting surface on which the switching element is to be mounted; mounting the switching element on a mounting surface of the mounting substrate on which the switching element is to be mounted by bonding the first main electrode to the first main electrode wiring and bonding the control electrode to the control wiring; bonding a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode to an area of ​​a mounting surface of the mounting substrate on which the switching elements are to be mounted, where the switching elements are not to be disposed; A manufacturing method comprising:

17. 17. The manufacturing method according to claim 16, further comprising: sealing with a sealant so as to cover a mounting surface of the switching element on the mounting substrate and a surface of the switching element facing the mounting substrate, while exposing the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate.

18. preparing a main substrate to which the first main electrode plate, the second main electrode or a second main electrode plate connected to the second main electrode, and the control electrode plate of at least one semiconductor device are connected on a rear surface thereof; connecting the at least one semiconductor device to a back surface of the main substrate; attaching a heat sink to a surface of the at least one semiconductor device opposite the main substrate; The method of claim 16 or 17, further comprising:

19. The method of claim 18, further comprising mounting at least one control device on a front surface of the main substrate for controlling the at least one semiconductor device.

20. at least one semiconductor device having a first main electrode plate, a second main electrode plate, and a control electrode plate on one surface thereof, the first main electrode being connected to the first main electrode plate, the second main electrode being connected to the second main electrode plate, and the control electrode being connected to the control electrode plate; a main substrate having a back surface to which the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected; a heat sink provided on a rear surface of the main board to which the at least one semiconductor device is connected; A semiconductor module comprising:

21. the main substrate has at least one main substrate recess on a rear surface thereof into which at least a portion of the at least one semiconductor device is embedded; 21. The semiconductor module of claim 20, wherein the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected to the main substrate at a bottom surface of the at least one main substrate recess.

22. The semiconductor module according to claim 20 , further comprising a thermally conductive material in at least a portion of a gap between the main board and the heat sink.

23. 21. The semiconductor module according to claim 20, wherein the heat sink has at least one heat sink protrusion on a surface facing the at least one semiconductor device at a position corresponding to the at least one semiconductor device.

24. The semiconductor module according to claim 20 , wherein the heat sink has at least one heat sink recess in a surface facing the at least one semiconductor device, in which at least a portion of the at least one semiconductor device is embedded.

25. The heat sink comprises: a plate-like member having a surface on the side of the main substrate and the at least one semiconductor device; at least one protruding member provided on a surface of the plate-like member opposite to the main substrate and the at least one semiconductor device; having The main board is fixed to the heat sink by at least one thermally conductive fixing member that penetrates the plate-like member of the heat sink from the front surface of the main board to the at least one protruding member. The semiconductor module according to claim 20.

26. each of the at least one fixing member is a screw; Each of the at least one protruding member has a screw hole into which the screw is fitted. The semiconductor module according to claim 25.

27. the at least one semiconductor device includes at least one first semiconductor device and at least one second semiconductor device; A negative-side main electrode plate of the first main electrode plate and the second main electrode plate of each of the at least one first semiconductor device is electrically connected to a positive-side main terminal plate of the first main electrode plate and the second main electrode plate of a corresponding second semiconductor device of the at least one second semiconductor device.

27. The semiconductor module according to any one of claims 20 to 26.

28. 27. The semiconductor module according to claim 20, wherein the at least one semiconductor device has a structure in which the second main electrode plate is disposed between a first main electrode plate and the control electrode plate on one surface.

29. 29. The semiconductor module according to claim 28, wherein on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are arranged with the first main electrode plates facing each other.

30. 29. The semiconductor module described in claim 28, wherein on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are arranged with the first main electrode plate and the control electrode plate facing each other.

31. The main board is a positive terminal connected to the positive main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via a positive wiring in the main substrate; a negative terminal connected to the negative main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via a negative wiring in the main substrate; an output terminal connected to a negative main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device and a positive main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via an output wiring in the main substrate; Equipped with The positive wiring, the negative wiring, and the output wiring are provided in a main wiring region of the main substrate corresponding to a region between the at least one first semiconductor device and the at least one second semiconductor device when viewed from above.

29. The semiconductor module according to claim 28.

32. First and second semiconductor devices arranged in a row on a rear surface of the main substrate; and a first and a second at least one second semiconductor device arranged in a line on a rear surface of the main substrate alongside the first and the second at least one first semiconductor device; a first output terminal connected to a negative main electrode plate of the first and second main electrode plates of the at least one first semiconductor device and a positive main electrode plate of the first and second main electrode plates of the at least one second semiconductor device via a first output wiring in the main substrate; a second output terminal connected to a negative main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device and a positive main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via a second output wiring in the main substrate; Equipped with The positive wiring, the negative wiring, the first output wiring, and the second output wiring are provided in a main wiring region of the main substrate corresponding to a region between a row of at least one of the first and second first semiconductor devices and a row of at least one of the first and second second semiconductor devices when viewed from above. The semiconductor module according to claim 31.

33. at least one first control device mounted on a front surface of the main substrate and electrically connected to the control electrode plate of at least one of the at least one first semiconductor device; at least one second control device mounted on a front surface of the main substrate and electrically connected to the control electrode plate of at least one of the at least one second semiconductor device; the at least one first control device is disposed in a first control wiring region on a side of the at least one first semiconductor device with respect to the main wiring region in a top view; The at least one second control device is disposed in a second control wiring region on the at least one second semiconductor device side with respect to the main wiring region in a top view. The semiconductor module according to claim 31.

34. a first control connector disposed in the first control wiring region on the front surface of the main board and electrically connected to the at least one first control device; a second control connector disposed in the second control wiring region on the front surface of the main board and electrically connected to the at least one second control device; The semiconductor module of claim 33 .

35. The semiconductor module according to claim 31 , further comprising at least one snubber capacitor disposed in the main wiring region on the front surface of the main board.

36. 29. The semiconductor module described in claim 28, wherein on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are arranged side by side in a direction perpendicular to the arrangement of the first main electrode plate, the second main electrode plate, and the control electrode plate.

37. The main board is a positive terminal connected to the positive main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via a positive wiring in the main substrate; a negative terminal connected to the negative main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via a negative wiring in the main substrate; an output terminal connected to a negative main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device and a positive main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via an output wiring in the main substrate; Equipped with The semiconductor module according to claim 36, wherein the positive wiring, the negative wiring, and the output wiring extend in a direction in which each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are aligned.

38. providing at least one semiconductor device having a first main electrode plate, a second main electrode plate, and a control electrode plate on one surface thereof, a first main electrode connected to the first main electrode plate, a second main electrode connected to the second main electrode plate, and a switching element having a control electrode connected to the control electrode plate; preparing a main substrate having a back surface to which the first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected; connecting the at least one semiconductor device to a back surface of the main substrate; attaching a heat sink to a rear surface of the main board to which the at least one semiconductor device is connected; A manufacturing method comprising: