Resistive non-volatile memory device and method for driving resistive non-volatile memory element

Abstract

A resistive resistance non-volatile memory device (10a) includes a memory cell (20) and a heater (30) that is thermally coupled to the memory cell (20), each of which can independently operate. The memory cell (20) has a first electrode layer (21), a second electrode layer (22), and a variable resistance layer (23) sandwiched between the first electrode layer (21) and the second electrode layer (22). The heater (30) has a heating element (31) and a third terminal (32) and a fourth terminal (33) that are connected to the heating element (31).

Description

Resistance variable nonvolatile memory device and method for driving resistance variable nonvolatile memory element

[0001] The present disclosure relates to a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element, and in particular to a variable resistance nonvolatile memory device that can suppress retention degradation.

[0002] 2. Description of the Related Art Conventionally, a technique for improving the retention (i.e., holding) characteristics of a resistive random access memory (hereinafter also referred to as "ReRAM") has been proposed (see Patent Document 1).

[0003] In the technology of Patent Document 1, in a first write process, before applying a first write pulse to a resistance change type nonvolatile memory element (hereinafter also referred to as a "memory cell"), a first pulse having the same polarity as the first write pulse but a shorter pulse width than the first write pulse, a second write pulse having the opposite polarity to the first write pulse, and a second pulse having the same polarity as the first write pulse are applied in this order. This improves the retention characteristics of the On state while ensuring a memory window in the ReRAM.

[0004] JP 2017-4579 A

[0005] However, in the technology of Patent Document 1, in the first write process, in addition to the original write pulse (i.e., the first write pulse), a separate pulse (i.e., the first pulse and the second pulse) is applied to the memory cell, which causes a problem that the endurance (i.e., rewrite endurance) characteristics may be deteriorated. In other words, there is a problem that the endurance characteristics are sacrificed.

[0006] Therefore, an object of the present disclosure is to provide a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element that can suppress retention degradation without increasing the number of write operations.

[0007] In order to achieve the above object, a variable resistance nonvolatile memory device according to one embodiment of the present disclosure comprises a variable resistance nonvolatile memory element having a first electrode layer, a second electrode layer, and a variable resistance layer sandwiched between the first electrode layer and the second electrode layer, a first terminal connected to the first electrode layer and a second terminal connected to the second electrode layer, a heating element, and a heater having a third terminal and a fourth terminal connected to the heating element, wherein the variable resistance nonvolatile memory element and the heater are independently operable and thermally coupled.

[0008] In order to achieve the above object, a method for driving a variable resistance nonvolatile memory element according to one embodiment of the present disclosure is a method for driving a variable resistance nonvolatile memory element that can be in a high resistance state and a low resistance state, and includes a high resistance step of driving the variable resistance nonvolatile memory element so that the variable resistance nonvolatile memory element is in a high resistance state, a low resistance step of driving the variable resistance nonvolatile memory element so that the variable resistance nonvolatile memory element is in a low resistance state, and a heating step of driving a heater thermally coupled to the variable resistance nonvolatile memory element at any time when the variable resistance nonvolatile memory element is selected for the high resistance step.

[0009] The present disclosure provides a variable resistance nonvolatile memory device and a method for driving a variable resistance nonvolatile memory element that can suppress retention degradation without increasing the number of write operations.

[0010] FIG. 1A is a schematic diagram showing a first structural example of a variable resistance nonvolatile memory device according to an embodiment. FIG. 1B is a schematic diagram showing a second structural example of a variable resistance nonvolatile memory device according to an embodiment. FIG. 1C is a schematic diagram showing a third structural example of a variable resistance nonvolatile memory device according to an embodiment. FIG. 2 is a diagram showing an example circuit configuration of a variable resistance nonvolatile memory device according to an embodiment. FIG. 3 is a timing chart showing a method of driving a memory cell according to an embodiment. FIG. 4A is a diagram showing retention characteristics of a memory cell after a cycling test in which a conventional write to a high resistance state and a low resistance state (write current: 125 μA) without "heat application" is repeated. FIG. 4B is a diagram showing retention characteristics of a memory cell after a cycling test in which a conventional write to a high resistance state and a low resistance state (write current: 75 μA) without "heat application" is repeated. FIG. 4C is a diagram showing retention characteristics of a memory cell after a cycling test in which a write to a high resistance state and a low resistance state (write current: 75 μA) with "heat application" is repeated according to an embodiment. Fig. 5 is a diagram illustrating the characteristics of a memory cell driving method according to an embodiment in comparison with a conventional method. Fig. 6 is a diagram illustrating an event that occurs when a cell current in a high resistance state is reduced by a conventional method of increasing the applied voltage during an erase operation, comparing the embodiment with the conventional method. Fig. 7 is a schematic structural diagram of a memory cell illustrating the mechanism of the cell current transition shown in Figs. 5 and 6. Fig. 8A is a timing chart illustrating a memory cell driving method according to a first modified example of the embodiment. Fig. 8B is a timing chart illustrating a memory cell driving method according to a second modified example of the embodiment.

[0011] Embodiments of the present disclosure will be described in detail below with reference to the drawings. Each embodiment described below represents a specific example of the present disclosure. The numerical values, shapes, materials, components, component placement and connection configurations, operation timing, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, each figure is not necessarily an exact illustration. In each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified. Furthermore, "A and B are connected" means that A and B are electrically connected, and includes not only cases where A and B are directly connected, but also cases where A and B are indirectly connected with another circuit element interposed between A and B. Furthermore, "upper" and "lower" refer to relative directions in the illustrated state and do not indicate a relationship to the vertical direction.

[0012] 1A is a schematic diagram showing a first structural example of a variable resistance nonvolatile memory device 10a according to an embodiment. More specifically, (a) of FIG. 1A is a cross-sectional view of the variable resistance nonvolatile memory device 10a, and (b) of FIG. 1A is a top view of the variable resistance nonvolatile memory device 10a.

[0013] The variable resistance nonvolatile memory device 10a is a one-chip semiconductor ReRAM and is characterized by including a memory cell 20, which is a variable resistance nonvolatile memory element, and a heater 30 thermally coupled to the memory cell 20, each of which can operate independently. The memory cell 20 includes a first electrode layer 21, a second electrode layer 22, and a variable resistance layer 23 sandwiched between the first electrode layer 21 and the second electrode layer 22. The heater 30 includes a heating element 31, and a third terminal 32 and a fourth terminal 33 connected to the heating element 31. In this embodiment, the variable resistance nonvolatile memory device 10a further includes a heat shield structure 40 that prevents heat generated by the heater 30 from being transferred to the outside of the variable resistance nonvolatile memory device 10a. However, the heat shield structure 40 is not an essential component of the variable resistance nonvolatile memory device 10a.

[0014] Note that two circuit elements being "independently operable" refers to a connection configuration that enables the operation of one of the two circuit elements to not affect the operation of the other, such as each of the two circuit elements having an independent terminal for operation. Furthermore, two circuit elements being "thermally coupled" refers to a relationship in which heat generated by one of the two circuit elements is transferred to the other, and includes not only cases in which the two circuit elements are in direct contact, but also cases in which they are in indirect contact via another object.

[0015] In this structural example, the heater 30 is disposed at a position (here, above the memory cell 20) alongside the memory cell 20 in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. The heat shield structure 40 surrounds the memory cell 20 and the heater 30 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. The "stacking direction" is also the direction perpendicular to the front or back surface of the wafer on which the variable resistance nonvolatile memory device 10a is formed.

[0016] Each component of the variable resistance nonvolatile memory device 10a will be described in detail below.

[0017] The memory cell 20 is a non-volatile resistance change element that takes on a high resistance state or a low resistance state depending on the voltage applied between the first electrode layer 21 and the second electrode layer 22. For example, the memory cell 20 takes on a high resistance state when a positive voltage is applied to the second electrode layer 22 with respect to the voltage applied to the first electrode layer 21, and takes on a low resistance state when a negative voltage is applied to the second electrode layer 22 with respect to the voltage applied to the first electrode layer 21.

[0018] The first electrode layer 21 is an electrode to which a wiring 21a, which is an example of a first terminal, is connected, and is made of, for example, a transition metal nitride such as tantalum nitride or titanium nitride, or a laminate of these. The second electrode layer 22 is an electrode to which a wiring 22a, which is an example of a second terminal, is connected, and is made of, for example, platinum, iridium, palladium, silver, nickel, tungsten, copper, or the like. The resistance change layer 23 includes a minute local region (i.e., a filament region composed of oxygen vacancy sites) whose degree of oxygen deficiency reversibly changes depending on the polarity of the applied voltage, and is made by laminating, for example, a first resistance change layer (a low-resistance tantalum oxide layer composed of oxygen-deficient Ta oxide) in contact with the first electrode layer 21 and a second resistance change layer (a high-resistance tantalum oxide layer) in contact with the second electrode layer 22.

[0019] The heating element 31 of the heater 30 is made of a material that exhibits a relatively high resistance and generates a relatively large amount of heat when a current flows through it, such as titanium nitride, titanium aluminum nitride, titanium tungsten, tantalum nitride, tantalum silicon nitride, tungsten nitride, etc. The third terminal 32 is one terminal of the heating element 31 to which a wiring 32a is connected, and the fourth terminal 33 is the other terminal of the heating element 31 to which a wiring 33a is connected.

[0020] The heat shield structure 40 is a heat insulating material with low thermal conductivity, and is made of, for example, silicon oxide, a low dielectric constant material, porous silicon oxide, aerogel, xerogel, or the like.

[0021] 1A(b), in top view, the memory cells 20 and the heater 30 have a rectangular shape, and the heat shield structure 40 has a rectangular ring shape. The heat shield structure may be a single block or may be divided into multiple parts. The variable resistance nonvolatile memory device 10a consisting of these components is fabricated by using a semiconductor substrate and repeating processes such as film formation and photolithography.

[0022] Furthermore, in this structural example, the heater 30 is positioned above the memory cell 20, in a position aligned with the memory cell 20 in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23. However, the position in the stacking direction is not limited to such an upper position, and instead of or in addition to such an upper position, the heater 30 may be positioned below the memory cell 20.

[0023] 1B is a schematic diagram showing a second structural example of a variable resistance nonvolatile memory device 10b according to an embodiment. More specifically, (a) of FIG. 1B is a cross-sectional view of the variable resistance nonvolatile memory device 10b, and (b) of FIG. 1B is a top view of the variable resistance nonvolatile memory device 10b.

[0024] 1A is that in this structural example, the heater 30 is arranged at a position next to the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23. Even in such a position, the heater 30 is thermally coupled to the memory cell 20. Note that the "direction perpendicular to the stacking direction" also refers to a direction perpendicular to the cross section of the wafer on which the resistance change nonvolatile memory device 10b is formed.

[0025] In this structural example, the heater 30 is positioned next to the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, and is positioned opposite one of the four side surfaces of the memory cell 20. However, the position in the direction perpendicular to the stacking direction is not limited to this position, and the heater 30 may be positioned opposite two or more of the four side surfaces of the memory cell 20.

[0026] Furthermore, in addition to the heater 30 according to this structural example, the heater 30 according to the first structural example may be added. When heaters 30 are provided at multiple locations for one memory cell 20, it is preferable that the multiple heaters 30 are electrically connected in series or in parallel.

[0027] 1C is a schematic diagram showing a third structural example of a variable resistance nonvolatile memory device 10c according to an embodiment. More specifically, (a) of FIG. 1C is a cross-sectional view of the variable resistance nonvolatile memory device 10c, and (b) of FIG. 1C is a top view of the variable resistance nonvolatile memory device 10c.

[0028] 1A is that the heater 30 surrounds the memory cell 20 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23. Even in such a position, the heater 30 is thermally coupled to the memory cell 20. Note that "when viewed in the stacking direction" also means "when viewed from the front side or back side of the wafer on which the variable resistance nonvolatile memory device 10c is formed."

[0029] In this structural example, the heater 30 surrounds the memory cell 20 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, but the position at which the heater 30 surrounds the memory cell 20 is not limited to this, and the heater 30 may surround the memory cell 20 when viewed in a direction perpendicular to the stacking direction.

[0030] In addition to the heater 30 according to this structural example, the heater 30 according to the first structural example and / or the heater 30 according to the second structural example may be added. When heaters 30 are provided at multiple locations for one memory cell 20, it is preferable that the multiple heaters 30 are electrically connected in series or in parallel.

[0031] 1A to 1C show a pair of a memory cell 20 and a heater 30, but if this pair is considered to be one bit, multiple bits may be arranged two-dimensionally or three-dimensionally. In this case, the heat shield structure 40 is located at the boundary between each bit.

[0032] In other words, in the above structural example, the heat shield structure 40 surrounds the memory cell 20 and the heater 30 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, but the position at which it surrounds the memory cell 20 and the heater 30 is not limited to this, and it may surround the memory cell 20 and the heater 30 when viewed in a direction perpendicular to the stacking direction.

[0033] 2 is a diagram showing an example of a circuit configuration of variable resistance nonvolatile memory devices 10a to 10c according to an embodiment, in which transistors 50a and 50b and a write control circuit 52 are added to the memory cell 20 and heater 30 shown in FIGS.

[0034] As shown in this figure, a memory cell 20 and a transistor 50a for driving the memory cell 20 are connected in series, and a heater 30 and a transistor 50b for driving the heater 30 are connected in series.

[0035] A word line WL is connected to the control terminals (i.e., gate terminals) of the transistors 50a and 50b, a bit line BL is connected to one terminal (e.g., the first electrode layer 21) of the memory cell 20, one input / output terminal (e.g., one of the source / drain) of the transistor 50a is connected to the other terminal (e.g., the second electrode layer 22) of the memory cell 20, a source line SL1 is connected to the other input / output terminal (e.g., the other of the source / drain) of the transistor 50a, a heater drive line HL is connected to one terminal (e.g., the third terminal 32) of the heater 30, one input / output terminal (e.g., one of the source / drain) of the transistor 50b is connected to the other terminal (e.g., the fourth terminal 33) of the heater 30, and a source line SL2 is connected to the other input / output terminal (e.g., the other of the source / drain) of the transistor 50b.

[0036] 3 to the word line WL, the bit line BL, the source line SL1, the heater drive line HL, and the source line SL2, thereby performing high-resistance programming (hereinafter also referred to as a "high-resistance step," "HR programming," or "erase operation") to transition the memory cell 20 to a high-resistance state, heating the memory cell 20 (hereinafter also referred to as a "heating step" or "heat application"), and low-resistance programming (hereinafter also referred to as a "low-resistance step," "LR programming," or "program operation") to transition the memory cell 20 to a low-resistance state. To this end, the write control circuit 52 includes a selection circuit (not shown) that outputs a selection signal to the word line, a voltage source circuit (not shown) that supplies a voltage pulse or a constant voltage to the bit line BL, the source line SL1, the heater drive line HL, and the source line SL2, a processor (not shown) that controls the selection circuit and the voltage source circuit, and the like.

[0037] Furthermore, in the circuit configuration example shown in this figure, a pair of memory cell 20 and heater 30 is shown, but if this pair is considered to be one bit, multiple bits may be arranged in a two-dimensional or three-dimensional manner.

[0038] 3 is a timing chart showing a method for driving the memory cell 20 according to the embodiment. More specifically, (a) to (e) of FIG. 3 respectively show signals on the word line WL, the bit line BL, the source line SL1, the heater drive line HL, and the source line SL2 in the circuit configuration example of FIG. 2. Here, a driving example is shown in which the memory cell 20 is written to a high resistance state ("HR state" and "heat application") and then written to a low resistance state ("LR state") in this order using the circuit configuration example shown in FIG.

[0039] In the conventional programming to a high-resistance state ("HR setting" and "heat application"), only "HR setting" is performed. However, in the present embodiment, both "HR setting" and "heat application" are performed. Specifically, the write control circuit 52 drives the word line WL to a select level (i.e., H level), thereby turning on the transistors 50a and 50b. Then, while maintaining the source line SL1 at a reference potential, a "HR setting" voltage pulse (e.g., 1.7 V) is applied to the bit line BL. Then, while maintaining the source line SL2 at a reference potential, a "heat application" voltage pulse (e.g., 3.0 V) is applied to the heater drive line HL. Then, the word line WL is driven to a non-select level (i.e., L level). Thus, after the "HR setting" voltage pulse is applied to the memory cell 20, a "heat application" voltage pulse is applied to the heater 30, thereby programming to a high-resistance state that can suppress retention degradation of the memory cell 20.

[0040] The subsequent writing to the low resistance state ("LR state") is the same as in the conventional case. Specifically, the write control circuit 52 drives the word line WL to the selection level (i.e., H level), which causes the transistors 50a and 50b to become conductive. Then, while maintaining the bit line BL at the reference potential, a voltage pulse for "LR state" (e.g., 2.0 V) is applied to the source line SL1, and then the word line WL is driven to the non-selection level (i.e., L level). When writing to the low resistance state, "heat application" is not performed.

[0041] 4A to 4C are diagrams illustrating the effects of the method for driving memory cell 20 according to the embodiment. More specifically, Fig. 4A shows the retention characteristics of a memory cell after a cycling test in which a conventional write to a high-resistance state and a low-resistance state (without applying heat) are repeated (however, a write current of 125 μA) is performed, Fig. 4B shows the retention characteristics of a memory cell after a cycling test in which a conventional write to a high-resistance state and a low-resistance state (without applying heat) are repeated (however, a write current of 75 μA) is performed, and Fig. 4C shows the retention characteristics of a memory cell after a cycling test in which a conventional write to a high-resistance state and a low-resistance state (without applying heat) are repeated (however, a write current of 75 μA) is performed according to the embodiment including applying heat.

[0042] The retention characteristics are measured by conducting a cycling test in which a certain number of memory cells with the same characteristics are written to a high-resistance state and then written to a low-resistance state 1,000 times, followed by an accelerated life test, and then plotting the normal expected values ​​(expected values ​​in units of standard deviation σ; Y axis) of the current ("cell current") corresponding to the resistance values ​​in the high-resistance state and the low-resistance state held by each memory cell after being left at 85° C. for one year and after being left at 85° C. for 10 years. The horizontal axis is the "cell current."

[0043] In each of Figures 4A to 4C, the series of plots consisting of black circles, black squares, and black triangles represent the normal expected values ​​of cell current in a low resistance state after a cycling test, after being left at 85°C for one year, and after being left at 85°C for 10 years, respectively. The series of plots consisting of white circles, white squares, and white triangles represent the normal expected values ​​of cell current in a high resistance state after a cycling test, after being left at 85°C for one year, and after being left at 85°C for 10 years, respectively.

[0044] As can be seen from Figure 4A, when a relatively large write current (i.e., 125 μA) is used to write to a conventional high-resistance state without "heat application," the window between the minimum resistance value in the high-resistance state and the maximum resistance value in the low-resistance state held by each memory cell after 10 years of storage at 85°C (specifically, the window within the range of ±3.5σ normal expected values ​​(hereinafter also referred to as "3.5σ-window")) of approximately 17 μA is secured. Note that σ is the standard deviation in the distribution of resistance values.

[0045] However, as can be seen from Figure 4B, when writing to a conventional high-resistance state is performed with a relatively small write current (i.e., 75 μA) and without "heat application," the 3.5σ-window of each memory cell after 10 years of storage at 85°C is extremely small at approximately 2 μA, and the retention characteristics of the memory cell are significantly deteriorated. This is because the resistance value of the memory cell in the low-resistance state increases (i.e., the cell current decreases).

[0046] In contrast, as can be seen from Figure 4C, when writing to a high resistance state according to the embodiment including "heat application" is performed with a relatively small write current (i.e., 75 μA), the 3.5σ-window after 10 years of storage at 85°C is approximately 15 μA, and the deterioration of the retention characteristics of the memory cell is significantly suppressed.

[0047] In recent years, with the miniaturization of semiconductors, high reliability in low-power operation has been required. However, as can be seen from Figures 4A and 4B, in conventional memory cell driving methods that do not include "heat application," reducing the write current increases the amount of retention degradation after cycling, making it impossible to ensure a sufficient memory window and ensuring high reliability. In contrast, as can be seen from Figure 4C, writing to a high-resistance state according to an embodiment that includes "heat application" suppresses the amount of retention degradation after cycling even when the write current is reduced. Therefore, by writing to a high-resistance state according to an embodiment that includes "heat application," variable resistance nonvolatile memory devices 10a to 10c that ensure high reliability in low-power operation are realized.

[0048] Furthermore, by writing to a high resistance state according to the embodiment including "heat application," it is possible to suppress retention degradation of memory cell 20 without sacrificing the endurance characteristics of memory cell 20 by increasing the number of writes as in the conventional method.

[0049] The features of the memory cell driving method according to this embodiment will be described below with reference to FIGS. 5 to 7, including a comparison with the conventional method and the mechanism in the memory cell.

[0050] FIG. 5 is a diagram illustrating the characteristics of the driving method of the memory cell 20 according to the present embodiment, comparing it with a conventional method. More specifically, FIG. 5A shows the transition of cell current in a first conventional example in which a normal erase voltage VH is applied to create a high-resistance state, and in this embodiment in which heat application is then performed to reduce the cell current in the high-resistance state. The horizontal axis represents the time series of operations, and the vertical axis represents cell current. FIG. 5B shows the timing of operations corresponding to the "HR transition," "heat application," and "LR transition" in FIG. 5A, as well as those thereafter. FIG. 5C shows the meaning of the line types indicating each transition in FIG. 5A.

[0051] As shown in FIG. 5A , according to the driving method of the memory cell 20 according to the present embodiment (the transitions indicated by the thin and thick solid lines passing through the black circles, black squares, and black triangles), by applying heat to the memory cell 20 after the HR process, the resistance change layer 23 of the memory cell 20 is oxidized, and oxygen defects in the filament region of the resistance change layer 23 are reduced. In other words, the cell current in the high-resistance state is reduced compared to when the heat application is not performed (the transitions indicated by the thin and thick dashed lines). As a result, in the subsequent LR process, a higher voltage is applied to the memory cell 20 than when the heat application is not performed, and oxygen defects in the filament region increase. In other words, compared to when the heat treatment is not performed, oxygen defects in the filament region increase, resulting in a higher cell current in the low-resistance state. As a result, the decrease in cell current due to the reduction in oxygen defects (reoxidation) that occurs over time is suppressed, leading to improved reliability.

[0052] 6A and 6B are diagrams illustrating the characteristics of the driving method of the memory cell 20 according to the present embodiment, comparing it with a second conventional example. More specifically, FIG. 6A shows the transition of cell current after "LR conversion" in the case of the second conventional example, in which the erase voltage VH is increased as a method for reducing the cell current in the high-resistance state, and in the case of the present embodiment, in which "heat application" is performed after "HR conversion." The horizontal axis represents the time series of operation, and the vertical axis represents cell current. FIG. 6B shows the meaning of the line types indicating each transition in FIG. 6A.

[0053] As shown in the transitions (indicated by double and triple lines) of the second conventional example in which the erase voltage VH is increased in FIG. 6A, the second conventional example reduces the cell current in the high-resistance state by increasing the pulse voltage applied to the memory cell during high-resistance transition. As a result, in the subsequent "LR transition," a higher voltage is applied to the memory cell 20 than in the first conventional example in which the normal erase voltage VH is applied to achieve the high-resistance state, increasing oxygen defects in the filament region and increasing the cell current in the low-resistance state. However, the cell current subsequently decreases over time, resulting in a problem of increased retention degradation.

[0054] In contrast, as shown in the transition with "heat application" in (a) of FIG. 6 (transitions indicated by thin and thick solid lines), in this embodiment, "heat application" is performed after "HR conversion," so that the resistance change layer 23 of the memory cell 20 is oxidized, and oxygen defects formed in the filament region of the resistance change layer 23 are reduced. As a result, in the subsequent "LR conversion," a high voltage is applied to the memory cell 20, increasing oxygen defects in the filament region and increasing the cell current in the low resistance state. However, in the operation of this embodiment, the decrease in cell current that occurs over time is suppressed, improving reliability. FIG. 7 is a schematic structural diagram of the memory cell 20, explaining the mechanism of the cell current transition shown in FIG. 6.

[0055] 7A shows a schematic structure of the memory cell 20 in the low resistance state ("LRS"), in which the variable resistance layer 23 is composed of a first variable resistance layer 23a containing oxygen ions and a second variable resistance layer 23b in which a filament 24 containing oxygen defects is formed.

[0056] 7B shows a schematic structure of the memory cell 20 in a high resistance state ("HRS") after being driven to a high erase voltage by a conventional driving method, using a write voltage higher than normal ("HR voltage VH: high") on the memory cell 20 in the state shown in FIG. 7A. Oxygen ions in the first variable resistance layer 23a move to the filament 24 in the second variable resistance layer 23b and combine with oxygen defects in the filament 24, causing re-oxidation, but many oxygen ions that do not contribute to the re-oxidation remain in the filament.

[0057] 7C shows a schematic structure of the memory cell 20 in a low resistance state ("LRS") after the memory cell 20 in the state shown in FIG. 7B is changed to a low resistance state by applying a write voltage for the low resistance state ("LR voltage application") The oxygen ions in the filament 24 move to the first variable resistance layer 23a, but many oxygen ions remain in the filament 24. As a result, if the memory cell 20 is held in this state for a long time, re-oxidation of oxygen defects occurs in the filament 24, the number of oxygen defects decreases, and the cell current in the low resistance state decreases (i.e., retention degradation progresses).

[0058] 7(d) shows a schematic structure of the memory cell 20 in the high resistance state ("HRS") after the memory cell 20 in the state of FIG. 7(a) is made high-resistance ("HRS voltage VH: normal") using a normal erase voltage ("HRS voltage VH: normal") (FIG. 7(d1)) and then further made high-resistance by "heat application" (FIG. 7(d2)), similar to the transition to FIG. 7(b) using the driving method according to this embodiment. By "heat application," oxygen ions and oxygen defects combine within the filament 24, causing re-oxidation and reducing the oxygen defects.

[0059] 7(e) shows a schematic structure of the memory cell 20 in a low resistance state ("LRS") after the memory cell 20 in the state shown in FIG. 7(d) is changed to a low resistance state by applying a write voltage for the low resistance state ("LR voltage application") The oxygen ions in the filament 24 move to the first variable resistance layer 23a, but the number of oxygen ions in the filament 24 is small. As a result, even if the memory cell 20 is held in this state for a long time, re-oxidation of oxygen defects is unlikely to occur, and therefore retention degradation is suppressed.

[0060] In the present embodiment, in the erase operation ("HR change" and "heat application") for the memory cell 20 to the high resistance state, "heat application" is performed after "HR change" as shown in FIG. 3 . However, this order is not limited to this. For example, "HR change" may be performed after "heat application" as shown in the timing chart of the first modified example of FIG. 8A , or "HR change" and "heat application" may be performed in parallel as shown in the timing chart of the second modified example of FIG. 8B . In other words, the order of "HR change" and "heat application" is not particularly limited as long as the variable resistance nonvolatile memory element is selected for the high resistance change step. The order of "HR change" and "heat application" and the pulse width of "heat application" are appropriately determined depending on the heat capacity of the memory cell 20, the heat generation amount of the heater 30, the degree of thermal coupling between the memory cell 20 and the heater 30, etc.

[0061] As described above, the variable resistance nonvolatile memory device 10a etc. according to this embodiment includes the memory cell 20, which is a variable resistance nonvolatile memory element, and the heater 30 thermally coupled to the memory cell 20, and each of these can operate independently. The memory cell 20 includes the first electrode layer 21, the second electrode layer 22, and the variable resistance layer 23 sandwiched between the first electrode layer 21 and the second electrode layer 22, and the heater 30 includes the heating element 31, and the third terminal 32 and the fourth terminal 33 connected to the heating element 31.

[0062] As a result, heat can be applied to the memory cell 20 by the heater 30 when writing the memory cell 20 to a high resistance state, thereby realizing a decrease in the cell current of the memory cell 20 after it has been changed to a high resistance state and an increase in the cell current of the memory cell 20 after it has been changed to a low resistance state. Therefore, it is possible to suppress retention degradation of the memory cell 20 without sacrificing the endurance characteristics of the memory cell 20 by increasing the number of write operations as in the past. Furthermore, retention degradation is suppressed even when writing with a low current, and a resistance variable nonvolatile memory device that ensures high reliability in low-power operation is realized.

[0063] Here, the heater 30 may be arranged at a position alongside the memory cell 20 in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, or the heater 30 may be arranged at a position alongside the memory cell 20 in a direction perpendicular to the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, or the heater 30 may surround the periphery of the memory cell 20 when viewed in the stacking direction, or the heater 30 may surround the periphery of the memory cell 20 when viewed in a direction perpendicular to the stacking direction. This allows the memory cell 20 and the heater 30 to be thermally coupled according to various structures.

[0064] Furthermore, the variable resistance nonvolatile memory device 10a etc. may include a heat shield structure 40 that suppresses the heat generated by the heater 30 from being transferred to the outside of the variable resistance nonvolatile memory device 10a. This prevents the heat generated by the heater 30 from escaping to the outside, thereby ensuring efficient heat application and suppressing the thermal impact on other memory cells etc. arranged adjacent to the memory cell 20.

[0065] In this case, the heat shield structure 40 may surround the periphery of the memory cell 20 and the heater 30 when viewed in the stacking direction of the first electrode layer 21, the second electrode layer 22, and the resistance change layer 23, or may surround the periphery of the memory cell 20 and the heater 30 when viewed in a direction perpendicular to the stacking direction. This makes it possible to more reliably apply heat to the memory cell 20.

[0066] Furthermore, the method for driving a memory cell 20 according to this embodiment is a method for driving a memory cell 20 that can take a high resistance state and a low resistance state, and includes a high resistance step for driving the memory cell 20 so that the memory cell 20 is in a high resistance state, a low resistance step for driving the memory cell 20 so that the memory cell 20 is in a low resistance state, and a heating step for driving a heater 30 thermally coupled to the memory cell 20 at any time when the memory cell 20 is selected for the high resistance step.

[0067] As a result, by performing a high resistance step and a heating step to write the memory cell 20 to a high resistance state, a decrease in the cell current of the memory cell 20 after the high resistance state is achieved, and an increase in the cell current of the memory cell 20 after the low resistance state is achieved. Therefore, it is possible to suppress retention degradation of the memory cell 20 without sacrificing the endurance characteristics of the memory cell 20 by increasing the number of write operations as in the conventional method. Furthermore, retention degradation is suppressed even when writing with a low current, and a resistance variable nonvolatile memory device that ensures high reliability in low-power operation is realized.

[0068] Here, in the heating step, the heater 30 may be driven while the memory cell 20 is selected for the high resistance step, or in the heating step, the heater 30 may be driven after the memory cell 20 is driven by the high resistance step, thereby ensuring a decrease in the cell current of the memory cell 20 after the high resistance step and an increase in the cell current of the memory cell 20 after the low resistance step.

[0069] While the variable resistance nonvolatile memory device and the method for driving the variable resistance nonvolatile memory element according to the present disclosure have been described above based on the embodiments and modifications, the present disclosure is not limited to these embodiments and modifications. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art could conceive of to the present embodiments and modifications, and other forms constructed by combining some of the components or steps in the embodiments and modifications, are also included within the scope of the present disclosure.

[0070] For example, in the above embodiment, a Ta oxide layer is exemplified as the resistance change layer 23 of the memory cell 20, but the material is not limited to this, and the resistance change layer 23 may be a metal oxide layer having a base metal of at least one of aluminum and a transition metal such as hafnium, titanium, zirconium, niobium, tungsten, nickel, or iron. The resistance change layer 23 of the memory cell 20 is not limited to a stacked structure of two types of resistance change layers, and may be a single type of resistance change layer.

[0071] Furthermore, in the circuit configuration example of the above embodiment, a 1T1R bit configuration in which the memory cell 20 and the transistor 50a are connected in series is shown, but a 1D1R bit configuration in which the memory cell 20 and a diode are connected in series may also be used.

[0072] The variable resistance nonvolatile memory device according to the present disclosure can be used as a ReRAM in which retention degradation is suppressed, and in particular as a ReRAM in which high reliability is ensured in low-power operation.

[0073] 10a, 10b, 10c Resistance variable nonvolatile memory device (ReRAM) 20 Resistance variable nonvolatile memory element (memory cell) 21 First electrode layer 21a, 22a, 32a, 33a Wiring 22 Second electrode layer 23 Resistance variable layer 23a First resistance variable layer 23b Second resistance variable layer 24 Filament 30 Heater 31 Heat generating element 32 Third terminal 33 Fourth terminal 40 Heat shield structure 50a, 50b Transistor 52 Write control circuit WL Word line BL Bit line SL1, SL2 Source line HL Heater drive line

Claims

1. a variable resistance nonvolatile memory element having a first electrode layer, a second electrode layer, a variable resistance layer sandwiched between the first electrode layer and the second electrode layer, a first terminal connected to the first electrode layer, and a second terminal connected to the second electrode layer; a heater having a heating element and a third terminal and a fourth terminal connected to the heating element; The variable resistance nonvolatile memory device is characterized in that the variable resistance nonvolatile memory element and the heater are independently operable and thermally coupled to each other.

2. the heater is disposed at a position next to the variable resistance nonvolatile memory element in a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer; The variable resistance nonvolatile memory device according to claim 1 .

3. the heater is disposed at a position next to the variable resistance nonvolatile memory element in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the variable resistance layer; 3. The variable resistance nonvolatile memory device according to claim 1.

4. the heater surrounds the resistance change type nonvolatile memory element when viewed in a stacking direction of the first electrode layer, the second electrode layer, and the resistance change layer.

3. The variable resistance nonvolatile memory device according to claim 1.

5. the heater surrounds the resistance change type nonvolatile memory element when viewed in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the resistance change layer.

3. The variable resistance nonvolatile memory device according to claim 1.

6. Further, a heat shield structure is provided to prevent the heat generated by the heater from being transferred to the outside of the variable resistance nonvolatile memory device.

3. The variable resistance nonvolatile memory device according to claim 1.

7. the heat shield structure surrounds the resistance change type nonvolatile memory element and the heater when viewed in a stacking direction of the first electrode layer, the second electrode layer, and the resistance change layer. The variable resistance nonvolatile memory device according to claim 6 .

8. the heat shield structure surrounds the resistance change type nonvolatile memory element and the heater when viewed in a direction perpendicular to a stacking direction of the first electrode layer, the second electrode layer, and the resistance change layer. The variable resistance nonvolatile memory device according to claim 6 .

9. A method for driving a variable resistance nonvolatile memory element that can take a high resistance state and a low resistance state, comprising: a high resistance step of driving the variable resistance nonvolatile memory element so that the variable resistance nonvolatile memory element is in a high resistance state; a low resistance step of driving the variable resistance nonvolatile memory element so that the variable resistance nonvolatile memory element is in a low resistance state; a heating step of driving a heater thermally coupled to the variable resistance nonvolatile memory element at any time when the variable resistance nonvolatile memory element is selected for the high resistance step; A method for driving a variable resistance nonvolatile memory element.

10. In the heating step, the heater is driven in the resistance increasing step, and then the variable resistance nonvolatile memory element is driven. A method for driving the variable resistance nonvolatile memory element according to claim 9.

11. In the heating step, the variable resistance nonvolatile memory element is driven in the high resistance step, and then the heater is driven. A method for driving the variable resistance nonvolatile memory element according to claim 9.