Semiconductor device

Abstract

This semiconductor device comprises a semiconductor element, a second coil, and a sealing resin. The semiconductor element includes: an element insulating layer including an element front surface and an element back surface facing the opposite side from each other in the z direction, and an insulating surface constituting the element front surface; and a first coil provided in the element insulating layer. The second coil is disposed spaced apart from the first coil in the z direction. The sealing resin contacts the element insulating layer and seals the semiconductor element and the second coil. The first coil and the second coil face each other in the thickness direction with the element insulating layer and the sealing resin in between.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices include a transformer used for transmitting signals and power, and the transformer includes a pair of coils arranged opposite each other in the vertical direction (see, for example, Patent Document 1).

[0003] JP 2018-78169 A

[0004] Incidentally, there are cases where an improvement in the withstand voltage is required for a transformer included in a semiconductor device, and similarly, there are cases where an improvement in the withstand voltage is required for a semiconductor device that includes a capacitor as an insulating element.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor element including an element front surface and an element back surface facing opposite each other in a thickness direction, the semiconductor element including an element insulating layer including an insulating surface constituting the element front surface, and a first conductor provided within the element insulating layer, a second conductor arranged at a distance from the first conductor in the thickness direction, and a sealing resin in contact with the element insulating layer and sealing the semiconductor element and the second conductor, the first conductor and the second conductor facing each other in the thickness direction across the element insulating layer and the sealing resin.

[0006] According to the semiconductor device according to one aspect of the present disclosure, it is possible to improve the dielectric strength voltage.

[0007] FIG. 1 is a circuit diagram schematically illustrating the configuration of a signal transmission device including a semiconductor device of a first embodiment. FIG. 2 is a perspective view schematically illustrating the signal transmission device of FIG. 1. FIG. 3 is a schematic perspective view illustrating the semiconductor device of FIG. 2. FIG. 4 is a schematic perspective view of the semiconductor device of FIG. 3 viewed from a different direction. FIG. 5 is a schematic plan view illustrating the configuration of the semiconductor device of FIG. 3. FIG. 6 is a schematic plan view illustrating the configuration of a semiconductor element included in the semiconductor device of FIG. 5. FIG. 7 is a schematic plan view illustrating the configuration of a second coil of the semiconductor device of FIG. 5. FIG. 8 is a schematic cross-sectional view taken along line 8-8 of FIG. 5. FIG. 9 is a schematic cross-sectional view taken along line 9-9 of FIG. 5. FIG. 10 is a schematic perspective view illustrating a semiconductor device of a modified example. FIG. 11 is a schematic perspective view of the semiconductor device of FIG. 10 viewed from a different direction. FIG. 12 is a schematic cross-sectional view of the semiconductor device of FIG. 10. FIG. 13 is a schematic perspective view illustrating a semiconductor device of a second embodiment. FIG. 14 is a schematic perspective view of the semiconductor device of FIG. 13 viewed from a different direction. FIG. 15 is a schematic plan view illustrating the configuration of the semiconductor device of FIG. 13. FIG. 16 is a schematic plan view showing a configuration relating to the second coil of the semiconductor device of FIG. 13. FIG. 17 is a schematic cross-sectional view taken along line 17-17 of FIG. 15. FIG. 18 is a schematic cross-sectional view taken along line 18-18 of FIG. 15. FIG. 19 is a schematic perspective view showing a semiconductor device of a modified example. FIG. 20 is a schematic perspective view of the semiconductor device of FIG. 19 viewed from a different direction. FIG. 21 is a schematic bottom view of the semiconductor device of FIG. 19. FIG. 22 is a schematic cross-sectional view of the semiconductor device of FIG. 19. FIG. 23 is a schematic perspective view showing a semiconductor device of a third embodiment. FIG. 24 is a schematic perspective view of the semiconductor device of FIG. 23 viewed from a different direction. FIG. 25 is a schematic plan view showing the configuration of the semiconductor device of FIG. 23. FIG. 26 is a schematic plan view showing a configuration relating to the second coil of the semiconductor device of FIG. 23. FIG. 27 is a schematic cross-sectional view taken along line 27-27 of FIG. 25. FIG. 28 is a schematic cross-sectional view taken along line 28-28 of FIG. 25. FIG. 29 is a schematic bottom view showing a semiconductor device of a modified example. Fig. 30 is a schematic cross-sectional view of the semiconductor device of Fig. 29. Fig. 31 is a schematic plan view showing a semiconductor device of a modified example. Fig. 32 is a schematic cross-sectional view of Fig. 31. Fig. 33 is a schematic plan view showing a semiconductor device of a modified example. Fig. 34 is a schematic cross-sectional view of the semiconductor device of Fig. 33.

[0008] Hereinafter, several embodiments of a signal transmission device and a semiconductor device according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] (First embodiment) (Schematic configuration of signal transmission device) The schematic configuration of a signal transmission device 900 will be described with reference to Figures 1 and 2. Figure 1 shows a simplified example of the circuit configuration of the signal transmission device 900. Figure 2 is a perspective view schematically showing the signal transmission device 900.

[0012] 1 , a signal transmission device 900 is a device that transmits a pulse signal while electrically isolating a first terminal 901 from a second terminal 902. The signal transmission device 900 is, for example, a digital isolator. The signal transmission device 900 includes a first circuit 911 electrically connected to the first terminal 901, a second circuit 912 electrically connected to the second terminal 902, and a transformer 913 that electrically isolates the first circuit 911 from the second circuit 912.

[0013] The first circuit 911 is configured to operate when a first voltage V1 is applied to it. The first circuit 911 is electrically connected to, for example, an external control device (not shown). The first circuit 911 includes a transmitting circuit 911A. The second circuit 912 is configured to operate when a second voltage V2 different from the first voltage V1 is applied to it. The second voltage V2 is, for example, higher than the first voltage V1. The first voltage V1 and the second voltage V2 are DC voltages. The second circuit 912 is electrically connected to, for example, a drive circuit that is controlled by the control device. An example of a drive circuit is a switching circuit. The second circuit 912 includes a receiving circuit 912A. The ground of the first circuit 911 and the ground of the second circuit 912 are provided independently of each other.

[0014] The transformer 913 is connected between the transmitting circuit 911A and the receiving circuit 912A. The transformer 913 includes two coils 913A and 913B. The coil 913A is connected to the transmitting circuit 911A, and the coil 913B is connected to the receiving circuit 912A.

[0015] A control signal from, for example, a control device is input to the transmitting circuit 911A of the first circuit 911 through the first terminal 901. The control signal is transmitted from the transmitting circuit 911A of the first circuit 911 through the transformer 913 and received by the receiving circuit 912A of the second circuit 912. The signal transmitted to the second circuit 912 is output from the second circuit 912 to the drive circuit through the second terminal 902. The first terminal 901 can be considered an input terminal for inputting a signal to the signal transmission device 900. The second terminal 902 can be considered an output terminal for outputting a signal from the signal transmission device 900.

[0016] As described above, in the signal transmission device 900, the first circuit 911 and the second circuit 912 are electrically isolated by the transformer 913. More specifically, the transformer 913 regulates the transmission of DC voltage between the first circuit 911 and the second circuit 912. Furthermore, the transformer 913 allows the transmission of pulse signals between the first circuit 911 and the second circuit 912.

[0017] That is, the state in which the first circuit 911 and the second circuit 912 are insulated means a state in which the transmission of DC voltage is blocked between the first circuit 911 and the second circuit 912, but the transmission of pulse signals from the first circuit 911 to the second circuit 912 is permitted. In this way, the second circuit 912 is configured to receive signals from the first circuit 911.

[0018] 2, the signal transmission device 900 includes a substrate 920 and a plurality of semiconductor devices 931, 932, and 10. The substrate 920 is formed, for example, in the shape of a rectangular plate. The substrate 920 includes a substrate front surface 921 and a substrate back surface 922 facing the opposite side to the substrate front surface 921. The substrate front surface 921 and the substrate back surface 922 are, for example, rectangular.

[0019] A plurality of first terminals 941 and a plurality of second terminals 942 are formed on the substrate surface 921. The plurality of first terminals 941 and the plurality of second terminals 942 are formed of a material containing, for example, Cu (copper). The plurality of first terminals 941 are arranged at a first end 923 of the substrate 920. The plurality of second terminals 942 are arranged at a second end 924 of the substrate 920 opposite the first end 923.

[0020] 1, a power supply terminal that supplies a first voltage V1, a ground terminal that is connected to the ground of the first circuit 911, and the first terminal 901. The second terminals 942 include a power supply terminal that supplies a second voltage V2, a ground terminal that is connected to the ground of the second circuit 912, and the second terminal 902.

[0021] The semiconductor devices 931, 932, and 10 are mounted on a substrate surface 921 of the substrate 920. In one example, the semiconductor devices 931, 932, and 10 are connected to pads (not shown) formed on the substrate surface 921. The pads are connected to a first terminal 941 and a second terminal 942 by wiring (not shown). The substrate 920 may be, for example, a semiconductor substrate, an insulating substrate formed from a material containing epoxy resin or the like, an insulating substrate formed from a material containing glass, or an insulating substrate formed from a material containing ceramics such as alumina.

[0022] The semiconductor device 931 includes the first circuit 911 shown in Fig. 1. The semiconductor device 932 includes the second circuit 912 shown in Fig. 1. The semiconductor device 10 includes the transformer 913 shown in Fig. 1. The semiconductor devices 931, 932, and 10 can be referred to as semiconductor chips. The signal transmission device 900 can be referred to as a semiconductor module. Furthermore, the signal transmission device 900 can be referred to as a multi-chip module including multiple semiconductor chips.

[0023] The semiconductor device 10 including the transformer 913 can also be said to be an insulating chip that provides insulation between the semiconductor device 931 including the first circuit 911 and the semiconductor device 932 including the second circuit 912. The semiconductor devices 931, 932, and 10 are arranged from the first terminal 941 toward the second terminal 942 in the order of the semiconductor device 931 including the first circuit 911, the semiconductor device 10 including the transformer 913, and the semiconductor device 932 including the second circuit 912.

[0024] The signal transmission device 900 may include a sealing member that seals the multiple semiconductor devices 931, 932, and 10 mounted on the substrate surface 921. The sealing member may be, for example, a case that houses the substrate 920 and the multiple semiconductor devices 931, 932, and 10. The case may be filled with a resin such as silicone resin. The sealing member may also be a sealing resin that covers at least the multiple semiconductor devices 931, 932, and 10. The sealing resin may be, for example, a mold resin containing epoxy resin or the like.

[0025] (Semiconductor Device Including a Transformer) The configuration of the semiconductor device 10 will be described with reference to FIGS. 3 to 9. FIGS. 3 and 4 are perspective views showing the appearance of the semiconductor device 10, with FIG. 3 being a perspective view of the semiconductor device 10 viewed from the top, and FIG. 4 being a perspective view of the semiconductor device 10 viewed from the bottom. FIG. 5 is a plan view of the semiconductor device 10 viewed from the bottom. Note that FIG. 5 shows the encapsulation resin 80 and the element insulating layer 22 in a see-through manner. FIG. 6 is a plan view showing the semiconductor element 20 in a see-through manner. Note that FIG. 6 shows the element insulating layer 22 in a see-through manner. FIG. 7 is a plan view showing the conductive portion 40 in a see-through manner. Note that FIG. 7 shows the encapsulation resin 80 in a see-through manner. In FIG. 7, the outline of the semiconductor element 20 is indicated by a dashed line. FIG. 8 is a schematic cross-sectional view of the semiconductor device 10 taken along line 8-8 in FIG. 5. FIG. 9 is a schematic cross-sectional view of the semiconductor device 10 taken along line 9-9 in FIG. 5. For the sake of convenience, in FIGS. 8 and 9, some components are shown that are not on the line indicating the cross-sectional position, and the positions and sizes of the components may differ from those in FIGS.

[0026] 3 and 4, the semiconductor device 10 is, for example, rectangular parallelepiped. In the following description, the thickness direction of the semiconductor device 10 is referred to as the z direction. The direction perpendicular to the z direction is referred to as the x direction, and the direction perpendicular to the z direction and the x direction is referred to as the y direction. Viewing an object from the z direction is referred to as a planar view.

[0027] The semiconductor device 10 includes a device top surface 10S, a device bottom surface 10R, and multiple device side surfaces 11, 12, 13, and 14. The device top surface 10S and the device bottom surface 10R face in opposite directions in the z direction. The multiple device side surfaces 11, 12, 13, and 14 intersect with the device top surface 10S and the device bottom surface 10R. The device side surfaces 11 and 12 face in opposite directions in the x direction. The device side surfaces 13 and 14 face in opposite directions in the y direction.

[0028] As shown in FIGS. 3 to 9 , the semiconductor device 10 includes a semiconductor element 20, a conductive portion 40, a joint portion SD, and a sealing resin 80. The semiconductor element 20 includes a first coil 26. The conductive portion 40 includes a second coil 43 and external connection terminals 51A, 51B, 61A, and 61B. The first coil 26 and the second coil 43 correspond to coils 913A and 913B shown in FIG. 1 . The semiconductor element 20 is mounted on the conductive portion 40, and the first coil 26 of the semiconductor element 20 faces the second coil 43 of the conductive portion 40 in the z-direction. As shown in FIG. 4 , the external connection terminals 51A, 51B, 61A, and 61B are exposed from the resin lower surface 80R of the sealing resin 80. The semiconductor device 10 is mounted on the substrate 920 shown in FIG. 2 by the external connection terminals 51A, 51B, 61A, and 61B.

[0029] (Semiconductor Element) As shown in FIGS. 6, 8, and 9, the semiconductor element 20 includes an element front surface 20S, an element rear surface 20R, and element side surfaces 201, 202, 203, and 204. The element front surface 20S and the element rear surface 20R face opposite each other in the z direction. The element front surface 20S faces the same direction as the resin lower surface 80R. The semiconductor element 20 is arranged so that the element front surface 20S faces the same direction as the resin lower surface. The element side surfaces 201, 202, 203, and 204 intersect with the element front surface 20S and the element rear surface 20R. In one example, the element side surfaces 201, 202, 203, and 204 are perpendicular to the element front surface 20S and the element rear surface 20R. The element side surfaces 201 and 202 face opposite each other in the x direction. The element side surfaces 203 and 204 face opposite each other in the y direction.

[0030] 8 and 9, the semiconductor device 20 includes an element substrate 21. The element substrate 21 is a semiconductor substrate and is formed of a material containing, for example, silicon (Si). In this embodiment, the element substrate 21 is a Si substrate.

[0031] The element substrate 21 has a substrate main surface 21S, a substrate back surface 21R, and multiple substrate side surfaces 211, 212, 213, and 214. The substrate main surface 21S and the substrate back surface 21R face opposite each other in the Z direction. As shown in FIGS. 3 and 4 , the substrate side surfaces 211 and 212 face opposite each other in the X direction. The substrate side surfaces 213 and 214 face opposite each other in the Y direction. The substrate main surface 21S faces the element connection portions 53A and 53B, dummy element connection portions 53C and 53D, and second coil 43 of the conductive portion 40. The substrate back surface 21R faces the same direction as the resin upper surface 80S.

[0032] The element insulating layer 22 is formed to cover the substrate main surface 21S. The element insulating layer 22 includes an insulating front surface 22S, an insulating back surface 22R, and multiple insulating side surfaces 221, 222, 223, and 224. The insulating front surface 22S of the element insulating layer 22 faces the same direction as the substrate main surface 21S. The insulating back surface 22R of the element insulating layer 22 faces the opposite side from the insulating front surface 22S of the element insulating layer 22. The insulating back surface 22R of the element insulating layer 22 faces the substrate main surface 21S and is in contact with the substrate main surface 21S. The insulating side surfaces 221, 222, 223, and 224 of the element insulating layer 22 face the same direction as the element side surfaces 201, 202, 203, and 204, respectively. The insulating front surface 22S of the element insulating layer 22 constitutes the element front surface 20S of the semiconductor element 20. The substrate rear surface 21R of the element substrate 21 constitutes the element rear surface 20R of the semiconductor element 20. The substrate side surfaces 211 to 214 of the element substrate 21 and the insulating side surfaces 221 to 224 of the element insulating layer 22 constitute the element side surfaces 201 to 204 of the semiconductor element 20.

[0033] The semiconductor element 20 includes a first coil 26. The first coil 26 corresponds to a "first conductor." The first coil 26 is formed in a spiral shape in a plan view. The first coil 26 includes an outer first end 26A and an inner second end 26B. The first end 26A corresponds to an "outer end." The second end 26B corresponds to an "inner end."

[0034] The first coil 26 is provided in the element insulating layer 22. In one example, the element insulating layer 22 includes three insulating layers 23, 24, and 25. The insulating layers 23, 24, and 25 are stacked in this order from the substrate main surface 21S of the element substrate 21. The first coil 26 is formed on the surface 24S of the second insulating layer 24. The first coil 26 and the surface 24S of the second insulating layer 24 are covered with the third insulating layer 25.

[0035] The element insulating layer 22 has insulating properties. The first insulating layer 23 and the second insulating layer 24 are made of a material containing, for example, Si (silicon). The first insulating layer 23 and the second insulating layer 24 are made of, for example, SiO ２ The third insulating layer 25 is made of an insulating resin such as polyimide resin, phenolic resin, or epoxy resin. The third insulating layer 25 may be made of a material containing Si.

[0036] The semiconductor element 20 includes a plurality of connection pads 27A, 27B, 27C, and 27D. The plurality of connection pads 27A to 27D are arranged at the same position as the first coil 26 in the z direction. The plurality of connection pads 27A to 27D are provided on a surface 24S of the second insulating layer 24. The third insulating layer 25 is formed so as to cover the peripheries of the connection pads 27A to 27D. The third insulating layer 25 includes an opening 25X that exposes a portion of the connection pads 27A to 27D.

[0037] 6, connection pad 27A is electrically connected to first end 26A of first coil 26. Connection pad 27B is electrically connected to second end 26B of first coil 26 by element wiring 28. Therefore, first coil 26 is connected between connection pad 27A and connection pad 27B. On the other hand, first coil 26 is not electrically connected to connection pad 27C and connection pad 27D. Connection pads 27C and 27D that are not electrically connected to first coil 26 in this manner correspond to "dummy connection pads."

[0038] 8 , the element wiring 28 is formed on the surface 23S of the first insulating layer 23. The element wiring 28 is formed of a material containing, for example, Cu, Al (aluminum), etc. A first end 28A of the element wiring 28 is electrically connected to the first coil 26 by a via 29A. A second end 28B of the element wiring 28 is electrically connected to the connection pad 27B by a via 29B. The vias 29A and 29B penetrate the second insulating layer 24. The vias 29A and 29B are formed of a material containing, for example, Cu, Al, W (tungsten), etc.

[0039] The semiconductor element 20 includes element electrodes 31A, 31B, 31C, and 31D electrically connected to a plurality of connection pads 27A, 27B, 27C, and 27D. The element electrodes 31A, 31B, 31C, and 31D are electrically connected to the connection pads 27A, 27B, 27C, and 27D, respectively, by connection wiring 30. The element electrodes 31A to 31D are arranged so as to overlap the connection pads 27A to 27D in a plan view.

[0040] The connection pads 27A and 27B are electrically connected to the first coil 26. Therefore, the element electrodes 31A and 31B electrically connected to the connection pads 27A and 27B are electrically connected to the first coil 26. On the other hand, the connection pads 27C and 27D are not electrically connected to the first coil 26. Therefore, the element electrodes 31C and 31D electrically connected to the connection pads 27C and 27D are not electrically connected to the first coil 26. In this way, the element electrodes 31C and 31D that are not electrically connected to the first coil 26 correspond to "dummy element electrodes."

[0041] The element electrodes 31A to 31D each include a conductive layer 32 and a barrier layer 33. The conductive layer 32 is made of a material containing Cu, for example. The conductive layer 32 may be made of multiple metal layers. The conductive layer 32 may also include a seed layer. The seed layer is made of, for example, Ti (titanium) / Cu. The barrier layer 33 is made of a material containing Ni. The barrier layer 33 may also be made of multiple metal layers. The barrier layer 33 is made of, for example, Ni (nickel), Pd (palladium), Au (gold), an alloy containing two or more of these metals, or the like.

[0042] (Conductive Portion) As shown in FIGS. 7, 8, and 9, the conductive portion 40 includes a first wiring member 41, a second wiring member 42, and a second coil 43.

[0043] The first wiring member 41 includes a first external connection terminal 51A, a second external connection terminal 51B, a first element connection portion 53A, a second element connection portion 53B, a first connection wiring 54A, and a second connection wiring 54B. The second wiring member 42 includes a third external connection terminal 61A, a fourth external connection terminal 61B, and a third connection wiring 64. The third connection wiring 64 corresponds to a "second lead wiring."

[0044] As shown in Fig. 7 , the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B are formed in a quadrangular shape in a plan view. Note that the shapes of the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view. As shown in Figs. 8 and 9 , the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B are exposed from the resin lower surface 80R of the sealing resin 80.

[0045] 5, the first external connection terminal 51A and the second external connection terminal 51B are arranged along the device side surface 12 of the semiconductor device 10, for example. The first external connection terminal 51A and the second external connection terminal 51B are arranged spaced apart in the y direction. The first external connection terminal 51A and the second external connection terminal 51B are arranged side by side in the y direction in a plan view. The first external connection terminal 51A is arranged at a corner formed by the device side surface 12 and the device side surface 13 of the semiconductor device 10. The second external connection terminal 51B is arranged at a corner formed by the device side surface 12 and the device side surface 14 of the semiconductor device 10.

[0046] The first external connection terminal 51A includes a connecting portion 52A. The connecting portion 52A extends toward the device side surface 12 and is exposed from the device side surface 12. The second external connection terminal 51B includes a connecting portion 52B. The connecting portion 52B extends toward the device side surface 12 and is exposed from the device side surface 12.

[0047] 5 and 7 , the first element connection portion 53A and the second element connection portion 53B are disposed at positions overlapping the semiconductor element 20 in a plan view. The first element connection portion 53A and the second element connection portion 53B are disposed at positions overlapping the element electrodes 31A, 31B of the semiconductor element 20 in the z direction.

[0048] The first element connection portion 53A and the second element connection portion 53B are formed in a quadrangular shape in a plan view, but the shapes of the first element connection portion 53A and the second element connection portion 53B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0049] The first element connection portion 53A is electrically connected to the first external connection terminal 51A by a first connection wiring 54A. The second element connection portion 53B is electrically connected to the second external connection terminal 51B by a second connection wiring 54B.

[0050] The third external connection terminal 61A is arranged on the device side surface 11 side of the semiconductor device 10. In one example, the third external connection terminal 61A is arranged at the center of the device side surface 11 in the y direction in a plan view. The arrangement position of the third external connection terminal 61A can be changed as desired. For example, the third external connection terminal 61A may be arranged at a corner formed by the device side surfaces 11 and 13 of the semiconductor device 10, or at a corner formed by the device side surfaces 11 and 14. The third external connection terminal 61A includes a connecting portion 62A. The connecting portion 62A extends toward the device side surface 11 and is exposed from the device side surface 11.

[0051] 4, 5, and 7, the fourth external connection terminal 61B is disposed at the center of the semiconductor device 10 in a plan view. In one example, the third external connection terminal 61A is disposed at the same position as the fourth external connection terminal 61B in the y direction in a plan view. In other words, the third external connection terminal 61A and the fourth external connection terminal 61B are disposed side by side in the x direction in a plan view.

[0052] 7, the second coil 43 is formed in a spiral shape in a plan view. The second coil 43 includes an outer first end 43A and an inner second end 43B. The first end 43A corresponds to the "outer end" and the second end 43B corresponds to the "inner end."

[0053] The first end 43A of the second coil 43 is electrically connected to the third external connection terminal 61A via the third connection wiring 64. The second end 43B of the second coil 43 is electrically connected to the fourth external connection terminal 61B.

[0054] As shown in FIGS. 5 and 7 , the conductive portion 40 includes dummy element connecting portions 53C and 53D. The dummy element connecting portions 53C and 53D are arranged at positions overlapping the semiconductor element 20 in a plan view. The dummy element connecting portions 53C and 53D are arranged at positions overlapping the element electrodes 31C and 31D of the semiconductor element 20 in the z direction. The dummy element connecting portions 53C and 53D are connected to, for example, the third connection wiring 64, the third external connection terminal 61A, etc., by connection leads (not shown). The dummy element connecting portions 53C and 53D are arranged at the same positions as the element connecting portions 53A and 53B in the z direction. Furthermore, the dummy element connecting portions 53C and 53D are held at the same positions as the element connecting portions 53A and 53B in the z direction by the connection leads.

[0055] 8 and 9 , the second coil 43, the element connection portions 53A and 53B, the dummy element connection portions 53C and 53D, and the connection wirings 54A, 54B, and 64 included in the conductive portion 40 are arranged at the same position in the z direction. In one example, the upper surfaces of the second coil 43, the element connection portions 53A and 53B, the dummy element connection portions 53C and 53D, and the connection wirings 54A, 54B, and 64 are arranged at the same position in the z direction as the upper surfaces 51S and 61S of the external connection terminals 51A, 51B, 61A, and 61B.

[0056] In one example, the conductive portion 40 is configured by a lead frame. The lead frame is made of a material containing Cu. The conductive portion 40 is connected to a frame formed, for example, by etching a Cu plate. After the process of forming the sealing resin 80, the conductive portion 40 is separated from the frame at the connecting portions 52A, 52B, and 62A.

[0057] The z-direction thickness T12 of the second coil 43 formed by the lead frame is greater than the thickness T11 of the first coil 26 formed by a semiconductor process. As shown in FIGS. 8 and 9 , the width W1 of the first coil 26 in a direction parallel to the element surface 20S is defined as, for example, the width in the x-direction. The width W2 of the second coil 43 in a direction parallel to the element surface 20S is defined as, for example, the width in the x-direction. The width W1 of the first coil 26 corresponds to the "first width dimension," and the width W2 of the second coil 43 corresponds to the "second width dimension." For example, the width W1 of the first coil 26 is equal to the width W2 of the second coil 43. The width W1 of the first coil 26 may be smaller than the width W2 of the second coil 43. The width W1 of the first coil 26 may also be larger than the width W2 of the second coil 43.

[0058] 8 and 9, the element electrodes 31A and 31B of the semiconductor element 20 are electrically connected to the element connection portions 53A and 53B by the joints SD. The element electrodes 31C and 31D of the semiconductor element 20 are electrically connected to the dummy element connection portions 53C and 53D by the joints SD. The joints SD are, for example, solder layers. The solder layers are made of a material containing Sn (tin). The solder layers are made of Sn, Sn-Ag (silver)-based alloys, Sn-Sb (antimony)-based alloys, etc.

[0059] The semiconductor element 20 is connected to the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D by joints SD. The element surface 20S of the semiconductor element 20 is spaced apart in the z direction from the upper surfaces of the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D. Therefore, the element surface 20S of the semiconductor element 20 is spaced apart in the z direction from the second coil 43, which is disposed in the same position as the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D.

[0060] (Sealing Resin) The sealing resin 80 seals the semiconductor element 20, the conductive portion 40, and the bonding portion SD. As shown in Figures 3 and 4, the sealing resin 80 forms the outer surface of the semiconductor device 10.

[0061] The sealing resin 80 includes a resin upper surface 80S, a resin lower surface 80R, and multiple resin side surfaces 81, 82, 83, and 84. The resin upper surface 80S and the resin lower surface 80R face opposite each other in the z direction. The resin side surfaces 81, 82, 83, and 84 are perpendicular to the resin upper surface 80S and the resin lower surface 80R. The resin side surfaces 81 and 82 face opposite each other in the x direction. The resin side surfaces 83 and 84 face opposite each other in the y direction.

[0062] The sealing resin 80 is made of, for example, a resin having electrical insulating properties. As this resin, for example, a synthetic resin containing an epoxy resin as a main component can be used. As the sealing resin 80, for example, a synthetic resin containing a filler can be used. The filler can be, for example, SiO ２ The sealing resin 80 is colored, for example, in black. The material and shape of the sealing resin 80 are not limited.

[0063] 8 and 9 , the sealing resin 80 contacts the element front surface 20S, element back surface 20R, and multiple element side surfaces 201 to 204 of the semiconductor element 20. Furthermore, the sealing resin 80 contacts the surface of the conductive portion 40. Therefore, the sealing resin 80 seals the semiconductor element 20 and the second coil 43. The second coil 43 is spaced apart from the element front surface 20S of the semiconductor element 20. Therefore, the sealing resin 80 includes a resin portion 85 between the element front surface 20S of the semiconductor element 20 and the second coil 43.

[0064] The thickness T22 of the resin portion 85 is greater than the thickness of the third insulating layer 25 covering the first coil 26 of the semiconductor element 20. Specifically, the thickness T22 of the resin portion 85 is greater than the thickness T21 of the element resin portion 25A of the third insulating layer 25 from the first coil 26 to the element surface 20S. The thickness T22 of the resin portion 85 of the sealing resin 80 corresponds to the thickness of the sealing resin 80 interposed between the first coil 26 and the second coil 43. The thickness T21 of the element resin portion 25A of the third insulating layer 25 corresponds to the thickness of the element insulating layer 22 interposed between the first coil 26 and the second coil 43. The sum of the thickness T22 of the sealing resin 80 and the thickness T21 of the element insulating layer 22 corresponds to the distance D12 between the first coil 26 and the second coil 43 in the z direction. The distance D12 between the first coil 26 and the second coil 43 can be, for example, 50 μm or more and 100 μm or less.

[0065] (Function) Next, the function of the semiconductor device 10 will be described. The semiconductor device 10 includes a semiconductor element 20, a second coil 43, and a sealing resin 80. The semiconductor element 20 includes an element front surface 20S and an element back surface 20R facing opposite each other in the z direction, an element insulating layer 22 including an insulating surface 22S constituting the element front surface 20S, and a first coil 26 provided within the element insulating layer 22. The second coil 43 is disposed spaced apart from the first coil 26 in the z direction. The sealing resin 80 contacts the element insulating layer 22 and seals the semiconductor element 20 and the second coil 43. The first coil 26 and the second coil 43 face each other in the thickness direction, with the element insulating layer 22 and the sealing resin 80 sandwiched between them.

[0066] The dielectric strength of the semiconductor device 10 is determined by the distance D12 between the first coil 26 and the second coil 43 in the z direction. An element insulating layer 22 and a sealing resin 80 are interposed between the first coil 26 and the second coil 43. Therefore, by increasing the thickness of the element insulating layer 22 and the sealing resin 80 between the first coil 26 and the second coil 43, the dielectric strength of the semiconductor device 10 can be improved.

[0067] The sealing resin 80 is formed by, for example, molding. Therefore, for example, SiN or SiO ２In comparison with the case where an insulator is used, the insulator between the first coil 26 and the second coil 43 can be easily formed.

[0068] The semiconductor element 20 includes connection pads 27A and 27B electrically connected to the first coil 26. The connection pads 27A and 27B are electrically connected to element electrodes 31A and 31B. The element electrodes 31A and 31B are electrically connected to element connection portions 53A and 53B of the conductive portion 40 via joint portions SD. The joint portions SD are, for example, solder layers. Therefore, the semiconductor element 20 can be electrically connected to the conductive portion 40 more easily than when using bonding wires or the like.

[0069] The semiconductor element 20 includes a first element electrode 31A and a second element electrode 31B electrically connected to the first coil 26. The semiconductor element 20 is arranged such that the element surface 20S on which the element electrodes 31A and 31B are provided faces the conductive portion 40 including the second coil 43. Therefore, the semiconductor device 10 can easily arrange the first coil 26 opposite the second coil 43.

[0070] The semiconductor device 10 includes a first external connection terminal 51A and a second external connection terminal 51B electrically connected to the first coil 26, and a third external connection terminal 61A and a fourth external connection terminal 61B electrically connected to the second coil 43. The first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B are exposed from the resin lower surface 80R of the sealing resin 80. The semiconductor device 10 is mounted on the substrate 920 shown in FIG. 2 by the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B exposed from the resin lower surface 80R of the sealing resin 80. In this manner, the semiconductor device 10 can be easily mounted on the substrate 920.

[0071] The element electrodes 31A, 31B connected to the first coil 26 are connected to element connection portions 53A, 53B of the conductive portion 40 via joints SD. The element electrodes 31C, 31D not connected to the first coil 26 are connected to dummy element connection portions 53C, 53D of the conductive portion 40 via joints SD. The dummy element connection portions 53C, 53D are located at the same positions as the element connection portions 53A, 53B in the z direction. Therefore, the element electrodes 31A, 31B, 31C, 31D of the semiconductor element 20 are located at the same positions as the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D in the z direction. The second coil 43 of the conductive portion 40 is located at the same positions as the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D. Therefore, the insulating surface 22S of the element insulating layer 22 of the semiconductor element 20 can face the upper surface 43S of the second coil 43 in the z direction. The first coil 26 provided in the element insulating layer 22 of the semiconductor element 20 can be opposed to the second coil 43 in the z direction.

[0072] (Effects) As described above, the first embodiment provides the following effects. (1-1) The semiconductor device 10 includes a semiconductor element 20, a second coil 43, and a sealing resin 80. The semiconductor element 20 includes an element front surface 20S and an element back surface 20R facing opposite each other in the z direction, an element insulating layer 22 including an insulating surface 22S constituting the element front surface 20S, and a first coil 26 provided within the element insulating layer 22. The second coil 43 is disposed spaced apart from the first coil 26 in the z direction. The sealing resin 80 contacts the element insulating layer 22 and seals the semiconductor element 20 and the second coil 43. The first coil 26 and the second coil 43 face each other in the thickness direction with the element insulating layer 22 and the sealing resin 80 sandwiched therebetween.

[0073] The dielectric strength of the semiconductor device 10 is determined by the distance D12 between the first coil 26 and the second coil 43 in the z direction. An element insulating layer 22 and a sealing resin 80 are interposed between the first coil 26 and the second coil 43. Therefore, by increasing the thickness of the element insulating layer 22 and the sealing resin 80 between the first coil 26 and the second coil 43, the dielectric strength of the semiconductor device 10 can be improved.

[0074] (1-2) The sealing resin 80 is formed by, for example, molding. Therefore, for example, SiN or SiO ２ In comparison with the case where an insulator is used, the insulator between the first coil 26 and the second coil 43 can be easily formed.

[0075] (1-3) The semiconductor element 20 includes connection pads 27A and 27B electrically connected to the first coil 26. The connection pads 27A and 27B are electrically connected to the element electrodes 31A and 31B. The element electrodes 31A and 31B are electrically connected to the element connection portions 53A and 53B of the conductive portion 40 by joint portions SD. The joint portions SD are, for example, solder layers. Therefore, the semiconductor element 20 can be electrically connected to the conductive portion 40 more easily than when using bonding wires or the like.

[0076] (1-4) The semiconductor element 20 includes a first element electrode 31A and a second element electrode 31B electrically connected to the first coil 26. The semiconductor element 20 is arranged such that the element surface 20S on which the element electrodes 31A and 31B are provided faces the conductive portion 40 including the second coil 43. Therefore, the semiconductor device 10 can easily arrange the first coil 26 opposite the second coil 43.

[0077] (1-5) The semiconductor device 10 includes a first external connection terminal 51A and a second external connection terminal 51B electrically connected to the first coil 26, and a third external connection terminal 61A and a fourth external connection terminal 61B electrically connected to the second coil 43. The first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B are exposed from the resin lower surface 80R of the sealing resin 80. The semiconductor device 10 is mounted on a substrate 920 of the signal transmission device 900 by the first external connection terminal 51A, the second external connection terminal 51B, the third external connection terminal 61A, and the fourth external connection terminal 61B exposed from the resin lower surface 80R of the sealing resin 80. In this manner, the semiconductor device 10 can be easily mounted on the substrate 920.

[0078] (1-6) The element electrodes 31A, 31B connected to the first coil 26 are connected to the element connection portions 53A, 53B of the conductive portion 40 via joints SD. The element electrodes 31C, 31D not connected to the first coil 26 are connected to the dummy element connection portions 53C, 53D of the conductive portion 40 via joints SD. The dummy element connection portions 53C, 53D are arranged in the same positions as the element connection portions 53A, 53B in the z direction. Therefore, the element electrodes 31A, 31B, 31C, 31D of the semiconductor element 20 are arranged in the same positions as the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D in the z direction. The second coil 43 of the conductive portion 40 is arranged in the same positions as the element connection portions 53A, 53B and the dummy element connection portions 53C, 53D. Therefore, the insulating surface 22S of the element insulating layer 22 of the semiconductor element 20 can be opposed to the upper surface 43S of the second coil 43 in the z direction. The first coil 26 provided in the element insulating layer 22 of the semiconductor element 20 can be opposed to the second coil 43 in the z direction.

[0079] (Modification of First Embodiment) A semiconductor device according to a modification of the first embodiment will now be described. In the semiconductor device according to the modification, components common to those of the first embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted.

[0080] The surfaces of the external connection terminals 51A, 51B, 61A exposed from the sealing resin 80 may be covered with an external conductive film. The external conductive film may be composed of, for example, multiple metal layers stacked on top of each other. Examples of the metal layers include Ni layers, Pd layers, and Au layers. The material of the external conductive film is not limited, but may be, for example, a stack of Ni layers and Au layers, or Sn.

[0081] 10 and 11 , the semiconductor device 110 includes a sealing resin 180. The resin side surfaces 81 and 82 of the sealing resin 180 include first side surfaces 81A and 82A and second side surfaces 82B and 82B, respectively. The first side surfaces 81A and 82A are disposed closer to the resin upper surface 80S than to the resin lower surface 80R in the z direction. The second side surfaces 81B and 82B are disposed closer to the resin lower surface 80R than to the resin upper surface 80S in the z direction. The second side surfaces 81B and 82B are located inside the sealing resin 180 relative to the first side surfaces 81A and 82A in a plan view. In other words, the sealing resin is formed so that the side of the resin upper surface 80S is larger than the side of the resin lower surface 80R in the z direction.

[0082] The first side surfaces 81A, 82A are perpendicular to the resin upper surface 80S. The second side surfaces 81B, 82B are perpendicular to the resin lower surface 80R. The sealing resin 180 has a step 183 that is recessed toward the inside of the sealing resin 180 in a plan view, depending on the positions of the first side surfaces 81A, 82A and the second side surfaces 81B, 82B of the resin side surfaces 81, 82. The step 183 may be provided on the resin side surfaces 81 to 84.

[0083] 10 to 12, the first external connection terminal 51A is exposed from the second side surface 82B of the resin side surface 82 in the x direction. That is, the first external connection terminal 51A is exposed from the resin lower surface 80R of the sealing resin 180 and the second side surface 82B of the resin side surface 82. The first external connection terminal 51A includes a lower surface 51A1 and a side surface 51A2 that are exposed from the sealing resin 180. The lower surface 51A1 and the side surface 51A2 of the first external connection terminal 51A may be covered with an external conductive film.

[0084] The second external connection terminal 51B is exposed from the second side surface 82B of the resin side surface 82 in the x direction. That is, the second external connection terminal 51B is exposed from the resin lower surface 80R of the sealing resin 180 and the second side surface 82B of the resin side surface 82. The second external connection terminal 51B includes a lower surface 51B1 and a side surface 51B2 exposed from the sealing resin 180. The lower surface 51B1 and the side surface 51B2 of the second external connection terminal 51B may be covered with an external conductive film.

[0085] The third external connection terminal 61A is exposed in the x direction from the second side surface 81B of the resin side surface 81. That is, the third external connection terminal 61A is exposed from the resin lower surface 80R of the sealing resin 180 and the second side surface 81B of the resin side surface 81. The third external connection terminal 61A includes a lower surface 61A1 and a side surface 61A2 that are exposed from the sealing resin 180. The lower surface 61A1 and the side surface 61A2 of the third external connection terminal 61A may be covered with an external conductive film.

[0086] The semiconductor device 110 of the modified example is mounted on a substrate 920 shown in FIG. 2 . At this time, the solder connecting each external connection terminal 51A, 51B, 61A, 61B to the mounting pads of the substrate 920 adheres to the undersides 51A1, 51B1, 61A1 and the side surfaces 51A2, 51B2, 61A2 of the external connection terminals 51A, 51B, 61A. For example, during a reflow process, the liquid-phase solder creeps up the side surfaces 51A2, 51B2, 61A2 of the external connection terminals 51A, 51B, 61A, forming solder fillets between the side surfaces 51A2, 51B2, 61A2 and the mounting pads. In this way, solder fillets are easily formed in the semiconductor device 110. These solder fillets increase the solder joint area and improve connection strength. Furthermore, the solder fillets make it easier to check the soldering condition of the semiconductor device 110.

[0087] Second Embodiment The configuration of a semiconductor device 210 of a second embodiment will be described with reference to Figures 13 to 18. The semiconductor device 210 is mounted on a substrate 920 instead of the semiconductor device 10 shown in Figure 2. The semiconductor device 210 of the second embodiment differs from the semiconductor device 10 of the first embodiment in the structure of the conductive portion 240 to which the semiconductor element 20 is connected. In the following description, components common to the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0088] 13 and 14 are perspective views showing the appearance of the semiconductor device 210, with FIG. 13 being a perspective view of the semiconductor device 210 viewed from the top, and FIG. 14 being a perspective view of the semiconductor device 210 viewed from the bottom. FIG. 15 is a plan view of the semiconductor device 210 viewed from the bottom. Note that FIG. 15 shows the semiconductor device 210 through a sealing resin 280. FIG. 16 is a plan view showing a conductive portion 240. FIG. 17 is a schematic cross-sectional view of the semiconductor device 210 taken along line 17-17 in FIG. 15. FIG. 18 is a schematic cross-sectional view of the semiconductor device 210 taken along line 18-18 in FIG. 15. Note that for convenience, FIGS. 17 and 18 may show components that are not on the line indicating the cross-sectional position, or the positions and sizes of components may differ from those in FIGS. 15 and 16.

[0089] 13 and 14, the semiconductor device 210 has, for example, a rectangular parallelepiped shape. As shown in FIGS. 13 to 18, the semiconductor device 210 includes a substrate 271, a substrate insulating film 272, a semiconductor element 20, a conductive portion 240, and a sealing resin 280.

[0090] The conductive section 240 includes a second coil 243 and external connection terminals 251A, 251B, 261A, and 261B. The semiconductor element 20 is mounted on the conductive section 240. The first coil 26 of the semiconductor element 20 faces the second coil 243 of the conductive section 240 in the z direction. The first coil 26 and the second coil 243 correspond to the coils 913A and 913B shown in FIG. 1. As shown in FIGS. 17 and 18 , the semiconductor device 210 includes an external conductive film 70 that covers the external connection terminals 251A, 251B, 261A, and 261B.

[0091] The semiconductor device 210 includes a device top surface 10S, a device bottom surface 10R, and multiple device side surfaces 11, 12, 13, and 14. (Substrate) The substrate 271 is formed in a rectangular plate shape in a plan view. The substrate 271 may have insulating properties. As an example, the substrate 271 may be a semiconductor substrate. The substrate 271 is formed of a material containing, for example, Si.

[0092] The substrate 271 includes an upper surface 271S, a lower surface 271R, and multiple side surfaces 271C. The upper surface 271S and the lower surface 271R face opposite each other in the z direction. The multiple side surfaces 271C intersect with the upper surface 271S and the lower surface 271R. The multiple side surfaces 271C face either the x direction or the y direction. The upper surface 271S of the substrate 271 constitutes the device upper surface 10S of the semiconductor device 210. The multiple side surfaces 271C constitute device side surfaces 11 to 14 of the semiconductor device 210.

[0093] The substrate insulating film 272 is provided on the lower surface 271R of the substrate 271. The substrate insulating film 272 is formed to have the same size as the substrate 271 in a plan view. The substrate insulating film 272 includes an upper surface 272S, a lower surface 272R, and multiple side surfaces 272C. The upper surface 272S and the lower surface 272R face opposite each other in the z direction. The multiple side surfaces 272C intersect with the upper surface 272S and the lower surface 272R. The multiple side surfaces 272C face either the x direction or the y direction. The upper surface 272S of the substrate insulating film 272 contacts the lower surface 272R of the substrate 271. The multiple side surfaces 272C constitute device side surfaces 11 to 14 of the semiconductor device 210.

[0094] The substrate insulating film 272 is formed of a material containing Si, for example. ２ , SiN, etc. The substrate insulating film 272 may be made up of a plurality of insulating films.

[0095] (Sealing Resin) The sealing resin 280 is provided on the lower surface 272R of the substrate insulating film 272. The sealing resin 280 is formed to have the same size as the substrate 271 and the substrate insulating film 272 in a plan view.

[0096] Sealing resin 280 includes a resin upper surface 80S, a resin lower surface 80R, and a plurality of resin side surfaces 81 to 84. Resin upper surface 80S of sealing resin 280 contacts lower surface 272R of substrate insulating film 272. It can be said that semiconductor device 210 includes substrate 271, substrate insulating film 272 laminated on lower surface 271R of substrate 271, and sealing resin 280.

[0097] The sealing resin 280 seals the semiconductor element 20, the conductive portion 240, and the bonding portion SD. The sealing resin 280 covers the element front surface 20S, the element back surface 20R, and the element side surfaces 201 to 204 of the semiconductor element 20. Therefore, it can be said that the semiconductor element 20 is embedded in the sealing resin 280. The semiconductor element 20 is disposed in the sealing resin 280 so that the element front surface 20S faces the same direction as the resin upper surface 80S of the sealing resin 280. Therefore, the element front surface 20S of the semiconductor element 20 faces the lower surface 272R of the substrate insulating film 272.

[0098] The sealing resin 280 is made of, for example, a resin having electrical insulating properties. As this resin, for example, a synthetic resin containing an epoxy resin as a main component can be used. As the sealing resin 280, for example, a synthetic resin containing a filler can be used. The filler can be, for example, SiO ２ The sealing resin 280 is colored, for example, black. The material and shape of the sealing resin 280 are not limited.

[0099] 15 to 17 , the conductive portion 240 includes a first wiring member 241, a second wiring member 242, and a second coil 243. The conductive portion 240 may be formed of, for example, a plating layer. The conductive portion 240 is formed of, for example, a material containing Cu.

[0100] (First Wiring Member) The first wiring member 241 includes a first external connection terminal 251A, a second external connection terminal 251B, a first element connection portion 253A, a second element connection portion 253B, a first connection wiring 254A, a second connection wiring 254B, a first terminal connection portion 255A, and a second terminal connection portion 255B. The first element connection portion 253A, the second element connection portion 253B, the first connection wiring 254A, the second connection wiring 254B, the first terminal connection portion 255A, and the second terminal connection portion 255B configure a "first lead-out wiring."

[0101] 15 and 18 , the first element connection portion 253A, the first connection wiring 254A, and the first terminal connection portion 255A are formed on the lower surface 272R of the substrate insulating film 272. The first element connection portion 253A is electrically connected to the first terminal connection portion 255A by the first connection wiring 254A. The first element connection portion 253A, the first connection wiring 254A, and the first terminal connection portion 255A may be an integrally formed one-piece body.

[0102] 15 and 17 , the second element connection portion 253B, the second connection wiring 254B, and the second terminal connection portion 255B are formed on the lower surface 272R of the substrate insulating film 272. The second element connection portion 253B is electrically connected to the second terminal connection portion 255B by the second connection wiring 254B. The second element connection portion 253B, the second connection wiring 254B, and the second terminal connection portion 255B may be an integrally formed one-piece member.

[0103] 15 , the first element connection portion 253A and the second element connection portion 253B are arranged at positions overlapping the semiconductor element 20 in a plan view. The first element connection portion 253A and the second element connection portion 253B are arranged at positions overlapping the element electrodes 31A, 31B of the semiconductor element 20 in the z direction.

[0104] The first element connection portion 253A and the second element connection portion 253B are formed in a quadrangular shape in a plan view, but the shapes of the first element connection portion 253A and the second element connection portion 253B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0105] 18, the first element connection portion 253A is electrically connected to the first element electrode 31A of the semiconductor element 20 via a joint SD. As shown in Fig. 17, the second element connection portion 253B is electrically connected to the second element electrode 31B of the semiconductor element 20 via a joint SD.

[0106] 18 , the first external connection terminal 251A is provided on the lower surface 255R of the first terminal connection portion 255A. The first external connection terminal 251A is electrically connected to the first terminal connection portion 255A. The first external connection terminal 251A extends from the first terminal connection portion 255A toward the resin lower surface 80R of the sealing resin 280. The lower surface 251A1 of the first external connection terminal 251A is exposed from the resin lower surface 80R of the sealing resin 280.

[0107] 17 , the second external connection terminal 251B is provided on the lower surface 255R of the second terminal connection portion 255B. The second external connection terminal 251B is electrically connected to the second terminal connection portion 255B. The second external connection terminal 251B extends from the second terminal connection portion 255B toward the resin lower surface 80R of the sealing resin 280. The lower surface 251B1 of the second external connection terminal 251B is exposed from the resin lower surface 80R of the sealing resin 280.

[0108] 15 and 16, the first external connection terminal 251A and the second external connection terminal 251B are formed in a quadrangular shape in a plan view. Note that the shapes of the first external connection terminal 251A and the second external connection terminal 251B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0109] 15 and 16 , the first external connection terminal 251A and the second external connection terminal 251B are arranged along the device side surface 12 of the semiconductor device 210, in one example. The first external connection terminal 251A and the second external connection terminal 251B are arranged spaced apart in the y direction. The first external connection terminal 251A and the second external connection terminal 251B are arranged side by side in the y direction in a plan view. The first external connection terminal 251A is arranged at a corner formed by the device side surface 12 and the device side surface 14 of the semiconductor device 210. The second external connection terminal 251B is arranged at a corner formed by the device side surface 12 and the device side surface 13 of the semiconductor device 210.

[0110] (Second Coil) As shown in Fig. 17 , the second coil 243 is formed on the lower surface 272R of the substrate insulating film 272. As shown in Fig. 15 and 16 , the second coil 243 is formed in a spiral shape in a plan view. As shown in Fig. 15 , the second coil 243 is arranged so as to overlap with the first coil 26 of the semiconductor element 20 in a plan view.

[0111] 15 to 18 , the second wiring member 242 includes a third external connection terminal 261A, a fourth external connection terminal 261B, a third connection wiring 264A, a fourth connection wiring 264B, a third terminal connection portion 265A, a fourth terminal connection portion 265B, and an end connection portion 266. The third connection wiring 264A, the fourth connection wiring 264B, the third terminal connection portion 265A, and the fourth terminal connection portion 265B configure a “second lead-out wiring.”

[0112] 15 and 16, the second coil 243 is formed in a spiral shape in a plan view. The second coil 243 includes an outer first end 243A and an inner second end 243B. The first end 243A corresponds to the "outer end." The second end 243B corresponds to the "inner end."

[0113] The end connection portion 266 is disposed inside the second coil 243. The end connection portion 266 is electrically connected to the second end 243B of the second coil 243. The first end 243A of the second coil 243 is electrically connected to the third terminal connection portion 265A via the third connection wiring 264A. The second coil 243, the end connection portion 266, the third connection wiring 264A, and the third terminal connection portion 265A may be integrally formed as a single unit.

[0114] 15 to 17 , the end connection portion 266 is electrically connected to the fourth terminal connection portion 265B by a fourth connection wiring 264B. As shown in FIG. 17 , the fourth connection wiring 264B is embedded in a substrate insulating film 272. The fourth connection wiring 264B includes a buried wiring 267 and vias 268A and 268B. A first end of the buried wiring 267 is electrically connected to the end connection portion 266 by the via 268A. A second end of the buried wiring 267 is electrically connected to the fourth terminal connection portion 265B by the via 268B.

[0115] 18 , the third external connection terminal 261A is provided on the lower surface 265R of the third terminal connection portion 265A. The third external connection terminal 261A is electrically connected to the third terminal connection portion 265A. The third external connection terminal 261A extends from the third terminal connection portion 265A toward the resin lower surface 80R of the sealing resin 280. A lower surface 261A1 of the third external connection terminal 261A is exposed from the sealing resin 280.

[0116] 17 , the fourth external connection terminal 261B is provided on the lower surface 265R of the fourth terminal connection portion 265B. The fourth external connection terminal 261B is electrically connected to the fourth terminal connection portion 265B. The fourth external connection terminal 261B extends from the fourth terminal connection portion 265B toward the resin lower surface 80R of the sealing resin 280. A lower surface 261B1 of the fourth external connection terminal 261B is exposed from the sealing resin 280.

[0117] 15 and 16, the third and fourth external connection terminals 261A and 261B are formed in a quadrangular shape in a plan view. However, the shape of the third and fourth external connection terminals 261A and 261B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0118] In one example, the third external connection terminal 261A and the fourth external connection terminal 261B are arranged along the device side surface 11 of the semiconductor device 210. The third external connection terminal 261A and the fourth external connection terminal 261B are arranged spaced apart in the y direction. The first external connection terminal 251A and the second external connection terminal 251B are arranged side by side in the y direction in a plan view. The third external connection terminal 261A is arranged at a corner formed by the device side surface 11 and the device side surface 14 of the semiconductor device 210. The fourth external connection terminal 261B is arranged at a corner formed by the device side surface 11 and the device side surface 13 of the semiconductor device 210.

[0119] (External Conductive Film) As shown in Figures 15 to 18, the external conductive film 70 is formed to cover the lower surfaces 251A1, 251B1, 261A1, and 261B1 of the external connection terminals 251A, 251B, 261A, and 261B, respectively. The external conductive film 70 is composed of, for example, a plurality of metal layers stacked on top of each other. Examples of the metal layers include Ni layers, Pd layers, and Au layers. The material of the external conductive film is not limited, but may be, for example, a stack of Ni layers and Au layers, or Sn.

[0120] (Effects) As described above, the second embodiment provides the following effects: (2-1) The same effects as those of the semiconductor device 10 of the first embodiment are provided.

[0121] (2-2) The conductive section 240 is formed of, for example, a plating layer. This semiconductor device 210 can be made smaller than the semiconductor device 10 in which the conductive section 40 is formed of a lead frame.

[0122] (Modification of Second Embodiment) A semiconductor device according to a modification of the second embodiment will now be described. In the semiconductor device according to the modification, components common to those of the second embodiment will be designated by the same reference numerals, and descriptions thereof will be omitted.

[0123] 19 to 21 , the semiconductor device 310 includes a sealing resin 380. The resin side surfaces 81 and 82 of the sealing resin 380 include first side surfaces 81A and 82A and second side surfaces 81B and 82B, respectively. The first side surfaces 81A and 82A are disposed closer to the resin upper surface 80S than the resin lower surface 80R in the z direction. The second side surfaces 81B and 82B are disposed closer to the resin lower surface 80R than the resin upper surface 80S in the z direction. The second side surfaces 81B and 82B of the resin side surfaces 81 and 82 are located inside the sealing resin 380 relative to the first side surfaces 81A and 82A of the resin side surfaces 81 and 82 in a plan view. In other words, the sealing resin is formed so that the side of the resin upper surface 80S is larger than the side of the resin lower surface 80R in the z direction.

[0124] The first side surfaces 81A, 82A of the resin side surfaces 81, 82 are perpendicular to the resin upper surface 80S. The second side surfaces 81B, 82B of the resin side surfaces 81, 82 are perpendicular to the resin lower surface 80R. The sealing resin 380 has a step 383 that is recessed toward the inside of the sealing resin 380 in a plan view due to the positions of the first side surfaces 81A, 82A and the second side surfaces 81B, 82B of the resin side surfaces 81, 82.

[0125] 19 to 22, the first external connection terminal 251A is exposed from the second side surface 82B of the resin side surface 82 in the x direction. That is, the first external connection terminal 251A is exposed from the resin lower surface 80R of the sealing resin 380 and the second side surface 82B of the resin side surface 82. The first external connection terminal 251A includes a lower surface 251A1 and a side surface 251A2 exposed from the sealing resin 380. The lower surface 251A1 and the side surface 251A2 of the first external connection terminal 251A are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 251A1 of the first external connection terminal 251A and a second conductive film 70B covering the side surface 251A2 of the first external connection terminal 251A.

[0126] The second external connection terminal 251B is exposed from the second side surface 82B of the resin side surface 82 in the x direction. That is, the second external connection terminal 251B is exposed from the resin lower surface 80R of the sealing resin 380 and the second side surface 82B of the resin side surface 82. The second external connection terminal 251B includes a lower surface 251B1 and a side surface 251B2 exposed from the sealing resin 380. The lower surface 251B1 and the side surface 251B2 of the second external connection terminal 251B are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 251B1 of the second external connection terminal 251B and a second conductive film 70B covering the side surface 251B2 of the first external connection terminal 251A.

[0127] The third external connection terminal 261A is exposed from the second side surface 81B of the resin side surface 81 in the x direction. That is, the third external connection terminal 261A is exposed from the resin lower surface 80R of the sealing resin 380 and the second side surface 81B of the resin side surface 81. The third external connection terminal 261A includes a lower surface 261A1 and a side surface 261A2 exposed from the sealing resin 380. The lower surface 261A1 and the side surface 261A2 of the third external connection terminal 261A are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 261A1 of the third external connection terminal 261A and a second conductive film 70B covering the side surface 261A2 of the first external connection terminal 261A.

[0128] The fourth external connection terminal 261B is exposed from the second side surface 81B of the resin side surface 81 in the x direction. That is, the fourth external connection terminal 261B is exposed from the resin lower surface 80R of the sealing resin 380 and the second side surface 81B of the resin side surface 81. The fourth external connection terminal 261B includes a lower surface 261B1 and a side surface 261B2 exposed from the sealing resin 380. The lower surface 261B1 and the side surface 261B2 of the fourth external connection terminal 261B are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 261B1 of the fourth external connection terminal 261B and a second conductive film 70B covering the side surface 261B2 of the first external connection terminal 261A.

[0129] The semiconductor device 310 of the modified example is mounted on a substrate 920 shown in FIG. 2 . At this time, the solder connecting each of the external connection terminals 251A, 251B, 261A, and 261B to the mounting pads of the substrate 920 adheres to the first conductive film 70A and the second conductive film 70B covering the external conductive film 70. For example, during a reflow process, the liquid-phase solder creeps up the second conductive film 70B and forms a solder fillet between the second conductive film 70B and the mounting pad. In this way, solder fillets are easily formed in the semiconductor device 310. These solder fillets increase the solder joint area and improve connection strength. Furthermore, the solder fillets make it easier to check the soldering condition of the semiconductor device 310.

[0130] The step 383 may be provided on each of the resin side surfaces 81 to 84. The external connection terminals may be exposed from the second side surfaces that constitute the steps provided on each of the resin side surfaces 81 to 84. The side surfaces of the external connection terminals that are exposed from the second side surfaces may be covered with an external conductive film.

[0131] 23 to 28, the configuration of a semiconductor device 410 of a third embodiment will be described. The semiconductor device 410 is mounted on a substrate 920 instead of the semiconductor device 10 shown in FIG. 2. The semiconductor device 410 of the third embodiment differs from the semiconductor devices 10 and 210 in the structure of a conductive portion 440 to which a semiconductor element 20 is connected. In the following description, components common to the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0132] 23 and 24 are perspective views showing the appearance of the semiconductor device 410, with FIG. 23 being a perspective view of the semiconductor device 410 viewed from the top, and FIG. 24 being a perspective view of the semiconductor device 410 viewed from the bottom. FIG. 25 is a plan view of the semiconductor device 410 viewed from the bottom. Note that FIGS. 25 and 26 show the semiconductor device 410 through a sealing resin 480. FIG. 26 is a plan view showing a conductive portion 440. FIG. 27 is a schematic cross-sectional view of the semiconductor device 410 taken along line 27-27 in FIG. 25. FIG. 28 is a schematic cross-sectional view of the semiconductor device 410 taken along line 28-28 in FIG. 15. Note that for convenience, FIGS. 27 and 28 may show components that are not on the line indicating the cross-sectional position, or the positions and sizes of components may differ from those in FIGS. 25 and 26.

[0133] 23 and 24, the semiconductor device 410 has, for example, a rectangular parallelepiped shape. As shown in FIGS. 23 to 28, the semiconductor device 410 includes a semiconductor element 20, a conductive portion 440, a sealing resin 480, and a resin layer 470.

[0134] The conductive portion 440 includes a second coil 443 and external connection terminals 451A, 451B, 461A, and 461B. The semiconductor element 20 is mounted on the conductive portion 440. The first coil 26 of the semiconductor element 20 faces the second coil 443 of the conductive portion 440 in the z direction. The first coil 26 and the second coil 443 correspond to the coils 913A and 913B shown in FIG. 1 . As shown in FIGS. 24 , 25 , 27 , and 28 , the semiconductor device 410 includes an external conductive film 70 that covers the external connection terminals 451A, 451B, 461A, and 461B.

[0135] The semiconductor device 410 includes a device top surface 10S, a device bottom surface 10R, and multiple device side surfaces 11, 12, 13, and 14. (Sealing Resin) The sealing resin 480 is formed in a rectangular plate shape. The sealing resin 480 includes a resin top surface 80S, a resin bottom surface 80R, and multiple resin side surfaces 81 to 84. The resin top surface 80S of the sealing resin 480 constitutes the device top surface 10S of the semiconductor device 410.

[0136] The sealing resin 480 seals the semiconductor element 20, the conductive portion 440, and the joint portion SD. The sealing resin 480 covers the element front surface 20S, the element back surface 20R, and the element side surfaces 201 to 204 of the semiconductor element 20. Therefore, it can be said that the semiconductor element 20 is embedded in the sealing resin 480. The semiconductor element 20 is disposed in the sealing resin 480 so that the element front surface 20S faces the same direction as the resin lower surface 80R of the sealing resin 480.

[0137] The sealing resin 480 is made of, for example, a resin having electrical insulating properties. As this resin, for example, a synthetic resin containing an epoxy resin as a main component can be used. As the sealing resin 480, for example, a synthetic resin containing a filler can be used. The filler can be, for example, SiO ２ The sealing resin 480 is colored, for example, black. The material and shape of the sealing resin 480 are not limited.

[0138] (Resin Layer) The resin layer 470 is formed in a rectangular plate shape in plan view, and has the same size as the sealing resin 480 in plan view.

[0139] The resin layer 470 has insulating properties. The resin layer 470 is a base member of the semiconductor device 410. The semiconductor element 20 is mounted on the resin layer 470. The resin layer 470 can be said to be a support member that supports the semiconductor element 20.

[0140] The resin layer 470 includes an upper surface 470S, a lower surface 470R, and multiple side surfaces 471, 472, 473, and 474. The upper surface 470S and the lower surface 470R face opposite each other in the z direction. The upper surface 470S of the resin layer 470 contacts the resin lower surface 80R of the sealing resin 480. The lower surface 470R of the resin layer 470 faces the same direction as the resin lower surface 80R of the sealing resin 480. The side surfaces 471 to 474 of the resin layer 470 intersect with the upper surface 470S and the lower surface 470R of the resin layer 470. The side surfaces 471 and 472 of the resin layer 470 face opposite each other in the x direction. The side surfaces 473 and 474 of the resin layer 470 face opposite each other in the y direction. The lower surface 470R of the resin layer 470 constitutes the device lower surface 10R of the semiconductor device 410. The resin side surfaces 81 to 84 of the sealing resin 480 and the side surfaces 471 to 474 of the resin layer 470 form the device side surfaces 11 to 14 of the semiconductor device 410 .

[0141] The resin layer 470 is made of, for example, a resin having electrical insulating properties. As this resin, for example, a synthetic resin containing an epoxy resin as a main component can be used. The resin layer 470 can be made of, for example, a synthetic resin containing a filler. The filler can be, for example, SiO ２ The resin layer 470 is colored, for example, black. The material and shape of the resin layer 470 are not limited. The resin layer 470 may be made of the same material as the sealing resin 480. If the resin layer 470 and the sealing resin 480 are made of the same material, the interface between the sealing resin 480 and the resin layer 470 (the resin lower surface 80R of the sealing resin 480 and the resin layer 470S) may not be formed.

[0142] 25 to 28 , the conductive portion 440 includes a first wiring member 441, a second wiring member 442, and a second coil 443. The conductive portion 440 may be formed of, for example, a plating layer. The conductive portion 240 is formed of, for example, a material containing Cu.

[0143] (First Wiring Member) The first wiring member 441 includes a first external connection terminal 451A, a second external connection terminal 451B, a first element connection portion 453A, a second element connection portion 453B, a first connection wiring 454A, a second connection wiring 454B, a first terminal connection portion 455A, and a second terminal connection portion 455B. The first element connection portion 453A, the second element connection portion 453B, the first connection wiring 454A, the second connection wiring 454B, the first terminal connection portion 455A, and the second terminal connection portion 455B configure a "first lead-out wiring."

[0144] 27 and 28 , the first element connection portion 453A, the first connection wiring 454A, and the first terminal connection portion 455A are formed on the upper surface 470S of the resin layer 470. The first element connection portion 453A is electrically connected to the first terminal connection portion 455A by the first connection wiring 454A. The first element connection portion 453A, the first connection wiring 454A, and the first terminal connection portion 455A may be an integrally formed one-piece member.

[0145] 27 and 28 , the second element connection portion 453B, the second connection wiring 454B, and the second terminal connection portion 455B are formed on the upper surface 470S of the resin layer 470. The second element connection portion 453B is electrically connected to the second terminal connection portion 455B by the second connection wiring 454B. The second element connection portion 453B, the second connection wiring 454B, and the second terminal connection portion 455B may be an integrally formed one-piece member.

[0146] 25 and 26 , the first element connection portion 453A and the second element connection portion 453B are arranged at positions overlapping the semiconductor element 20 in a plan view. The first element connection portion 453A and the second element connection portion 453B are arranged at positions overlapping the element electrodes 31A, 31B of the semiconductor element 20 in the z direction.

[0147] The first element connection portion 453A and the second element connection portion 453B are formed in a quadrangular shape in a plan view. Note that the shapes of the first element connection portion 453A and the second element connection portion 453B can be changed to any shape, such as a circle or a polygon, in a plan view.

[0148] 27 , a barrier layer 47 is formed on the first element connection portion 453A. The first element connection portion 453A is electrically connected to the first element electrode 31A of the semiconductor element 20 via the barrier layer 47 and a joint SD. A barrier layer 47 is formed on the second element connection portion 453B. The second element connection portion 453B is electrically connected to the second element electrode 31B of the semiconductor element 20 via the barrier layer 47 and a joint SD.

[0149] The first external connection terminal 451A is electrically connected to the first terminal connection portion 455A. The first external connection terminal 451A extends from the first terminal connection portion 455A toward the resin lower surface 80R of the sealing resin 480. A lower surface 451A1 of the first external connection terminal 451A is exposed from the lower surface 470R of the resin layer 470. The second external connection terminal 451B is electrically connected to the second terminal connection portion 455B. The second external connection terminal 451B extends from the second terminal connection portion 455B toward the resin lower surface 80R of the sealing resin 480. A lower surface 451B1 of the second external connection terminal 451B is exposed from the lower surface 470R of the resin layer 470.

[0150] 25 and 26, the first external connection terminal 451A and the second external connection terminal 451B are formed in a quadrangular shape in a plan view. Note that the shapes of the first external connection terminal 451A and the second external connection terminal 451B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0151] 25 and 26 , the first external connection terminal 451A and the second external connection terminal 451B are arranged along the device side surface 12 of the semiconductor device 410, in one example. The first external connection terminal 451A and the second external connection terminal 451B are arranged spaced apart in the y direction. The first external connection terminal 451A and the second external connection terminal 451B are arranged side by side in the y direction in a plan view. The first external connection terminal 451A is arranged at a corner formed by the device side surface 12 and the device side surface 13 of the semiconductor device 410. The second external connection terminal 451B is arranged at a corner formed by the device side surface 12 and the device side surface 14 of the semiconductor device 410.

[0152] 25 to 28 , the second wiring member 442 includes a third external connection terminal 461A, a fourth external connection terminal 461B, a third connection wiring 464A, a fourth connection wiring 464B, a third terminal connection portion 465A, a fourth terminal connection portion 465B, and an end connection portion 466. The third connection wiring 464A, the fourth connection wiring 464B, the third terminal connection portion 465A, the fourth terminal connection portion 465B, and the end connection portion 466 configure a “second lead-out wiring.”

[0153] As shown in Fig. 27, the second coil 443 is formed on the upper surface 470S of the resin layer 470. As shown in Figs. 25 and 26, the second coil 443 is formed in a spiral shape in a plan view. As shown in Fig. 25, the second coil 443 is arranged so as to overlap the first coil 26 of the semiconductor element 20 in a plan view. The second coil 443 includes an outer first end 443A and an inner second end 443B. The first end 443A corresponds to the "outer end". The second end 443B corresponds to the "inner end".

[0154] 25 and 26 , the end connection portion 466 is disposed inside the second coil 443. The end connection portion 466 is electrically connected to the second end 443B of the second coil 443. The first end 443A of the second coil 443 is electrically connected to the third terminal connection portion 465A via a third connection wiring 464A. The second coil 443, the end connection portion 466, the third connection wiring 464A, and the third terminal connection portion 465A may be integrally formed as a single unit.

[0155] 25 and 26 , the end connection portion 466 is electrically connected to the fourth terminal connection portion 465B by a fourth connection wiring 464B. As shown in FIG. 27 , the fourth connection wiring 464B is embedded in a resin layer 470. The fourth connection wiring 464B includes a buried wiring 467 and vias 468A connected to both ends of the buried wiring 467. A first end of the buried wiring 467 is electrically connected to the end connection portion 466 by the via 468A. A second end of the buried wiring 467 is electrically connected to the fourth terminal connection portion 465B (see FIG. 26 ) by the via 468A.

[0156] 28 , the third external connection terminal 461A is provided on the lower surface 465R of the third terminal connection portion 465A. The third external connection terminal 461A is electrically connected to the third terminal connection portion 465A. The third external connection terminal 461A extends from the third terminal connection portion 465A toward the lower surface 470R of the resin layer 470. A lower surface 461A1 of the third external connection terminal 461A is exposed from the lower surface 470R of the resin layer 470.

[0157] The fourth external connection terminal 461B is provided on the lower surface 465R of the fourth terminal connection portion 465B. The fourth external connection terminal 461B is electrically connected to the fourth terminal connection portion 465B. The fourth external connection terminal 461B extends from the fourth terminal connection portion 465B toward the lower surface 470R of the resin layer 470. A lower surface 461B1 of the fourth external connection terminal 461B is exposed from the lower surface 470R of the resin layer 470.

[0158] 25 and 26, the third external connection terminal 461A and the fourth external connection terminal 461B are formed in a quadrangular shape in a plan view. Note that the shapes of the third external connection terminal 461A and the fourth external connection terminal 461B can be changed to any shape, such as a circular shape or a polygonal shape, in a plan view.

[0159] In one example, the third external connection terminal 461A and the fourth external connection terminal 461B are arranged along the device side surface 11 of the semiconductor device 410. The third external connection terminal 461A and the fourth external connection terminal 461B are arranged spaced apart in the y direction. The first external connection terminal 451A and the second external connection terminal 451B are arranged side by side in the y direction in a plan view. The third external connection terminal 461A is arranged at a corner formed by the device side surface 11 and the device side surface 13 of the semiconductor device 410. The fourth external connection terminal 461B is arranged at a corner formed by the device side surface 11 and the device side surface 14 of the semiconductor device 410.

[0160] (Effects) As described above, the third embodiment provides the following effects: (3-1) The same effects as those of the semiconductor device 10 of the first embodiment and the semiconductor device 210 of the second embodiment are provided.

[0161] (3-2) The semiconductor device 410 includes external connection terminals 451A, 451B, 461A, and 461B that penetrate the resin layer 470. The device top surface 10S of the semiconductor device 410 is formed by the resin top surface 80S of the sealing resin 480 that seals the semiconductor element 20. Therefore, compared to the semiconductor device 210 that includes the substrate 271 and the substrate insulating film 272, it is possible to achieve a smaller size (lower profile).

[0162] (Modification of Third Embodiment) A semiconductor device according to a modification of the third embodiment will now be described. In the semiconductor device according to the modification, components common to those of the third embodiment will be designated by the same reference numerals, and description thereof will be omitted.

[0163] 29 and 30 , the semiconductor device 510 includes a sealing resin 580. The resin side surfaces 83 and 84 of the sealing resin 580 include first side surfaces 83A and 84A and second side surfaces 83B and 84B, respectively. The first side surfaces 83A and 84A are disposed closer to the resin upper surface 80S than the resin lower surface 80R in the z direction. The second side surfaces 83B and 84B are disposed closer to the resin lower surface 80R than the resin upper surface 80S in the z direction. The second side surfaces 83B and 84B of the resin side surfaces 83 and 84 are located inside the sealing resin 580 relative to the first side surfaces 83A and 84A of the resin side surfaces 83 and 84 in a plan view. In other words, the sealing resin is formed so that the side of the resin upper surface 80S is larger than the side of the resin lower surface 80R in the z direction.

[0164] The first side surfaces 83A, 84A of the resin side surfaces 83, 84 are perpendicular to the resin upper surface 80S. The second side surfaces 83B, 84B of the resin side surfaces 83, 84 are perpendicular to the resin lower surface 80R. The sealing resin 580 has a step 583 that is recessed toward the inside of the sealing resin 580 in a plan view, depending on the positions of the first side surfaces 83A, 84A and the second side surfaces 83B, 84B of the resin side surfaces 83, 84. The step 583 may be provided on the resin side surfaces 81 to 84.

[0165] When viewed from the z direction, the resin layer 470 is formed to have the same size as the resin lower surface 80R of the sealing resin 580. Therefore, when viewed from the z direction, the side surfaces 473 and 474 of the resin layer 470 facing the y direction are located more inward of the resin layer 470 than the first side surfaces 83A and 84A of the sealing resin 580. When the step 583 is provided on the resin side surfaces 81 and 82, the positions of the side surfaces 471 and 472 are changed accordingly.

[0166] 29 and 30 , the first external connection terminal 551A is exposed from the side surface 473 of the resin layer 470 in the y direction. That is, the first external connection terminal 551A is exposed from the lower surface 470R and the side surface 473 of the resin layer 470. The first external connection terminal 551A includes a lower surface 551A1 and a side surface 551A2 exposed from the resin layer 470. The lower surface 551A1 and the side surface 551A2 of the first external connection terminal 551A are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 551A1 of the first external connection terminal 551A and a second conductive film 70B covering the side surface 551A2 of the first external connection terminal 551A.

[0167] The second external connection terminal 551B is exposed from the side surface 474 of the resin layer 470 in the y direction. That is, the second external connection terminal 551B is exposed from the lower surface 470R and the side surface 474 of the resin layer 470. The second external connection terminal 551B includes a lower surface 551B1 and a side surface 551B2 exposed from the resin layer 470. The lower surface 551B1 and the side surface 551B2 of the second external connection terminal 551B are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 551B1 of the second external connection terminal 551B and a second conductive film 70B covering the side surface 551B2 of the first external connection terminal 551A.

[0168] 29 , the third external connection terminal 561A is exposed from the side surface 473 of the resin layer 470 in the y direction. That is, the third external connection terminal 561A is exposed from the lower surface 470R and the side surface 473 of the resin layer 470. The third external connection terminal 561A includes a lower surface 561A1 and a side surface 561A2 exposed from the resin layer 470. The lower surface 561A1 and the side surface 561A2 of the third external connection terminal 561A are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 561A1 of the third external connection terminal 561A and a second conductive film 70B covering the side surface 561A2 of the first external connection terminal 561A.

[0169] The fourth external connection terminal 561B is exposed from the side surface 474 of the resin layer 470 in the y direction. That is, the fourth external connection terminal 561B is exposed from the lower surface 470R and the side surface 474 of the resin layer 470. The fourth external connection terminal 561B includes a lower surface 561B1 and a side surface 561B2 exposed from the resin layer 470. The lower surface 561B1 and the side surface 561B2 of the fourth external connection terminal 561B are covered by an external conductive film 70. The external conductive film 70 includes a first conductive film 70A covering the lower surface 561B1 of the fourth external connection terminal 561B and a second conductive film 70B covering the side surface 561B2 of the first external connection terminal 561A.

[0170] The semiconductor device 510 of the modified example is mounted on a substrate 920 shown in FIG. 2 . At this time, the solder connecting each of the external connection terminals 551A, 551B, 561A, and 561B to the mounting pads of the substrate 920 adheres to the first conductive film 70A and the second conductive film 70B covering the external connection terminals 551A, 551B, 561A, and 561B. For example, during a reflow process, the liquid-phase solder creeps up the second conductive film 70B and forms a solder fillet between the second conductive film 70B and the mounting pad. In this way, solder fillets are easily formed in the semiconductor device 510. These solder fillets increase the solder joint area and improve connection strength. Furthermore, the solder fillets make it easier to check the soldering condition of the semiconductor device 510.

[0171] 29 and 30 show a case where the external connection terminals 551A and 561A are exposed on a side surface 473 of the resin layer 470, and the external connection terminals 551B and 561B are exposed on a side surface 474 of the resin layer 470. The side surfaces on which the external connection terminals 551A, 551B, 561A, and 561B are exposed can be changed as desired. For example, a configuration in which the external connection terminals 551A and 551B are exposed on a side surface 472 of the resin layer 470, and the external connection terminals 561A and 561B are exposed on a side surface 471 of the resin layer 470, is also possible. Alternatively, a configuration in which the external connection terminal 551A is exposed on two adjacent side surfaces, such as the side surfaces 472 and 473 of the resin layer 470, is also possible. Similarly, a configuration in which the external connection terminals 551B, 561A, and 561B are exposed on two adjacent side surfaces is also possible.

[0172] (Other Modifications) The above embodiment can be modified, for example, as follows. The above embodiment and each of the following modifications can be combined with each other as long as no technical contradiction occurs. In the following modifications, parts that are common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0173] The overall shape, terminal arrangement and shape, etc. of the semiconductor devices 10, 110, 210, 310, 410, and 510 of the above-described embodiments and modifications can be arbitrarily modified. As an example, a modification of the semiconductor device 410 of the third embodiment is shown in FIGS. 31 and 32. FIG. 31 is a plan view of a semiconductor device 610 of the modification, viewed from the bottom. FIG. 32 is a schematic cross-sectional view showing external connection terminals 451A and 451B connected to a semiconductor element 620 in the semiconductor device 610 of the modification.

[0174] 31 and 32 , when viewed from the z direction, the element electrodes 31A, 31B are positioned at positions offset from the connection pads 27A, 27B. The connection wiring 630 is electrically connected to the connection pads 27A, 27B exposed from the openings 25X of the third insulating layer 25 of the element insulating layer 22. The connection wiring 630 extends from the connection pads 27A, 27B to the insulating surface 22S of the element insulating layer 22. The connection wiring 630 is sometimes referred to as a redistribution layer. The element electrodes 31A, 31B are electrically connected to the portions of the connection wiring 630 arranged on the insulating surface 22S of the element insulating layer 22.

[0175] 31, the element electrodes 31C and 31D are arranged so as to overlap with the connection pads 27C and 27D in a plan view. Similar to the element electrodes 31A and 31B, these element electrodes 31C and 31D may also be arranged at positions that do not overlap with the connection pads 27C and 27D.

[0176] 1, a semiconductor element capacitor chip that uses a capacitor to provide insulation between the first circuit 911 and the second circuit 912 can be used. A capacitor chip including a capacitor is an example of a semiconductor device including an insulated configuration.

[0177] Fig. 33 is a schematic plan view of a semiconductor device 710 including a capacitor, and Fig. 34 shows a schematic cross-sectional view of the semiconductor device 710 of Fig. 33. The semiconductor device 710 includes a semiconductor element 720. The semiconductor element 720 includes a first electrode plate 726. The first electrode plate 726 is electrically connected to an element electrode 31B by an element wiring 728. A first end 728A of the element wiring 728 is electrically connected to the first electrode plate 726 by a via 729A. A second end 728B of the element wiring 728 is electrically connected to a connection pad 27B by a via 729B. An element electrode 31B is connected to the connection pad 27B.

[0178] A second electrode plate 743 is disposed on an upper surface 470S of the resin layer 470 of the semiconductor device 710. The conductive portion 740 includes a first wiring member 741, a second wiring member 742, and a second electrode plate 743. The first wiring member 741 includes an external connection terminal 451A, a second external connection terminal 451B, a first element connection portion 453A, a second element connection portion 453B, a second connection wiring 454B, a first terminal connection portion 455A, and a second terminal connection portion 455B. The second wiring member 742 includes a third external connection terminal 461A, a fourth external connection terminal 461B, a third connection wiring 464A, a third terminal connection portion 465A, and a fourth terminal connection portion 465B.

[0179] The first electrode plate 726 and the second electrode plate 743 face each other in the z direction. The first electrode plate 726 and the second electrode plate 743 form a capacitor. In other words, the semiconductor device is a capacitor chip including a capacitor. The first electrode plate 726 corresponds to the "first conductor." The second electrode plate 743 corresponds to the "second conductor."

[0180] In one example, the element electrode 31B is electrically connected to the second external connection terminal 451B through the second element connection portion 453B, the second connection wiring 454B, and the second terminal connection portion 455B that constitute the first wiring member 741 of the conductive portion 740. In one example, the second electrode plate 743 is electrically connected to the third external connection terminal 461A through the third connection wiring 464A and the third terminal connection portion 465A that constitute the second wiring member 742 of the conductive portion 740. Note that the external connection terminals to which the first electrode plate 726 and the second electrode plate 743 are connected can be changed as desired.

[0181] The semiconductor device 710 of this modified example can also achieve the same effects as the semiconductor device 10 of the first embodiment. The above-described embodiments and modified examples have been described as semiconductor devices in which the first coil and the second coil are used for signal transmission, but each semiconductor device can be used for other purposes. For example, the semiconductor device may be used in a direct current voltage conversion circuit (DC-DC converter), a digital isolator, an isolated AD conversion circuit, etc.

[0182] The term "on" as used in this disclosure includes both the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0183] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0184] (Supplementary Notes) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the Supplementary Notes are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples to aid understanding, and the components described in each Supplementary Note should not be limited to the components indicated by the reference symbols.

[0185] (Supplementary Note 1) A semiconductor device comprising: a semiconductor element (20) including an element front surface (20S) and an element back surface (20R) facing opposite each other in a thickness direction (z), an element insulating layer (22) including an insulating surface (22S) constituting the element front surface (20S), and a first conductor (26) provided in the element insulating layer (22); a second conductor (43) arranged spaced apart from the first conductor (26) in the thickness direction (z); and a sealing resin (80) in contact with the element insulating layer (22) and sealing the semiconductor element (20) and the second conductor (43), wherein the first conductor (26) and the second conductor (43) face each other in the thickness direction (z) with the element insulating layer (22) and the sealing resin (80) sandwiched therebetween.

[0186] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the semiconductor element (20) includes a plurality of element side surfaces (201-204) intersecting the element front surface (20S) and the element back surface (20R), and the sealing resin (80) covers the element back surface (20R) and the plurality of element side surfaces (201-204).

[0187] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or Supplementary Note 2, wherein the thickness of the sealing resin (80) is greater than the thickness of the element insulating layer (22).

[0188] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the thickness of the second conductor (43) is greater than the thickness of the first conductor (26).

[0189] (Appendix 5) The semiconductor device described in any one of Appendix 1 to Appendix 4, wherein the sealing resin (80) includes a resin underside (80R) facing the same direction as the element surface (20S), and includes: a first wiring member (41) electrically connected to the first conductor (26) and exposed from the resin underside (80R); and a second wiring member (42) electrically connected to the second conductor (43) and exposed from the resin underside (80R).

[0190] (Supplementary Note 6) The semiconductor device according to Supplementary Note 5, wherein the semiconductor element (20) includes element electrodes (31A, 31B) electrically connected to the first conductors (26), and the first wiring member (41) includes: first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B) embedded in the sealing resin (80) and electrically connected to the element electrodes (31A, 31B); and first external connection terminals electrically connected to the first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B) and exposed from the resin bottom surface (80R).

[0191] (Supplementary Note 7) The semiconductor device according to Supplementary Note 6, wherein the first lead-out wiring (253A, 253B, 254A, 254B, 255A, 255B) includes element connection portions (53A, 53B) to which the element electrodes (31A, 31B) are connected, and connection wiring that electrically connects the element connection portions (53A, 53B) and the first external connection terminals.

[0192] (Supplementary Note 8) The semiconductor device according to Supplementary Note 6 or Supplementary Note 7, wherein the first external connection terminal is disposed at a position where at least a portion of the first external connection terminal does not overlap with the semiconductor element (20) when viewed from the thickness direction (z).

[0193] (Appendix 9) The semiconductor device described in any one of Appendices 5 to 8, wherein the second wiring member (42) includes: a second lead-out wiring (64) embedded in the sealing resin (80) and electrically connected to the second conductor (43); and a second external connection terminal electrically connected to the second lead-out wiring (64) and exposed from the bottom surface (80R) of the resin.

[0194] (Supplementary Note 10) The semiconductor device according to Supplementary Note 9, wherein the second conductor (43) and the second lead-out wiring (64) are embedded in the sealing resin (80) at the same position in the thickness direction (z).

[0195] (Supplementary Note 11) The semiconductor device according to any one of Supplementary Note 5 to Supplementary Note 10, wherein the second wiring member (42) is electrically connected to an outer end of the second conductor (43), and includes a third external connection terminal that is electrically connected to an inner end of the second conductor (43) and exposed from the resin lower surface (80R).

[0196] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Note 5 to Supplementary Note 11, wherein the second conductor (43) and the second wiring member (42) are configured by a lead frame.

[0197] (Supplementary Note 13) The semiconductor device according to Supplementary Note 12, wherein the semiconductor element (20) includes dummy element electrodes (31C, 31D) (31A, 31B) electrically insulated from the first conductor (26), and the lead frame includes dummy element connection portions (53A, 53B) (53C, 53D) connected to the dummy element electrodes (31C, 31D) (31A, 31B).

[0198] (Appendix 14) A semiconductor device according to any one of appendices 1 to 4, comprising: a substrate having an upper surface and a lower surface; and a substrate insulating film provided on the lower surface of the substrate; wherein the second conductor (43) is provided on the lower surface of the substrate insulating film; and the sealing resin (80) is in contact with the lower surface of the substrate insulating film.

[0199] (Appendix 15) The semiconductor device according to appendix 14, wherein the sealing resin (80) includes a resin lower surface (80R) facing in the same direction as the lower surface of the substrate, a first wiring member (41) electrically connected to the first conductor (26) and exposed from the resin lower surface (80R), and a second wiring member (42) electrically connected to the second conductor (43) and exposed from the resin lower surface (80R).

[0200] (Appendix 16) The semiconductor device according to Appendix 15, wherein the semiconductor element (20) includes element electrodes (31A, 31B) electrically connected to the first conductors (26), and the first wiring member (41) includes: first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B) provided on the lower surface of the substrate insulating film and electrically connected to the element electrodes (31A, 31B); and first external connection terminals electrically connected to the first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B), penetrating the sealing resin (80) in the thickness direction (z) and exposed from the resin lower surface (80R).

[0201] (Supplementary Note 17) The semiconductor device according to Supplementary Note 16, wherein the first lead-out wiring (253A, 253B, 254A, 254B, 255A, 255B) includes an element connection portion (53A, 53B) to which the element electrode (31A, 31B) is connected, a terminal connection portion connected to the first external connection terminal, and a connection wiring electrically connecting the element connection portion (53A, 53B) and the terminal connection portion.

[0202] (Supplementary Note 18) The semiconductor device according to Supplementary Note 16 or Supplementary Note 17, wherein the first external connection terminal is disposed at a position not overlapping the semiconductor element (20) when viewed from the thickness direction (z).

[0203] (Appendix 19) The semiconductor device described in any one of Appendices 15 to 18, wherein the second wiring member (42) includes: second lead-out wiring (264A, 264B, 265A, 265B) provided on the underside of the substrate insulating film and electrically connected to the second conductor (43); and second external connection terminals electrically connected to the second lead-out wiring (264A, 264B, 265A, 265B), penetrating the sealing resin (80) in the thickness direction (z) and exposed from the resin underside (80R).

[0204] (Supplementary Note 20) The semiconductor device according to Supplementary Note 19, wherein the second lead-out wiring includes a terminal connection portion (265A, 265B) connected to the second external connection terminal, and a connection wiring (264A, 264B) that electrically connects the second conductor (43) and the terminal connection portion.

[0205] (Supplementary Note 21) The semiconductor device according to Supplementary Note 19 or Supplementary Note 20, wherein the second external connection terminal is disposed at a position not overlapping the semiconductor element (20) when viewed from the thickness direction (z).

[0206] (Supplementary Note 22) The semiconductor device according to any one of Supplementary Note 15 to Supplementary Note 21, wherein the semiconductor element (20) includes dummy element electrodes (31C, 31D) (31A, 31B) electrically insulated from the first conductor (26), and includes dummy element connection portions (53A, 53B) (53C, 53D) provided on the lower surface of the substrate insulating film and connected to the dummy element electrodes (31C, 31D) (31A, 31B).

[0207] (Appendix 23) The semiconductor device described in any one of Appendix 1 to Appendix 4, wherein the sealing resin (80) has a resin lower surface (80R) facing the same direction as the element surface (20S), and includes a resin layer including an upper surface in contact with the resin lower surface (80R), and the second conductor (43) is provided on the upper surface of the resin layer.

[0208] (Appendix 24) The semiconductor device described in Appendix 23, wherein the resin layer includes a lower surface facing the same direction as the element surface (20S), and includes: a first wiring member (41) electrically connected to the first conductor (26) and exposed from the lower surface of the resin layer; and a second wiring member (42) electrically connected to the second conductor (43) and exposed from the lower surface of the resin layer.

[0209] (Supplementary Note 25) The semiconductor device according to Supplementary Note 24, wherein the semiconductor element (20) includes element electrodes (31A, 31B) electrically connected to the first conductors (26), and the first wiring member (41) includes: first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B) provided on the upper surface of the sealing resin (80) and electrically connected to the element electrodes (31A, 31B); and first external connection terminals electrically connected to the first lead-out wirings (253A, 253B, 254A, 254B, 255A, 255B), penetrating the resin layer in the thickness direction (z) and exposed from the lower surface of the resin layer.

[0210] (Appendix 26) The semiconductor device according to Appendix 25, wherein the first lead-out wiring (253A, 253B, 254A, 254B, 255A, 255B) includes an element connection portion (53A, 53B) to which the element electrode (31A, 31B) is connected, a terminal connection portion connected to the first external connection terminal, and a connection wiring electrically connecting the element connection portion (53A, 53B) and the terminal connection portion.

[0211] (Supplementary Note 27) The semiconductor device according to Supplementary Note 25 or Supplementary Note 26, wherein the first external connection terminal is disposed at a position not overlapping the semiconductor element (20) when viewed from the thickness direction (z).

[0212] (Appendix 28) A semiconductor device described in any one of Appendices 24 to 27, wherein the second wiring member (42) includes: a second lead-out wiring provided on the underside of the sealing resin (80) and electrically connected to the second conductor (43); and a second external connection terminal electrically connected to the second lead-out wiring, penetrating the resin layer in the thickness direction (z) and exposed from the upper surface.

[0213] (Supplementary Note 29) The semiconductor device according to Supplementary Note 28, wherein the second lead-out wiring includes a terminal connection portion connected to the second external connection terminal, and a connection wiring that electrically connects the second conductor (43) and the terminal connection portion.

[0214] (Supplementary Note 30) The semiconductor device according to Supplementary Note 28 or Supplementary Note 29, wherein the second external connection terminal is disposed at a position not overlapping the semiconductor element (20) when viewed from the thickness direction (z).

[0215] (Supplementary Note 31) The semiconductor device according to any one of Supplementary Note 24 to Supplementary Note 30, wherein the semiconductor element (20) includes dummy element electrodes (31C, 31D) (31A, 31B) electrically insulated from the first conductor (26), and includes dummy element connection portions (53A, 53B) (53C, 53D) provided on the lower surface of the resin layer and connected to the dummy element electrodes (31C, 31D) (31A, 31B).

[0216] (Supplementary Note 32) The semiconductor device described in any one of Supplementary Note 1 to Supplementary Note 31, wherein the first conductor (26) includes a first coil formed in a spiral shape when viewed from the thickness direction (z), and the second conductor (43) includes a second coil formed in a spiral shape when viewed from the thickness direction (z).

[0217] (Supplementary Note 33) The semiconductor device according to Supplementary Note 32, wherein a second width dimension of the second coil in a direction parallel to the element surface (20S) is larger than a first width dimension of the first coil in a direction parallel to the element surface (20S).

[0218] (Supplementary Note 34) A semiconductor device described in any one of Supplementary Note 1 to Supplementary Note 31, wherein the first conductor (26) includes a first electrode plate extending parallel to the element surface (20S), the second conductor (43) is a second electrode plate extending parallel to the element surface (20S), and the first electrode plate and the second electrode plate form a capacitor.

[0219] (Supplementary Note 35) A semiconductor element (20) including: an element front surface (20S) and an element back surface (20R) facing opposite each other in a thickness direction (z); a plurality of element side surfaces (201-204) intersecting the element front surface (20S) and the element back surface (20R); a first coil (26) formed in a spiral shape when viewed from the thickness direction (z); and element electrodes (31A, 31B) electrically connected to the first coil (26); a conductive portion including a first wiring member (41) electrically connected to the element electrodes (31A, 31B) by a joint portion, a second coil (43) facing the first coil (26), and a second wiring member (42) electrically connected to the second coil (43); and a sealing resin (80) including a resin undersurface (80R) facing in the same direction as the element front surface (20S), and sealing the semiconductor element (20) and the conductive portion, the first wiring member (41) and the second wiring member (42) include external connection terminals exposed from the resin lower surface (80R).

[0220] (Supplementary Note 36) A semiconductor element (20) including: an element front surface (20S) and an element back surface (20R) facing opposite to each other in a thickness direction (z); a plurality of element side surfaces (201-204) intersecting the element front surface (20S) and the element back surface (20R); a first coil (26) formed in a spiral shape when viewed from the thickness direction (z); and element electrodes (31A, 31B) electrically connected to the first coil (26); a semiconductor substrate including a bottom surface facing the element front surface (20S); and a substrate insulating film formed on the bottom surface of the semiconductor substrate, the bottom surface facing the element front surface (20S); a conductive portion formed on the lower surface of the substrate insulating film and including a first wiring member (41) electrically connected to the element electrodes (31A, 31B) by a joint portion, a second coil (243) facing the first coil (26), and a second wiring member (42) electrically connected to the second coil (243); and a sealing resin (80) including a lower surface facing the same direction as the element back surface (20R), the sealing resin being filled between the semiconductor element (20) and the substrate insulating film and sealing the semiconductor element (20), wherein the first wiring member (41) and the second wiring member (42) include external connection terminals exposed from the lower surface of the sealing resin (80).

[0221] (Supplementary Note 37) A semiconductor element (20) including: an element front surface (20S) and an element back surface (20R) facing opposite sides in a thickness direction (z); a plurality of element side surfaces (201-204) intersecting the element front surface (20S) and the element back surface (20R); a first coil (26) formed in a spiral shape when viewed from the thickness direction (z); and element electrodes (31A, 31B) electrically connected to the first coil (26); a resin layer including a bottom surface facing the element front surface (20S) in the thickness direction (z) and a top surface facing the opposite side to the bottom surface; a first external connection terminal formed through the resin layer; and a second external connection terminal formed through the resin layer. a conductive portion formed on the upper surface of the resin layer and including a first wiring member (41) electrically connected to the first external connection terminal, a second wiring member (42) electrically connected to the second external connection terminal, and a second coil (443) facing the first coil (26) and electrically connected to the second wiring member (42); a joint portion electrically connecting the first wiring member (41) and the element electrodes (31A, 31B); and a sealing resin (80) filled between the semiconductor element (20) and the resin layer and sealing the semiconductor element (20).

[0222] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0223] 10 Semiconductor device 10R Device bottom surface 10S Device top surface 11-14 Device side surface 20 Semiconductor element 20R Element back surface 20S Element front surface 201-204 Element side surface 21 Element substrate 21R Substrate back surface 21S Substrate main surface 22 Element insulating layer 22R Insulating back surface 22S Insulating front surface 23 First insulating layer 23S Front surface 24 Second insulating layer 24S Front surface 25 Third insulating layer 25A Element resin portion 25X Opening 26 First coil 26A First end 26B Second end 27A-27D Connection pad 28 Element wiring 28A First end 28B Second end 29A, 29B Via 30 Connection wiring 31A-31D Element electrode 32 Conductive layer 33 Barrier layer 40 Conductive portion 41 First wiring member 42 Second wiring member 43 Second coil 43A First end 43B Second end 43S Upper surface 47 Barrier layer 51A First external connection terminal 51A1 Lower surface 51A2 Side surface 51B Second external connection terminal 51B1 Lower surface 51B2 Side surface 51S Upper surface 52A Connection portion 52B Connection portion 53A First element connection portion 53B Second element connection portion 53C, 53D Dummy element connection portion 54A First connection wiring 54B Second connection wiring 61A Third external connection terminal 61A1 Lower surface 61A2 Side surface 61B Fourth external connection terminal 62A Connection portion 64 Third connection wiring 70 External conductive film 70A First conductive film 70B Second conductive film 80 Sealing resin 80R Resin bottom surface 80S Resin top surface 81-84 Resin side surface 81A, 82A First side surface 81B,82B Second side surface 110 Semiconductor device 180 Sealing resin 183 Step 210 Semiconductor device 211-214 Substrate side surfaces 221-224 Insulated side surfaces 240 Conductive portion 241 First wiring member 242 Second wiring member 243 Second coil 243A First end 243B Second end 251A First external connection terminal 251A1 Lower surface 251A2 Side surface 251B Second external connection terminal 251B1 Lower surface 251B2 Side surface 253A First element connection portion 253B Second element connection portion 254A First connection wiring 254B Second connection wiring 255A First terminal connection portion 255B Second terminal connection portion 255R Lower surface 261A Third external connection terminal 261A1 Lower surface 261A2 Side surface 261B Fourth external connection terminal 261B1 Lower surface 261B2 Side surface 264A Third connection wiring 264B Fourth connection wiring 265A Third terminal connection portion 265B Fourth terminal connection portion 265R Lower surface 266 End connection portion 267 Buried wiring 268A,268B Via 271 Substrate 271C Side surface 271R Bottom surface 271S Top surface 272 Substrate insulating film 272C Side surface 272R Bottom surface 272S Top surface 280 Sealing resin 310 Semiconductor device 380 Sealing resin 383 Step 410 Semiconductor device 440 Conductive portion 441 First wiring member 442 Second wiring member 443 Second coil 443A First end 443B Second end 451A First external connection terminal 451A1 Bottom surface 451B Second external connection terminal 451B1 Bottom surface 453A First element connection portion 453B Second element connection portion 454A First connection wiring 454B Second connection wiring 455A First terminal connection portion 455B Second terminal connection portion 461A Third external connection terminal 461A1 Lower surface 461B Fourth external connection terminal 461B1 Lower surface 464A Third connection wiring 464B Fourth connection wiring 465A Third terminal connection portion 465B Fourth terminal connection portion 465R Lower surface 466 End connection portion 467 Buried wiring 468A Via 470 Resin layer 470R Lower surface 470S Upper surface 471 to 474 Side surface 480 Sealing resin 510 Semiconductor device 551A First external connection terminal 551A1 Lower surface 551A2 Side surface 551B Second external connection terminal 551B1 Lower surface 551B2 Side surface 561A Third external connection terminal 561A1 Lower surface 561A2 Side surface 561B Fourth external connection terminal 561B1 Bottom surface 561B2 Side surface 580 Sealing resin 580R Resin bottom surface 583 Step 610 Semiconductor device 620 Semiconductor element 630 Connection wiring 710 Semiconductor device 720 Semiconductor element 726 First electrode plate 743 Second electrode plate 900 Signal transmission device 901 First terminal 902 Second terminal 911 First circuit 911A Transmitting circuit 912 Second circuit 912A Receiving circuit 913 Transformer 913A Coil 913B Coil 920 Substrate 921 Substrate surface 922 Substrate back surface 923 First end 924 Second end 931 Semiconductor device 932 Semiconductor device 941 First terminal 942 Second terminal D12 Distance SD Joint T11,T12 Thickness T21, T22 Thickness V1 First voltage V2 Second voltage W1, W2 Width,

Claims

1. a semiconductor element including an element front surface and an element back surface facing opposite to each other in a thickness direction, an element insulating layer including an insulating surface constituting the element front surface, and a first conductor provided in the element insulating layer; a second conductor disposed apart from the first conductor in the thickness direction; a sealing resin that contacts the element insulating layer and seals the semiconductor element and the second conductor; Including, the first conductor and the second conductor face each other in the thickness direction with the element insulating layer and the sealing resin interposed therebetween; Semiconductor device.

2. the semiconductor element includes a plurality of element side surfaces intersecting the element front surface and the element back surface; the sealing resin covers the back surface of the element and the plurality of side surfaces of the element; The semiconductor device according to claim 1 .

3. The thickness of the sealing resin is greater than the thickness of the element insulating layer. The semiconductor device according to claim 1 .

4. The thickness of the second conductor is greater than the thickness of the first conductor. The semiconductor device according to claim 1 .

5. the sealing resin includes a resin lower surface facing the same direction as the element surface, a first wiring member electrically connected to the first conductor and exposed from the lower surface of the resin; a second wiring member electrically connected to the second conductor and exposed from the lower surface of the resin; Including, The semiconductor device according to claim 1 .

6. the semiconductor element includes an element electrode electrically connected to the first conductor; The first wiring member is a first lead wiring embedded in the sealing resin and electrically connected to the element electrode; a first external connection terminal electrically connected to the first lead wiring and exposed from the lower surface of the resin; Including, The semiconductor device according to claim 5 .

7. the first lead wiring includes an element connection portion to which the element electrode is connected, and a connection wiring that electrically connects the element connection portion and the first external connection terminal; The semiconductor device according to claim 6.

8. the first external connection terminal is disposed at a position where at least a portion thereof does not overlap the semiconductor element when viewed from the thickness direction; The semiconductor device according to claim 6.

9. The second wiring member is a second lead wiring embedded in the sealing resin and electrically connected to the second conductor; a second external connection terminal electrically connected to the second lead wiring and exposed from the lower surface of the resin; Including, The semiconductor device according to claim 5 .

10. a substrate including a top surface and a bottom surface; a substrate insulating film provided on the lower surface of the substrate; Including, the second conductor is provided on the lower surface of the substrate insulating film, the sealing resin is in contact with the lower surface of the substrate insulating film; The semiconductor device according to claim 1 .

11. the sealing resin includes a resin lower surface facing the same direction as the lower surface of the substrate; a first wiring member electrically connected to the first conductor and exposed from the lower surface of the resin; a second wiring member electrically connected to the second conductor and exposed from the lower surface of the resin; Including, The semiconductor device according to claim 10.

12. the semiconductor element includes an element electrode electrically connected to the first conductor; The first wiring member is a first lead wiring provided on the lower surface of the substrate insulating film and electrically connected to the element electrode; a first external connection terminal electrically connected to the first lead wiring, penetrating the sealing resin in the thickness direction and exposed from the bottom surface of the resin; Including, The semiconductor device according to claim 11.

13. the first lead wiring includes an element connection portion to which the element electrode is connected, a terminal connection portion connected to the first external connection terminal, and a connection wiring that electrically connects the element connection portion and the terminal connection portion; The semiconductor device according to claim 12.

14. the first external connection terminal is disposed at a position not overlapping the semiconductor element when viewed from the thickness direction; The semiconductor device according to claim 12.

15. the sealing resin has a resin lower surface facing the same direction as the element surface, a resin layer including an upper surface in contact with the resin lower surface, the second conductor is provided on the upper surface of the resin layer; The semiconductor device according to claim 1 .

16. the resin layer includes a lower surface facing the same direction as the surface of the element; a first wiring member electrically connected to the first conductor and exposed from the lower surface of the resin layer; a second wiring member electrically connected to the second conductor and exposed from the lower surface of the resin layer; Including, The semiconductor device according to claim 15.

17. the semiconductor element includes an element electrode electrically connected to the first conductor; The first wiring member is a first lead wiring provided on the upper surface of the sealing resin and electrically connected to the element electrode; a first external connection terminal electrically connected to the first lead wiring, penetrating the resin layer in the thickness direction and exposed from the lower surface of the resin layer; Including, The semiconductor device according to claim 16.

18. the first lead wiring includes an element connection portion to which the element electrode is connected, a terminal connection portion connected to the first external connection terminal, and a connection wiring that electrically connects the element connection portion and the terminal connection portion; 18. The semiconductor device according to claim 17.

19. the first external connection terminal is disposed at a position not overlapping the semiconductor element when viewed from the thickness direction; 18. The semiconductor device according to claim 17.

20. the first conductor includes a first coil formed in a spiral shape when viewed from the thickness direction, The second conductor includes a second coil formed in a spiral shape when viewed from the thickness direction. The semiconductor device according to claim 1 .